Semiconductor device

Abstract

To provide a semiconductor device which can be desirably manufactured.SOLUTION: The semiconductor device includes: a first wafer including a plurality of die regions arranged in a first direction (X) and a second direction (Y); a plurality of conductive layers and a plurality of insulating layers provided in a device region on the first wafer and alternately stacked in a stacking direction (Z); and a plurality of first layers and a plurality of second layers provided in an edge region on the first wafer and arranged in the stacking direction, a plurality of first die regions of the plurality of die regions positioned in the device region each including a terrace region provided with a part of the plurality of conductive layers, and in a region where a plurality of second die regions of the plurality of die regions overlap the edge region in the stacking direction, the number of the plurality of first layers provided in the plurality of second die regions corresponding to positions each including at least a part of the terrace region being greater than the number of the plurality of conductive layers arranged in the stacking direction at positions including at least a part of the terrace region.SELECTED DRAWING: Figure 23

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] A semiconductor device is known that includes a plurality of conductive layers and a plurality of insulating layers alternately stacked in a stacking direction, a semiconductor layer extending in the stacking direction and facing the plurality of conductive layers, and a gate insulating film provided between the plurality of conductive layers and the semiconductor layer. The gate insulating film includes a memory portion capable of storing data, such as an insulating charge storage film made of silicon nitride (SiN) or a conductive charge storage film made of a floating gate. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-60704 [Patent Document 2] Japanese Patent Application Publication No. 2023-137395 [Patent Document 3] Japanese Patent Publication No. 2022-104020 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device that can be suitably manufactured is provided. [Means for solving the problem]

[0005] According to one embodiment, the semiconductor device includes a first wafer including a plurality of die regions aligned in a first direction and a second direction intersecting the first direction; a plurality of conductive layers and a plurality of insulating layers provided in a device region of the first wafer outside a predetermined distance from an outer edge of the first wafer, the conductive layers and the insulating layers being alternately stacked in a stacking direction intersecting the first and second directions; and a plurality of first layers and a plurality of second layers provided in an edge region of the first wafer within the predetermined distance from the outer edge of the first wafer, the plurality of first layers being aligned in the stacking direction corresponding to the conductive layers and the insulating layers, respectively. Among the plurality of die regions, a plurality of first die regions located within the device region each include a terrace region in which some of the conductive layers are provided and others are not. Within a region where a plurality of second die regions overlap the edge region in the stacking direction, the number of the plurality of first layers aligned in the stacking direction in the plurality of second die regions corresponding to positions including at least a portion of the terrace region is greater than the number of the plurality of conductive layers aligned in the stacking direction and including at least a portion of the terrace region. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic perspective view showing the configuration of a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a schematic exploded perspective view showing the configuration of the semiconductor memory device. [Figure 3] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 4] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 5] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 6] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 7] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 8] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 9] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 10] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 11] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 12] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 13] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 14] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 15] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 16] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 17] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 18] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 19] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 20] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 21] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 22] FIG. 2 is a schematic bottom view showing a configuration of a part of the semiconductor memory device. [Figure 23] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 24] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 25] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 26] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 27]FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device. [Figure 28] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor memory device. [Figure 29] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 30] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 31] FIG. 10 is a schematic bottom view for explaining the manufacturing method. [Figure 32] FIG. 10 is a schematic bottom view for explaining the manufacturing method. [Figure 33] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 34] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 35] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 36] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 39] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 40] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 41] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 42] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 43] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 44] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 45] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 46] FIG. 2 is a schematic perspective view for explaining the manufacturing method. [Figure 47] FIG. 2 is a schematic perspective view for explaining the manufacturing method. [Figure 48] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 49] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 50] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 51] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 52] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 53] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 54] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 55] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 56] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 57] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 58] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 59] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 60] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 61] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 62] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 63] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 64] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 65] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 66] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 67] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 68] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 69] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 70] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 71] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 72] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 73] FIG. 10 is a schematic cross-sectional view for explaining a semiconductor memory device according to a comparative example. [Figure 74] FIG. 10 is a schematic cross-sectional view for explaining a semiconductor memory device according to a comparative example. [Figure 75] FIG. 10 is a schematic cross-sectional view for explaining a semiconductor memory device according to a comparative example. [Figure 76] FIG. 10 is a schematic cross-sectional view for explaining a semiconductor memory device according to a comparative example. [Figure 77] 1 is a schematic cross-sectional view for explaining a semiconductor memory device according to a first embodiment. [Figure 78] 1 is a schematic cross-sectional view for explaining a semiconductor memory device according to a first embodiment. [Figure 79] 1 is a schematic cross-sectional view for explaining a semiconductor memory device according to a first embodiment. [Figure 80] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 81] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 82] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 83] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a second embodiment. [Figure 84] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor memory device according to a third embodiment. [Figure 85] FIG. 10 is a schematic perspective view for explaining a manufacturing method according to a fourth embodiment. [Figure 86] 10A to 10C are schematic cross-sectional views for explaining a manufacturing method according to a fourth embodiment. [Figure 87] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 88] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 89] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. [Figure 90] FIG. 10 is a schematic cross-sectional view showing the configuration of a portion of a semiconductor memory device according to a fifth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and for the sake of convenience, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and descriptions thereof may be omitted.

[0008] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0009] In this specification, a predetermined direction parallel to the surface of the substrate is called the X direction, a direction parallel to the surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the surface of the substrate is called the Z direction.

[0010] In this specification, the direction intersecting the surface of the substrate may be referred to as the stacking direction. The direction along a predetermined plane intersecting the stacking direction may be referred to as the first direction, and the direction intersecting the first direction along this plane may be referred to as the second direction. The stacking direction may or may not coincide with the Z direction. The first and second directions may or may not correspond to either the X or Y direction.

[0011] [First embodiment] [Overall composition] 1 is a schematic perspective view showing the configuration of a semiconductor memory device according to the first embodiment. As shown in FIG. 1, the semiconductor memory device according to this embodiment includes a wafer W M and wafer W P The wafer W M The wafer W includes, for example, a memory cell array of a NAND flash memory. P is equipped with peripheral circuits for NAND flash memory.

[0012] In the following description, the wafer W M Wafer W P The surface on the side of the wafer W is called the "bottom surface" or "top surface." P The surface opposite to the wafer W is called the "top surface" or "back surface." P Wafer W MThe surface on the side is called the "top surface" or "front surface," and the surface on the side is called the "wafer W" M The surface opposite to this is called the "bottom surface" or "back surface."

[0013] 2 is a schematic exploded perspective view showing the configuration of the semiconductor memory device according to this embodiment. M On the underside of I1 Also, the wafer W P On the top surface of I2 The wafer W M Multiple configurations in the wafer W P The multiple configurations in the figure refer to multiple laminated electrodes P I1 ,P I2 are electrically connected to each other via

[0014] FIG. 3 is a schematic bottom view showing a partial configuration of the semiconductor memory device according to this embodiment, in which a wafer W M In addition, in FIG. 3, a plurality of laminated electrodes P I1 Some components have been omitted, such as (Figure 2).

[0015] Wafer W M has multiple die regions R MD and these multiple die regions R MD Kerf area R between K and a plurality of die regions R MD are individually separated by dicing. K includes the dicing line. Kerf area R K is a plurality of kerf regions R extending in the Y direction and aligned in the X direction. KY and a plurality of kerf regions R extending in the X direction and aligned in the Y direction. KX and a kerf region R K The middle configuration is not used to input or output voltages to or from the memory cell array, or to input or output data signals or other signals to or from the memory cell array.

[0016] In addition, wafer W M The device region R DVand the edge region R ED The device region R DV is wafer W M Outside the specified distance from the outer edge of the wafer ( M The edge area R is located within a predetermined distance from the center of the circumscribing circle. ED is wafer W M Within a predetermined distance from the outer edge of the wafer ( M The die area R is located outside the range of a predetermined distance from the center of the circumscribing circle of the die area R. MD Among them, device region R DV The semiconductor device provided in the above is separated into individual pieces, and then mounted on a memory card, SSD (Solid State Drive), or the like, and functions as a device.

[0017] In addition, the edge region R ED In the flat region R FL and the round area R RN The flat region R FL is the edge region R ED Inside, wafer W M Outside the range of other specified distances from the outer edge of the wafer ( M The round area R is located within a specified distance from the center of the circumscribing circle of the RN is the edge region R ED Inside, wafer W M Within another predetermined distance from the outer edge of the wafer ( M (outside the range of other specified distances from the center of the circumscribing circle of the

[0018] FIG. 4 is a schematic bottom view showing a configuration of a part of the semiconductor memory device according to this embodiment. DV As shown in Figure 4, a part of the device region R DV Die area R MD is two plane regions R aligned in the X direction. PN and these two plane regions R PN A peripheral circuit region R is provided on one side in the Y direction with respect to P The die area R MDThe configuration inside can be adjusted as needed. For example, the die area R MD is a set of four plane regions R aligned in the X and Y directions. PN or four plane regions R arranged in the X direction. PN In addition, the plane area R PN The kerf region R can be controlled independently by the peripheral circuits, and can be associated with an operation unit that can operate in parallel. KY are the two laminated regions R aligned in the Y direction. SS and a non-laminated region R provided therebetween. SN The laminate region R SS and non-laminated region R SN are aligned in the X direction with a plurality of finger structures FS, which will be described later.

[0019] [Device Region R DV ] [Device Region R DV Plain area R PN ] FIG. 5 is a schematic bottom view showing a partial configuration of a semiconductor memory device according to this embodiment, enlarging a portion of FIG. 4. FIG. 6 is a schematic bottom view showing a partial configuration of the semiconductor memory device, enlarging a portion indicated by A in FIG. 5. FIG. 7 is a schematic bottom view showing a partial configuration of the semiconductor memory device, enlarging a portion indicated by B in FIG. 6. FIG. 8 is a schematic bottom view showing a partial configuration of the semiconductor memory device, enlarging a portion indicated by C in FIG. 7. Note that a portion of FIG. 8 shows an XY cross section at a height position corresponding to a conductive layer 110 (WL) described later. Also, a portion of FIG. 8 shows a plan view omitting a bit line BL described later and an insulating layer 102 described later. Also, a portion of FIG. 8 illustrates a bit line BL described later. FIG. 9 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, showing a cross section of the structure shown in FIG. 7 taken along line DD′ and viewed in the direction of the arrow. FIG. 10 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, showing a cross section of the structure shown in FIG. 8 taken along line E-E' and viewed in the direction of the arrow. FIG. 11 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, showing an enlarged view of the portion indicated by F in FIG. 10. Note that although FIG. 11 shows a YZ cross section, a structure similar to that of FIG. 11 can also be observed when a cross section other than the YZ cross section (for example, an XZ cross section) along the central axis of a semiconductor pillar 120 (described later) is observed. FIG. 12 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device.

[0020] FIG. 13 is a schematic bottom view showing a partial configuration of the semiconductor memory device, and shows an enlarged view of the portion indicated by G in FIG. 6. FIG. 14 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 6 taken along line HH' and viewed in the direction of the arrow. FIG. 15 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 6 taken along line JJ' and viewed in the direction of the arrow. FIG. 16 is a schematic cross-sectional view showing a partial configuration of the semiconductor memory device, and shows a cross section of the structure shown in FIG. 13 taken along line KK' and viewed in the direction of the arrow.

[0021] As shown in Figure 5, the plane area R PN is two memory regions R aligned in the X direction. MH and these two memory regions R MH Two hook-up regions R arranged in the X direction between HU1 And these two hookup areas R HU1 Hook-up area R provided between HU2 The plane area R PN The configuration inside can be adjusted as needed. For example, the plain area R PN is the memory region R MH It is also possible to have only one hook-up region R HU1 ,R HU2 is the memory region R MH The second electrode 11 may be provided on one side in the X direction or on both sides in the X direction.

[0022] As shown in Figure 5, the plane area R PN has a plurality of finger structures FS arranged in the Y direction. Each finger structure FS has two memory regions R MH , 2 hookup areas R HU1 and hookup area R HU2 stretched in the X direction.

[0023] As shown in Fig. 7, each finger structure FS includes a plurality of string units SU arranged in the Y direction. An inter-finger structure ST is provided between two adjacent finger structures FS in the Y direction. Furthermore, as shown in Fig. 8, an inter-string unit insulating member SHE made of silicon oxide (SiO2) or the like is provided between two adjacent string units SU in the Y direction.

[0024] In this embodiment, one finger structure FS functions as one memory block. Each finger structure FS has five string units SU arranged in the Y direction. However, multiple finger structures FS may function as one memory block. A finger structure FS may have one to four string units SU, or six or more.

[0025] [Device Region R DV Memory area R in MH ] Device Region R DV Memory area R in MH 9, the finger structure FS includes a plurality of structures ML1, ML2, and ML3 (three in the illustrated example) aligned in the Z direction. A semiconductor layer 112 is provided above the plurality of structures ML1, ML2, and ML3. Furthermore, a plurality of bit lines BL are provided below the plurality of structures ML1, ML2, and ML3.

[0026] As shown in Figures 9 and 10, each of the multiple structures ML1, ML2, and ML3 includes multiple conductive layers 110 stacked in the Z direction, multiple semiconductor pillars 120 (sub-semiconductor pillars) extending in the Z direction, and a gate insulating film 130 provided between the multiple conductive layers 110 and the multiple semiconductor pillars 120.

[0027] The conductive layer 110 has a generally plate-like shape extending in the X direction. The conductive layer 110 may include a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The conductive layer 110 may also include polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). An insulating layer 101 such as silicon oxide (SiO2) is provided between the multiple conductive layers 110 arranged in the Z direction. As shown in FIG. 9, an insulating layer 102 such as silicon oxide (SiO2) is provided on the lower surface of each of the lowest conductive layers 110 in the structures ML1, ML2, and ML3.

[0028] Among the multiple conductive layers 110 included in the structure ML1 (FIG. 9), one or more uppermost conductive layers 110 function as source-side select gate lines of the NAND flash memory and gate electrodes of multiple select transistors connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110(SGS) (FIG. 10).

[0029] Among the multiple conductive layers 110 included in the structure ML3 (FIG. 9), one or more conductive layers 110 provided at the bottom function as select gate lines on the drain side of the NAND flash memory and the gate electrodes of multiple select transistors connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layer 110(SGD) (FIG. 10).

[0030] The remaining conductive layers 110 included in the structures ML1 and ML3 (FIG. 9) and the multiple conductive layers 110 included in the structure ML2 (FIG. 9) function as word lines of the NAND flash memory and gate electrodes of multiple memory cells connected thereto. In the following description, such conductive layers 110 may be referred to as conductive layers 110(WL) (FIG. 10).

[0031] The plurality of conductive layers 110 (SGS) and the plurality of conductive layers 110 (WL) are electrically independent for each finger structure FS. When focusing on two finger structures FS adjacent to each other in the Y direction, one or more conductive layers 110 (SGS) or multiple conductive layers 110 (WL) in these two finger structures FS and the multiple insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction by an inter-finger structure ST.

[0032] As shown in FIG. 8, the width Y of the conductive layer 110 (SGD) in the Y direction SGD is the width Y in the Y direction of the conductive layer 110 (WL). WL is smaller than.

[0033] The multiple conductive layers 110 (SGD) are electrically independent for each string unit SU. In each finger structure FS, when focusing on two string units SU adjacent to each other in the Y direction, one or more conductive layers 110 (SGD) in these two string units SU and the multiple insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction by an inter-string unit insulating member SHE. When focusing on the string unit SU closest to the other of the multiple string units SU included in one of two finger structures FS adjacent to each other in the Y direction, and the string unit SU closest to the one of the multiple string units SU included in the other finger structure FS, the one or more conductive layers 110 (SGD) in these two string units SU and the multiple insulating layers 101 provided on the upper and lower surfaces thereof are separated in the Y direction by an inter-finger structure ST.

[0034] The semiconductor pillars 120 are arranged in a predetermined pattern in the X and Y directions, as shown in Fig. 8. For example, the finger structure FS includes 24 semiconductor pillar arrays SC arranged from one side in the Y direction to the other side in the Y direction. Each of these 24 semiconductor pillar arrays SC includes a plurality of semiconductor pillars 120 arranged in the X direction.

[0035] The semiconductor pillar 120 includes, for example, polycrystalline silicon (Si) or the like. As shown in Fig. 10, the semiconductor pillar 120 has a substantially cylindrical shape, and an insulating pillar 125 made of, for example, silicon oxide (SiO2) is provided in the center. The semiconductor pillar 120 functions as the channel region of the memory cell and the select transistor.

[0036] An impurity region 121 (FIG. 10) is provided at the upper end of semiconductor pillar 120 included in structure ML1. The lower end of semiconductor pillar 120 included in structure ML1 is continuous with the upper end of semiconductor pillar 120 included in structure ML2. The lower end of semiconductor pillar 120 included in structure ML2 is continuous with the upper end of semiconductor pillar 120 included in structure ML3. An impurity region 122 (FIG. 10) is provided at the lower end of semiconductor pillar 120 included in structure ML3.

[0037] The outer diameter and cross-sectional area of ​​the bottom end of the semiconductor pillar 120 included in structure ML1 are larger than those of the top end of the semiconductor pillar 120 included in structure ML2, and the outer diameter and cross-sectional area of ​​the bottom end of the semiconductor pillar 120 included in structure ML2 are larger than those of the top end of the semiconductor pillar 120 included in structure ML3.

[0038] The impurity region 121 contains an N-type impurity such as phosphorus (P). The impurity region 121 has a substantially cylindrical shape. The impurity region 121 is connected to the semiconductor layer 112.

[0039] The impurity region 122 contains an N-type impurity such as phosphorus (P). The impurity region 122 has a substantially cylindrical shape. The impurity region 122 is connected to a via contact electrode Ch. The semiconductor pillar 120 is electrically connected to a bit line BL via the via contact electrodes Ch and Vy.

[0040] The gate insulating film 130 has a substantially cylindrical shape that covers the outer circumferential surface of the semiconductor pillar 120. The gate insulating film 130 includes a tunnel insulating film 131, a charge storage film 132, and a block insulating film 133 that are stacked between the semiconductor pillar 120 and the conductive layer 110, as shown in FIG. 11 , for example. The tunnel insulating film 131 and the block insulating film 133 include, for example, silicon oxide (SiO2) or the like. The charge storage film 132 includes, for example, a film capable of storing charges, such as silicon nitride (SiN). The tunnel insulating film 131, the charge storage film 132, and the block insulating film 133 have a substantially cylindrical shape and extend in the Z direction along the outer circumferential surface of the semiconductor pillar 120, excluding the contact portion between the semiconductor pillar 120 and the semiconductor layer 112, as shown in FIG. 10 , for example.

[0041] 11 shows an example in which the gate insulating film 130 includes a charge storage film 132 made of silicon nitride or the like. However, the charge storage film included in the gate insulating film 130 may be, for example, a floating gate made of polycrystalline silicon or the like containing N-type or P-type impurities.

[0042] The semiconductor layer 112 (FIG. 10) may include, for example, polycrystalline silicon containing N-type impurities such as phosphorus (P). A metal such as tungsten (W), a conductive material such as tungsten silicide, or other conductive materials may be provided on the upper surface of the semiconductor layer 112. The semiconductor layer 112 functions as a part of the source line of the NAND flash memory.

[0043] The inter-string unit insulating member SHE extends in the X and Z directions, for example, as shown in FIGS. 8 to 10. The inter-string unit insulating member SHE includes, for example, silicon oxide (SiO2) or the like. The upper end of the inter-string unit insulating member SHE is located below the upper surface of the conductive layer 110 (WL) located in the lowest layer. The upper end of the inter-string unit insulating member SHE is located above the upper surface of the conductive layer 110 (SGD) located in the highest layer. The lower end of the inter-string unit insulating member SHE is located below the lower surface of the conductive layer 110 (SGD) located in the lowest layer.

[0044] The inter-finger structure ST extends in the X and Z directions, as shown in FIGS. 8 to 10. The inter-finger structure ST includes an inter-finger insulating member 140 extending in the X and Z directions, and an inter-finger electrode 141 provided inside the inter-finger insulating member 140. The inter-finger insulating member 140 includes silicon oxide (SiO2) or the like. The inter-finger electrode 141 is spaced in the Y direction, via the inter-finger insulating member 140, from the plurality of conductive layers 110 arranged in the Z direction, the plurality of insulating layers 101 provided between them, and the insulating layer 102. The upper ends of the inter-finger insulating member 140 and the inter-finger electrode 141 are connected to the semiconductor layer 112. The inter-finger electrode 141 may be a conductive member including, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The inter-finger electrodes 141 may also be semiconductor materials such as polycrystalline silicon containing impurities such as phosphorus (P) or boron (B). The inter-finger electrodes 141 may include both conductive and semiconductor materials. The inter-finger electrodes 141 function as part of the source lines of the NAND flash memory.

[0045] 8, the via contact electrodes Ch are arranged in a predetermined pattern in the X and Y directions in correspondence with the semiconductor pillars 120. As shown in Fig. 10, the via contact electrodes Ch extend in the Z direction, and are connected at their upper ends to the impurity regions 122 of the semiconductor pillars 120 and at their lower ends to the via contact electrodes Vy.

[0046] 8, the bit lines BL extend in the Y direction and are aligned in the X direction. The pitch of the bit lines BL in the X direction is ¼ of the pitch of the semiconductor pillars 120 aligned in the X direction. The bit lines BL may include, for example, a stacked film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu). The above-mentioned via contact electrode Vy is provided at a position where the bit line BL and the via contact electrode Ch overlap when viewed from the Z direction.

[0047] 12, the plurality of bit lines BL are respectively connected to a plurality of wirings m1 provided below the plurality of bit lines BL, and a plurality of bonding electrodes P I1 , a plurality of bonded electrodes P I1 A plurality of adhesive electrodes P are provided below the I2 , a plurality of bonded electrodes P I2 The wafer W is connected to the substrate W through a plurality of wirings d4 and the like provided below the substrate W. P The semiconductor device is electrically connected to a transistor or other component (not shown) therein.

[0048] The plurality of wirings m1 and d4 may include, for example, a laminated film including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W) or copper (Cu).

[0049] Multiple bonded electrodes P I1 is a barrier conductive film p such as titanium nitride (TiN) I1B and metal films such as copper (Cu) I1M The laminated electrode P may include a laminated film of the above. I2 is a barrier conductive film p such as titanium nitride (TiN) I2Band metal films such as copper (Cu) I2M The film may include a laminated film of the above.

[0050] Here, the bonded electrode P I1 and laminated electrode P I2 In particular, metal films such as copper (Cu) I1M ,p I2M When using the metal film p I1M and metal film p I2M However, the bonded electrode P due to the misalignment of the bonding position is I1 and laminated electrode P I2 Distortion of the bonded shape, barrier conductive film p I1B ,p I2B The bonded structure can be confirmed by the positional misalignment (the occurrence of discontinuous areas on the side). I1 and adhesive electrode P I2 When the laminated electrode P is formed by the damascene method, each side surface has a tapered shape. I1 and laminated electrode P I2 The cross section of the bonded electrode P along the Z direction has a non-rectangular shape, with the side walls not being linear. I1 and laminated electrode P I2 When these are bonded together, the bottom, side, and top surfaces of each Cu that forms them are covered with barrier metal. In contrast, in a typical wiring layer using Cu, an insulating layer (such as SiN or SiCN) that functions to prevent oxidation of Cu is provided on the top surface of the Cu, and no barrier metal is provided. For this reason, it is possible to distinguish it from a typical wiring layer even if there is no misalignment in the bonding.

[0051] In addition, the bonded electrode P I1 ,P I2 The configuration of the memory area R MH In addition to hookup areas HU1 ,R HU2 Also, the laminated electrode P I1 ,P I2 The configuration of the device region R DV Not only in the middle but also in the edge area R ED It is also formed inside.

[0052] [Device Region R DV Hookup area in R HU1 ] Device Region R DV Hookup area in R HU1 As shown in FIG. 7, a plurality of terrace portions T corresponding to a plurality of conductive layers 110 (SGD) are provided in the memory region R. The terrace portion T is, for example, a portion of the lower surface of the conductive layer 110 that does not overlap with other conductive layers 110 when viewed from below. The terrace portion T of the conductive layer 110 (SGD) is provided at the end of the conductive layer 110 (SGD) in the X direction. In the example of FIG. 7, four terrace portions T corresponding to the first to fourth conductive layers 110 (SGD) counting from the bottom are provided in the memory region R. MH Hook-up area R from the side HU2 The terrace portions T are arranged in the X direction from the top to the bottom. The terrace portions T are covered with the insulating layer 102 described above.

[0053] Also, hook-up area R HU1 A plurality of via contact electrodes CC are provided in the insulating layer 102 corresponding to the plurality of terrace portions T. The via contact electrodes CC may include, for example, a stacked film including a barrier conductive film such as titanium nitride (TiN) and a metal film such as tungsten (W). The via contact electrodes CC extend in the Z direction through the insulating layer 102 and are connected at their upper ends to the terrace portions T of the conductive layer 110.

[0054] Also, hook-up area R HU1 A plurality of supporting insulating members HR are provided in the terrace portion T. The supporting insulating members HR include, for example, silicon oxide (SiO2). The supporting insulating members HR extend in the Z direction, penetrating the plurality of conductive layers 110 and the insulating layer 101. The outer periphery of each supporting insulating member HR is surrounded by a through-hole provided in the conductive layer 110. In the example of FIG. 7, one supporting insulating member HR is provided at each of the four corners of each terrace portion T.

[0055] [Device Region R DV Hookup area in R HU2 ] Hookup Area RHU2 As shown in FIG. 6, the memory cell 100 includes a plurality of conductive layers 110 (WL), a plurality of terrace portions T corresponding to one or more conductive layers 110 (SGS), and two memory regions R arranged in the X direction. MH and a connecting portion 111 that connects the conductive layer 110 between the hook-up region R in the X direction. HU2 The memory region R on one side in the X direction of the plurality of conductive layers 110(WL) and one or more conductive layers 110(SGS) extends from one end to the other end. MH The portion (hereinafter, sometimes referred to as the “electrode portion”) that faces the outer peripheral surface of the semiconductor pillar 120 and functions as a gate electrode of a memory cell or the like is connected to the memory region R MH The terrace portions T and the connection portions 111 are continuous with the portions (electrode portions) provided on the upper surface of the substrate 101. The plurality of terrace portions T and the connection portions 111 are covered with the insulating layer 102 described above.

[0056] In the example of FIG. 14, among the plurality of conductive layers 110 included in the structure ML1, 11 A plurality of terrace portions T (hereinafter referred to as "terrace portions T") corresponding to the terrace portions T 11 "). For example, the conductive layer 110 provided on the positive side of the X direction corresponds to the lower conductive layer 110, and the conductive layer 110 provided on the negative side of the X direction corresponds to the upper conductive layer 110. 11 A plurality of terrace portions T (hereinafter referred to as "terrace portions T") corresponding to the terrace portions T 12 For example, the conductive layer 110 provided on the negative side of the X direction corresponds to the lower conductive layer 110, and the conductive layer 110 provided on the positive side of the X direction corresponds to the upper conductive layer 110.

[0057] In the illustrated example, the structure ML1 is provided with a hole H1 penetrating a laminated structure made up of a plurality of conductive layers 110 and a plurality of insulating layers 101. A part of the hole H1 is formed on the terrace portion T 11 ,T 12The width of the hole H1 in the X direction is larger in the lower portion. A part of the insulating layer 102 is buried in the hole H1. Therefore, the insulating layer 102 in the structure ML1 contacts the semiconductor layer 112.

[0058] Furthermore, among the plurality of conductive layers 110 included in the structure ML2, 12 A plurality of terrace portions T (hereinafter referred to as "terrace portions T") corresponding to the terrace portions T 21 "). For example, the conductive layer 110 provided on the positive side of the X direction corresponds to the lower conductive layer 110, and the conductive layer 110 provided on the negative side of the X direction corresponds to the upper conductive layer 110. 12 A plurality of terrace portions T (hereinafter referred to as "terrace portions T") corresponding to the terrace portions T 22 For example, the conductive layer 110 provided on the negative side of the X direction corresponds to the lower conductive layer 110, and the conductive layer 110 provided on the positive side of the X direction corresponds to the upper conductive layer 110.

[0059] In the illustrated example, the structure ML2 is provided with a hole H2 penetrating a laminated structure made up of a plurality of conductive layers 110 and a plurality of insulating layers 101. A part of the hole H2 is formed on the terrace portion T 21 ,T 22 The width of the hole H2 in the X direction is larger in the lower portion. A part of the insulating layer 102 is buried in the hole H2. Therefore, the insulating layer 102 in the structure ML2 contacts the insulating layer 102 in the structure ML1.

[0060] In addition, among the plurality of conductive layers 110(WL) included in the structure ML3, 13 A plurality of terrace portions T (hereinafter referred to as "terrace portions T") corresponding to the terrace portions T 31 "). For example, the conductive layer 110(WL) provided on the positive side of the X direction corresponds to the lower conductive layer 110(WL), and the conductive layer 110(WL) provided on the negative side of the X direction corresponds to the upper conductive layer 110(WL). 13A plurality of terrace portions T (hereinafter referred to as "terrace portions T") corresponding to the terrace portions T 32 "). For example, the one provided on the negative side of the X direction corresponds to the lower conductive layer 110(WL), and the one provided on the positive side of the X direction corresponds to the upper conductive layer 110(WL).

[0061] In the illustrated example, the structure ML3 is provided with a hole H3 penetrating a laminated structure made up of a plurality of conductive layers 110 (WL) and a plurality of insulating layers 101. A part of the hole H3 is formed on the terrace portion T 31 ,T 32 The width of hole H3 in the X direction is larger in the lower portion. A part of insulating layer 102 is buried in hole H3. Therefore, insulating layer 102 in structure ML3 contacts insulating layer 102 in structure ML2.

[0062] Also, hook-up area R HU2 16, a plurality of via contact electrodes CC are provided in the insulating layer 102 corresponding to the plurality of terrace portions T. As illustrated in FIG. 16, the via contact electrodes CC extend in the Z direction through the insulating layer 102 and are connected at their upper ends to the terrace portions T of the conductive layer 110.

[0063] Also, hook-up area R HU2 A plurality of supporting insulating members HR are provided in the finger structure FS. As shown in FIG. 16, the supporting insulating members HR extend in the Z direction, penetrating the plurality of conductive layers 110 and insulating layers 101. The supporting insulating members HR are arranged in a predetermined pattern in the X and Y directions, as shown in FIG. 13, for example. For example, the finger structure FS includes eleven supporting insulating member rows HRR arranged from one side in the Y direction to the other side in the Y direction. Each of these eleven supporting insulating member rows HRR includes a plurality of supporting insulating members HR arranged in the X direction.

[0064] [Device Region R DV Plain area R PN [pause] FIG. 17 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to this embodiment, and shows a cross section of the configuration shown in FIG. 5 taken along line LL′ and viewed in the direction of the arrow.

[0065] As shown in Figure 17, the plane area R PN At the X-direction ends of the finger structures FS, an X-direction end of the semiconductor layer 112 is provided. A part of the insulating layer 102 is provided between the two finger structures FS aligned in the X direction. An insulating layer 103 is provided between the two semiconductor layers 112 aligned in the X direction.

[0066] [Device Region R DV Kerf area R K ] As explained with reference to Figure 4, the kerf region R KY is the laminate region R SS and the non-laminated region R SN And, it is equipped with.

[0067] Laminate area R SS In a part of the laminate region R, a plurality of conductive layers 110 and a plurality of insulating layers 101 are provided which are alternately stacked in the Z direction, as described with reference to FIG. SS In a part of the insulating layer 110, a plurality of insulating layers 110A and a plurality of insulating layers 101 are provided which are alternately stacked in the Z direction, as will be described later with reference to FIG.

[0068] 18 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment, and shows a cross section of the configuration shown in FIG. 5 taken along line MM′ and viewed in the direction of the arrow. As shown in FIG. 18, the non-laminated region R SN The non-laminated region R does not include the plurality of conductive layers 110, the plurality of insulating layers 110A, or the plurality of insulating layers 101. SN , an insulating layer 102 is provided at a height position corresponding to the structures ML1, ML2, and ML3. Also, an insulating layer 103 is provided at a height position corresponding to the semiconductor layer 112.

[0069] [Edge Area R ED ] As will be described later with reference to FIGS. 31 and 32, in the lithography process, the device region R DV and edge region R ED Therefore, a common pattern is transferred to the edge region R ED Die area R MD and kerf area R K is the device region R DV Die area R MD and kerf area R K However, as will be described later with reference to FIGS. 46 and 47, some etching processes may involve etching the edge region R ED This is performed while the edge region R is protected by the resist RG6. ED Die area R MD and kerf area R K is the device region R DV Die area R MD and kerf area R K It includes a different configuration.

[0070] Hereafter, the edge region R ED In the device region R DV The different configuration will be described below.

[0071] [Edge Area R ED (flat region R FL ) memory region R MH ] 19 is a schematic bottom view showing a partial configuration of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DV Die area R MD 20 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DVDie area R MD 21 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DV Die area R MD corresponds to the position in

[0072] As shown in Figure 19, the edge region R ED The structure FSA is provided at a position corresponding to the finger structure FS in the edge region R. ED is not provided with an inter-finger structure ST.

[0073] As shown in Fig. 20, the structure FSA includes a plurality of structures MLA1, MLA2, and MLA3 (three in the illustrated example) aligned in the Z direction. As shown in Fig. 21, above these multiple structures MLA1, MLA2, and MLA3, a semiconductor layer 112A such as silicon, an insulating layer 112B such as silicon oxide, an insulating layer 112C such as silicon nitride (SiN), an insulating layer 112D such as silicon oxide, and a semiconductor layer 112E such as silicon are provided in this order from top to bottom. Also, as shown in Fig. 20, a plurality of bit lines BL are provided below the multiple structures MLA1, MLA2, and MLA3.

[0074] The multiple structures MLA1, MLA2, and MLA3 each include, for example, as shown in FIG. 21, multiple insulating layers 110A stacked in the Z direction, multiple semiconductor pillars 120 extending in the Z direction, and a gate insulating film 130 provided between the multiple insulating layers 110A and the multiple semiconductor pillars 120.

[0075] The insulating layer 110A has a generally plate-like shape extending in the X direction. The insulating layer 110A may contain, for example, silicon nitride (SiN). The number of insulating layers 110A aligned in the Z direction in the structure FSA is equal to the number of conductive layers 110 aligned in the Z direction in the finger structure FS. An insulating layer 101 made of silicon oxide (SiO2) or the like is provided between the insulating layers 110A aligned in the Z direction. As shown in FIG. 20, an insulating layer 102 made of silicon oxide (SiO2) or the like is provided on the lower surface of each of the lowest insulating layers 110A in the structures MLA1, MLA2, and MLA3.

[0076] Here, as described above, the edge region R ED Therefore, among the multiple insulating layers 110A, those provided at height positions corresponding to the conductive layers 110(WL) and those provided at height positions corresponding to the conductive layers 110(SGS) are continuous in the X and Y directions across the multiple structures FSA.

[0077] As mentioned above, the device region R DV The edge region R includes two conductive layers 110 (SGD) adjacent to each other in the Y direction with an inter-finger structure ST interposed therebetween. ED The two insulating layers 110A provided at positions corresponding to these two conductive layers 110 (SGD) are continuous with each other.

[0078] As explained with reference to FIG. 10, the device region R DV 21, an impurity region 121 is provided at the top end of a semiconductor pillar 120 included in the structure ML1. ED In the structure MLA1, the impurity region 121 is not provided at the upper end of the semiconductor pillar 120. ED In the structure MLA1, the semiconductor pillar 120 included in the structure MLA1 is separated from the semiconductor layers 112A and 112E via the gate insulating film 130 and the insulating layers 112B, 112C, and 112D, and is insulated from these components.

[0079] [Edge Area RED (flat region R FL ) Hook-up area R HU1 ,R HU2 ] 22 is a schematic bottom view showing a partial configuration of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DV Die area R MD 23 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DV Die area R MD 24 is a schematic cross-sectional view showing a configuration of a part of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DV Die area R MD corresponds to the position in

[0080] Edge area R ED Hookup area in R HU1 ,R HU2 19 and 23, a plurality of terrace portions TA corresponding to the plurality of insulating layers 110A are provided on the insulating layer 110A. The terrace portions TA are, for example, portions of the lower surface of the insulating layer 110A provided at positions corresponding to the terrace portions T of the conductive layer 110 provided at the corresponding height positions, and are portions that do not overlap with at least one other insulating layer 110A when viewed from below. These plurality of terrace portions TA are covered with the insulating layer 102 described above.

[0081] where the device region R DV Hookup area in R HU1 ,R HU2 In this embodiment, a plurality of terrace portions T corresponding to all of the conductive layers 110 are provided in the edge region RED Hookup area in R HU1 ,R HU2 Only the terrace portion TA of a part of the insulating layer 110A is provided.

[0082] That is, in the structure MLA1, the height position Z 21 Approximately half of the insulating layers 110A provided below the height position Z each include a terrace portion TA. When viewed from below, these terrace portions TA do not overlap with other insulating layers 110A in the structure MLA1, but overlap with some of the insulating layers 110A in the structures MLA2 and MLA3. 21 The remaining insulating layers 110A, which are approximately half of the total number of insulating layers 110A provided above the insulating layer 102 in the structure MLA1, do not include the terrace portion TA. These remaining insulating layers 110A each extend in the X and Y directions above the insulating layer 102 in the structure MLA1.

[0083] In the illustrated example, the structure MLA1 has a hole HA1 that does not penetrate through a stacked structure made up of a plurality of insulating layers 110A and a plurality of insulating layers 101. A portion of the hole HA1 is made up of a terrace portion TA. A portion of the insulating layer 102 is buried in the hole HA1. The insulating layer 102 in the structure MLA1 does not contact the semiconductor layer 112.

[0084] Similarly, in the structure MLA2, at the height position Z 22 Approximately half of the insulating layers 110A provided below the height position Z each include a terrace portion TA. When viewed from below, these terrace portions TA do not overlap with other insulating layers 110A in the structure MLA2, but do overlap with some of the insulating layers 110A in the structure MLA3. 22 The remaining insulating layers 110A, which are approximately half of the total number of insulating layers 110A provided above the insulating layer 102 in the structure MLA2, do not include the terrace portion TA. These remaining insulating layers 110A each extend in the X and Y directions above the insulating layer 102 in the structure MLA2.

[0085] In the illustrated example, the structure MLA2 has a hole HA2 that does not penetrate through a stacked structure made up of a plurality of insulating layers 110A and a plurality of insulating layers 101. A portion of the hole HA2 is made up of a terrace portion TA. A portion of the insulating layer 102 is buried in the hole HA2. The insulating layer 102 in the structure MLA2 does not contact the insulating layer 102 in the structure MLA1.

[0086] Similarly, in structure MLA3, at height position Z 23 Approximately half of the insulating layers 110A provided below the height position Z each include a terrace portion TA. These terrace portions TA do not overlap with other insulating layers 110A when viewed from below. 23 The remaining insulating layers 110A, which are approximately half of the total number of insulating layers 110A provided above the insulating layer 102 in the structure MLA3, do not include the terrace portion TA. These remaining insulating layers 110A each extend in the X and Y directions above the insulating layer 102 in the structure MLA3.

[0087] In the illustrated example, the structure MLA3 has a hole HA3 that does not penetrate through a stacked structure made up of a plurality of insulating layers 110A and a plurality of insulating layers 101. A portion of the hole HA3 is made up of a terrace portion TA. A portion of the insulating layer 102 is buried in the hole HA3. The insulating layer 102 in the structure MLA3 does not contact another insulating layer 102 in the structure MLA3.

[0088] In FIG. 13, the region where the terrace portion T of the conductive layer 110 (WL) is provided is referred to as the terrace region R T The terrace region R shown in FIG. T In the edge region R, some of the conductive layers 110 (WL) arranged in the Z direction are provided, and other conductive layers 110 (WL) are not provided. ED In the terrace area R T Region R is provided at a position corresponding to TA The region R shown in FIG. TA Some of the insulating layers 110A arranged in the Z direction are provided on the upper surface of the substrate 110, and other insulating layers 110A are not provided.

[0089] As described with reference to FIGS. 14 and 15, the device region R DV Hookup Area R HU2 In the case of the edge region R, all of the conductive layers 110 (WL) arranged in the Z direction have terrace portions T. On the other hand, as described with reference to FIGS. ED Hookup Area R HU2 In this example, only about half of the insulating layers 110A arranged in the Z direction have terrace portions TA, and the remaining half do not have terrace portions TA.

[0090] In such a configuration, a predetermined region R TA In FIG. 22, the number of insulating layers 110A stacked in the Z direction is determined based on the number of insulating layers 110A in this predetermined region R TA The terrace area R is provided at a position corresponding to T 13, the number of the conductive layers 110 (WL) stacked in the Z direction is larger than the number of the conductive layers 110 (WL) stacked in the Z direction. Such a relationship is true for all the regions R1 included in the region R1 in FIG. TA and all the corresponding terrace areas R T This holds true for the following:

[0091] [Edge Area R ED (flat region R FL ) in the region R PNA [pause] 25 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment. ED Die area R MD The position in the device region R DV Die area R MD corresponds to the position in

[0092] Edge area R ED Die area R MD ,plane area R PN At the position corresponding to PNA Area R PNA includes a plurality of structures FSA instead of a plurality of finger structures FS and a plurality of inter-finger structures ST arranged alternately in the Y direction.

[0093] Here, as explained with reference to FIG. 17, the device region R DV In this case, two plane regions R adjacent in the X or Y direction are PN Between the edge region R, all the conductive layers 110 and the insulating layers 101 are divided in the X direction or the Y direction by the insulating layer 102. ED Then, two adjacent regions R in the X or Y direction PNA Between them, only a part of the insulating layer 110A and the insulating layer 101 is divided in the X direction or the Y direction via the insulating layer 102.

[0094] That is, in the structure MLA1, the height position Z 21 The insulating layers 110A, which are approximately half of the total number of layers, are located below the region R PNA On the other hand, the insulating layer 102 separates the structure MLA1 at a height position Z 21 The remaining half of the insulating layer 110A, which is provided above the region R, is located between two regions R adjacent in the X direction or Y direction. PNA and extend in the X and Y directions above the insulating layer 102 in the structure MLA1, respectively.

[0095] Similarly, in the structure MLA2, at the height position Z 22 The insulating layers 110A, which are approximately half of the total number of layers, are located below the region R PNA On the other hand, in the structure MLA2, the insulating layer 102 is interposed between the vertical position Z 22 The remaining half of the insulating layer 110A, which is provided above the region R, is located between two regions R adjacent in the X direction or Y direction. PNA and extend in the X and Y directions above the insulating layer 102 in the structure MLA2, respectively.

[0096] Similarly, in structure MLA3, at height position Z 23 The insulating layers 110A, which are approximately half of the total number of layers, are located below the region R PNAOn the other hand, in the structure MLA3, the insulating layer 102 is interposed between the vertical position Z 23 The remaining half of the insulating layer 110A, which is provided above the region R, is located between two regions R adjacent in the X direction or Y direction. PNA and extend in the X and Y directions above the insulating layer 102 in the structure MLA3, respectively.

[0097] [Edge Area R ED (flat region R FL ) in the kerf area R K ] 26 is a schematic cross-sectional view showing a part of the configuration of the semiconductor memory device according to this embodiment. ED Kerf area R K The position in the device region R DV Kerf area R K It corresponds to the position in the device region R DV Middle and edge area R ED Kerf area R K The location in, for example, the die region R MD It is possible to define the positional relationship between the

[0098] As mentioned above, the device region R DV Now, the kerf area R KY Non-laminated region R SN In the edge region R, the plurality of conductive layers 110 and the plurality of insulating layers 101 or the plurality of insulating layers 110A and the plurality of insulating layers 101 alternately stacked in the Z direction are not provided. ED Now, the kerf area R KY Non-laminated region R SN A plurality of insulating layers 110A and parts of a plurality of insulating layers 101 alternately stacked in the Z direction are provided on the insulating layer 110A.

[0099] That is, in the structure MLA1, the height position Z 21 Approximately half of the insulating layers 110A provided below the non-laminated region R SNThe insulating layer 110A is removed at a height position Z 21 The remaining half of the insulating layer 110A provided above the non-laminated region R SN and extend in the X and Y directions above the insulating layer 102 in the structure MLA1, respectively.

[0100] Similarly, in the structure MLA2, at the height position Z 22 Approximately half of the insulating layers 110A provided below the non-laminated region R SN The insulating layer 110A is removed at a height position Z 22 The remaining half of the insulating layer 110A provided above the non-laminated region R SN and extend in the X and Y directions above the insulating layer 102 in the structure MLA2, respectively.

[0101] Similarly, in structure MLA3, at height position Z 23 Approximately half of the insulating layers 110A provided below the non-laminated region R SN The insulating layer 110A is removed at a height position Z 23 The remaining half of the insulating layer 110A provided above the non-laminated region R SN and extend in the X and Y directions above the insulating layer 102 in the structure MLA3, respectively.

[0102] [Edge Area R ED Round area R RN ] FIG. 27 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to this embodiment.

[0103] Edge area R ED The flat region R FLIn the structures MLA1, MLA2, and MLA3, the semiconductor layer 112 is formed substantially flat along the XY plane and has a substantially uniform length in the Z direction. The insulating layers 110A and 101 in the structures MLA1, MLA2, and MLA3 are also formed substantially flat along the XY plane.

[0104] On the other hand, the edge region R ED The round area R RN In this case, the length of the semiconductor layer 112 in the Z direction is M That is, the upper surface of the semiconductor layer 112 is formed to be approximately flat along the XY plane, but the lower surface of the semiconductor layer 112 is formed to be approximately flat along the XY plane. M The insulating layer 110A and the insulating layer 101 in the structures MLA1, MLA2, and MLA3 are curved so as to approach the upper surface of the semiconductor layer 112 as they approach the outer edge of the structure. M The curved portion is closer to the top surface of the semiconductor layer 112 as it approaches the outer edge.

[0105] In this embodiment, the insulating layers 110A and 110B in the structures MLA1, MLA2, and MLA3 are formed in the round region R RN In the illustrated example, the outer edge of the semiconductor layer 112 is covered by the structure MLA1, the outer edge of the structure MLA1 is covered by the structure MLA2, and the outer edge of the structure MLA2 is covered by the structure MLA3.

[0106] [Manufacturing method] Next, a method for manufacturing the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 28 to 72. FIGS. 28, 57, 60, 61, and 64 to 66 are schematic cross-sectional views for explaining the manufacturing method, showing a configuration corresponding to FIG. 9. FIGS. 29, 54 to 56, and 67 to 72 are schematic cross-sectional views for explaining the manufacturing method, showing a configuration corresponding to FIG. 10. FIGS. 31 and 32 are schematic bottom views for explaining the manufacturing method, showing a configuration corresponding to FIG. 3. FIGS. 30, 33 to 39 are schematic cross-sectional views for explaining the manufacturing method. FIGS. 40, 42, 44, 48, 50, 52, 58, and 62 are schematic cross-sectional views for explaining the manufacturing method, showing a configuration corresponding to FIG. 14. Figures 41, 43, 45, 49, 51, 53, 59, and 63 are schematic cross-sectional views for explaining the manufacturing method, and show a configuration corresponding to Figure 15. Figures 46 and 47 are schematic perspective views for explaining the manufacturing method.

[0107] In manufacturing the semiconductor memory device according to this embodiment, for example, as shown in Figures 28 and 29, a semiconductor layer 112A, insulating layers 112B, 112C, 112D, and a semiconductor layer 112E are formed. Also, a plurality of insulating layers 101 and a plurality of insulating layers 110A are formed alternately. This process is performed by a method such as CVD (Chemical Vapor Deposition).

[0108] In this step, of the multiple insulating layers 101, those included in the structure ML1 (FIG. 9) and the structure MLA1 (FIG. 20) and the multiple insulating layers 110A corresponding to the conductive layer 110 in the structure ML1 and those included in the structure MLA1 are formed. Hereinafter, the configuration including these is referred to as the structure MLB1 (FIG. 28).

[0109] Next, as shown in Fig. 30, a resist RG1 is formed on the surface side of the structure described with reference to Fig. 28 and Fig. 29. This resist RG1 is, for example, HU2Some areas in the plain area R PN between, area R PNA Between and non-laminated regions R SN It exposes the inner structure and covers the other structures.

[0110] When forming the resist RG1, for example, a resist is applied, patterned by means of photolithography or the like, and a part of the resist is removed. In the photolithography, for example, as shown in FIGS. 31 and 32, a stepper or the like is used to remove the device region R DV and edge region R ED Wafer W including M In all regions in multiple die regions R MD In the illustrated example, the shot patterns SP are arranged in a total of eight die regions R, four in the X direction and two in the Y direction. MD It should be noted that Fig. 31 illustrates an example of the state after the tenth transfer has been performed, and Fig. 32 illustrates an example of the state after the eleventh transfer has been performed.

[0111] Next, the removal of the insulating layer 110A, the removal of the insulating layer 101, and the removal of a portion of the resist RG1 are repeated multiple times to form multiple terrace portions TA.

[0112] For example, as shown in Fig. 33, one layer of insulating layer 110A is selectively removed by means of dry etching or the like, and one layer of insulating layer 101 is selectively removed by means of dry etching or the like.

[0113] 34, a portion of the resist RG1 is isotropically removed to expose a portion of the surface of the insulating layer 110A that was covered with the resist RG1. This step is performed by, for example, dry etching or other means.

[0114] Next, as shown in Fig. 35, one layer of insulating layer 110A is selectively removed by means of dry etching or the like, and one layer of insulating layer 101 is selectively removed by means of dry etching or the like.

[0115] Thereafter, the resist RG1 is removed.

[0116] Next, as shown in Fig. 36, a resist RG2 is formed on the surface side of the structure described with reference to Fig. 35. This resist RG2 is, for example, HU2 Some areas in the plain area R PN between, area R PNA Between and non-laminated regions R SN It exposes the inner structure and covers the other structures.

[0117] When forming the resist RG2, for example, a resist is applied, patterned by means of photolithography or the like, and a part of the resist is removed. When performing photolithography, for example, a method such as that described with reference to FIGS. 31 and 32 is performed.

[0118] Next, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeated multiple times to form multiple terrace portions TA.

[0119] For example, in the example of FIG. 36, the hook-up region R HU2 In this case, a plurality of terrace portions TA corresponding to the three insulating layers 110A are formed in the insulating layer 101. In this case, a resist RG2 covers a portion of the plurality of terrace portions TA corresponding to each of the three insulating layers 110A, and exposes a portion of the plurality of terrace portions TA corresponding to each of the three insulating layers 110A. Also, as shown in FIG. 37, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeated three times. As a result, the hook-up region R HU2 A plurality of terrace portions TA and holes HA1 corresponding to the six insulating layers 110A are formed in the insulating layer 110. The insulating layers 110A and 101 are removed by, for example, dry etching or the like.

[0120] Thereafter, the resist RG2 is removed.

[0121] Next, as shown in Fig. 38, a resist RG3 is formed on the surface side of the structure described with reference to Fig. 37. This resist RG3 is, for example, HU2 Some areas in the plain area R PN between, area R PNA Between and non-laminated regions R SN It exposes the inner structure and covers the other structures.

[0122] When forming the resist RG3, for example, a resist is applied, patterned by means of photolithography or the like, and then a part of the resist is removed. When performing photolithography, for example, a method such as that described with reference to FIGS. 31 and 32 is performed.

[0123] Next, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeated multiple times to form multiple terrace portions TA.

[0124] For example, in the example of FIG. 38, the hook-up region R HU2 In this case, a plurality of terrace portions TA corresponding to the six insulating layers 110A are formed on the insulating layer 101. In this case, a resist RG3 covers a portion of the plurality of terrace portions TA corresponding to each of the six insulating layers 110A, thereby exposing a portion of the plurality of terrace portions TA corresponding to each of the six insulating layers 110A. As shown in FIG. 39, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeated six times each. This results in the formation of a plurality of terrace portions TA and holes HA1 corresponding to the twelve insulating layers 110A. The removal of the insulating layer 110A and the insulating layer 101 is performed by, for example, dry etching or other means.

[0125] Thereafter, the resist RG3 is removed.

[0126] Hereinafter, the steps described with reference to FIGS. 36 and 37 and steps similar to the steps described with reference to FIGS. 38 and 39 will each be referred to as a terrace portion forming step.

[0127] Similarly, the terrace portion forming step is carried out as appropriate thereafter to further form a plurality of terrace portions TA corresponding to the plurality of insulating layers 110A and holes HA1.

[0128] For example, as shown in Figures 40 and 41, a resist RG4 is formed on the surface side of the structure MLB1. This resist RG4 is, for example, HU2 Some areas in the plain area R PN between, area R PNA Between and non-laminated regions R SN It exposes the inner structure and covers the other structures.

[0129] Next, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeated multiple times to form multiple terrace portions TA.

[0130] For example, in the examples of FIGS. 40 and 41, the hook-up region R HU2 In this case, a plurality of terrace portions TA corresponding to approximately one-quarter of the insulating layers 110A in the structure MLB1 are formed. In this case, resist RG4 covers a portion of the plurality of terrace portions TA corresponding to each of these approximately one-quarter of the insulating layers 110A, thereby exposing a portion of the plurality of terrace portions TA corresponding to each of these approximately one-quarter of the insulating layers 110A. As shown in FIGS. 42 and 43, the removal of the insulating layers 110A and the removal of the insulating layers 101 are repeated the same number of times as the number of approximately one-quarter of the insulating layers 110A. This results in the formation of a plurality of terrace portions TA and holes HA1 corresponding to approximately half of the insulating layers 110A in the structure MLB1. The removal of the insulating layers 110A and the insulating layers 101 is performed by, for example, dry etching or other means.

[0131] Thereafter, the resist RG4 is removed.

[0132] 44 and 45, a resist RG5 is formed on the surface side of the structure MLB1. This resist RG5 is, for example, HU2 Some areas in the plain area R PN between, area R PNA Between and non-laminated regions R SN It exposes the inner structure and covers the other structures.

[0133] Here, in the final terrace portion forming process corresponding to the structure MLB1, as shown in FIGS. 46 and 47, the edge region R ED When forming the resist RG6, for example, as shown in FIG. M While rotating the wafer W, and the resist is being discharged from the nozzle NZ, the nozzle NZ is M Next, the nozzle NZ is moved in a direction approaching the rotation axis of the edge region R. ED Resist RG6 is applied to the device region R DV The resist RG6 is stopped for a certain period of time at a position where the resist RG6 is not applied to the edge region R. ED Next, as shown in FIG. 47, the nozzle NZ is moved to the wafer W. M Move it away from the axis of rotation.

[0134] Next, as shown in FIGS. 48 and 49, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeated multiple times to form multiple terrace portions TA.

[0135] For example, in the examples of FIGS. 44 and 45, the hook-up region R HU2In this case, a plurality of terrace portions TA corresponding to about half of the insulating layers 110A are formed in the insulating layer 101. In this case, a resist RG5 covers a part of the plurality of terrace portions TA corresponding to each of these about half of the insulating layers 110A, and a part of the plurality of terrace portions TA corresponding to each of these about half of the insulating layers 110A is exposed. Also, as shown in FIGS. 48 and 49, the removal of the insulating layer 110A and the removal of the insulating layer 101 are repeatedly carried out the same number of times as the number of the about half of the insulating layers 110A. As a result, the hook-up region R HU2 In this way, a plurality of terrace portions TA and holes H1 corresponding to all of the insulating layers 110A in the structure MLB1 are formed. The insulating layers 110A and 101 are removed by, for example, dry etching or other means.

[0136] In this process, the edge region R ED The structure in the edge region R is protected by the resist RG6. ED So, hookup area R HU2 , region R PNA Between and non-laminated regions R SN The structure remains as it is after the terrace portion forming step, which is executed second to last.

[0137] Thereafter, the resist RG5 is removed.

[0138] 50 and 51, an insulating layer 102 is formed on the surface side of the structure shown in FIGS. 48 and 49. This process is performed by, for example, CVD. The insulating layer 102 is formed on the hook-up region R HU2 The insulating layer 102 is embedded in the holes H1 and HA1 and covers the terraces TA. PN between, area R PNA Between and non-laminated regions R SN It is also formed inside.

[0139] 52 and 53, the structure shown in Figures 50 and 51 is subjected to a planarization process to remove part of the insulating layer 102. This process is performed by, for example, CMP (Chemical Mechanical Polishing) or the like.

[0140] 54, resists 151, 152, 153, 154, and 155 are formed on the surface side of the insulating layer 102. Next, patterning is performed by means of photolithography or the like to remove parts of the resists 151, 152, 153, 154, and 155. For photolithography, a method such as that described with reference to FIGS.

[0141] Next, as shown in FIG. 55, a plurality of memory holes MH are formed at positions corresponding to the plurality of semiconductor pillars 120 described with reference to FIGS. 8 to 10. Furthermore, although not shown, a plurality of via holes are formed at positions corresponding to the plurality of support insulating members HR described with reference to FIGS. 7, 13, etc. These memory holes MH and via holes each extend in the Z direction and penetrate insulating layer 102, insulating layer 101, insulating layer 110A, semiconductor layer 112E, and insulating layers 112D, 112C, and 112B to expose the top surface of semiconductor layer 112A. This step is performed by, for example, a method such as RIE (Reactive Ion Etching) using resists 151, 152, 153, 154, and 155 as a mask.

[0142] Next, as shown in Fig. 56, the semiconductor layers 112A and 112E are selectively oxidized inside the memory holes MH and via holes. Also, sacrificial pillars 120A made of silicon (Si) or the like are formed inside the memory holes MH and via holes. This process is performed by, for example, CVD or the like.

[0143] Next, as shown in Fig. 57, for example, structure MLB2 is formed on the surface side of structure MLB1. Structure MLB2 includes, among the multiple insulating layers 101, those included in structure ML2 (Fig. 9) and structure MLA2 (Fig. 20), as well as, among the multiple insulating layers 110A, those corresponding to conductive layer 110 in structure ML2 and those included in structure MLA2.

[0144] Next, steps similar to those described with reference to FIGS. 30 to 53 are carried out to form a plurality of terrace portions TA corresponding to the plurality of insulating layers 110A included in the structure MLB2, as shown in FIGS.

[0145] In this process, the edge region R ED So, hookup area R HU2 , region R PNA Between and non-laminated regions R SN The structure remains as it is after the second-to-last terrace portion forming step corresponding to the structure MLB2 is performed.

[0146] Next, steps substantially similar to those described with reference to Figures 54 to 56 are performed to form sacrificial pillars 120A of silicon (Si) or the like, as shown in Figure 60. Note that in the step described with reference to Figure 56, oxidation treatment corresponding to the semiconductor layer 112A and the semiconductor layer 112E is performed, but in the step corresponding to Figure 60, oxidation treatment corresponding thereto is not performed.

[0147] Next, as shown in Fig. 61, for example, structure MLB3 is formed on the surface side of structure MLB2. Structure MLB3 includes, among the multiple insulating layers 101, those included in structure ML3 (Fig. 9) and structure MLA3 (Fig. 20), as well as, among the multiple insulating layers 110A, those corresponding to conductive layer 110 in structure ML3 and those included in structure MLA3.

[0148] Next, steps similar to those described with reference to FIGS. 30 to 53 are performed to form a plurality of terrace portions TA corresponding to the plurality of insulating layers 110A included in the structure MLB3, as shown in FIGS.

[0149] In this process, the edge region R ED So, hookup area R HU2 , region R PNA Between and non-laminated regions R SN The structure remains as it is after the second-to-last terrace portion forming step corresponding to the structure MLB3 is performed.

[0150] Next, steps substantially similar to those described with reference to FIGS. 54 and 55 are carried out to form via holes corresponding to the plurality of memory holes MH and the supporting insulating members HR, as shown in FIG.

[0151] Next, as shown in Fig. 65, the sacrificial pillars 120A in the structures MLA1 and MLA2 are removed. This step is performed by, for example, wet etching or the like.

[0152] 66 and 67, the gate insulating film 130, the semiconductor pillars 120, and the insulating pillars 125 are formed inside the memory holes MH. This process is performed by, for example, CVD or the like.

[0153] Furthermore, although not shown in the drawings, the supporting insulating members HR are formed inside the plurality of via holes corresponding to the plurality of supporting insulating members HR. This step is performed by, for example, CVD or the like.

[0154] Next, as shown in Fig. 68, an insulating layer 102 is further formed. This step is performed by a method such as CVD.

[0155] Furthermore, grooves STA are formed at positions corresponding to the inter-finger structures ST. The grooves STA extend in the Z and X directions, dividing the insulating layers 102, 101, 110A, the semiconductor layer 112E, and the insulating layer 112D in the Y direction, and exposing the top surface of the insulating layer 112C. This step is performed by a method such as RIE, for example.

[0156] In forming the groove STA, as described with reference to FIGS. 46 and 47, the edge region RED Therefore, the trench STA is formed in the device region R DV formed only in the edge region R ED is not formed.

[0157] Next, as shown in FIG. 69, the semiconductor layer 112 is formed. In this step, the insulating layers 112B, 112C, and 112D are removed by a method such as wet etching. Also, a portion of the gate insulating film 130 is removed by a method such as wet etching to expose a portion of the outer circumferential surface of the semiconductor pillar 120. Also, the semiconductor layer 112 is formed by a method such as epitaxial growth.

[0158] As described above, the groove STA is formed in the edge region R ED Therefore, the edge region R ED In this case, the semiconductor layer 112 is not formed, and the semiconductor layer 112A, the insulating layers 112B, 112C, 112D, and the semiconductor layer 112E remain.

[0159] Next, as shown in FIG. 70, the insulating layer 110A is removed through the trench STA. This forms a plurality of voids 110B aligned in the Z direction. In other words, a hollow structure is formed that includes a plurality of insulating layers 101 aligned in the Z direction and a structure that supports the insulating layers 101. MH In the hook-up region R, the insulating layer 101 is supported by the structure in the memory hole MH (the semiconductor pillar 120, the gate insulating film 130, and the insulating pillar 125). HU1 ,R HU2 In this step, the insulating layer 101 is supported by the supporting insulating members HR. This step is performed by, for example, wet etching or the like.

[0160] As described above, the groove STA is formed in the edge region R ED Therefore, the edge region R ED In this case, the insulating layer 110A is not removed and the void 110B is not formed.

[0161] Next, a plurality of conductive layers 110 are formed in the plurality of gaps 110B aligned in the Z direction, as shown in Fig. 71. This step is performed by a method such as CVD.

[0162] Next, an inter-finger structure ST is formed inside the trench STA as shown in Fig. 72. This step is performed by, for example, CVD or the like.

[0163] Thereafter, the via contact electrodes CC described with reference to FIGS. 7 and 13, the via contact electrodes Ch and Vy and the bit line BL described with reference to FIGS. 8 to 10, and the pasted electrode P described with reference to FIG. I2 etc. to form a wafer W M The structure in the wafer W is formed. M and wafer W P By bonding these together, the semiconductor memory device according to the first embodiment is formed.

[0164] [Comparative Example] 73 to 76 are schematic cross-sectional views for explaining a semiconductor memory device according to a comparative example, which show a substrate Sub.

[0165] In manufacturing the semiconductor memory device according to the comparative example, the steps described with reference to FIGS. 46 and 47 are not performed when forming the plurality of terrace portions TA corresponding to the insulating layer 110A in the structures MLB1, MLB2, and MLB3.

[0166] Therefore, in the comparative example, after the steps described with reference to FIGS. 48 and 49 are performed, the edge region R ED Even hookup area R HU2 In the region R, a plurality of terrace portions TA and holes H1 corresponding to all the insulating layers 110A in the structure MLB1 are formed. PNA Between the non-laminated body regions R, all the insulating layers 110A are divided in the X and Y directions. SN In step 1, all of the insulating layer 110A is removed.

[0167] Also, in the steps corresponding to FIGS. 58 and 59, the edge region RED Hookup area in R HU2 In the region R, a plurality of terrace portions TA and holes H2 corresponding to all the insulating layers 110A in the structure MLB2 are formed. PNA Between the non-laminated body regions R, all the insulating layers 110A are divided in the X and Y directions. SN In step 1, all of the insulating layer 110A is removed.

[0168] Also, in the steps corresponding to FIGS. 62 and 63, the edge region R ED Hookup area in R HU2 In the region R, a plurality of terrace portions TA and holes H3 corresponding to all the insulating layers 110A in the structure MLB3 are formed. PNA Between the non-laminated body regions R, all the insulating layers 110A are divided in the X and Y directions. SN In step 1, all of the insulating layer 110A is removed.

[0169] 50 and 51, the hole H1 is filled with the insulating layer 102. In this process, depending on the characteristics of a film forming apparatus such as CVD, the edge region R ED The embedding in the device region R DV 73, a void V may be formed in the hole H1, which may cause cracks or the like.

[0170] 51, if irregularities are formed on the upper surface of the insulating layer 102, the irregularities will be distorted into a rounded region R as shown in FIG. 74 after the planarization process described with reference to FIGS. 52 and 53 is performed. RN If resists 151, 152, 153, 154, and 155 are formed in such uneven portions in the process described with reference to Fig. 54, a portion of the resists 151, 152, 153, 154, and 155 will become thin at the corners, as shown in Fig. 75. If the process described with reference to Fig. 55 is carried out in this state, erroneous formation may occur, as shown in Fig. 76.

[0171] [Effects of the first embodiment] 77 to 79 are schematic cross-sectional views for explaining the semiconductor memory device according to the first embodiment. In Fig. 77 to Fig. 79, a substrate Sub is shown.

[0172] In this embodiment, in the step described with reference to FIGS. 48 and 49 (the step of forming the terrace portion corresponding to the structure MLB1, which is executed last), the edge region R ED The structure in the edge region R is protected by the resist RG6. ED So, hookup area R HU2 , region R PNA Between and non-laminated regions R SN The structure of the edge region R remains as it is after the second-to-last terrace portion forming process corresponding to the structure MLB2. As a result, as shown in FIG. ED Since a relatively shallow hole HA1 is formed in the insulating layer 102, it becomes relatively easy to form the insulating layer 102 without generating a void V.

[0173] In addition, the edge region R ED 78, a relatively shallow hole HA1 is formed in the rounded region R after the flattening process described with reference to FIGS. 52 and 53 is performed. RN 79, it is possible to form resists 151, 152, 153, 154, and 155 relatively uniformly, thereby making it possible to prevent the above-mentioned erroneous formation from occurring.

[0174] [Second embodiment] In the first embodiment, in the terrace portion forming process corresponding to the structure MLB1, the edge region R ED On the other hand, in the terrace portion forming process corresponding to the structure MLB1, from the first to the second to last, the edge region R EDThe inner structure is not protected by the resist RG6. The same applies to the terrace portion forming process corresponding to the structure MLB2 and the structure MLB3.

[0175] However, such a method is merely an example, and in any terrace portion forming step, the edge region R ED Whether the internal configuration is protected can be adjusted as appropriate.

[0176] 36 to 45, 48, and 49, among the terrace portion forming steps corresponding to structure MLB1, the later the step is performed, the more insulating layers 110A and 101 are removed, resulting in a deeper hole HA1. Furthermore, in order to reduce the number of manufacturing steps, it is preferable to perform the step described with reference to FIGS. 46 and 47 (the step of applying resist RG6) fewer times. For these reasons, the manufacturing method according to the first embodiment makes it possible to efficiently make the hole HA1 filled with insulating layer 102 shallower while minimizing the number of times the step of applying resist RG6 is performed.

[0177] However, depending on the depth and width in the Y direction of the hole HA1, the embedding property of the insulating layer 102, etc., it may be preferable to apply the resist RG6 not only in the last terrace portion forming step corresponding to the structure MLB1, but also in the penultimate terrace portion forming step and other terrace portion forming steps. It is also possible to apply the resist RG6 in all terrace portion forming steps.

[0178] Hereinafter, an example of a semiconductor memory device manufactured by executing the steps of applying resist RG6 in all terrace portion forming steps will be described as the semiconductor memory device according to the second embodiment. In the following description, parts similar to those in the first embodiment will be given the same reference numerals and will not be described again.

[0179] The semiconductor memory device according to the second embodiment is basically formed in the same manner as the semiconductor memory device according to the first embodiment. However, the edge region R EDThe configuration in the edge region R ED The configuration is different from that in

[0180] Figures 80 to 83 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the second embodiment, each showing a cross section corresponding to Figures 23 to 26.

[0181] As described above, in the manufacturing process of the semiconductor memory device according to the second embodiment, a step of applying the resist RG6 is performed in all terrace portion forming steps. ED So, hookup area R HU2 , region R PNA Between and non-laminated regions R SN The structure of the hook-up region R remains the same as it was before the terrace portion forming step was performed. HU2 Although a plurality of terrace portions TA as shown in FIG. 35 are provided in the substrate 1, no hole portions HA1 are formed.

[0182] [Third embodiment] As described with reference to FIG. 27, in the first embodiment, the insulating layers 110A and 101 in the structures MLA1, MLA2, and MLA3 are formed in the round region R RN However, this configuration is merely an example, and the specific configuration can be adjusted as appropriate. For example, in the steps described with reference to FIGS. 30 to 35 and the terrace portion forming step, the round region R RN In addition, the insulating layers 110A and 101 in the structures MLA1, MLA2, and MLA3 may be removed in the vicinity thereof. Hereinafter, such a process will be referred to as edge cutting.

[0183] Hereinafter, an example in which edge cutting is performed in the terrace portion forming process etc. will be described as a semiconductor memory device according to the third embodiment. In the following description, the same parts as those in the first embodiment will be given the same reference numerals, and description thereof will be omitted.

[0184] 84 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor memory device according to the third embodiment. The semiconductor memory device according to the third embodiment is basically configured in the same way as the semiconductor memory device according to the first embodiment.

[0185] However, in the third embodiment, as shown in FIG. 84, the insulating layers 110A and 101 in the structures MLA1, MLA2, and MLA3 are formed in the round region R RN In addition, the edge region R according to the third embodiment does not reach ED is the flat region R FL and the round area R RN The edge cut area R EC Edge cut area R EC In the structure MLA1, MLA2, MLA3, the insulating layers 110A and 101 of the wafer W M An outer edge portion is provided.

[0186] [Fourth embodiment] As described with reference to FIGS. 46 and 47, in the first embodiment, the edge region R ED However, this method is merely an example, and the edge region R ED The method for protecting the structure inside can be adjusted as appropriate. For example, a resist such as the resist RG5 described with reference to FIGS. 44 and 45 may be used to protect the edge region R ED The internal structure may be protected.

[0187] Hereinafter, using resist RG5, edge region R ED An example of protecting the internal configuration will be described as a semiconductor memory device according to the fourth embodiment. In the following description, the same parts as those in the first embodiment will be denoted by the same reference numerals, and description thereof will be omitted.

[0188] Fig. 85 is a schematic perspective view for explaining the manufacturing method according to the fourth embodiment, and Fig. 86 is a schematic cross-sectional view for explaining the same manufacturing method.

[0189] The manufacturing method according to the fourth embodiment is basically carried out in the same manner as the manufacturing method according to the first embodiment.

[0190] However, in the manufacturing method according to the fourth embodiment, the method of forming the resist RG5 described with reference to Figures 44 and 45 is different from that of the first embodiment. That is, the resist RG5 is formed by, for example, forming a resist RG5 on the wafer W as shown in Figure 85. M While rotating, the wafer W M Apply to the center of the

[0191] Here, in the first embodiment, the wafer W M The wafer W is rotated at a relatively high speed. M Resist RG5 is applied on top to a relatively uniform thickness.

[0192] On the other hand, in the fourth embodiment, the wafer W M For example, the wafer W is rotated at a relatively slow speed. M As shown in FIG. 86, the edge region R of the resist RG5 ED The film thickness in the device region R DV The film is rotated at a speed such that the thickness of the film is sufficiently larger than that of the film at the time of rotation.

[0193] Subsequently, patterning is performed by means of photolithography or the like, and part of the resist is removed.

[0194] In the first embodiment, the resist RG5 has a relatively uniform film thickness, so that the resist RG5 is M The entire surface is removed in accordance with the shot pattern SP (FIGS. 31 and 32).

[0195] On the other hand, in the fourth embodiment, the edge region R of the resist RG5 ED The film thickness in the device region R DV Therefore, the thickness of the edge region R ED In this case, only the surface of the resist RG5 is exposed, and the edge region R EDTherefore, in the method according to the fourth embodiment, the resist RG5, which is applied in the terrace portion forming step, is used to remove the resist from the edge region R. ED It is possible to protect the internal structure.

[0196] This method can be used for applying resist for any terrace forming step.

[0197] Furthermore, in the fourth embodiment, the steps described with reference to Figures 46 and 47 are not performed, so the number of manufacturing steps can be reduced.

[0198] [Fifth embodiment] In the first embodiment, the steps of forming the structures MLB1, MLB2, and MLB3 and the terrace portion forming step are performed multiple times alternately. That is, the structure MLB1 is formed as described with reference to FIGS. 28 and 29, and the terrace portion forming step is performed multiple times as described with reference to FIGS. 36 to 53. Furthermore, the structure MLB2 is formed as described with reference to FIG. 57, and the terrace portion forming step is performed multiple times as described with reference to FIGS. 58 and 59. Furthermore, the structure MLB3 is formed as described with reference to FIG. 61, and the terrace portion forming step is performed multiple times as described with reference to FIGS. 62 and 63.

[0199] However, this method is merely an example, and after forming the plurality of structures MLB1, MLB2, MLB3, the terrace portion forming steps corresponding to these plurality of structures MLB1, MLB2, MLB3 may be performed all at once.

[0200] Hereinafter, an example of a semiconductor memory device manufactured by forming all of the structures MLB1, MLB2, and MLB3 and then simultaneously performing multiple terrace portion formation processes corresponding to all of these structures MLB1, MLB2, and MLB3 will be described as the semiconductor memory device of the fifth embodiment.

[0201] 28 and 29 are performed, the steps described with reference to FIGS. 30 to 53 are not performed, the steps described with reference to FIGS. 54 to 57 are performed, and the steps described with reference to FIGS. 58 and 59 are not performed, but the steps described with reference to FIGS. 60 and 61 are performed. Next, the steps described with reference to FIGS. 30 to 35 are performed, and multiple terrace portion formation steps corresponding to all of the structures MLB1, MLB2, and MLB3 are performed. After that, the steps from the step described with reference to FIG. 64 onwards are performed.

[0202] Among the multiple terrace portion forming steps corresponding to all of the above structures MLB1, MLB2, and MLB3, in which terrace portion forming step is the edge region R ED In the following description, the edge region R is protected in the last of the multiple terrace portion forming steps corresponding to all the structures MLB1, MLB2, and MLB3. ED An example in which the internal structure is protected by a resist RG6 will be described.

[0203] The semiconductor memory device according to the fifth embodiment is basically formed in the same manner as the semiconductor memory device according to the first embodiment. However, the edge region R ED The configuration in the edge region R ED The configuration is different from that in

[0204] Figures 87 to 90 are schematic cross-sectional views showing the configuration of a portion of the semiconductor memory device according to the fifth embodiment. Figures 87 to 90 show cross sections of portions corresponding to Figures 23 to 26, respectively. In the following explanation, the same parts as in the first embodiment are given the same reference numerals, and explanations thereof will be omitted.

[0205] As shown in FIGS. 87 and 88, the edge region R ED Hookup area in R HU2In the example shown, all of the insulating layers 110A in structure MLB3 and approximately half of the insulating layers 110A in structure MLB2 that are located below height position Z3 each include a terrace portion TA. These terrace portions TA do not overlap with other insulating layers 110A when viewed from below. Meanwhile, approximately half of the remaining insulating layers 110A in structure MLB2 that are located above height position Z3 and all of the insulating layers 110A in structure MLB1 do not include a terrace portion TA. These insulating layers 110A extend in the X and Y directions above the insulating layers 102 in structures MLB2 and MLB3, respectively.

[0206] In the illustrated example, the structure MLB3 has a hole HA4 that penetrates the laminated structure made up of a plurality of insulating layers 110A and a plurality of insulating layers 101. The structure MLB2 has a hole HA2 that does not penetrate the laminated structure made up of a plurality of insulating layers 110A and a plurality of insulating layers 101. The structure MLB1 does not have a hole HA1 (FIG. 23). A portion of the hole HA4 is formed from a terrace portion TA. A portion of the insulating layer 102 is buried in the hole HA4.

[0207] As shown in FIG. 89, the edge region R ED Region R PNA Between them, all the insulating layers 110A in the structure MLB3 and about half of the insulating layers 110A provided below the height position Z3 in the structure MLB2 are located between two regions R adjacent in the X direction or Y direction. PNA On the other hand, in the structure MLB2, about half of the insulating layers 110A provided above the height position Z3, and all of the insulating layers 110A in the structure MLB1, are separated by the insulating layer 102 between two regions R adjacent in the X direction or the Y direction. PNA and extend in the X and Y directions above the insulating layer 102 in the structures MLB2 and MLB3, respectively.

[0208] That is, in this embodiment, the structure MLB3 is formed by two regions R adjacent to each other in the X direction or the Y direction. PNAIn addition, the structure MLB1 does not include a continuous insulating layer 110A between two regions R adjacent in the X direction or the Y direction. PNA The insulating layer 110A does not include the insulating layer 102 separating the two.

[0209] As shown in FIG. 90, the edge region R ED Non-laminated region R SN In this case, all the insulating layers 110A in the structure MLB3 and about half of the insulating layers 110A provided below the height position Z3 in the structure MLB2 are located in the non-laminated body region R SN The insulating layer 102 is provided in the region where the insulating layer 110A has been removed. On the other hand, about half of the insulating layers 110A provided above the height position Z3 in the structure MLB2 and all of the insulating layers 110A in the structure MLB1 are provided in the non-laminated region R SN 1 and extend in the X and Y directions above the insulating layer 102 in structures MLB2 and MLB3, respectively.

[0210] [Other embodiments] The semiconductor memory devices according to the first to fifth embodiments have been described above. However, the configurations shown above are merely examples, and the specific configurations can be adjusted as appropriate.

[0211] For example, in the above embodiment, as described above, the device region R DV Multiple die regions in R MD In the device region R, a plurality of conductive layers 110 and a plurality of insulating layers 101 are provided, which are arranged alternately in the Z direction. DV Laminate region R SS , and the edge region R ED Multiple die regions in R MD , laminate area R SS , non-laminate region R SN etc. (hereinafter referred to as "edge region R ED Multiple die regions in R MD The insulating layer 110A and the insulating layer 101 are provided in the insulating layer 110B, which are alternately arranged in the Z direction.

[0212] 70, a plurality of insulating layers 110A aligned in the Z direction are removed to form a plurality of voids 110B aligned in the Z direction. Also, in the process described with reference to FIG. 71, a plurality of conductive layers 110 aligned in the Z direction are formed in the plurality of voids 110B aligned in the Z direction. Therefore, the device region R DV Multiple die regions in R MD a plurality of conductive layers 110 arranged in the Z direction in the edge region R ED Multiple die regions in R MD In the above, a plurality of layers (hereinafter referred to as "first layers") arranged in the Z direction corresponding to the plurality of conductive layers 110 contain different materials.

[0213] On the other hand, in the above embodiment, the insulating layers 101 arranged in the Z direction are not removed to form the voids arranged in the Z direction, and the other layers arranged in the Z direction are not formed in the voids. DV Multiple die regions in R MD In the edge region R, a plurality of insulating layers 101 are arranged in the Z direction. ED Multiple die regions in R MD In the above, a plurality of layers (hereinafter referred to as "second layers") arranged in the Z direction corresponding to the plurality of insulating layers 101 contain the same material.

[0214] However, this configuration is merely an example and can be modified as appropriate. For example, the first layer may contain the same material as the conductive layer 110. The second layer may contain a material different from that of the insulating layer 101. The conductive layer 110 may contain, for example, a metal oxide film around a barrier conductive film. DV Multiple die regions in R MD In the figure, the insulating layers 101 and the conductive layers 110 arranged alternately in the Z direction may be considered to be a configuration including such a metal oxide film.

[0215] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0216] 101...insulating layer, 110...conductive layer, 110A...insulating layer, 120...semiconductor pillar, 130...gate insulating film, 131...tunnel insulating film, 132...charge storage film, 133...block insulating film, CC...via contact electrode, FS...finger structure, H1, H2, H3, HA1, HA2, HA3...hole, ML1, ML2, ML3, MLA1, MLA2, MLA3...structure, R DV …device region, R ED …edge region, R MD …die area, R K …kerf area, R MH …memory area, R HU1 ,R HU2 …Hookup area, R T …Terrace region, ST…Inter-finger structure, T, TA…Terrace section, W M ,W P ...Wafer.

Claims

1. a first wafer including a plurality of die regions aligned in a first direction and a second direction intersecting the first direction; a plurality of conductive layers and a plurality of insulating layers provided in a device region on the first wafer outside a range of a predetermined distance from an outer edge of the first wafer, the conductive layers and the insulating layers being alternately stacked in a stacking direction intersecting the first direction and the second direction; a plurality of first layers provided in an edge region on the first wafer within the predetermined distance from the outer edge of the first wafer, the first layers being aligned in the stacking direction in correspondence with the plurality of conductive layers, and a plurality of second layers being aligned in the stacking direction in correspondence with the plurality of insulating layers; a plurality of first die regions located within the device region among the plurality of die regions each include a terrace region in which some of the plurality of conductive layers are provided and other parts are not provided, In a region where a plurality of second die regions among the plurality of die regions overlap with the edge region as viewed in the stacking direction, the number of the plurality of first layers provided side by side in the stacking direction at positions in the plurality of second die regions corresponding to positions including at least a portion of the terrace region, respectively, is greater than the number of the plurality of conductive layers provided side by side in the stacking direction at the positions including at least a portion of the terrace region. Semiconductor device.

2. The plurality of first die regions include: a first semiconductor pillar and a second semiconductor pillar spaced apart in the first direction, extending in the stacking direction, and facing the plurality of conductive layers, respectively; a first charge storage film provided between the plurality of conductive layers and the first semiconductor pillar; a second charge storage film provided between the plurality of conductive layers and the second semiconductor pillar; Equipped with At least some of the plurality of conductive layers are a first electrode portion facing the first semiconductor pillar; a second electrode portion facing the second semiconductor pillar; a terrace portion provided in the terrace region between the first electrode portion and the second electrode portion; a connection portion that is arranged between the first electrode portion and the second electrode portion and is aligned with the terrace portion in the second direction, and that connects the first electrode portion and the second electrode portion; The semiconductor device according to claim 1 , comprising:

3. a first structure and a second structure aligned in the stacking direction are provided in the device region; the first structure includes: some of the plurality of conductive layers and some of the plurality of insulating layers alternately stacked in the stacking direction; and a first sub-semiconductor pillar extending in the stacking direction and facing the some of the plurality of conductive layers; the second structure includes other parts of the plurality of conductive layers and other parts of the plurality of insulating layers alternately stacked in the stacking direction, and a second sub-semiconductor pillar extending in the stacking direction, facing the other parts of the plurality of conductive layers, and electrically connected to the first sub-semiconductor pillar; a third structure including a portion of the plurality of first layers corresponding to the portion of the plurality of conductive layers and a portion of the plurality of second layers corresponding to the portion of the plurality of insulating layers; a fourth structure including another portion of the plurality of first layers corresponding to the other portion of the plurality of conductive layers, and another portion of the plurality of second layers corresponding to the other portion of the plurality of insulating layers; is provided in the edge region, the terrace portions of the part of the plurality of conductive layers provided in the terrace region and the other part of the plurality of conductive layers do not overlap any of the plurality of conductive layers when viewed from one side in the stacking direction, The terrace portions of the part of the first layers provided at the positions in the second die regions overlap with any of the other parts of the first layers when viewed from the one side in the stacking direction. The semiconductor device according to claim 1.

4. a first structure and a second structure aligned in the stacking direction are provided in the device region; the first structure includes: some of the plurality of conductive layers and some of the plurality of insulating layers alternately stacked in the stacking direction; and a first sub-semiconductor pillar extending in the stacking direction and facing the some of the plurality of conductive layers; the second structure includes other parts of the plurality of conductive layers and other parts of the plurality of insulating layers alternately stacked in the stacking direction, and a second sub-semiconductor pillar extending in the stacking direction, facing the other parts of the plurality of conductive layers, and electrically connected to the first sub-semiconductor pillar; a third structure including a portion of the plurality of first layers corresponding to the portion of the plurality of conductive layers and a portion of the plurality of second layers corresponding to the portion of the plurality of insulating layers; a fourth structure including another portion of the plurality of first layers corresponding to the other portion of the plurality of conductive layers, and another portion of the plurality of second layers corresponding to the other portion of the plurality of insulating layers; is provided in the edge region, the terrace portions of the part of the plurality of conductive layers provided in the terrace region and the other part of the plurality of conductive layers do not overlap any of the plurality of conductive layers when viewed from one side in the stacking direction, The terrace portions of the parts of the first layers provided at the positions in the second die regions and the other parts of the first layers do not overlap any of the first layers when viewed from the one side in the stacking direction. The semiconductor device according to claim 1.

5. a first wafer including a plurality of die regions aligned in a first direction and a second direction intersecting the first direction; a plurality of conductive layers and a plurality of insulating layers provided in a device region on the first wafer outside a range of a predetermined distance from an outer edge of the first wafer, the conductive layers and the insulating layers being alternately stacked in a stacking direction intersecting the first direction and the second direction; a plurality of first layers provided in an edge region on the first wafer within the predetermined distance from the outer edge of the first wafer, the first layers being aligned in the stacking direction in correspondence with the plurality of conductive layers, and a plurality of second layers being aligned in the stacking direction in correspondence with the plurality of insulating layers; a plurality of first die regions located within the device region among the plurality of die regions include a first plane region and a second plane region, each of the first plane region and the second plane region including a plurality of finger structures and a plurality of inter-finger structures that are aligned in the first direction or the second direction and alternately aligned in the second direction, and a source line that is provided at a position that overlaps the plurality of finger structures and the plurality of inter-finger structures when viewed from the stacking direction; each of the plurality of finger structures includes the plurality of conductive layers, the plurality of insulating layers, and a plurality of semiconductor pillars extending in the stacking direction, facing the plurality of conductive layers, and commonly connected to the source line; the plurality of conductive layers, the plurality of insulating layers, and the source line are divided in the first direction or the second direction between the first plane region and the second plane region; When positions in the second die regions corresponding to positions where the first die regions include the first plane region and the second plane region are defined as first regions and second regions, respectively, within a region where the second die regions overlap with the edge region as viewed in the stacking direction, among the plurality of die regions, the first region and the second region each include the plurality of first layers and the plurality of second layers; At least a portion of the first layers and the second layers are continuous between the first region and the second region. Semiconductor device.

Images