Semiconductor device and semiconductor storage device

Abstract

To provide a semiconductor device and a semiconductor storage device capable of manufacturing a high quality semiconductor device.SOLUTION: A semiconductor device includes: a gate electrode extending in a first direction; an oxide semiconductor extending in a vertical direction intersecting the first direction and penetrating the gate electrode; a first electrode connected to a first lower end of the oxide semiconductor; a second electrode connected to a first upper end of the oxide semiconductor; and a first insulating film including a gate upper film portion covering an upper surface of the gate electrode, a gate lower film portion covering a lower surface of the gate electrode, and a gate insulating film portion covering a first surface of the gate electrode facing the oxide semiconductor and formed of a first insulating material.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device and a semiconductor memory device. [Background technology]

[0002] Some semiconductor elements use metal oxides containing indium and tin for electrodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] US Patent Application Publication US2022 / 0285350 Summary of the Invention [Problem to be solved by the invention]

[0004] In the manufacturing process of semiconductor elements in which metal oxides are used for electrodes, there is a demand for technology for manufacturing high-quality semiconductor devices.

[0005] An object of the present disclosure is to provide a semiconductor device and a semiconductor memory device that can be manufactured with high quality. [Means for solving the problem]

[0006] The semiconductor device according to the present disclosure comprises a gate electrode formed to extend in a first direction, an oxide semiconductor formed to extend in a vertical direction intersecting the first direction and penetrating the gate electrode, a first electrode connected to a first lower end of the oxide semiconductor, a second electrode connected to a first upper end of the oxide semiconductor, a gate upper film portion covering an upper surface of the gate electrode, a gate lower film portion covering a lower surface of the gate electrode, and a first insulating film formed of a first insulating material.

[0007] The semiconductor device according to the present disclosure comprises a first oxide semiconductor extending in a vertical direction, a first interlayer insulating film extending along a plane parallel to a direction intersecting the vertical direction and through which the first oxide semiconductor passes, a first electrode containing oxygen, indium, and tin, a first film formed of a semiconductor or a conductor and provided between the first oxide semiconductor and the first electrode, electrically connected to the first oxide semiconductor and the first electrode, and a gate electrode facing the first oxide semiconductor via a gate insulating film, wherein the first film contains atoms whose bond energy with oxygen atoms is greater than the bond energy between oxygen atoms and indium atoms in the first electrode.

[0008] The semiconductor memory device according to the present disclosure comprises the semiconductor device, a first capacitor electrode connected to the first electrode, a second capacitor electrode facing the first capacitor electrode, and a dielectric film provided between the first capacitor electrode and the second capacitor electrode. [Brief explanation of the drawings]

[0009] [Figure 1] 2 is a circuit diagram for explaining an example of a circuit configuration of a memory cell array according to the first embodiment. FIG. [Figure 2] FIG. 2 is a cross-sectional view illustrating a structural example of the semiconductor memory device according to the first embodiment, taken along a line parallel to the ZX plane. [Figure 3] 1 is a cross-sectional view illustrating a structural example of a semiconductor device according to a first embodiment, taken along a line parallel to the ZX plane of the semiconductor device; [Figure 4] 1 is a cross-sectional view illustrating a structural example of a semiconductor device according to a first embodiment, taken along a line parallel to a YZ plane of the semiconductor device; [Figure 5] FIG. 5 is a cross-sectional view taken along line VV shown in FIGS. 3 and 4. [Figure 6] 3 is a cross-sectional view illustrating a structural example in the vicinity of a word line contact in the semiconductor device according to the first embodiment, showing a cross-sectional view parallel to the YZ plane of the semiconductor device. FIG. [Figure 7]2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 8] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 9] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 10] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view taken along the line XI-XI shown in FIGS. 9 and 10. [Figure 12] 3A to 3C are cross-sectional views parallel to the YZ plane showing the manufacturing process in the vicinity of a word line contact in the semiconductor device of the first embodiment. [Figure 13] 3A to 3C are cross-sectional views parallel to the YZ plane showing the manufacturing process in the vicinity of a word line contact in the semiconductor device of the first embodiment. [Figure 14] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 15] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views parallel to the YZ plane showing the manufacturing process in the vicinity of a word line contact in the semiconductor device of the first embodiment. [Figure 17] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 18] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 19] 3A to 3C are cross-sectional views parallel to the YZ plane showing the manufacturing process in the vicinity of a word line contact in the semiconductor device of the first embodiment. [Figure 20] 3A to 3C are cross-sectional views parallel to the YZ plane showing the manufacturing process in the vicinity of a word line contact in the semiconductor device of the first embodiment. [Figure 21] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 22] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 23] 23 is a cross-sectional view taken along the line XXIII-XXIII shown in FIGS. 21 and 22. FIG. [Figure 24] 3A to 3C are cross-sectional views parallel to the YZ plane showing the manufacturing process in the vicinity of a word line contact in the semiconductor device of the first embodiment. [Figure 25] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 26] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 27] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 28] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 29] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 30] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 31] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 32] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 33] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 34] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 35] FIG. 35 is a cross-sectional view taken along the line XXXV-XXXV shown in FIGS. 33 and 34. [Figure 36] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 37] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 38] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 39] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 40] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 41] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 42] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 43] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 44] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 45] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 46] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 47] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 48] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 49] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 50] 2A to 2C are cross-sectional views parallel to the ZX plane showing the manufacturing process of the semiconductor device of the first embodiment. [Figure 51] 2A to 2C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the first embodiment. [Figure 52] 10A to 10C are cross-sectional views parallel to the ZX plane showing a manufacturing process of a semiconductor device of a comparative example. [Figure 53]FIG. 10 is a cross-sectional view illustrating a structural example of a semiconductor device according to a second embodiment, taken along a line parallel to the YZ plane of the semiconductor device. [Figure 54] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 55] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 56] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 57] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 58] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 59] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 60] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 61] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 62] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 63] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. [Figure 64] 10A to 10C are cross-sectional views parallel to the YZ plane showing the manufacturing process of the semiconductor device according to the second embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. To facilitate understanding of the description, the same components in the drawings will be denoted by the same reference numerals as much as possible, and duplicated descriptions will be omitted.

[0011] [First embodiment] The configuration of a semiconductor memory device according to a first embodiment will be described. Each drawing may show an X-axis, a Y-axis, and a Z-axis. The X-axis, Y-axis, and Z-axis form a right-handed, three-dimensional Cartesian coordinate system. Hereinafter, the direction of the X-axis arrow may be referred to as the X-axis + direction, and the direction opposite to the arrow may be referred to as the X-axis - direction. The same applies to the other axes. The Z-axis + direction and the Z-axis - direction may be referred to as "upper" and "lower," respectively. Furthermore, planes perpendicular to the X-axis, Y-axis, or Z-axis may be referred to as the YZ plane, ZX plane, or XY plane. Furthermore, the Z-axis direction may be referred to as the "vertical direction." "Upward," "downward," and "vertical direction" merely indicate relative positional relationships within the drawings, and do not define orientations relative to the vertical direction.

[0012] In addition, unless otherwise specifically explained, the dimensions of the components shown in each drawing may be shown differently from the actual dimensions in order to make the explanation easier to understand.

[0013] In this specification, the term "connection" includes not only physical connection but also electrical connection, and unless otherwise specified, includes not only direct connection but also indirect connection.

[0014] In this specification, "formed above" does not only mean forming in contact with the upper part, but also includes forming above via another object unless otherwise specified. The same applies to "formed below" and the like.

[0015] The semiconductor memory device 101 according to the first embodiment is an OS-RAM (Oxide Semiconductor-Random Access Memory) and includes a memory cell array.

[0016] As shown in FIG. 1, the memory cell array includes a plurality of memory cells MC, a plurality of word lines WL, and a plurality of bit lines BL.

[0017] FIG. 1 shows a word line WL as an example of a plurality of word lines WL. n , word line WL n+1 and word line WL n+2(where n is a positive integer). Also, in FIG. 1, as an example of the bit line BL, m , bit line BL m+1 and bit line BL m+2 (where m is a positive integer). Note that the number of memory cells MC is not limited to the number shown in FIG.

[0018] A plurality of memory cells MC are arranged in a matrix to form a memory cell array, for example. Each memory cell MC includes a memory transistor MTR, which is a field effect transistor (FET), and a memory capacitor MCP.

[0019] A series of memory cells MC arranged along the row direction are connected to a word line WL (for example, word line WL) corresponding to the row to which they belong (for example, the nth row). n A series of memory cells MC arranged in the column direction are connected to a bit line BL (for example, bit line BL m+2 ) is connected.

[0020] Specifically, the gate of the memory transistor MTR included in the memory cell MC is connected to the word line WL corresponding to the row to which the memory cell MC belongs, and one of the source and drain of the memory transistor MTR is connected to the bit line BL corresponding to the column to which the memory cell MC belongs.

[0021] One electrode of a memory capacitor MCP included in a memory cell MC is connected to the other of the source or drain of a memory transistor MTR included in the memory cell MC, and the other electrode of the memory cell MC is connected to a power supply line (not shown) that supplies a specific potential.

[0022] The memory cell MC is configured to be able to hold data by storing charge in the memory capacitor MCP due to a current flowing through the corresponding bit line BL when the memory transistor MTR is switched based on the potential of the corresponding word line WL.

[0023] As shown in FIG. 2, the semiconductor memory device 101 includes a semiconductor substrate 10, a circuit 11 (an example of a "semiconductor circuit"), a capacitor 20, a semiconductor device 30, a conductor 33, and insulating layers 34, 35, and 63.

[0024] Capacitor 20 includes conductor 21, insulating film 22 (an example of a "dielectric film"), conductor 23, capacitor electrode 24 (an example of a "first capacitor electrode"), and capacitor electrode 25 (an example of a "second capacitor electrode").

[0025] The semiconductor device 30 includes a field effect transistor 40 (an example of a "semiconductor element"), an upper electrode 50 (an example of a "second electrode") provided above the field effect transistor 40, and a lower electrode 32 (an example of a "first electrode") provided below the field effect transistor 40.

[0026] The field effect transistor 40 includes an oxide semiconductor layer 70 (an example of an "oxide semiconductor" and a "first oxide semiconductor"), a gate insulating film 43, a conductive layer 42 (an example of a "gate electrode"), and an insulating layer 45.

[0027] The oxide semiconductor layer 70 is formed in the insulating layer 45 and has an upper end 70a (an example of a "first upper end") and a lower end 70b (an example of a "first lower end"). The oxide semiconductor layer 70 is a columnar body extending in the positive direction of the Z axis from the lower end 70b toward the upper end 70a. The oxide semiconductor layer 70 forms the channel of the field-effect transistor 40, and the oxide semiconductor layer 70 has an amorphous structure.

[0028] The conductive layer 42 faces the oxide semiconductor layer 70 via the gate insulating film 43. Specifically, the conductive layer 42 functions as a gate electrode of the field-effect transistor 40, and surrounds the oxide semiconductor layer 70 between an upper end 70a and a lower end 70b of the oxide semiconductor layer 70 via the gate insulating film 43. The conductive layer 42 contains, for example, tungsten (W).

[0029] The gate insulating film 43 includes, for example, a silicon nitride film (Si3N4) containing silicon and nitrogen.

[0030] The upper electrode 50 is formed in the positive Z-axis direction relative to the oxide semiconductor layer 70, and is connected to an upper end 70a of the oxide semiconductor layer 70. The upper electrode 50 includes a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c.

[0031] The metal film 50c contains tungsten. The metal oxide layer 50a is formed between the metal film 50c and the upper end 70a of the oxide semiconductor layer 70 and contains a metal oxide. The metal oxide contains, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin-oxide (ITO).

[0032] The barrier metal layer 50b contains titanium and nitrogen and is formed between the metal oxide layer 50a and the metal film 50c. In this embodiment, the barrier metal layer 50b is made of, for example, titanium nitride (TiN).

[0033] The lower electrode 32 is connected to the lower end 70b of the oxide semiconductor layer 70. The lower electrode 32 contains a metal oxide. Specifically, the lower electrode 32 contains, for example, indium and tin as metal elements. In this embodiment, the metal oxide layer 50a is formed of indium-tin-oxide (ITO).

[0034] The lower electrode 32 is not limited to ITO, and may be made of at least one of indium, tin, zinc, cadmium, gold, silver, platinum, lead, copper, nickel, tungsten, and iron.

[0035] The circuit 11 constitutes peripheral circuits such as a decoder for selecting a predetermined memory cell MC from among the multiple memory cells MC, i.e., capacitors 20 and field effect transistors 40, of the semiconductor memory device 101, a sense amplifier connected to the bit line BL, and a register constituted by an SRAM. The circuit 11 may include a CMOS circuit having field effect transistors, such as a P-channel field effect transistor (Pch-FET) and an N-channel field effect transistor (Nch-FET), formed by a CMOS process.

[0036] The field-effect transistors of the circuit 11 can be formed using a semiconductor substrate 10 such as a single-crystal silicon substrate. The Pch-FET and Nch-FET are so-called lateral field-effect transistors that have a channel region, a source region, and a drain region in the semiconductor substrate 10 and have a channel for flowing carriers in the X-axis direction or the Y-axis direction substantially parallel to the surface of the semiconductor substrate 10 in a region close to the surface of the semiconductor substrate 10. The semiconductor substrate 10 may have a conductivity type of P-type or N-type. For convenience, FIG. 2 illustrates an example of a field-effect transistor of the circuit 11.

[0037] The capacitor 20 is a memory capacitor MCP included in the memory cell MC (see FIG. 1). Although four capacitors 20 are shown in FIG. 2, the number of capacitors 20 is not limited to four.

[0038] In this embodiment, the capacitor 20 is provided above the semiconductor substrate 10. The capacitor electrode 24 of the capacitor 20 is connected to the conductor 21 and the lower electrode 32. The capacitor electrode 25 faces the capacitor electrode 24. The insulating film 22 is provided between the capacitor electrode 24 and the capacitor electrode 25.

[0039] The capacitor 20 is a three-dimensional capacitor such as a pillar-type capacitor. Note that other capacitors having a configuration capable of storing electric charge may also be used as the capacitor of this embodiment.

[0040] The capacitor electrode 24 is located below the lower electrode 32. The capacitor electrode 24 has an upper end that faces the lower end face of the lower electrode 32 via the conductor 21, and has a columnar shape that extends downward from the upper end. The conductor 21 is formed so as to cover the lower electrode 32 and the capacitor electrode 24. The insulating film 22 is formed so as to cover the conductor 21. The capacitor electrode 25 surrounds a lower portion of the insulating film 22, and has a lower end that abuts against the upper end face of the conductor 23.

[0041] The capacitor electrode 24 may include a material containing silicon and germanium, such as SiGe. The insulating film 22 may include a material containing zirconium, aluminum, and oxygen, such as ZrAlO. The conductor 21 may include a material containing nitrogen and titanium, such as titanium nitride. The conductor 23 and the capacitor electrode 25 may include a material containing tungsten and titanium nitride.

[0042] The conductor 33 includes wiring that electrically connects the circuit 11 and the semiconductor device 30. The conductor 33 may include via wiring, and for example, as shown in FIG. 2, the conductor 33 has via wiring that extends in the Z-axis direction and connects the word line WL and the circuit 11 provided on the semiconductor substrate 10. The conductor 33 includes, for example, copper.

[0043] The insulating layer 34 is provided between the plurality of capacitors 20. The insulating layer 34 is, for example, a silicon oxide film containing silicon and oxygen.

[0044] The insulating layer 35 is provided above the insulating layer 34. The insulating layer 35 is, for example, a silicon nitride film containing silicon and nitrogen.

[0045] The semiconductor device 30 is provided above the capacitor 20. A field effect transistor 40 in the semiconductor device 30 corresponds to the memory transistor MTR of the memory cell MC (see FIG. 1).

[0046] In the semiconductor device 30, the field-effect transistor 40 is provided above the lower electrode 32. Specifically, the oxide semiconductor layer 70 of the field-effect transistor 40 is located above the lower electrode 32, in a direction away from the semiconductor substrate 10.

[0047] The upper electrode 50 is located in a direction away from the semiconductor substrate 10, i.e., above the oxide semiconductor layer 70. With this configuration, the field-effect transistor 40 is a so-called vertical transistor, which has a channel extending in the Z-axis direction (up-down direction) that is approximately perpendicular to the surface of the semiconductor substrate 10.

[0048] The oxide semiconductor layer 70 is a semiconductor in which oxygen vacancies serve as donors, and contains indium (In), zinc (Zn), and gallium (Ga) as metal elements. Specifically, the oxide semiconductor layer 70 is an oxide of indium, gallium, and zinc, i.e., IGZO (InGaZnO). Note that the oxide semiconductor layer 70 may be made of other types of oxide semiconductors.

[0049] Fig. 3 shows a cross-sectional view of the semiconductor device 30 taken along a cross-section 70ZX parallel to the ZX plane and included in the oxide semiconductor layer 70. Fig. 4 shows a cross-sectional view of the semiconductor device 30 taken along a cross-section 70YZ parallel to the YZ plane and included in the oxide semiconductor layer 70. Fig. 5 is a cross-sectional view taken along the cutting line VV shown in Figs. 3 and 4.

[0050] 3 to 5, compared to the semiconductor device 30 shown in Fig. 2, the semiconductor device 30 includes an insulating film 321 (an example of a "first insulating film") instead of the gate insulating film 43, and further includes a spacer film 311 (an example of a "third insulating film"). The insulating layer 45 includes insulating films 45a, 45b (an example of a "fourth insulating film" and a "first interlayer insulating film"), and 45c (an example of a "second insulating film").

[0051] The plurality of conductive layers 42 are repeatedly provided in the X-axis direction (an example of a "second direction"). The plurality of oxide semiconductor layers 70 are arranged two-dimensionally. That is, some of the plurality of oxide semiconductor layers 70 are repeatedly provided along the Y-axis direction (an example of a "first direction"). Furthermore, other parts of the plurality of oxide semiconductor layers 70 are repeatedly provided along the positive X-axis direction.

[0052] The conductive layer 42 is made of a first conductive material. In this embodiment, the conductive layer 42 contains tungsten. The conductive layer 42 may contain other elements.

[0053] The conductive layer 42 extends along the Y-axis direction. In detail, the conductive layer 42 includes a surrounding portion 42b that surrounds the oxide semiconductor layer 70 and a connecting portion 42c that connects the two surrounding portions 42b.

[0054] A hole 405 extending in the vertical direction is formed in the surrounding portion 42b of the conductive layer 42. The oxide semiconductor layer 70 passes through the hole 405.

[0055] When the conductive layer 42 is viewed from above, the width of the connecting portion 42c in the X-axis direction is narrower than the width of the surrounding portion 42b in the X-axis direction.

[0056] The insulating film 321 is made of a first insulating material. The first insulating material contains silicon and nitrogen. In this embodiment, the insulating film 321 is a nitride of silicon. Note that the insulating film 321 may also be an oxide of silicon, an oxide of hafnium, an oxide of aluminum, or the like.

[0057] The insulating film 321 includes a gate upper film portion 321a, a gate lower film portion 321b, and a gate insulating film portion 321c.

[0058] The gate upper film portion 321a covers an upper surface 42d of the conductive layer 42. The gate lower film portion 321b covers a lower surface 42e of the conductive layer 42.

[0059] The gate insulating film portion 321c covers the first surface of the conductive layer 42 facing the oxide semiconductor layer 70. In this embodiment, the gate insulating film portion 321c covers the inner wall surface 405b of the hole 405. The gate insulating film portion 321c contacts the oxide semiconductor layer 70 and surrounds the entire periphery of a central portion of the oxide semiconductor layer 70 that is away from the upper end 70a and the lower end 70b.

[0060] The gate upper film portion 321a, the gate lower film portion 321b, and the gate insulating film portion 321c are integrally formed, that is, the composition of each element in the gate upper film portion 321a, the gate lower film portion 321b, and the gate insulating film portion 321c is approximately the same.

[0061] The conductive layer 42 has a side surface 42f having a normal in the X-axis direction. The side surface 42f is not covered with the insulating film 321 and is in contact with the insulating film 45c.

[0062] The insulating film 45c is made of, for example, a second insulating material different from the first insulating material, and in this embodiment, the insulating film 45c is an oxide of silicon.

[0063] The spacer film 311 (an example of a "third insulating film") is formed of a third insulating material different from the first insulating material. The oxygen permeability of the first insulating material is lower than that of the third insulating material. In this embodiment, the spacer film 311 is, for example, an oxide of silicon.

[0064] The spacer film 311 has a hole 401 (an example of a "first hole") extending in the vertical direction, through which the oxide semiconductor layer 70 penetrates and contacts, and is provided above the gate upper film portion 321a.

[0065] Specifically, the spacer film 311 includes a cylindrical portion 311a and a plate-like portion 311b. The cylindrical portion 311a is provided above the surrounding portion 42b of the conductive layer 42 via a gate upper film portion 321a, and extends substantially parallel to the Z axis.

[0066] The cylindrical portion 311a has a hole 401. The lower end of the cylindrical portion 311a forms an annular surface that contacts the gate upper film portion 321a. An inner wall surface 401b of the hole 401 contacts the oxide semiconductor layer 70 and surrounds an upper portion of the oxide semiconductor layer 70 over the entire periphery. The plate-like portion 311b is provided above the connecting portion 42c of the conductive layer 42 via the gate upper film portion 321a, and extends along a plane that is approximately parallel to the XY plane.

[0067] The insulating film 45a is provided above the plate-shaped portion 311b. The insulating film 45a is made of, for example, an oxide of silicon.

[0068] The insulating film 45b is made of a fourth insulating material different from the first insulating material. The oxygen permeability of the first insulating material is lower than that of the fourth insulating film. In this embodiment, the insulating film 45b is made of, for example, an oxide of silicon.

[0069] The insulating film 45b has a hole 403 (an example of a "third hole") extending in the vertical direction, through which the oxide semiconductor layer 70 passes and contacts, formed therein, and is provided below the gate lower film portion 321b. An inner wall surface 403b of the hole 403 contacts the oxide semiconductor layer 70 and surrounds a lower portion of the oxide semiconductor layer 70 over the entire periphery.

[0070] The insulating film 45c separates two conductive layers 42 adjacent in the X-axis direction. Specifically, the insulating film 45c is located between two conductive layers 42 adjacent in the X-axis direction and extends substantially parallel to the Y-axis.

[0071] An upper end of the insulating film 45c is connected to the lower surface of the insulating film 45a. The lower part of the insulating film 45c is buried in the insulating film 45b. In this embodiment, the insulating films 45a and 45c are integrally formed.

[0072] FIG. 6 shows a cross-sectional view of the semiconductor device 30 near the word line contact when viewed at a cross-section 70YZ parallel to the YZ plane and included in the oxide semiconductor layer 70.

[0073] 6, the semiconductor device 30 further includes a via electrode 270. The via electrode 270 is formed of a first conductive material. That is, the via electrode 270 includes tungsten.

[0074] The via electrode 270 is formed in the insulating layer 45 and has an upper end 270a (an example of a "second upper end") and a lower end 270b (an example of a "second lower end"). The via electrode 270 is a columnar body extending in the positive direction of the Z axis from the lower end 270b toward the upper end 270a.

[0075] The via electrode 270 is electrically connected to the conductive layer 42. In this embodiment, the via electrode 270 penetrates the conductive layer 42. Note that the via electrode 270 may not penetrate the conductive layer 42.

[0076] The spacer film 311 further has a hole 402 (an example of a "second hole") extending in the vertical direction, through which an upper part of the via electrode 270 penetrates.

[0077] In detail, the spacer film 311 further includes a cylindrical portion 311c. The cylindrical portion 311c is provided above the conductive layer 42 via a gate upper film portion 321a, and extends substantially parallel to the Z axis.

[0078] The cylindrical portion 311c has a hole 402. The lower end of the cylindrical portion 311c forms an annular surface that contacts the gate upper film portion 321a of the insulating film 321.

[0079] The insulating film 45b further has a hole 404 (an example of a "fourth hole") extending in the vertical direction, through which the via electrode 270 passes.

[0080] The insulating film 321 further includes a via upper film portion 321d and a via lower film portion 321e, which cover the inner wall surface 402b of the hole 402 and the inner wall surface 404b of the hole 404, respectively.

[0081] Specifically, the via upper film portion 321d has a substantially cylindrical shape. The outer peripheral surface of the via upper film portion 321d contacts the entire periphery of the inner wall surface 402b of the hole 402. In other words, the inner wall surface 402b surrounds the entire periphery of the via upper film portion 321d.

[0082] The inner peripheral surface of the via upper film portion 321d contacts the entire circumference of an upper portion of the via electrode 270. That is, the via upper film portion 321d surrounds the entire circumference of an upper portion of the via electrode 270. In other words, the via upper film portion 321d covers the upper portion of the via electrode 270 between the cylindrical portion 311c and the upper portion of the via electrode 270.

[0083] The via lower film portion 321e has a substantially cylindrical shape. The outer peripheral surface of the via lower film portion 321e contacts the entire periphery of the inner wall surface 404b of the hole 404. In other words, the inner wall surface 404b surrounds the via lower film portion 321e over the entire periphery.

[0084] The inner peripheral surface of the via lower film portion 321e contacts the entire periphery of a lower portion of the via electrode 270. That is, the via lower film portion 321e surrounds the entire periphery of the lower portion of the via electrode 270. In other words, the via lower film portion 321e covers the lower portion of the via electrode 270 between the insulating film 45b and the lower portion of the via electrode 270.

[0085] [Method of manufacturing a semiconductor device] Hereinafter, a method for manufacturing the semiconductor device 30 will be described as an example of a method for manufacturing the semiconductor device according to the first embodiment.

[0086] First, as shown in FIGS. 7 and 8, an insulating film 45b, an insulating film 142, and an insulating film 45ba are provided in this order above the insulating layer 35. The insulating films 45b, 142, and 45ba extend along a plane substantially parallel to the XY plane. The insulating film 142 is, for example, silicon nitride. A transistor hole TH is formed extending substantially parallel to the Z axis and penetrating the insulating films 45ba, 142, and 45b, and then cleaned. The lower electrode 32 is exposed at the bottom of the transistor hole TH.

[0087] 9 to 12, a sacrificial amorphous silicon layer 170 is formed above the semiconductor device 30. As a result, the transistor hole TH is filled with the sacrificial amorphous silicon layer 170.

[0088] 13, a mask is formed by lithography on the surface of the semiconductor device 30 through processes such as film formation, resist application, exposure, development, and peeling, and then via holes VH extending substantially parallel to the Z axis are formed in the semiconductor device 30 by etching. In this embodiment, the via holes VH penetrate through the insulating films 45ba, 142, and 45b to the conductor 33. Below the via holes VH is a hole 404 formed in the insulating film 45b.

[0089] Next, as shown in FIGS. 14 to 16, the insulating film 142 inside the via hole VH and the insulating film 142 between the insulating film 45ba and the insulating film 45b are removed by etching with a phosphoric acid solution, and a cavity 242 is formed.

[0090] 17 to 19, an insulating film 321 is formed by, for example, atomic layer deposition. In detail, a gate upper film portion 321a and a gate lower film portion 321b are formed on the lower surface of the insulating film 45ba and the upper surface of the insulating film 45b, respectively. A gate insulating film portion 321c is formed around the sacrificial amorphous silicon layer 170 exposed to the cavity 242. A via upper film portion 321d and a via lower film portion 321e are formed on the inner wall surface 402b of the hole 402 and the inner wall surface 404b of the hole 404, respectively.

[0091] Next, as shown in FIG. 20, the upper part of the semiconductor device 30 is etched back by reactive ion etching to expose the conductor 33 at the bottom of the via hole VH.

[0092] 21 to 24, tungsten is filled into cavity 242 by physical vapor deposition to form conductive layer 42. This brings conductive layer 42 into contact with conductor 33, and they are electrically connected.

[0093] 25 and 26, the sacrificial amorphous silicon layer 170 is etched back to remove an upper portion of the sacrificial amorphous silicon layer 170 and expose the upper surface of the insulating film 45ba. At this time, the upper end of the sacrificial amorphous silicon layer 170 is located above the conductive layer 42 inside the transistor hole TH, for example.

[0094] 27 and 28, the insulating film 45ba is removed by etching, thereby exposing the gate upper film portion 321a.

[0095] 29 and 30, a spacer film 311 is formed above the semiconductor device 30. As a result, the sacrificial amorphous silicon layer 170 exposed above the gate upper film portion 321a and the upper surface of the gate upper film portion 321a are covered with the spacer film 311.

[0096] Next, as shown in Figures 31 and 32, lithography is used to form a film on the surface of the semiconductor device 30, apply resist, expose, develop, and peel, etc., to form a mask layer 145 having a groove portion 145a extending approximately parallel to the Y axis.

[0097] 33 to 35, a groove 45ca is formed in the semiconductor device 30 by etching, the groove 45ca penetrating the insulating film 45b and extending substantially parallel to the Y-axis. This separates the spacer film 311 into a cylindrical portion 311a and a plate-like portion 311b. The conductive layer 42 is also separated into a plurality of electrodes extending substantially parallel to the Y-axis and repeatedly arranged in the positive direction of the X-axis. These electrodes correspond to the word lines WL (see FIG. 1).

[0098] The surrounding portion 42b of the conductive layer 42 is formed by a self-alignment process. More specifically, even if the mask formation position by lithography is misaligned, the cylindrical portion 311a of the spacer film 311 located on the side surface of the sacrificial amorphous silicon layer 170 functions as a mask, and therefore the surrounding portion 42b is formed around the transistor hole TH in a self-aligned manner.

[0099] 36 and 37, insulating films 45c and 45a are integrally formed above the semiconductor device 30. Then, the upper surface of the semiconductor device 30 is subjected to chemical mechanical polishing, whereby the upper surface of the sacrificial amorphous silicon layer 170 is exposed from the insulating film 45a.

[0100] Next, as shown in FIGS. 38 and 39, the sacrificial amorphous silicon layer 170 inside the transistor hole TH is removed by etching.

[0101] 40 and 41, an oxide semiconductor layer 70 is formed inside the transistor hole TH. Then, the upper surface of the semiconductor device 30 is chemically mechanically polished.

[0102] 42 and 43, a metal oxide layer 50a, a barrier metal layer 50b, and a metal film 50c are formed from bottom to top on the upper surface of the semiconductor device 30. Then, an LPHM (Landing Pad Hard Mask) film 50e containing, for example, a silicon oxide is formed above the metal film 50c.

[0103] 44 and 45, a mask is formed by lithography on the surface of the semiconductor device 30 through film formation, resist application, exposure, development, and peeling, and then an upper electrode 50 that functions as a landing pad is formed by etching on the semiconductor device 30. The upper electrode 50 includes a barrier metal layer 51a, a barrier metal layer 50b, and a metal film 50c.

[0104] 46 and 47, an LP liner film 50d containing, for example, an oxide of silicon is formed on the upper surface of the semiconductor device 30. An insulating layer 63 is formed above the LP liner film 50d to fill the gaps formed by the LP liner film 50d. The insulating layer 63 contains, for example, an oxide of silicon. Then, the upper surface of the semiconductor device 30 is chemically mechanically polished.

[0105] 48 and 49, a barrier metal layer 51a, a conductive layer 51b, and a barrier metal layer 51c are formed from bottom to top on the upper surface of the semiconductor device 30. The barrier metal layers 51a and 51c include, for example, titanium nitride. The conductive layer 51b includes, for example, tungsten.

[0106] Then, BLHM (Bit Line Hard Mask) films 66a and 66b are formed from bottom to top on the upper surface of the barrier metal layer 51c. The BLHM films 66a and 66b contain, for example, silicon nitride and silicon oxide, respectively.

[0107] 50 and 51, a mask is formed by lithography on the surface of the semiconductor device 30 through processes such as film formation, resist coating, exposure, development, and stripping. Then, a trench 66ca is formed in the semiconductor device 30 by etching, penetrating the insulating layer 63 and the metal film 50c and extending substantially parallel to the X-axis. This separates the barrier metal layer 51a, the conductive layer 51b, and the barrier metal layer 51c into electrodes that extend substantially parallel to the X-axis and are repeatedly arranged in the positive direction of the Y-axis. These electrodes correspond to the bit lines BL (see FIG. 1).

[0108] 3 and 4, an insulating film 66c filling the groove portion 66ca is formed above the semiconductor device 30. The insulating film 66c includes, for example, an oxide of silicon.

[0109] (effect) As in a semiconductor device 90 of a comparative example shown in FIG. 52, a gate insulating film 43 may be provided on the inner surface of the transistor hole TH instead of the insulating film 321.

[0110] For example, in the process of etching back the bottom of the gate insulating film 43 by reactive ion etching to expose the lower electrode 32, the bottom of the gate insulating film 43 may not be completely removed and may remain partially. This is likely to occur when the dielectric constant of the gate insulating film 43 is high.

[0111] In this case, a sufficient on-state current cannot be obtained, and reliability is reduced due to variations in the contact area between the oxide semiconductor layer 70 and the lower electrode 32 and increased gate leakage.

[0112] Furthermore, when the gate insulating film 43 is formed in the transistor hole TH, the film is formed in a state in which the lower electrode 32 is exposed. Therefore, if the temperature rises due to heating, the ITO of the lower electrode 32 may disappear due to the temperature rise.

[0113] In contrast, in the semiconductor device 30, the process of etching back the bottom of the gate insulating film 43 by reactive ion etching is not performed in the first place, so it is possible to prevent part of the bottom of the gate insulating film 43 from remaining.

[0114] Furthermore, since the insulating film 321 is formed in a state where the exposure of the lower electrode 32 is prevented by the sacrificial amorphous silicon layer 170, the loss of the lower electrode 32 can be suppressed.

[0115] Furthermore, the gate upper film portion 321a surrounds the entire central portion of the oxide semiconductor layer 70, away from the upper end 70a and the lower end 70b, and the spacer film 311 and the insulating film 45b surround an upper portion (hereinafter sometimes referred to as the upper semiconductor portion) and a lower portion (hereinafter sometimes referred to as the lower semiconductor portion) of the oxide semiconductor layer 70, respectively, thereby making it possible to prevent a large difference in oxygen permeability between the upper semiconductor portion and the lower semiconductor portion.

[0116] This allows the amount of oxygen in the upper and lower semiconductor regions to be closer to symmetry, thereby making the resistance value of the upper and lower semiconductor regions closer to each other, thereby enabling a symmetrical on-current to be obtained even when the source and drain are interchanged.

[0117] Furthermore, since the dielectric constant of the material between the conductive layer 42 and the upper semiconductor portion and the dielectric constant of the material between the conductive layer 42 and the lower semiconductor portion can be made closer to each other, it is possible to prevent the fringe electric field between the conductive layer 42 and the upper semiconductor portion from being significantly different from the fringe electric field between the conductive layer 42 and the lower semiconductor portion.

[0118] [Second embodiment] A semiconductor device 30B according to a second embodiment will be described. From the second embodiment onward, descriptions of matters common to the first embodiment will be omitted, and only differences will be described. In particular, similar effects resulting from similar configurations will not be mentioned in each embodiment.

[0119] FIG. 53 shows a cross-sectional view of the semiconductor device 30B when viewed at a cross section 70YZ parallel to the YZ plane and included in the oxide semiconductor layer 70.

[0120] As shown in Figure 53, compared to the semiconductor device 30 shown in Figures 3 to 5, the semiconductor device 30B of the second embodiment has a gate insulating film 43 instead of the insulating film 321, and further has an interface film 501 (an example of a "first film").

[0121] The gate insulating film 43 has a cylindrical shape with a hole 43a extending in the vertical direction, penetrating the insulating film 45a, the conductive layer 42, and the insulating film 45b. The outer surface of the gate insulating film 43 contacts the entire inner wall surface of the transistor hole TH. In other words, the inner wall surface of the transistor hole TH surrounds the gate insulating film 43 over the entire periphery.

[0122] The inner circumferential surface of the gate insulating film 43 contacts the entire periphery of the side surface of the oxide semiconductor layer 70. In other words, the gate insulating film 43 surrounds the entire periphery of the side surface of the oxide semiconductor layer 70.

[0123] The interface film 501 is provided between the oxide semiconductor layer 70 and the lower electrode 32, and is electrically connected to the oxide semiconductor layer 70 and the lower electrode 32. In this embodiment, the interface film 501 is provided between the oxide semiconductor layer 70 and the lower electrode 32 and between the oxide semiconductor layer 70 and the insulating film 45b and the lower electrode 32.

[0124] Specifically, a hole 35a (an example of a "fifth hole") extending in the vertical direction is formed in the insulating layer 35 (an example of a "second interlayer insulating film"). The interface film 501 is provided inside the hole 35a and has a flattened columnar shape. The interface film 501 is exposed from the insulating layer 35. Specifically, an upper surface 501a of the interface film 501 is exposed from the opening 35c of the hole 35a and contacts the lower end 70b of the oxide semiconductor layer 70, the lower end 43c of the gate insulating film 43, and the lower surface of the insulating film 45b.

[0125] The lower electrode 32 has a cross section that is substantially the same shape as the interface film 501 and is a flattened column. The lower electrode 32 is provided inside the insulating layer 35 and is not exposed from the insulating layer 35. More specifically, the lower electrode 32 is provided inside the hole 35a and is not exposed from the opening 35c. In this embodiment, the lower electrode 32 is provided below the interface film 501 and contacts the lower surface 501b of the interface film 501. The lower electrode 32 faces the capacitor electrode 24 provided below it, with the conductor 21 interposed therebetween.

[0126] The contact area between the lower surface 501b of the interface film 501 and the lower electrode 32 (hereinafter, sometimes referred to as the lower contact area) is larger than the contact area between the lower end 70b of the oxide semiconductor layer 70 and the upper surface 501a of the interface film 501 (hereinafter, sometimes referred to as the upper contact area).

[0127] The side surfaces of the interface film 501, the lower electrode 32, and the capacitor electrode 24 are surrounded by the conductor 21. The insulating film 22 surrounds the conductor 21. The upper outer surface of the insulating film 22 contacts the entire inner wall surface 35b of the hole 35a.

[0128] The interface film 501 is made of a semiconductor or a conductor and contains atoms whose bond energy with oxygen atoms is greater than the bond energy between oxygen atoms and indium atoms in the lower electrode 32 .

[0129] In this embodiment, the interface film 501 contains, for example, gallium. The interface film 501 is, for example, an oxide semiconductor (an example of a "second oxide semiconductor"). Specifically, the interface film 501 contains indium, gallium, zinc, and oxygen. More specifically, the interface film 501 is IGZO. Note that the interface film 501 may also be made of IGO, IZO, GZO, InO, ZnO, GaO, SnO, or the like.

[0130] The composition ratio of indium, gallium, and zinc in the oxide semiconductor layer 70 is different from the composition ratio of indium, gallium, and zinc in the interface film 501.

[0131] [Method of manufacturing a semiconductor device] Hereinafter, a method for manufacturing the semiconductor device 30B will be described as an example of a method for manufacturing a semiconductor device according to the second embodiment.

[0132] 54, a hole 35a is formed in the insulating layer 35. Inside the hole 35a, an insulating film 22, a conductor 21, and a capacitor electrode 24 are formed.

[0133] Next, as shown in Fig. 55, a conductor 21 is further formed above the semiconductor device 30B. The conductor 21 functions as, for example, a barrier film.

[0134] Next, as shown in FIG. 56, a lower electrode 32 is formed above the semiconductor device 30B.

[0135] Next, as shown in FIG. 57, the upper surface of the semiconductor device 30B is chemically and mechanically polished, thereby exposing the lower electrode 32 from the opening 35c.

[0136] Next, as shown in FIG. 58, the upper surface of the lower electrode 32 is lowered by wet etching so that the lower electrode 32 is not exposed from the opening 35c.

[0137] Next, as shown in FIG. 59, an interface film 501 is formed above the semiconductor device 30B.

[0138] Next, as shown in FIG. 60, the upper surface of the semiconductor device 30B is chemically and mechanically polished, so that the upper surface 501a of the interface film 501 is exposed from the opening 35c of the hole 35a.

[0139] Next, as shown in FIG. 61, an insulating film 45b, a conductive layer 42, and an insulating film 45a are formed in this order above the insulating layer 35. Transistor holes TH are formed extending substantially parallel to the Z axis and penetrating the insulating film 45b, the conductive layer 42, and the insulating film 45a, and then cleaned. A gate insulating film 43 is formed on the inner surface of the transistor hole TH. At this time, the gate insulating film 43 is formed by heating, and the ITO of the lower electrode 32 may disappear due to the temperature rise.

[0140] Next, as shown in FIG. 62, the bottom of the gate insulating film 43 is etched back by reactive ion etching, and the interface film 501 is exposed at the bottom of the transistor hole TH.

[0141] Next, an oxide semiconductor layer 70 is formed inside the transistor hole TH as shown in Fig. 53. Then, the upper surface of the semiconductor device 30B is chemically and mechanically polished.

[0142] 56, the conductor 21 does not remain inside the hole 35a, but is deposited so that it protrudes from the opening 35c to the outside of the hole 35a. On the other hand, when the conductor 21 is deposited so that it remains inside the hole 35a as shown in FIG. 63, the chemical mechanical polishing step shown in FIG. 57 and the wet etching step shown in FIG. 58 may be omitted, and an interface film 501 may be deposited above the semiconductor device 30B as shown in FIG.

[0143] (effect) For example, when the indium concentration in the interface film 501 is higher than the indium concentration in the oxide semiconductor layer 70, the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 can be reduced.

[0144] The contact resistance can be reduced even when the zinc concentration in the interface film 501 is higher than the zinc concentration in the oxide semiconductor layer 70. The contact resistance can be reduced even when the gallium concentration in the interface film 501 is lower than the gallium concentration in the oxide semiconductor layer 70. When the indium concentration in the interface film 501 is higher than the indium concentration in the oxide semiconductor layer 70, the contact resistance can be effectively reduced.

[0145] Furthermore, compared to the oxide semiconductor layer 70, even when the gallium concentration of the interface film 501 is lower and the zinc concentration of the interface film 501 is higher, the contact resistance between the oxide semiconductor layer 70 and the lower electrode 32 can be reduced.

[0146] Furthermore, if the interface film 501 is not provided, the lower electrode 32 is exposed. Therefore, the ITO of the lower electrode 32 may disappear due to the temperature rise when the gate insulating film 43 is formed by heating.

[0147] The bond energy with oxygen decreases in the order of gallium, indium, and zinc. The structure in which the interface film 501 containing gallium is provided allows the interface film 501 to function as a strong lid. This makes it possible to suppress the disappearance of the lower electrode 32 when the gate insulating film 43 is formed.

[0148] That is, when the gallium concentration in the interface film 501 is higher than the gallium concentration in the lower electrode 32, the bond energy between gallium and oxygen is large, so that the disappearance of the lower electrode 32 during the formation of the gate insulating film 43 can be suppressed.

[0149] Furthermore, since the contact area between the ITO and the IGZO can be increased by configuring the lower contact area to be larger than the upper contact area, the contact resistance with the lower electrode 32 can be reduced.

[0150] In the semiconductor device 30, the configuration in which the lower electrode 32 is in physical contact with the oxide semiconductor layer 70 has been described, but the present invention is not limited to this. As long as the lower electrode 32 is electrically connected to the oxide semiconductor layer 70, the lower electrode 32 may not be in physical contact with the oxide semiconductor layer 70.

[0151] In addition, in the semiconductor device 30, the upper electrode 50 is in physical contact with the oxide semiconductor layer 70, but the present invention is not limited to this. As long as the upper electrode 50 is electrically connected to the oxide semiconductor layer 70, the upper electrode 50 may not be in physical contact with the oxide semiconductor layer 70.

[0152] In addition, in the semiconductor device 30B, the configuration in which the interface film 501 is in physical contact with the oxide semiconductor layer 70 has been described, but the present invention is not limited to this. As long as the interface film 501 is electrically connected to the oxide semiconductor layer 70, the interface film 501 may not be in physical contact with the oxide semiconductor layer 70.

[0153] Furthermore, in the semiconductor device 30B, the configuration in which the interface film 501 is in physical contact with the lower electrode 32 has been described, but the present invention is not limited to this. As long as the interface film 501 is electrically connected to the lower electrode 32, the interface film 501 may not be in physical contact with the lower electrode 32.

[0154] (a) an oxide semiconductor having a first upper end and a first lower end and extending in a vertical direction; a first electrode in contact with the first lower end of the oxide semiconductor; a second electrode in contact with the first upper end of the oxide semiconductor; a gate electrode formed of a first conductive material; a first insulating film formed of a first insulating material; the gate electrode has a sixth hole portion extending in the vertical direction, the sixth hole portion passing through the oxide semiconductor, and extends in a first direction intersecting with the vertical direction; the first insulating film includes a gate upper film portion, a gate lower film portion, and a gate insulating film portion, which respectively cover an upper surface and a lower surface of the gate electrode and an inner wall of the sixth hole portion; Semiconductor device.

[0155] (b) the semiconductor device a via electrode having a second upper end and a second lower end and extending in the vertical direction; a third insulating film provided with a first hole portion and a second hole portion extending in the vertical direction, the first hole portion and the second hole portion through which the oxide semiconductor and the via electrode pass, respectively, and provided above the gate upper film portion; a fourth insulating film provided below the gate lower film portion, in which a third hole portion and a fourth hole portion extending in the vertical direction are provided, the third hole portion and the fourth hole portion being penetrated by the oxide semiconductor and the via electrode, respectively; the second lower end of the via electrode is electrically connected to a semiconductor circuit; the first insulating film further includes a via upper film portion and a via lower film portion covering an inner wall surface of the second hole portion and an inner wall surface of the fourth hole portion, respectively; the gate electrode comprises a first conductive material; the via electrode includes the first conductive material and is electrically connected to the gate electrode. Semiconductor device.

[0156] (c) the semiconductor device a third insulating film formed of a third insulating material different from the first insulating material; a fourth insulating film formed of a fourth insulating material different from the first insulating material; the third insulating film has a first hole portion extending in the vertical direction, the first hole portion being in contact with the oxide semiconductor through which the third insulating film is formed, and the third insulating film is provided above the gate upper film portion; the fourth insulating film has a third hole portion extending in the vertical direction, the third hole portion penetrating and contacting the oxide semiconductor, and is provided below the gate lower film portion; Semiconductor device.

[0157] (d) the semiconductor device a second interlayer insulating film having a fifth hole formed therein, the second interlayer insulating film being provided so that the first interlayer insulating film is located between the second interlayer insulating film and the gate electrode; the first film is exposed from the opening of the fifth hole portion, the first electrode is provided inside the fifth hole portion and is not exposed from the opening portion; Semiconductor device.

[0158] The present embodiment has been described above with reference to specific examples. However, the present disclosure is not limited to these specific examples. Design modifications to these specific examples made by a person skilled in the art as appropriate are also included within the scope of the present disclosure as long as they comprise the features of the present disclosure. The elements of the above-described specific examples, as well as their arrangement, conditions, shape, etc., are not limited to those exemplified and can be modified as appropriate. The elements of the above-described specific examples can be combined in various ways as appropriate, as long as no technical contradictions arise. [Explanation of symbols]

[0159] 10...Semiconductor substrate 11...Circuit 20...Capacitor 21...Conductor 22...insulating film 23...Conductor 24, 25...Capacitor electrodes 30, 30B...Semiconductor device 32...Lower electrode 33...Conductor 34, 35...insulating layer 35a...hole 35b...inner wall surface 35c…opening 40...Field effect transistor 42...Conductive layer 42b...Encirclement 42c...Connection part 42d…Top surface 42e…Bottom surface 42f…side 43...Gate insulating film 43a...hole 43c...end 45...insulating layer 45a, 45b, 45ba, 45c...insulating film 45ca…Groove 50…Top electrode 50a...metal oxide layer 50b...Barrier metal layer 50c…Metal film 70...Oxide semiconductor layer 170...Sacrificial amorphous silicon layer 70a…Top end 70b…lower end 101...Semiconductor memory device 142...insulating film 242...Cavity 270...Via electrode 270a…Top end 270b…lower end 311...Spacer film 311a, 311c...Cylindrical part 311b...plate-shaped part 321...insulating film 321a...Gate upper membrane part 321b...Gate lower membrane part 321c...Gate insulating film part 321d...Via upper film part 321e…Via lower film part 401, 402, 403, 404, 405...hole 401b, 402b, 403b, 404b, 405b...inner wall surface 501…Interfacial film 501a…Top surface 501b…Bottom surface

Claims

1. a gate electrode extending in a first direction; an oxide semiconductor extending in a vertical direction intersecting the first direction and penetrating the gate electrode; a first electrode connected to a first lower end of the oxide semiconductor; a second electrode connected to a first upper end of the oxide semiconductor; a first insulating film including a gate upper film portion covering an upper surface of the gate electrode, a gate lower film portion covering a lower surface of the gate electrode, and a gate insulating film portion covering a first surface of the gate electrode facing the oxide semiconductor, the first insulating film being formed of a first insulating material; Semiconductor device.

2. The semiconductor device includes: a second insulating film including a second insulating material different from the first insulating material; the gate electrode has a side surface having a normal direction in a second direction intersecting the up-down direction and the first direction, the second insulating film is in contact with the side surface; The semiconductor device according to claim 1 .

3. the first insulating material contains silicon and nitrogen; The semiconductor device according to claim 1 .

4. The semiconductor device includes: a via electrode having a second upper end and a second lower end and extending in the up-down direction; a third insulating film through which the oxide semiconductor and the via electrode pass and which is provided above the gate upper film portion; a fourth insulating film through which the oxide semiconductor and the via electrode pass and which is provided below the gate lower film portion, the second lower end of the via electrode is electrically connected to a semiconductor circuit; the first insulating film further includes a via upper film portion covering the via electrode between the third insulating film and the via electrode, and a via lower film portion covering the via electrode between the fourth insulating film and the via electrode, the gate electrode comprises a first conductive material; the via electrode includes the first conductive material and is electrically connected to the gate electrode. The semiconductor device according to claim 1 .

5. The semiconductor device includes: a third insulating film formed of a third insulating material different from the first insulating material; a fourth insulating film formed of a fourth insulating material different from the first insulating material; the third insulating film is formed above the gate upper film portion and is in contact with the oxide semiconductor film passing therethrough; the fourth insulating film is in contact with the oxide semiconductor and is provided below the gate lower film portion; The semiconductor device according to claim 1 .

6. the oxygen permeability of the first insulating material is less than the oxygen permeability of the third insulating material; The semiconductor device according to claim 5 .

7. the oxygen permeability of the first insulating material is lower than the oxygen permeability of the fourth insulating film; The semiconductor device according to claim 5 .

8. the first electrode includes a metal oxide; The semiconductor device according to claim 1 .

9. a first oxide semiconductor extending in the vertical direction; a first interlayer insulating film extending along a plane parallel to a direction intersecting the vertical direction and penetrated by the first oxide semiconductor; a first electrode containing oxygen, indium, and tin; a first film formed of a semiconductor or a conductor and provided between the first oxide semiconductor and the first electrode, electrically connected to the first oxide semiconductor and the first electrode; a gate electrode facing the first oxide semiconductor via a gate insulating film; the first film contains atoms having a bond energy with oxygen atoms that is greater than a bond energy between oxygen atoms and indium atoms in the first electrode; Semiconductor device.

10. the first film is provided between the first oxide semiconductor and the first interlayer insulating film and the first electrode; The semiconductor device according to claim 9 .

11. the gate insulating film penetrates the first interlayer insulating film and surrounds the first oxide semiconductor; the first film is in contact with the first interlayer insulating film, the gate insulating film, and the first oxide semiconductor; The semiconductor device according to claim 9 .

12. The semiconductor device includes: a second interlayer insulating film provided such that the first interlayer insulating film is located between the second interlayer insulating film and the gate electrode; the first film is exposed from the second interlayer insulating film, the first electrode is provided inside the second interlayer insulating film and is not exposed from the second interlayer insulating film; The semiconductor device according to claim 9 .

13. the first film is a second oxide semiconductor; The semiconductor device according to claim 9 .

14. each of the first oxide semiconductor and the second oxide semiconductor contains indium, gallium, zinc, and oxygen; a composition ratio of indium, gallium, and zinc in the first oxide semiconductor is different from a composition ratio of indium, gallium, and zinc in the second oxide semiconductor; The semiconductor device according to claim 13.

15. the first film contains gallium; The semiconductor device according to claim 9 .

16. the first film is in contact with the first electrode and the first oxide semiconductor; The contact area between the first film and the first electrode is larger than the contact area between the first film and the first oxide semiconductor. The semiconductor device according to claim 13.

17. The semiconductor device according to claim 1 or 9; a first capacitor electrode connected to the first electrode; a second capacitor electrode facing the first capacitor electrode; a dielectric film provided between the first capacitor electrode and the second capacitor electrode, Semiconductor memory device.

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