Input circuit and semiconductor device

Abstract

To provide an input circuit in which the occurrence of a BTI phenomenon can be suppressed while the flow of current between input terminals is suppressed, and a semiconductor device including such an input circuit.SOLUTION: An input circuit includes a first input wiring part to which a first voltage is applied, a second input wiring part to which a second voltage is applied, a first output wiring part, a second output wiring part, a voltage generation circuit part that generates a third voltage on the basis of at least one of the first voltage and the second voltage, a first transistor disposed between the first input wiring part and the first output wiring part, and a second transistor disposed between the second input wiring part and the second output wiring part. To a driving terminal of the first transistor and a driving terminal of the second transistor, the third voltage is applied. If the difference between the first voltage and the second voltage is larger than a first predetermined value, the difference between the third voltage and the lower one of the first voltage and the second voltage is smaller than the difference between the first voltage and the second voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD Embodiments of the present invention relate to an input circuit and a semiconductor device. [Background technology]

[0002] A differential circuit having a pair of differential transistors forming a differential pair is known. In such a differential circuit, different voltages are applied to the drive terminals of the pair of differential transistors. If a large difference in voltages is maintained between the drive terminals of the pair of differential transistors, the differential transistor to which the larger voltage is applied deteriorates, causing a problem known as bias temperature instability (BTI), in which the threshold voltage of the differential transistor fluctuates. To address this problem, there is a technology that uses diodes to suppress the large voltage difference applied to the drive terminals of the pair of differential transistors. However, this technology has the problem of allowing a relatively large current to flow between the input terminals via the diodes. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 4-63014 Summary of the Invention [Problem to be solved by the invention]

[0004] The problem to be solved by the present invention is to provide an input circuit that can suppress the occurrence of the BTI phenomenon while suppressing the flow of current between input terminals, and a semiconductor device that includes such an input circuit. [Means for solving the problem]

[0005] An input circuit according to an embodiment is an input circuit that inputs a voltage to each of drive terminals of a pair of differential transistors that form a differential pair. The input circuit includes a first input wiring section to which a first voltage is applied, a second input wiring section to which a second voltage different from the first voltage is applied, a first output wiring section that outputs a voltage to one of the pair of differential transistors, a second output wiring section that outputs a voltage to the other of the pair of differential transistors, a voltage generation circuit section that generates a third voltage based on at least one of the first voltage and the second voltage, a first transistor disposed between the first input wiring section and the first output wiring section, and a second transistor disposed between the second input wiring section and the second output wiring section. The third voltage is applied to the drive terminal of the first transistor and the drive terminal of the second transistor. When the difference between the first voltage and the second voltage is greater than a first predetermined value, the difference between the lower of the first voltage and the second voltage and the third voltage is smaller than the difference between the first voltage and the second voltage. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a circuit diagram showing a semiconductor device according to an embodiment; [Figure 2] FIG. 1 is a circuit diagram showing a part of a semiconductor device according to an embodiment. [Figure 3] FIG. 4 is a circuit diagram showing another part of the semiconductor device according to the embodiment. [Figure 4] FIG. 2 is a circuit diagram showing an example of the operation of the semiconductor device according to the embodiment. [Figure 5] FIG. 10 is a circuit diagram showing another example of the operation of the semiconductor device according to the embodiment. [Figure 6] FIG. 4 is a circuit diagram showing a current that flows when electric charges are released by a first diode according to the embodiment. [Figure 7] FIG. 10 is a circuit diagram showing a current that flows when charges are released by a second diode according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, an input circuit and a semiconductor device according to an embodiment will be described with reference to the drawings.

[0008] FIG. 1 is a circuit diagram showing a semiconductor device 100 of this embodiment. FIG. 2 is a circuit diagram showing a part of the semiconductor device 100 of this embodiment. FIG. 3 is a circuit diagram showing another part of the semiconductor device 100 of this embodiment. FIG. 4 is a circuit diagram showing an example of the operation of the semiconductor device 100 of this embodiment. FIG. 5 is a circuit diagram showing another example of the operation of the semiconductor device 100 of this embodiment. The semiconductor device 100 shown in FIG. 1 outputs two output values ​​to an output circuit C. The two output values ​​are two voltage values ​​or two current values. The output circuit C is, for example, a comparator. The output circuit C is not particularly limited as long as it is a circuit to which two values ​​are input.

[0009] 1, the semiconductor device 100 includes an input circuit 10 and a differential circuit 20. The input circuit 10 is a circuit that inputs two different voltages to the differential circuit 20. The differential circuit 20 is a circuit that generates two output values ​​to be output to an output circuit C based on the two voltages input from the input circuit 10.

[0010] The input circuit 10 includes a first input terminal 10a, a second input terminal 10b, a first input wiring section 11, a second input wiring section 12, a first output wiring section 13, a second output wiring section 14, a first transistor 31, a second transistor 32, a fifth transistor 35, a sixth transistor 36, a voltage generation circuit section 40, a voltage comparison circuit section 50, a first diode 71, and a second diode 72. The first input terminal 10a and the second input terminal 10b are exposed to the outside of the semiconductor device 100. A first voltage V1 is applied to the first input terminal 10a. A second voltage V2 different from the first voltage V1 is applied to the second input terminal 10b.

[0011] The first input wiring section 11 is connected to the first input terminal 10a. The first voltage V1 applied to the first input terminal 10a is applied to the first input wiring section 11. The second input wiring section 12 is connected to the second input terminal 10b. The second input wiring section 12 is applied to the second voltage V2 applied to the second input terminal 10b.

[0012] The first output wiring section 13 and the second output wiring section 14 output different voltages to the differential circuit 20. The first output wiring section 13 outputs a voltage to a first differential transistor 21, which will be described later, in the differential circuit 20. The second output wiring section 14 outputs a voltage to a first differential transistor 22, which will be described later, in the differential circuit 20.

[0013] The first transistor 31 is disposed between the first input wiring section 11 and the first output wiring section 13. The second transistor 32 is disposed between the second input wiring section 12 and the second output wiring section 14. In this embodiment, the first transistor 31 and the second transistor 32 are field effect transistors (FETs). More specifically, the first transistor 31 and the second transistor 32 are N-channel metal-oxide-semiconductor field-effect transistors (MOSFETs). As shown in FIG. 2 , a drain terminal 31d of the first transistor 31 is connected to the first input wiring section 11. A source terminal 31s of the first transistor 31 is connected to the first output wiring section 13. A drain terminal 32d of the second transistor 32 is connected to the second input wiring section 12. A source terminal 32s of the second transistor 32 is connected to the second output wiring section 14. In this embodiment, the absolute value Vth of the threshold voltage of the first transistor 31 and the absolute value Vth of the threshold voltage of the second transistor 32 are the same. Note that the absolute value Vth of the threshold voltage of the first transistor 31 and the absolute value Vth of the threshold voltage of the second transistor 32 may be different from each other.

[0014] In the circuits disclosed herein, the term "threshold voltage" may refer to a narrowly defined threshold voltage, which is a voltage value required to turn a transistor ON, or may refer to a broadly defined threshold voltage obtained by adding an excess voltage (overdrive voltage) required to cause current from each current source, etc., to flow through the transistor to the narrowly defined threshold voltage. In other words, the absolute value Vth of the threshold voltage of each transistor in the embodiments may be the absolute value of the voltage required to turn each transistor ON, or the absolute value of the voltage required to turn each transistor ON and cause current from each current source to flow through each transistor.

[0015] In the circuits disclosed herein, "another element is disposed between a certain element and another element" means that the other element is disposed on the circuit between the certain element and the other element, leading from one to the other.

[0016] The voltage generating circuit unit 40 generates a third voltage V3 based on at least one of the first voltage V1 and the second voltage V2. When the difference between the first voltage V1 and the second voltage V2 is greater than a first predetermined value, the difference between the third voltage V3 and the lower of the first voltage V1 and the second voltage V2 is smaller than the difference between the first voltage V1 and the second voltage V2. In this embodiment, the first predetermined value is the absolute value Vth of the threshold voltages of a third transistor 33 and a fourth transistor, which will be described later. Note that the first predetermined value is not particularly limited. In this embodiment, the voltage generating circuit unit 40 generates the third voltage V3 based on the lower of the first voltage V1 and the second voltage V2. The voltage generating circuit unit 40 includes a third transistor 33, a fourth transistor 34, and a first current source 61.

[0017] The first current source 61 is connected to the power supply voltage wiring section 41 to which the power supply voltage VDD is applied. The first current source 61 is configured to pass a constant current Id1. The first current source 61 may have any configuration as long as it can pass a constant current Id1. The magnitude of the current Id1 is not particularly limited.

[0018] In this embodiment, the third transistor 33 and the fourth transistor 34 are field-effect transistors. More specifically, the third transistor 33 and the fourth transistor 34 are P-channel MOSFETs. The third transistor 33 and the fourth transistor 34 are arranged in parallel between the power supply voltage wiring section 41, to which the power supply voltage VDD is applied, and ground GND. In this embodiment, the third transistor 33 and the fourth transistor 34 are arranged in parallel between the first current source 61 and ground GND. The ground GND has a reference potential. The reference potential is, for example, 0 V. The reference potential is not particularly limited and may be a potential other than 0 V. Note that the voltages described in this embodiment are voltages based on the reference potential of the ground GND. In other words, the voltage of the ground GND is 0 V.

[0019] The source terminal 33s of the third transistor 33 and the source terminal 34s of the fourth transistor 34 are connected to each other. The source terminal 33s of the third transistor 33 and the source terminal 34s of the fourth transistor 34 are connected to the first current source 61, the gate terminal 31g of the first transistor 31, and the gate terminal 32g of the second transistor 32. The drain terminal 33d of the third transistor 33 and the drain terminal 34d of the fourth transistor 34 are connected to each other. The drain terminal 33d of the third transistor 33 and the drain terminal 34d of the fourth transistor 34 are connected to ground GND. The gate terminal 33g of the third transistor 33 is connected to the first input wiring section 11. The gate terminal 34g of the fourth transistor 34 is connected to the second input wiring section 12.

[0020] In this disclosure, the gate terminal of a field-effect transistor corresponds to a "drive terminal." The drive terminal of a transistor is a terminal to which a voltage is applied to drive the transistor. In this embodiment, the source terminal 33s of the third transistor 33 and the source terminal 34s of the fourth transistor 34 correspond to a "first terminal." The drain terminal 33d of the third transistor 33 and the drain terminal 34d of the fourth transistor 34 correspond to a "second terminal."

[0021] The third voltage V3 generated in the voltage generating circuit unit 40 is applied to the gate terminal 31g of the first transistor 31 and the gate terminal 32g of the second transistor 32. In this embodiment, the value of the third voltage V3 is the lower of the first voltage V1 and the second voltage V2 plus the absolute value Vth of the threshold voltage of the third transistor 33 or the fourth transistor 34 included in the voltage generating circuit unit 40. In this embodiment, the absolute value Vth of the threshold voltage of the third transistor 33 and the absolute value Vth of the threshold voltage of the fourth transistor 34 are the same. In this embodiment, the absolute value Vth of the threshold voltage of the third transistor 33 and the absolute value Vth of the threshold voltage of the fourth transistor 34 are also the same as the absolute value Vth of the threshold voltage of the first transistor 31 and the absolute value Vth of the threshold voltage of the second transistor 32. Note that the absolute value Vth of the threshold voltage of the third transistor 33 and the absolute value Vth of the threshold voltage of the fourth transistor 34 may be different from each other.

[0022] When a voltage is applied to each of the first input terminal 10a and the second input terminal 10b, a first voltage V1 is applied to the gate terminal 33g of the third transistor 33 in the voltage generating circuit unit 40, and a second voltage V2 is applied to the gate terminal 34g of the fourth transistor 34. In this embodiment, the third transistor 33 and the fourth transistor 34 are P-channel MOSFETs. Therefore, the third transistor 33 and the fourth transistor 34 are turned ON when the voltage applied to each gate terminal is lower than the voltage applied to each source terminal by at least the absolute value Vth of the threshold voltage, i.e., when the negative gate voltage is equal to or lower than the threshold voltage. When the third transistor 33 and the fourth transistor 34 are turned OFF, the current Id1 flowing from the first current source 61 connected to the power supply voltage VDD does not flow to ground GND, and therefore the voltages at the source terminal 33s of the third transistor 33 and the source terminal 34s of the fourth transistor 34 are the power supply voltage VDD. In this case, if the first voltage V1 and the second voltage V2 are lower than the power supply voltage VDD by the absolute value Vth or more of the threshold voltages of the third transistor 33 and the fourth transistor 34, the third transistor 33 and the fourth transistor 34 are turned on.

[0023] Furthermore, when the third transistor 33 and the fourth transistor 34 are in the ON state, the lower the voltage applied to the gate terminal, the more easily a current flows between the source terminal and the drain terminal of the third transistor 33 and the fourth transistor 34. Therefore, if the second voltage V2 is lower than the first voltage V1, a current flows more easily between the source terminal 34s and the drain terminal 34d of the fourth transistor 34 than between the source terminal 33s and the drain terminal 33d of the third transistor 33. On the other hand, if the first voltage V1 is lower than the second voltage V2, a current flows more easily between the source terminal 33s and the drain terminal 33d of the third transistor 33 than between the source terminal 34s and the drain terminal 34d of the fourth transistor 34.

[0024] 4 illustrates a case in which the second voltage V2 is lower than the first voltage V1 and is lower than the power supply voltage VDD by at least the absolute value Vth of the threshold voltages of the third transistor 33 and the fourth transistor 34. In the example of FIG. 4, the first voltage V1 is higher than the second voltage V2 and is lower than the power supply voltage VDD. In the example of FIG. 4, the difference between the first voltage V1 and the second voltage V2 is greater than the absolute value Vth (first predetermined value) of the threshold voltages of the third transistor 33 and the fourth transistor 34. In FIG. 4, current flows more easily through the fourth transistor 34 than through the third transistor 33, so the current Id1 flowing from the first current source 61 more easily flows to ground GND via the fourth transistor 34. As the current Id1 flows through the fourth transistor 34, the voltage at the source terminal 34s of the fourth transistor 34 decreases and becomes equal to the second voltage V2 applied to the gate terminal 34g of the fourth transistor 34 plus the absolute value Vth of the threshold voltage of the fourth transistor 34. The voltage at the source terminal 34s at this time is the third voltage V3 generated by the voltage generating circuit unit 40. In other words, the relationship between the second voltage V2, the absolute value Vth of the threshold voltage of the fourth transistor 34, and the third voltage V3 is expressed as V3 = V2 + Vth. In the example of FIG. 4, the first voltage V1 is higher than the second voltage V2, and the difference between the first voltage V1 and the second voltage V2 is greater than the absolute value Vth. Therefore, the third voltage V3 is lower than the first voltage V1. The difference between the second voltage V2, which is lower than the first voltage V1, and the third voltage V3 is equal to the absolute value Vth. That is, the difference between the second voltage V2 and the third voltage V3 is smaller than the difference between the first voltage V1 and the second voltage V2. The generated third voltage V3 is applied to the gate terminal 31g of the first transistor 31 and the gate terminal 32g of the second transistor 32, which are connected to the source terminal 34s.

[0025] Since the source terminal 33s of the third transistor 33 is connected to the source terminal 34s of the fourth transistor 34, the voltage of the source terminal 33s of the third transistor 33 also becomes the third voltage V3. At this time, since the first voltage V1 higher than the second voltage V2 is applied to the gate terminal 33g of the third transistor 33, if the absolute value Vth of the threshold voltage of the third transistor 33 is the same as the absolute value Vth of the threshold voltage of the fourth transistor 34, the third transistor 33 is turned OFF.

[0026] When the first voltage V1 is lower than the second voltage V2, similarly to the example described above, the value of the third voltage V3 is the value obtained by adding the absolute value Vth of the threshold voltage of the third transistor 33 to the value of the first voltage V1 applied to the gate terminal 33g of the third transistor 33. In this case, if the difference between the first voltage V1 and the second voltage V2 is greater than the absolute value Vth, the third voltage V3 is lower than the second voltage V2, and the difference between the first voltage V1, which is lower than the second voltage V2, and the third voltage V3 is equal to the absolute value Vth. In other words, in this case, the difference between the first voltage V1 and the third voltage V3 is smaller than the difference between the first voltage V1 and the second voltage V2.

[0027] As described above, in this embodiment, the third voltage V3 is the sum of the lower of the first voltage V1 and the second voltage V2 and the absolute value Vth of the third transistor 33 and the fourth transistor 34, so if the difference between the first voltage V1 and the second voltage V2 is greater than the absolute value Vth, the difference between the lower of the first voltage V1 and the second voltage V2 and the third voltage V3 will be smaller than the difference between the first voltage V1 and the second voltage V2. In this way, the voltage generation circuit unit 40 generates the third voltage V3.

[0028] As shown in FIG. 1 , the fifth transistor 35 is arranged between the first input wiring section 11 and the first output wiring section 13. The fifth transistor 35 is connected in parallel with the first transistor 31. The sixth transistor 36 is arranged between the second input wiring section 12 and the second output wiring section 14. The sixth transistor 36 is connected in parallel with the second transistor 32. In this embodiment, the fifth transistor 35 and the sixth transistor 36 are field-effect transistors. More specifically, the fifth transistor 35 and the sixth transistor 36 are P-channel MOSFETs.

[0029] 3, a source terminal 35s of the fifth transistor 35 is connected to the first input wiring section 11. A drain terminal 35d of the fifth transistor 35 is connected to the first output wiring section 13. A source terminal 36s of the sixth transistor 36 is connected to the second input wiring section 12. A drain terminal 36d of the sixth transistor 36 is connected to the second output wiring section 14.

[0030] The voltage comparison circuit unit 50 is a circuit that compares the first voltage V1 and the second voltage V2 with the power supply voltage VDD. The voltage comparison circuit unit 50 includes a seventh transistor 37, an eighth transistor 38, a second current source 62, and a third current source 63. The power supply voltage VDD is applied to the second current source 62. The third current source 63 is connected to ground GND. The second current source 62 and the third current source 63 are configured to pass constant currents. The current Id3 output by the third current source 63 is smaller than the current Id2 output by the second current source 62. The second current source 62 and the third current source 63 may have any configuration as long as they can pass constant currents Id2 and Id3, respectively. As long as the current Id3 is smaller than the current Id2, the magnitudes of the currents Id2 and Id3 are not particularly limited.

[0031] The seventh transistor 37 and the eighth transistor 38 are arranged in parallel between the output side of the second current source 62 and the input side of the third current source 63. In this embodiment, the seventh transistor 37 and the eighth transistor 38 are field-effect transistors. More specifically, the seventh transistor 37 and the eighth transistor 38 are P-channel MOSFETs. A source terminal 37s of the seventh transistor 37 and a source terminal 38s of the eighth transistor 38 are connected to each other. The source terminals 37s of the seventh transistor 37 and the source terminals 38s of the eighth transistor 38 are connected to the second current source 62. A drain terminal 37d of the seventh transistor 37 and a drain terminal 38d of the eighth transistor 38 are connected to each other. The drain terminal 37d of the seventh transistor 37 and the drain terminal 38d of the eighth transistor 38 are connected to the third current source 63, the gate terminal 35g of the fifth transistor 35, and the gate terminal 36g of the sixth transistor 36. A gate terminal 37g of the seventh transistor 37 is connected to the first input wiring section 11. A gate terminal 38g of the eighth transistor 38 is connected to the second input wiring section 12. In this embodiment, the absolute value Vth of the threshold voltage of the seventh transistor 37 and the absolute value Vth of the threshold voltage of the eighth transistor 38 are the same as each other, and are the same as the absolute value Vth of the threshold voltage of the third transistor 33 and the absolute value Vth of the threshold voltage of the fourth transistor 34.

[0032] In the present disclosure, of the drain terminal and source terminal of a field-effect transistor, the terminal from which current flows when the field-effect transistor is in an ON state corresponds to the “output terminal.” That is, in a P-channel field-effect transistor, the drain terminal corresponds to the “output terminal,” and in an N-channel field-effect transistor, the source terminal corresponds to the “output terminal.”

[0033] The voltage comparison circuit unit 50 turns off the fifth transistor 35 and the sixth transistor 36 when at least one of the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD is equal to or greater than a second predetermined value. In this embodiment, the second predetermined value is the absolute value Vth of the threshold voltages of the seventh transistor 37 and the eighth transistor 38. Note that the second predetermined value is not particularly limited and may be a value other than the absolute value Vth. FIG. 4 illustrates a case in which the second voltage V2 is lower than the first voltage V1 and the difference between the second voltage V2 and the power supply voltage VDD (VDD - V2) is equal to or greater than the second predetermined value, i.e., the absolute value Vth. In this case, the eighth P-channel transistor 38 is turned on, and the current Id2 output from the second current source 62 flows through the eighth transistor 38 and attempts to flow to ground GND via the third current source 63. However, the current Id3 output from the third current source 63 to ground GND is smaller than the current Id2 output from the second current source 62. Therefore, only a portion of the current Id2 output from the second current source 62 flows to ground GND, and charge accumulates in the drain terminal 38d of the eighth transistor 38. As a result, the voltage at the drain terminal 38d of the eighth transistor 38 becomes the power supply voltage VDD. Therefore, the voltages applied to the gate terminal 35g of the fifth transistor 35 and the gate terminal 36g of the sixth transistor 36, which are connected to the drain terminal 38d, also become the power supply voltage VDD. Meanwhile, since the first voltage V1 applied to the source terminal 35s of the fifth transistor 35 and the second voltage V2 applied to the source terminal 36s of the sixth transistor 36 are equal to or lower than the power supply voltage VDD, the P-channel fifth transistor 35 and the sixth transistor 36 are in the OFF state. The same applies when the first voltage V1 is lower than the second voltage V2 and the difference (VDD - V1) between the first voltage V1 and the power supply voltage VDD is equal to or higher than the second predetermined value, i.e., the absolute value Vth, except that the current Id2 flows through the seventh transistor 37.

[0034] The voltage comparator circuit 50 turns on the fifth transistor 35 and the sixth transistor 36 when both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are smaller than the second predetermined value, i.e., the absolute value Vth. Figure 5 shows a case where the second voltage V2 is lower than the first voltage V1, and both the difference between the first voltage V1 and the power supply voltage VDD (VDD - V1) and the difference between the second voltage V2 and the power supply voltage VDD (VDD - V2) are smaller than the second predetermined value (absolute value Vth). In this case, the voltages applied to the gate terminal 37g of the seventh transistor 37 and the gate terminal 38g of the eighth transistor 38 are not lower than the power supply voltage VDD by the absolute value Vth or more, so the P-channel seventh transistor 37 and the eighth transistor 38 are turned off. When both the seventh transistor 37 and the eighth transistor 38 are turned OFF, the gate terminal 35g of the fifth transistor 35 and the gate terminal 36g of the sixth transistor 36 are shorted to ground GND via the third current source 63, and the voltage applied to the gate terminal 35g of the fifth transistor 35 and the gate terminal 36g of the sixth transistor 36 becomes the voltage of ground GND, i.e., 0 V. Meanwhile, the first voltage V1 applied to the source terminal 35s of the fifth transistor 35 and the second voltage V2 applied to the source terminal 36s of the sixth transistor 36 are close to the power supply voltage VDD, so the P-channel fifth transistor 35 and the sixth transistor 36 are turned ON. This also applies when the first voltage V1 is lower than the second voltage V2 and both the difference (VDD-V1) between the first voltage V1 and the power supply voltage VDD and the difference (VDD-V2) between the second voltage V2 and the power supply voltage VDD are smaller than the second predetermined value (absolute value Vth).

[0035] As shown in FIG. 1 , the first diode 71 and the second diode 72 are arranged between the first output wiring section 13 and the second output wiring section 14. The anode of the first diode 71 is connected to the first output wiring section 13. The cathode of the first diode 71 is connected to the second output wiring section 14. The anode of the second diode 72 is connected to the second output wiring section 14. The cathode of the second diode 72 is connected to the first output wiring section 13. The forward voltage of the first diode 71 and the forward voltage of the second diode 72 are, for example, the same. The forward voltage of the first diode 71 and the forward voltage of the second diode 72 may be different from each other.

[0036] The differential circuit 20 includes a pair of first differential transistors 21 and 22 that form a differential pair, a pair of second differential transistors 23 and 24 that form a differential pair, a pair of auxiliary transistors 25 and 26, a fourth current source 64, a fifth current source 65, a sixth current source 66, and a seventh current source 67. The fourth current source 64, the fifth current source 65, the sixth current source 66, and the seventh current source 67 are each configured to pass a constant current. A power supply voltage VDD is applied to the fourth current source 64 and the fifth current source 65. The sixth current source 66 and the seventh current source 67 are connected to ground GND. The currents output from the fourth current source 64 and the fifth current source 65 are, for example, the same in magnitude. The currents output from the sixth current source 66 and the seventh current source 67 are, for example, the same in magnitude. The current output from the sixth current source 66 and the current output from the seventh current source 67 are smaller than the current output from the fourth current source 64 and the current output from the fifth current source 65, for example.

[0037] In this embodiment, the pair of first differential transistors 21, 22, the pair of second differential transistors 23, 24, and the pair of auxiliary transistors 25, 26 are field-effect transistors. More specifically, the pair of first differential transistors 21, 22 and the pair of second differential transistors 23, 24 are P-channel MOSFETs. The pair of auxiliary transistors 25, 26 are N-channel MOSFETs. The absolute values ​​Vth of the threshold voltages of the pair of first differential transistors 21, 22 are the same. The absolute values ​​Vth of the threshold voltages of the pair of second differential transistors 23, 24 are the same. The absolute values ​​Vth of the threshold voltages of the pair of auxiliary transistors 25, 26 are the same. The absolute value Vth of the threshold voltage of the pair of first differential transistors 21, 22, the absolute value Vth of the threshold voltage of the pair of second differential transistors 23, 24, and the absolute value Vth of the threshold voltage of the pair of auxiliary transistors 25, 26 are the same as, for example, the absolute value Vth of the threshold voltage of the third transistor 33 and the absolute value Vth of the threshold voltage of the fourth transistor 34.

[0038] The pair of first differential transistors 21, 22 are arranged in parallel between a fourth current source 64 connected to a power supply voltage VDD and an output circuit C. A source terminal 21s of the first differential transistor 21 and a source terminal 22s of the first differential transistor 22 are connected to each other. The source terminals 21s of the first differential transistor 21 and the source terminals 22s of the first differential transistor 22 are connected to the fourth current source 64. A drain terminal 21d of the first differential transistor 21 is connected to a terminal C1 of the output circuit C. A drain terminal 22d of the first differential transistor 22 is connected to a terminal C2 of the output circuit C. A gate terminal 21g of the first differential transistor 21 is connected to a first output wiring section 13. As a result, a voltage is output from the first output wiring section 13 to the first differential transistor 21. A gate terminal 22g of the first differential transistor 22 is connected to a second output wiring section 14. As a result, a voltage is output from the second output wiring section 14 to the first differential transistor 22.

[0039] The pair of second differential transistors 23, 24 are arranged in parallel with each other between a fifth current source 65 connected to a power supply voltage VDD and an output circuit C. A source terminal 23s of the second differential transistor 23 and a source terminal 24s of the second differential transistor 24 are connected to each other. The source terminals 23s of the second differential transistor 23 and the source terminals 24s of the second differential transistor 24 are connected to the fifth current source 65. A drain terminal 23d of the second differential transistor 23 is connected to a terminal C1 of the output circuit C. A drain terminal 24d of the second differential transistor 24 is connected to a terminal C2 of the output circuit C.

[0040] The first output wiring section 13 is connected to a gate terminal 25g of the auxiliary transistor 25. A power supply voltage VDD is applied to a drain terminal 25d of the auxiliary transistor 25. A source terminal 25s of the auxiliary transistor 25 is connected to a sixth current source 66 and a gate terminal 23g of the second differential transistor 23.

[0041] The second output wiring section 14 is connected to a gate terminal 26g of the auxiliary transistor 26. A power supply voltage VDD is applied to a drain terminal 26d of the auxiliary transistor 26. A source terminal 26s of the auxiliary transistor 26 is connected to a seventh current source 67 and a gate terminal 24g of the second differential transistor 24.

[0042] Next, the operation of the semiconductor device 100 will be described. First, a case where at least one of the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD is equal to or greater than the second predetermined value (absolute value Vth) will be described. In the following description, the case shown in FIG. 4, i.e., the case where the second voltage V2 is lower than the first voltage V1, will be used as an example. When at least one of the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD is equal to or greater than the second predetermined value (absolute value Vth), as described above, the voltage comparison circuit unit 50 turns off the fifth transistor 35 and the sixth transistor 36. Therefore, no current flows through the fifth transistor 35 and the sixth transistor 36.

[0043] Meanwhile, the voltage generating circuit unit 40 generates a third voltage V3 and applies it to the gate terminal 31g of the first transistor 31 and the gate terminal 32g of the second transistor 32. If the voltage at the source terminal 31s of the first transistor 31 is lower than the third voltage V3 by at least the threshold voltage, the first transistor 31 is turned on, and current flows from the drain terminal 31d to the source terminal 31s of the first transistor 31. When current flows through the first transistor 31, the voltage at the source terminal 31s attempts to rise toward the first voltage V1 applied to the drain terminal 31d. However, because only the third voltage V3, which is the sum of the second voltage V2 and the absolute value Vth of the threshold voltage, is applied to the gate terminal 31g, current becomes less likely to flow through the first transistor 31 as the voltage at the source terminal 31s rises. As a result, the voltage at the source terminal 31s can only rise to the third voltage V3 applied to the gate terminal 31g, and ultimately becomes the third voltage V3. As a result, the voltage of the first output wiring section 13 connected to the source terminal 31s of the first transistor 31 becomes the third voltage V3, and the third voltage V3 is applied to the gate terminal 21g of the first differential transistor 21 connected to the first output wiring section 13.

[0044] In the second transistor 32, the second voltage V2 is applied to the drain terminal 32d, and the third voltage V3 is applied to the gate terminal 32g. Therefore, even if a current flows through the second transistor 32 and the voltage of the source terminal 32s rises to the second voltage V2, the gate voltage remains equal to or higher than the threshold voltage, and the second transistor 32 remains in the ON state. Therefore, the voltage of the source terminal 32s becomes the second voltage V2, and the voltage of the second output wiring section 14 connected to the source terminal 32s of the second transistor 32 becomes the second voltage V2. As a result, the second voltage V2 is applied to the gate terminal 22g of the first differential transistor 22 connected to the source terminal 32s of the second transistor 32.

[0045] When the third voltage V3 is applied to the gate terminal 21g of the first differential transistor 21 and the second voltage V2 is applied to the gate terminal 22g of the first differential transistor 22, the current output from the fourth current source 64 is divided and flows through the first differential transistor 21 and the first differential transistor 22. At this time, the magnitude of the current flowing through each of the first differential transistors 21 and 22 is determined by the magnitude of the voltage applied to the gate terminal of each of the first differential transistors 21 and 22. In this embodiment, the first differential transistors 21 and 22 are P-channel MOSFETs, so the lower the voltage applied to the gate terminal, the easier it is for current to flow. Therefore, in the example of FIG. 4 , the current Ie2 flowing through the first differential transistor 22 to which the second voltage V2, which is lower than the third voltage V3, is applied, is larger than the current Ie1 flowing through the first differential transistor 21. The current Ie1 is output to the terminal C1 of the output circuit C, and the current Ie2 is output to the terminal C2 of the output circuit C. As a result, two different currents are output from the semiconductor device 100 to the output circuit C. For example, a resistor or the like may be disposed between the pair of first differential transistors 21, 22 and the output circuit C, so that two different voltages are output to the output circuit C.

[0046] Next, a case where both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are smaller than the second predetermined value (absolute value Vth) will be described. In the following description, the case shown in FIG. 5, i.e., the case where the second voltage V2 is lower than the first voltage V1, will be described as an example. When both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are smaller than the second predetermined value, both the first voltage V1 and the second voltage V2 are close to the power supply voltage VDD. Therefore, the gate voltages of the third transistor 33 and the fourth transistor 34 in the voltage generating circuit unit 40 cannot be lowered below the threshold voltage, and the third transistor 33 and the fourth transistor 34 are turned off. In this case, the voltages at the source terminal 33s of the third transistor 33 and the source terminal 34s of the fourth transistor 34 are the power supply voltage VDD, and the voltages applied to the gate terminal 31g of the first transistor 31 and the gate terminal 32g of the second transistor 32 are also the power supply voltage VDD. As a result, the voltage generating circuit unit 40 is unable to generate the third voltage V3.

[0047] On the other hand, as described above, when both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are smaller than the second predetermined value (absolute value Vth), the voltage comparison circuit unit 50 turns on the fifth transistor 35 and the sixth transistor 36. As a result, the voltage at the drain terminal 35d of the fifth transistor 35 becomes the first voltage V1, which is the same as the voltage at the source terminal 35s, and the voltage at the drain terminal 36d of the sixth transistor 36 becomes the second voltage V2, which is the same as the voltage at the source terminal 36s. As a result, the first voltage V1 is applied to the gate terminal 21g of the first differential transistor 21, and the second voltage V2 is applied to the gate terminal 22g of the first differential transistor 22.

[0048] In this case, the differences between the first voltage V1 and the second voltage V2 and the power supply voltage VDD are lower than the absolute value Vth of the threshold voltages of the first differential transistors 21 and 22. Therefore, even when the first voltage V1 and the second voltage V2 are applied to the first differential transistors 21 and 22, respectively, the first differential transistors 21 and 22 remain in the OFF state. Meanwhile, in this case, the first voltage V1 is also applied to the gate terminal 25g of the auxiliary transistor 25, and the second voltage V2 is also applied to the gate terminal 26g of the auxiliary transistor 26. As a result, the auxiliary transistors 25 and 26 are turned ON, and a current output to ground GND by the sixth current source 66 or the seventh current source 67 flows from the drain terminal to the source terminal of the auxiliary transistors 25 and 26. As a result, the voltages of the source terminals 25s and 26s of the auxiliary transistors 25 and 26 rise, but the voltages of the source terminals 25s and 26s remain at the minimum voltage value required to keep the auxiliary transistors 25 and 26 in the ON state. That is, the voltages at the source terminals 25s, 26s are lower than the voltages applied to the gate terminals 25g, 26g by the absolute value Vth of the threshold voltage of each auxiliary transistor 25, 26. Therefore, the voltage at the source terminal 25s of the auxiliary transistor 25 is a voltage V1a that is lower than the first voltage V1 by the absolute value Vth of the threshold voltage of the auxiliary transistor 25. The voltage at the source terminal 26s of the auxiliary transistor 26 is a voltage V2a that is lower than the second voltage V2 by the absolute value Vth of the threshold voltage of the auxiliary transistor 26. As a result, the voltage V1a is applied to the gate terminal 23g of the second differential transistor 23, and the voltage V2a is applied to the gate terminal 24g of the second differential transistor 24.

[0049] Because the voltages V1a and V2a are lower than the power supply voltage VDD by at least the absolute value of the threshold voltages of the pair of second differential transistors 23 and 24, both of the pair of second differential transistors 23 and 24 are turned ON. As a result, current from the fifth current source 65 flows through each of the pair of second differential transistors 23 and 24 at a rate based on the magnitude of the voltage applied to each of the gate terminals 23g and 24g. In the example of FIG. 5, because the voltage V2a is lower than the voltage V1a, the second differential transistor 24 is more likely to pass current than the second differential transistor 23. As a result, the current Ie4 flowing through the second differential transistor 24 is larger than the current Ie3 flowing through the second differential transistor 23. The current Ie3 is output to the terminal C1 of the output circuit C, and the current Ie4 is output to the terminal C2 of the output circuit C. As a result, two different currents are output from the semiconductor device 100 to the output circuit C. In this case, for example, a resistor or the like may be disposed between the pair of second differential transistors 23, 24 and the output circuit C, so that two different voltages are input to the output circuit C.

[0050] Note that when both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are equal to or greater than the second predetermined value (absolute value Vth) and the difference between the first voltage V1 and the second voltage V2 is equal to or less than the first predetermined value (absolute value Vth), the third voltage V3 is generated as described above, but the third voltage V3 is equal to or greater than the higher of the first voltage V1 and the second voltage V2. That is, the third voltage V3 is equal to or greater than the first voltage V1 and the second voltage V2. In this case, both the first transistor 31 and the second transistor 32 are turned ON, and the first voltage V1 is applied to the gate terminal 21g of the first differential transistor 21 and the second voltage V2 is applied to the gate terminal 22g of the first differential transistor 22.

[0051] For example, when the difference between the voltages applied to the gate terminals of a pair of first differential transistors 21 and 22 is large, a large amount of current flows through one of the first differential transistors having a lower voltage applied to its gate terminal, resulting in a lower voltage at the source terminal of that first differential transistor. In this case, the voltage at the source terminal of the other first differential transistor connected to the source terminal of that first differential transistor also decreases. Meanwhile, because a higher voltage is applied to the gate terminal of the other first differential transistor than to the gate terminal of the first differential transistor, the voltage difference between the source terminal and gate terminal of the other first differential transistor increases. If this condition persists, the first differential transistors deteriorate, causing a BTI phenomenon in which the threshold voltage of the first differential transistor fluctuates.

[0052] In contrast, according to this embodiment, the input circuit 10, which inputs a voltage to each of the gate terminals 21g, 22g (drive terminals) of a pair of first differential transistors 21, 22 that constitute a differential pair, includes a first input wiring section 11 to which a first voltage V1 is applied, a second input wiring section 12 to which a second voltage V2 different from the first voltage V1 is applied, a first output wiring section 13 that outputs a voltage to one of the pair of first differential transistors 21, 22, a second output wiring section 14 that outputs a voltage to the other of the pair of first differential transistors 21, 22, a voltage generation circuit section 40 that generates a third voltage V3 based on at least one of the first voltage V1 and the second voltage V2, a first transistor 31 arranged between the first input wiring section 11 and the first output wiring section 13, and a second transistor 32 arranged between the second input wiring section 12 and the second output wiring section 14. A third voltage V3 is applied to a gate terminal 31g (drive terminal) of the first transistor 31 and a gate terminal 32g (drive terminal) of the second transistor 32. When the difference between the first voltage V1 and the second voltage V2 is larger than the absolute value Vth (first predetermined value) of the threshold voltages of the third transistor 33 and the fourth transistor 34, the difference between the lower of the first voltage V1 and the second voltage V2 and the third voltage V3 is smaller than the difference between the first voltage V1 and the second voltage V2. When the difference between the first voltage V1 and the second voltage V2 is larger than the absolute value Vth of the threshold voltages of the third transistor 33 and the fourth transistor 34, as described above, the lower of the first voltage V1 and the second voltage V2 is applied directly to one of the pair of first differential transistors 21, 22 via one of the first transistor 31 and the second transistor 32, and the higher of the first voltage V1 and the second voltage V2 is converted to the third voltage V3 via the other of the first transistor 31 and the second transistor 32 and applied to the other of the pair of first differential transistors 21, 22. In this case, the difference between the lower of the first voltage V1 and the second voltage V2 and the third voltage V3 is smaller than the difference between the first voltage V1 and the second voltage V2, so the third voltage V3 is lower than the higher of the first voltage V1 and the second voltage V2. This makes it possible to reduce the voltage difference applied to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22.Therefore, even if a voltage continues to be applied to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22 when the difference between the first voltage V1 and the second voltage V2 is greater than the absolute value Vth, which is the first predetermined value, the BTI phenomenon can be suppressed. Furthermore, when the higher voltage of the first voltage V1 and the second voltage V2 is converted to the third voltage V3 via the other of the first transistor 31 and the second transistor 32, the other transistor is substantially in the OFF state, resulting in a very large impedance of the other transistor. As a result, almost no current flows through the other transistor, and even if a current does flow, it is extremely small. As described above, according to this embodiment, the BTI phenomenon can be suppressed while suppressing the flow of current between the first input terminal 10a and the second input terminal 10b.

[0053] Alternatively, for example, the second voltage V2 may be a separately generated internal voltage rather than a voltage input from the second input terminal 10b, and the first voltage V1 may be converted to a voltage lower than the first voltage V1 using the internal voltage and a transistor. However, this requires a separate internal voltage lower than the first voltage V1, which poses a problem that only one voltage higher than the internal voltage can be input to the input circuit. In other words, the voltage range usable as input to the input circuit is limited to the internal voltage. In contrast, in this embodiment, the voltage generation circuit unit 40 generates the third voltage V3 based on at least one of the first voltage V1 and the second voltage V2. Therefore, a third voltage V3 of an appropriate magnitude can be generated in accordance with the magnitude of at least one of the input first voltage V1 and the second voltage V2 without the need for a separate internal voltage. This allows the voltages input to the input circuit 10 to be limited to two, the first voltage V1 and the second voltage V2 input from the first input terminal 10a and the second input terminal 10b, and the voltage range that can be input to the input circuit 10 can be made equal to or greater than the ground GND voltage, i.e., 0V.

[0054] Furthermore, according to this embodiment, the voltage generating circuit unit 40 generates the third voltage V3 based on the lower of the first voltage V1 and the second voltage V2. Therefore, compared to generating the third voltage V3 based on the higher of the first voltage V1 and the second voltage V2, the third voltage V3 can be made closer to the lower of the first voltage V1 and the second voltage V2. This can further reduce the difference in voltages applied to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22. Therefore, the occurrence of the BTI phenomenon can be further suppressed.

[0055] Furthermore, according to this embodiment, the first predetermined value is the absolute value Vth of the threshold voltages of the third transistor 33 and the fourth transistor 34 included in the voltage generating circuit unit 40. The value of the third voltage V3 is the value obtained by adding the absolute value Vth of the threshold voltages of the third transistor 33 and the fourth transistor 34 included in the voltage generating circuit unit 40 to the value of the lower voltage of the first voltage V1 or the second voltage V2. This makes it possible to suitably reduce the difference between the second voltage V2 and the third voltage V3, thereby more suitably reducing the difference in voltages applied to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22. This more suitably prevents the BTI phenomenon from occurring.

[0056] Furthermore, according to this embodiment, the voltage generating circuit unit 40 includes a third transistor 33 having a gate terminal 33g (drive terminal) connected to the first input wiring unit 11 and a fourth transistor 34 having a gate terminal 34g (drive terminal) connected to the second input wiring unit 12. The source terminal 33s (first terminal) of the third transistor 33 and the source terminal 34s (first terminal) of the fourth transistor 34 are connected to each other and to the gate terminal 31g (drive terminal) of the first transistor 31 and the gate terminal 32g (drive terminal) of the second transistor 32. The drain terminal 33d (second terminal) of the third transistor 33 and the drain terminal 34d (second terminal) of the fourth transistor 34 are connected to each other. Therefore, the degree of ON / OFF of each transistor can be changed depending on the magnitude relationship between the first voltage V1 applied to the gate terminal 33g of the third transistor 33 and the second voltage V2 applied to the gate terminal 34g of the fourth transistor 34. This allows the third voltage V3 to be generated as the voltage at the source terminal of each transistor as described above, and the third voltage V3 to be applied to the gate terminal 31g of the first transistor 31 and the gate terminal 32g of the second transistor 32.

[0057] Furthermore, according to this embodiment, the voltage generating circuit unit 40 has a first current source 61 connected to the source terminal 33s (first terminal) of the third transistor 33 and the source terminal 34s (first terminal) of the fourth transistor 34. The third transistor 33 and the fourth transistor 34 are arranged in parallel between a power supply voltage wiring unit 41 to which a power supply voltage VDD is applied and ground GND. The first current source 61 is connected to the power supply voltage wiring unit 41. Therefore, as described above, the ease of current flow between the third transistor 33 and the fourth transistor 34 changes depending on the magnitude relationship between the first voltage V1 and the second voltage V2, and the third voltage V3 can be generated based on the voltage applied to the gate terminal of the transistor through which the current Id1 from the first current source 61 flows more easily. In this embodiment, since the third transistor 33 and the fourth transistor 34 are P-channel field effect transistors, the current Id1 output from the first current source 61 is more likely to flow through the transistor to which the lower of the first voltage V1 and the second voltage V2 is applied, and a third voltage V3 can be generated that is higher than the lower of the first voltage V1 and the second voltage V2 by the absolute value Vth of the threshold voltage.

[0058] Furthermore, according to the present embodiment, the input circuit 10 includes a voltage comparison circuit unit 50 that compares the first voltage V1 and the second voltage V2 with a power supply voltage VDD, a fifth transistor 35 that is arranged between the first input wiring unit 11 and the first output wiring unit 13 and connected in parallel to the first transistor 31, and a sixth transistor 36 that is arranged between the second input wiring unit 12 and the second output wiring unit 14 and connected in parallel to the second transistor 32. The voltage comparison circuit unit 50 turns the fifth transistor 35 and the sixth transistor 36 off when at least one of the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD is equal to or greater than the absolute value Vth of a threshold voltage (a second predetermined value), and turns the fifth transistor 35 and the sixth transistor 36 on when both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are smaller than the absolute value Vth. Therefore, as described above, when both the first voltage V1 and the second voltage V2 are close to the power supply voltage VDD and the third voltage V3 cannot be generated properly in the voltage generating circuit unit 40, the fifth transistor 35 and the sixth transistor 36 can be turned on, and the first voltage V1 and the second voltage V2 can be applied directly to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22, respectively. This allows different voltages to be applied to the pair of first differential transistors 21 and 22, even when the third voltage V3 cannot be generated properly. Furthermore, in this case, because both the first voltage V1 and the second voltage V2 are close to the power supply voltage VDD, the difference between the first voltage V1 and the second voltage V2 is small. Therefore, even if the first voltage V1 and the second voltage V2 continue to be applied directly to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22, the BTI phenomenon can be suppressed.

[0059] Furthermore, when both the difference between the first voltage V1 and the power supply voltage VDD and the difference between the second voltage V2 and the power supply voltage VDD are equal to or greater than the second predetermined value (absolute value Vth) and the difference between the first voltage V1 and the second voltage V2 is equal to or less than the first predetermined value (absolute value Vth), as described above, the first voltage V1 and the second voltage V2 are applied as is to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22. However, even in this case, because the difference between the first voltage V1 and the second voltage V2 is equal to or less than the first predetermined value (absolute value Vth), the occurrence of BTI can be suppressed even if the state in which the first voltage V1 and the second voltage V2 are applied as is to the gate terminals 21g and 22g of the pair of first differential transistors 21 and 22 continues.

[0060] As described above, in this embodiment, even if the first voltage V1 and the second voltage V2 input to the input circuit 10 are any value within the range of 0 V or more and the power supply voltage VDD or less, two voltages based on the first voltage V1 and the second voltage V2 can be input to the differential circuit 20 while suppressing the occurrence of the BTI phenomenon.

[0061] According to this embodiment, the voltage comparison circuit unit 50 includes a seventh transistor 37 having a gate terminal 37g (drive terminal) connected to the first input wiring unit 11, an eighth transistor 38 having a gate terminal 38g (drive terminal) connected to the second input wiring unit 12, a second current source 62 to which a power supply voltage VDD is applied, and a third current source 63 connected to ground GND. The seventh transistor 37 and the eighth transistor 38 are arranged in parallel between the output side of the second current source 62 and the input side of the third current source 63. The drain terminal 37d (output terminal) of the seventh transistor 37 and the drain terminal 38d (output terminal) of the eighth transistor 38 are connected to each other and to the third current source 63, the gate terminal 35g (drive terminal) of the fifth transistor 35, and the gate terminal 36g (drive terminal) of the sixth transistor 36. The current Id3 output by the third current source 63 is smaller than the current Id2 output by the second current source 62. Therefore, when at least one of the seventh transistor 37 and the eighth transistor 38 is ON, the current Id2 flowing from the second current source 62 cannot be fully diverted to ground GND, and the voltages at the drain terminals 37d of the seventh transistor 37 and 38d of the eighth transistor 38 become equal to the power supply voltage VDD. On the other hand, when both the seventh transistor 37 and the eighth transistor 38 are OFF, the voltages at the drain terminals 37d of the seventh transistor 37 and 38d of the eighth transistor 38 become equal to the reference potential of ground GND, i.e., 0V. Therefore, by switching the states of the seventh transistor 37 and the eighth transistor 38 depending on the magnitudes of the first voltage V1 and the second voltage V2 relative to the power supply voltage VDD, the voltages applied to the gate terminal 35g of the fifth transistor 35 and the gate terminal 36g of the sixth transistor 36 can be switched between the power supply voltage VDD and 0V. This allows the states of the fifth transistor 35 and the sixth transistor 36 to be suitably switched.

[0062] Furthermore, according to this embodiment, the input circuit 10 includes a first diode 71 having an anode connected to the first output wiring section 13 and a cathode connected to the second output wiring section 14, and a second diode 72 having an anode connected to the second output wiring section 14 and a cathode connected to the first output wiring section 13. Therefore, even if an unintended charge is applied to the output wiring section connected to one of the first transistor 31 and the second transistor 32 that is in a substantially OFF state, the charge can be released via the first diode 71 or the second diode 72.

[0063] FIG. 6 is a circuit diagram showing the current Ie5 that flows when the first diode 71 releases charge. FIG. 6 illustrates a case where the first voltage V1 is higher than the second voltage V2 and the first transistor 31 is substantially in an OFF state. In this case, the voltage of the first output wiring unit 13 connected to the source terminal 31s of the first transistor 31 is the third voltage V3, as described above. In this case, without the first diode 71, even if charge is applied to the first output wiring unit 13 for some reason, there is no place for the charge to escape, and the voltage of the first output wiring unit 13 may become higher than the third voltage V3. In contrast, according to this embodiment, the provision of the first diode 71 allows the current Ie5 to flow and release charge when the voltage of the first output wiring unit 13 increases. The current Ie5 flows from the first input terminal 10a through the first input wiring section 11, the first transistor 31, the first output wiring section 13, the first diode 71, the second output wiring section 14, the second transistor 32, and the second input wiring section 12 in this order, and then to the second input terminal 10b. Even in this case, the impedance of the first transistor 31 is sufficiently large, so the magnitude of the flowing current Ie5 can be suitably reduced.

[0064] FIG. 7 is a circuit diagram showing the current Ie6 that flows when the second diode 72 releases charge. This diagram illustrates a case where the second voltage V2 is higher than the first voltage V1 and the second transistor 32 is substantially in an OFF state. In this case, the provision of the second diode 72 allows the current Ie6 to flow and release charge when the voltage of the second output wiring section 14 rises. The current Ie6 flows from the second input terminal 10b through the second input wiring section 12, the second transistor 32, the second output wiring section 14, the second diode 72, the first output wiring section 13, the first transistor 31, and the first input wiring section 11, in this order, to the first input terminal 10a. Even in this case, the impedance of the second transistor 32 is sufficiently large, allowing the magnitude of the flowing current Ie6 to be suitably reduced.

[0065] According to at least one of the above-described embodiments, the input circuit is an input circuit that inputs a voltage to each of the drive terminals of a pair of differential transistors that form a differential pair. The input circuit includes a first input wiring section to which a first voltage is applied, a second input wiring section to which a second voltage different from the first voltage is applied, a first output wiring section that outputs a voltage to one of the pair of differential transistors, a second output wiring section that outputs a voltage to the other of the pair of differential transistors, a voltage generation circuit section that generates a third voltage based on at least one of the first voltage and the second voltage, a first transistor disposed between the first input wiring section and the first output wiring section, and a second transistor disposed between the second input wiring section and the second output wiring section. The third voltage is applied to the drive terminal of the first transistor and the drive terminal of the second transistor. When the difference between the first voltage and the second voltage is greater than a first predetermined value, the difference between the lower of the first voltage and the second voltage and the third voltage is smaller than the difference between the first voltage and the second voltage. This prevents current from flowing between the input terminals and prevents the BTI phenomenon from occurring.

[0066] In the above-described embodiment, the absolute values ​​of the threshold voltages of the transistors are the same, but this is not limiting. The multiple transistors in the above-described embodiment may include transistors whose absolute values ​​of threshold voltages are different from each other. The voltage generation circuit unit may have any configuration as long as it generates the third voltage based on at least one of the first voltage and the second voltage. The voltage generation circuit unit may be a circuit that generates the third voltage based on the higher of the first voltage and the second voltage, or a circuit that generates the third voltage based on both the first voltage and the second voltage. The third voltage generated by the voltage generation circuit unit may be a voltage of any value as long as the difference between the lower of the first voltage and the second voltage is smaller than the difference between the first voltage and the second voltage when the difference between the first voltage and the second voltage is greater than a first predetermined value.

[0067] The first current source in the voltage generating circuit unit may be connected to ground. In this case, for example, the third voltage may be generated based on the higher of the first voltage and the second voltage, and the value of the third voltage may be the value obtained by subtracting the absolute value of the threshold voltage of the third transistor or the fourth transistor from the value of the higher voltage. Even in this case, the difference between the two voltages applied to the pair of differential transistors is smaller than the difference between the first voltage and the second voltage, thereby preventing the BTI phenomenon from occurring. In this case, the third transistor and the fourth transistor may be, for example, N-channel transistors.

[0068] The voltage comparison circuit unit may be a circuit of any configuration as long as it turns the fifth transistor and the sixth transistor to an OFF state when at least one of the difference between the first voltage and the power supply voltage and the difference between the second voltage and the power supply voltage is equal to or greater than a second predetermined value, and turns the fifth transistor and the sixth transistor to an ON state when both the difference between the first voltage and the power supply voltage and the difference between the second voltage and the power supply voltage are smaller than the second predetermined value.

[0069] Each of the transistors in the above-described embodiments, including the first to eighth transistors, may be any type of transistor. Each of the transistors may be an N-channel field-effect transistor or a P-channel field-effect transistor. At least one of the transistors may be a bipolar transistor.

[0070] The input circuit and the semiconductor device according to the embodiments include the following additional aspects. (Appendix 1) An input circuit that inputs a voltage to each of drive terminals of a pair of differential transistors that form a differential pair, a first input wiring section to which a first voltage is applied; a second input wiring section to which a second voltage different from the first voltage is applied; a first output wiring section that outputs a voltage to one of the pair of differential transistors; a second output wiring section that outputs a voltage to the other of the pair of differential transistors; a voltage generating circuit unit that generates a third voltage based on at least one of the first voltage and the second voltage; a first transistor disposed between the first input wiring section and the first output wiring section; a second transistor disposed between the second input wiring section and the second output wiring section; Equipped with the third voltage is applied to a drive terminal of the first transistor and a drive terminal of the second transistor; an input circuit, wherein when the difference between the first voltage and the second voltage is greater than a first predetermined value, the difference between the lower of the first voltage and the second voltage and the third voltage is smaller than the difference between the first voltage and the second voltage. (Appendix 2) 2. The input circuit according to claim 1, wherein the voltage generating circuit unit generates the third voltage based on a lower voltage of the first voltage and the second voltage. (Appendix 3) the first predetermined value is an absolute value of a threshold voltage of a transistor included in the voltage generating circuit unit, The input circuit according to claim 2, wherein the value of the third voltage is the value of the lower of the first voltage and the second voltage plus the absolute value of the threshold voltage of a transistor included in the voltage generating circuit unit. (Appendix 4) The voltage generating circuit unit a third transistor having a drive terminal connected to the first input wiring portion; a fourth transistor having a drive terminal connected to the second input wiring portion; and a first terminal of the third transistor and a first terminal of the fourth transistor are connected to each other and to a driving terminal of the first transistor and a driving terminal of the second transistor; 4. The input circuit according to claim 1, wherein the second terminal of the third transistor and the second terminal of the fourth transistor are connected to each other. (Appendix 5) the voltage generating circuit unit has a first current source connected to the first terminal of the third transistor and the first terminal of the fourth transistor; the third transistor and the fourth transistor are arranged in parallel with each other between a power supply voltage wiring portion to which a power supply voltage is applied and ground, 5. The input circuit according to claim 4, wherein the first current source is connected to the power supply voltage wiring section or the ground. (Appendix 6) a voltage comparison circuit unit that compares the first voltage and the second voltage with the power supply voltage; a fifth transistor disposed between the first input wiring section and the first output wiring section and connected in parallel to the first transistor; a sixth transistor disposed between the second input wiring section and the second output wiring section and connected in parallel to the second transistor; Equipped with The voltage comparison circuit unit turning the fifth transistor and the sixth transistor into an OFF state when at least one of a difference between the first voltage and the power supply voltage and a difference between the second voltage and the power supply voltage is equal to or greater than a second predetermined value; 6. The input circuit of claim 5, wherein the fifth transistor and the sixth transistor are turned on when both a difference of the first voltage from the power supply voltage and a difference of the second voltage from the power supply voltage are smaller than the second predetermined value. (Appendix 7) The voltage comparison circuit unit a seventh transistor having a drive terminal connected to the first input wiring portion; an eighth transistor having a drive terminal connected to the second input wiring portion; a second current source to which the power supply voltage is applied; a third current source connected to the ground; and the seventh transistor and the eighth transistor are arranged in parallel with each other between the output side of the second current source and the input side of the third current source, an output terminal of the seventh transistor and an output terminal of the eighth transistor are connected to each other, and are also connected to the third current source, a driving terminal of the fifth transistor, and a driving terminal of the sixth transistor; 7. The input circuit of claim 6, wherein the current output by the third current source is smaller than the current output by the second current source. (Appendix 8) a first diode having an anode connected to the first output wiring portion and a cathode connected to the second output wiring portion; a second diode having an anode connected to the second output wiring portion and a cathode connected to the first output wiring portion; 8. The input circuit of claim 1, comprising: (Appendix 9) an input circuit according to any one of Supplementary Note 1 to Supplementary Note 8; a differential circuit having the pair of differential transistors; A semiconductor device comprising:

[0071] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0072] 10...input circuit, 11...first input wiring section, 12...second input wiring section, 13...first output wiring section, 14...second output wiring section, 20...differential circuit, 21, 22...first differential transistor (differential transistor), 31...first transistor, 32...second transistor, 33...third transistor, 33d, 34d...drain terminal (second terminal), 33s, 34s...source terminal (first terminal), 34...fourth transistor, 35...fifth transistor, 36...sixth transistor transistor, 37...seventh transistor, 37d, 38d...drain terminal (output terminal), 38...eighth transistor, 40...voltage generating circuit section, 41...power supply voltage wiring section, 50...voltage comparison circuit section, 61...first current source, 62...second current source, 63...third current source, 71...first diode, 72...second diode, 100...semiconductor device, GND...ground, V1...first voltage, V2...second voltage, V3...third voltage, VDD...power supply voltage, Vth...absolute value of threshold voltage

Claims

1. An input circuit that inputs a voltage to each of drive terminals of a pair of differential transistors that form a differential pair, a first input wiring section to which a first voltage is applied; a second input wiring portion to which a second voltage different from the first voltage is applied; a first output wiring section that outputs a voltage to one of the pair of differential transistors; a second output wiring section that outputs a voltage to the other of the pair of differential transistors; a voltage generating circuit unit that generates a third voltage based on at least one of the first voltage and the second voltage; a first transistor disposed between the first input wiring section and the first output wiring section; a second transistor disposed between the second input wiring section and the second output wiring section; Equipped with the third voltage is applied to a drive terminal of the first transistor and a drive terminal of the second transistor; an input circuit, wherein when a difference between the first voltage and the second voltage is greater than a first predetermined value, a difference between a lower voltage of the first voltage and the second voltage and the third voltage is smaller than a difference between the first voltage and the second voltage.

2. 2. The input circuit according to claim 1, wherein the voltage generating circuit generates the third voltage based on the lower of the first voltage and the second voltage.

3. the first predetermined value is an absolute value of a threshold voltage of a transistor included in the voltage generating circuit unit, 3. The input circuit according to claim 2, wherein the value of the third voltage is a value obtained by adding the absolute value of a threshold voltage of a transistor included in the voltage generating circuit unit to the value of the lower voltage of the first voltage and the second voltage.

4. The voltage generating circuit unit a third transistor having a drive terminal connected to the first input wiring portion; a fourth transistor having a drive terminal connected to the second input wiring portion; and a first terminal of the third transistor and a first terminal of the fourth transistor are connected to each other and to a driving terminal of the first transistor and a driving terminal of the second transistor; 2. The input circuit according to claim 1, wherein the second terminal of the third transistor and the second terminal of the fourth transistor are connected to each other.

5. the voltage generating circuit unit has a first current source connected to the first terminal of the third transistor and the first terminal of the fourth transistor; the third transistor and the fourth transistor are arranged in parallel with each other between a power supply voltage wiring portion to which a power supply voltage is applied and ground, 5. The input circuit according to claim 4, wherein the first current source is connected to the power supply voltage wiring section or the ground.

6. a voltage comparison circuit unit that compares the first voltage and the second voltage with the power supply voltage; a fifth transistor disposed between the first input wiring section and the first output wiring section and connected in parallel to the first transistor; a sixth transistor disposed between the second input wiring section and the second output wiring section and connected in parallel to the second transistor; Equipped with The voltage comparison circuit unit when at least one of a difference between the first voltage and the power supply voltage and a difference between the second voltage and the power supply voltage is equal to or greater than a second predetermined value, the fifth transistor and the sixth transistor are turned off; 6. The input circuit according to claim 5, wherein the fifth transistor and the sixth transistor are turned on when both the difference of the first voltage from the power supply voltage and the difference of the second voltage from the power supply voltage are smaller than the second predetermined value.

7. The voltage comparison circuit unit a seventh transistor having a drive terminal connected to the first input wiring portion; an eighth transistor having a drive terminal connected to the second input wiring portion; a second current source to which the power supply voltage is applied; a third current source connected to the ground; and the seventh transistor and the eighth transistor are arranged in parallel with each other between the output side of the second current source and the input side of the third current source, an output terminal of the seventh transistor and an output terminal of the eighth transistor are connected to each other, and are also connected to the third current source, a drive terminal of the fifth transistor, and a drive terminal of the sixth transistor; 7. The input circuit according to claim 6, wherein the current output by the third current source is smaller than the current output by the second current source.

8. a first diode having an anode connected to the first output wiring portion and a cathode connected to the second output wiring portion; a second diode having an anode connected to the second output wiring portion and a cathode connected to the first output wiring portion; 2. The input circuit of claim 1, comprising:

9. an input circuit according to any one of claims 1 to 8; a differential circuit having the pair of differential transistors; A semiconductor device comprising:

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