Composite electronic component

Abstract

To provide composite electronic components that are each able to suppress an increase in electrical resistance, while handling a large current.SOLUTION: A composite electronic component 1 includes a multilayer ceramic capacitor 10 including a multilayer body 12 and first to fourth external electrodes 30a-30d, and a conductor portion (chip type coil component) 40 electrically connected to the first and second external electrodes. The first external electrode includes a first region disposed on a surface on the side of a first face 12a and a second region disposed on a surface on the side of a third face 12c. The conductor portion includes: a first body electrode 60a connected to the first external electrode by a first electrically conductive adhesive 70a; and a second body electrode 60b connected to the second external electrode by a second electrically conductive adhesive 70b. When Rdc1 represents the DC resistance of the multilayer ceramic capacitor and Rdc2 represents the DC resistance of the conductor portion, Rdc2≤Rdc1 is satisfied. The first electrically conductive adhesive is arranged from the first region to the second region in the first external electrode.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a composite electronic component. [Background technology]

[0002] For example, feedthrough three-terminal capacitors are known as decoupling capacitors used to stabilize power supply voltages supplied to integrated circuit components (ICs) operating at high speeds and as noise suppression components for power lines supplied to integrated circuit components (ICs). A feedthrough three-terminal capacitor generally includes a laminate having first and second principal surfaces facing each other, fifth and sixth surfaces facing each other, and third and fourth surfaces facing each other. A plurality of first and second internal electrode layers are alternately arranged in the lamination direction within the laminate. The first internal electrode layer has both ends extending to the third and fourth surfaces, and the second internal electrode layer has both ends extending to the fifth and sixth surfaces. The first internal electrode layer is connected to the first and second external electrodes, and the second internal electrode layer is connected to the third and fourth external electrodes.

[0003] When a typical feedthrough three-terminal capacitor is used as a noise filter, a direct current flows through the signal internal electrodes (first internal electrode layers). However, when the capacitance is low, the number of signal internal electrodes (first internal electrode layers) decreases, which increases the direct current resistance and causes the problem of increased heat being generated by the capacitor.

[0004] Therefore, as a structure of a low-capacitance feedthrough three-terminal capacitor that can suppress an increase in capacitance while suppressing an increase in DC resistance, a structure such as that shown in Patent Document 1 is provided. By increasing the number of signal internal electrodes (first internal electrode layers) and arranging the signal internal electrodes (first internal electrode layers) to face each other, both the capacitance and the DC resistance are suppressed. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 9-55335 Summary of the Invention [Problem to be solved by the invention]

[0006] However, the structure described in Patent Document 1 has the following problems. That is, there is a limit to how many signal internal electrodes (first internal electrode layers) can be increased within the given size constraints, making it difficult to handle larger currents. Furthermore, it is necessary to design the internal structure individually for each capacitance, which reduces the expandability of the product lineup. Furthermore, when the volume of the metal component at the ridge line of the multilayer ceramic capacitor becomes smaller, the electrical resistance increases.

[0007] Therefore, a main object of the present invention is to provide a composite electronic component that can handle a large current while suppressing an increase in electrical resistance. [Means for solving the problem]

[0008] The composite electronic component according to the present invention comprises: a laminate having a first surface and a second surface opposed to each other in the stacking direction, a third surface and a fourth surface opposed to each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface opposed to each other in a second direction perpendicular to the stacking direction and the first direction; a multilayer ceramic capacitor including first external electrodes arranged on the first surface and the third surface, second external electrodes arranged on the first surface and the fourth surface, a third external electrode arranged on the fifth surface and the first surface, and a fourth external electrode arranged on the sixth surface and the first surface; a conductor portion electrically connected to a first external electrode, wherein the first external electrode has a first region arranged on the surface on the first face side and a second region arranged on the surface on the third face side; the conductor portion has a first electrode connected to the first external electrode by a first conductive adhesive and a second electrode connected to the second external electrode by a second conductive adhesive; and wherein, when the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the conductor portion is Rdc2, Rdc2≦Rdc1; and the first conductive adhesive is arranged across the first region and the second region of the first external electrode.

[0009] In the composite electronic component according to the present invention, when the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the conductor portion is Rdc2, Rdc2≦Rdc1 holds. This allows AC current to flow preferentially through the multilayer ceramic capacitor with lower impedance, while DC current can flow through the portion with lower DC resistance. The first conductive adhesive is disposed across the first and second regions of the first external electrode, which increases the volume of the metal component at at least one ridge portion of the multilayer ceramic capacitor, thereby suppressing an increase in electrical resistance. [Effects of the Invention]

[0010] According to the present invention, it is possible to provide a composite electronic component that can handle a large current while suppressing an increase in electrical resistance.

[0011] The above and other objects, features, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments of the present invention, which proceeds with reference to the accompanying drawings. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is an external perspective view showing a stacked composite electronic component according to a first embodiment of the present invention. [Figure 2] 1 is a front view of a composite electronic component according to a first embodiment of the present invention. [Figure 3] FIG. 2 is a bottom view of the composite electronic component according to the first embodiment of the present invention. [Figure 4] 1 is a plan view of a composite electronic component according to a first embodiment of the present invention. [Figure 5] FIG. 4 is a cross-sectional view taken along line VV in FIG. [Figure 6] 5. (a) is an enlarged view of part A in FIG. 5, and (b) is an enlarged view of part B in FIG. [Figure 7] FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. [Figure 8] 1(a) is an external perspective view of a multilayer ceramic capacitor included in a composite electronic component according to a first embodiment of the present invention, and FIG. 1(b) is an external perspective view of the multilayer ceramic capacitor from another direction. [Figure 9] 1 is an exploded perspective view schematically showing a configuration of a main part of a multilayer ceramic capacitor included in a composite electronic component according to a first embodiment of the present invention. [Figure 10] 1 is an exploded perspective view schematically showing the configuration of a main part of a multilayer ceramic conductor portion (chip-type coil component) included in a composite electronic component according to a first embodiment of the present invention. [Figure 11] 1 is a cross-sectional view in the stacking direction showing a mounting structure of a composite electronic component according to a first embodiment of the present invention. [Figure 12] FIG. 10 is an external perspective view showing a composite electronic component according to a second embodiment of the present invention. [Figure 13] FIG. 10 is a front view of a composite electronic component according to a second embodiment of the present invention. [Figure 14] FIG. 14 is a cross-sectional view taken along line XIV-XIV in FIG. [Figure 15] FIG. 6 is a cross-sectional view showing an example of a conductor portion included in a composite electronic component according to a second embodiment of the present invention. [Figure 16a] FIG. 10 is a cross-sectional view showing a first modified example of a conductor portion according to a second embodiment of the present invention. [Figure 16b] FIG. 10 is a cross-sectional view showing a second modified example of a conductor portion according to the second embodiment of the present invention. [Figure 16c] FIG. 10 is a cross-sectional view showing a third modified example of the conductor portion according to the second embodiment of the present invention. [Figure 16d] FIG. 10 is a cross-sectional view showing a fourth modified example of the conductor portion according to the second embodiment of the present invention. [Figure 17] FIG. 10 is a cross-sectional view in the lamination direction showing a mounting structure of a composite electronic component according to a second embodiment of the present invention. [Figure 18] FIG. 10 is an external perspective view showing a composite electronic component according to a third embodiment of the present invention. [Figure 19] FIG. 10(a) is a front view of a composite electronic component according to a third embodiment of the present invention, and FIG. 10(b) is a rear view of the composite electronic component according to the third embodiment of the present invention. [Figure 20] FIG. 10 is an external perspective view showing a composite electronic component according to a fourth embodiment of the present invention. [Figure 21] FIG. 10 is a front view of a composite electronic component according to a fourth embodiment of the present invention. [Figure 22] FIG. 3 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. [Figure 23] FIG. 3 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. [Figure 24] FIG. 4 is a cross-sectional view showing a dielectric layer on which a first internal electrode layer is arranged in a first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. [Figure 25] FIG. 4 is a cross-sectional view showing a dielectric layer on which a second internal electrode layer is arranged in a first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. [Figure 26] FIG. 4 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. [Figure 27] FIG. 4 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0013] 1. Composite electronic components A composite electronic component 1 according to an embodiment of the present invention will be described.

[0014] FIG. 1 is an external perspective view showing a composite electronic component according to a first embodiment of the present invention. FIG. 2 is a front view of the composite electronic component according to the first embodiment of the present invention. FIG. 3 is a bottom view of the composite electronic component according to the first embodiment of the present invention. FIG. 4 is a plan view of the composite electronic component according to the first embodiment of the present invention. FIG. 5 is a cross-sectional view taken along line VV in FIG. 1. FIG. 6(a) is an enlarged view of part A in FIG. 5, and FIG. 6(b) is an enlarged view of part B in FIG. 5. FIG. 7 is a cross-sectional view taken along line VII-VII in FIG. 1. FIG. 8(a) is an external perspective view of a multilayer ceramic capacitor included in the composite electronic component according to the first embodiment of the present invention, and FIG. 8(b) is an external perspective view of the multilayer ceramic capacitor from another direction. FIG. 9 is an exploded perspective view schematically showing a configuration of a main part of the multilayer ceramic capacitor included in the composite electronic component according to the first embodiment of the present invention. FIG. 10 is an exploded perspective view schematically showing a configuration of a main part of a multilayer ceramic conductor part (chip-type coil component) included in the composite electronic component according to the first embodiment of the present invention.

[0015] As shown in FIGS. 1 to 7, a composite electronic component 1 according to an embodiment of the present invention includes a multilayer ceramic capacitor 10 and a conductor portion 40.

[0016] (a) Multilayer ceramic capacitor A multilayer ceramic capacitor 10 according to an embodiment of the present invention will be described.

[0017] The multilayer ceramic capacitor 10 has a first laminate 12 and external electrodes 30. The configuration of each will be described below in the order of the first laminate 12 and the external electrodes 30.

[0018] (First laminate) The first laminate 12 includes a plurality of stacked dielectric layers 14. The first laminate 12 further includes a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y. The first laminate 12 has a rectangular parallelepiped shape. The corners and ridges of the first laminate 12 are preferably rounded. The corners refer to the intersections of three adjacent surfaces of the first laminate 12, and the ridges refer to the intersections of two adjacent surfaces of the first laminate 12. Furthermore, unevenness may be formed on part or all of the first surface 12a, the second surface 12b, the third surface 12c, the fourth surface 12d, and the fifth surface 12e and the sixth surface 12f.

[0019] As shown in Figure 5, the first laminate 12 has an inner layer portion 15a in which multiple internal electrode layers 16 are arranged alternately with dielectric layers 14 interposed therebetween, a first outer layer portion 15b1 located on the first surface 12a side and formed from multiple dielectric layers 14 located between the first surface 12a and the outermost surface of the inner layer portion 15a on the first surface 12a side, and a second outer layer portion 15b2 located on the second surface 12b side and formed from multiple dielectric layers 14 located between the second surface 12b and the outermost surface of the inner layer portion 15a on the second surface 12b side.

[0020] Here, the plurality of dielectric layers 14 for inner layers that constitute the inner layer portion 15a are formed so as to be sandwiched between a first inner electrode layer 16a and a second inner electrode layer 16b, which will be described later.

[0021] The number of dielectric layers 14 to be laminated is not particularly limited, but is preferably 10 to 1000, including the first outer layer portion 15b1 and the second outer layer portion 15b2. The thickness of the dielectric layers 14 is preferably 0.5 μm to 15 μm.

[0022] The dielectric layer 14 can be formed of a dielectric material, such as a ceramic material. Examples of such dielectric materials include dielectric ceramics containing components such as BaTiO3, CaTiO3, SrTiO3, and CaZrO3. When the dielectric material is a primary component, it may contain a secondary component, such as a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound, in a smaller amount than the primary component, depending on the desired characteristics of the first laminate 12.

[0023] Furthermore, the dielectric layer 14 may have a plurality of crystal grains containing a perovskite compound having a basic structure of BaTiO3. The size of the crystal grains is appropriately designed depending on the thickness of the dielectric layer 14. In this embodiment, the thinner the thickness of the dielectric layer 14, the greater the capacitance of the capacitor, so it is preferable that the crystal grain size be 1 μm or less.

[0024] Furthermore, the outer dielectric layers 14 constituting the first outer layer portion 15b1 and the second outer layer portion 15b2 are formed from the same dielectric ceramic material as the dielectric layers 14 of the inner layer portion 15a. The dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 may be formed from a material different from that of the dielectric layers 14 of the inner layer portion 15a. The dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 may each have a multiple layer structure or a single layer structure. Furthermore, when the dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 each have a multi-layer structure, it is preferable that the segregated portions of Si in the dielectric layers 14 of the first outer layer portion 15b1 and the second outer layer portion 15b2 located closest to the first internal electrode layer 16a and the second internal electrode layer 16b are larger than the segregated portions of Si in the other dielectric layers of the first outer layer portion 15b1 and the second outer layer portion 15b2. This improves the bending strength of the multilayer ceramic capacitor 10 from the lamination direction x side.

[0025] The first laminate 12 includes side portions (hereinafter referred to as "W gaps") 22a, 22b of the first laminate 12 located between the first internal electrode layer 16a and the fifth surface 12e and between the first internal electrode layer 16a and the sixth surface 12f.

[0026] The first laminate 12 also includes ends 24a, 24b (hereinafter referred to as "L gaps") of the first laminate 12 located between the second internal electrode layer 16b and the third surface 12c and between the second internal electrode layer 16b and the fourth surface 12d.

[0027] (Internal electrode layer) As shown in Figures 5 and 9, the internal electrode layer 16 has a first internal electrode layer 16a exposed on the third surface 12c and the fourth surface 12d, and a second internal electrode layer 16b exposed on the fifth surface 12e and the sixth surface 12f.

[0028] The first internal electrode layer 16a has a first opposing electrode portion 18a facing the second internal electrode layer 16b, a first extraction electrode portion 20a located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the third surface 12c of the first laminate 12, and a second extraction electrode portion 20b located on one end side of the first internal electrode layer 16a and extending from the first opposing electrode portion 18a to the fourth surface 12d of the first laminate 12.

[0029] The second internal electrode layer 16b has a second opposing electrode portion 18b facing the first internal electrode layer 16a, a third extraction electrode portion 20c located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the fifth surface 12e of the first laminate 12, and a fourth extraction electrode portion 20d located on one end side of the second internal electrode layer 16b and extending from the second opposing electrode portion 18b to the sixth surface 12f of the first laminate 12.

[0030] The shape of the first opposing electrode portion 18a of the first internal electrode layer 16a is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing in either direction.

[0031] The shape of the second opposing electrode portion 18b of the second internal electrode layer 16b is not particularly limited, but is preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing in either direction.

[0032] The shapes of the first lead electrode portion 20a and the second lead electrode portion 20b of the first internal electrode layer 16a are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0033] The shapes of the third lead electrode portion 20c and the fourth lead electrode portion 20d of the second internal electrode layer 16b are not particularly limited, but are preferably rectangular in plan view. However, the corners in plan view may be rounded or may be formed obliquely in plan view (tapered). Alternatively, the shape may be tapered in plan view, with a slope increasing toward either side.

[0034] The width of the first opposing electrode portion 18a of the first internal electrode layer 16a and the width of the first extraction electrode portion 20a and the second extraction electrode portion 20b of the first internal electrode layer 16a may be formed to be the same width, or either one may be formed to be narrower in width.

[0035] The width of the second opposing electrode portion 18b of the second internal electrode layer 16b and the width of the third extraction electrode portion 20c and the fourth extraction electrode portion 20d of the second internal electrode layer 16b may be formed to be the same width, or either one may be formed to be narrower in width.

[0036] In this embodiment, the width in the first direction y of the third extraction electrode portion 20c and the fourth extraction electrode portion 20d of the second internal electrode layer 16b is made narrower than the width in the first direction y of the second opposing electrode portion 18b of the second internal electrode layer 16b.

[0037] Furthermore, although it is preferable that the first internal electrode layers 16a have a uniform thickness, the thickness of the edge portions of the first internal electrode layers 16a may be thicker than the thickness of the central portion. Increasing the thickness of the first internal electrode layers 16a improves coverage. This shortens the current path and improves ESL characteristics. Furthermore, the thickness of the edge portions of the first internal electrode layers 16a may be thinner than the thickness of the central portion. By making the thickness thinner, the step corresponding to the thickness of the first internal electrode layers 16a is alleviated, thereby suppressing structural defects.

[0038] The first internal electrode layer 16a and the second internal electrode layer 16b can be made of an appropriate conductive material, such as, but not limited to, metals such as Ni, Cu, Ag, Pd, and Au, or alloys containing at least one of these metals, such as an Ag-Pd alloy. Furthermore, the first internal electrode layer 16a and the second internal electrode layer 16b containing Sn can mitigate electric field concentration at the interface, leading to improved high-temperature load reliability. In this case, Sn can be sufficiently effective even if it is contained in only one of the internal electrode layers 16, the first internal electrode layer 16a or the second internal electrode layer 16b.

[0039] In this embodiment, the first opposing electrode portion 18a of the first internal electrode layer 16a and the second opposing electrode portion 18b of the second internal electrode layer 16b face each other via the dielectric layer 14, thereby forming capacitance and exhibiting the characteristics of a capacitor.

[0040] The thickness of each of the first internal electrode layers 16a and the second internal electrode layers 16b is preferably 0.5 μm or more and 1.5 μm or less. The number of stacked first internal electrode layers 16a and second internal electrode layers 16b can be appropriately changed depending on the size, etc. Increasing the number of first internal electrode layers 16a can prevent the DC resistance from increasing. The total number of first internal electrode layers 16a and second internal electrode layers 16b is preferably 10 or more and 1000 or less.

[0041] The first lead electrode portion 20a and the second lead electrode portion 20b of the first internal electrode layer 16a may be curved. The third lead electrode portion 20c and the fourth lead electrode portion 20d of the second internal electrode layer 16b may also be curved. In this case, they may be arranged so as to be curved on either the first surface 12a or the second surface 12b. In this case, by making the mounting surface the curved surface, the current path can be shortened.

[0042] The distance between the first internal electrode layer 16a closest to the first surface 12a and the first internal electrode layer 16a closest to the second surface 12b of the first internal electrode layer 16a extended to the third surface 12c and the fourth surface 12d may be shorter than the distance between the first opposing electrode portion 18a of the first internal electrode layer 16a closest to the first surface 12a and the first opposing electrode portion 18a of the first internal electrode layer 16a closest to the second surface 12b.

[0043] Furthermore, the distance between the second internal electrode layer 16b closest to the first surface 12a and the second internal electrode layer 16b closest to the second surface 12b of the second internal electrode layer 16b extended to the fifth surface 12e and the sixth surface 12f may be shorter than the distance between the second opposing electrode portion 18b of the second internal electrode layer 16b closest to the first surface 12a and the second opposing electrode portion 18b of the second internal electrode layer 16b closest to the second surface 12b.

[0044] In order to increase the capacitance of the capacitor, it is necessary to increase the area of ​​the internal electrode layers 16, so it is preferable that the LW surface coverage of the internal electrode layers 16 is 90% or more. Here, the LW surface coverage of the internal electrode layers 16 is defined as the ratio of the area inside the edge of the internal electrode layers 16 when viewed from the LW surface of the first laminate 12 minus the area of ​​the gap. The higher the LW surface coverage of the internal electrode layers 16, the higher the capacitance of the capacitor. However, even if the LW surface coverage is low, the dielectric layers 14 are bonded to each other via gaps, so the bonding strength between the layers is high and delamination is less likely to occur.

[0045] (external electrode) The external electrodes 30 include a first external electrode 30a, a second external electrode 30b, a third external electrode 30c, and a fourth external electrode 30d.

[0046] The first external electrode 30a is connected to the first internal electrode layer 16a and is formed on the third surface 12c. The first external electrode 30a is disposed so as to wrap around a part of the first surface 12a and a part of the second surface 12b. Preferably, the first external electrode 30a is disposed so as to wrap around from the third surface 12c to a part of the fifth surface 12e and a part of the sixth surface 12f.

[0047] The second external electrode 30b is connected to the first internal electrode layer 16a and is formed on the fourth surface 12d. The second external electrode 30b is disposed so as to wrap around a part of the first surface 12a and a part of the second surface 12b. Preferably, the second external electrode 30b is disposed so as to wrap around a part of the fifth surface 12e and a part of the sixth surface 12f from the fourth surface 12d.

[0048] As shown in FIG. 8(a), the first external electrode 30a has a first region 36a arranged on the surface facing the first face 12a and a second region 36b arranged on the surface facing the third face 12c.

[0049] As shown in FIG. 8(b), the second external electrode 30b has a third region 36c arranged on the surface facing the first face 12a and a fourth region 36d arranged on the surface facing the fourth face 12d.

[0050] On the first surface 12a, the thickness of each of the first external electrode 30a and the second external electrode 30b in the stacking direction x is preferably 5 μm to 15 μm. The thickness of each of the first external electrode 30a and the second external electrode 30b is defined as the total thickness of the base electrode layer 32 and the plating layer 34, which will be described later.

[0051] The thickness of each of the first external electrode 30a and the second external electrode 30b in the stacking direction x is measured by the method described below. That is, the first laminate 12 is polished to half the dimension in the second direction z so as to expose the surface (LT surface) in the first direction y × stacking direction x. In the cross section (LT surface) in the first direction y × stacking direction x obtained by polishing, the first external electrode 30a and the second external electrode 30b arranged on the first surface 12a are observed with a digital microscope (Keyence Corporation: VHX-8000) at a magnification of 1500 times. At this time, the thickness of each of the thickest portions of the first external electrode 30a and the second external electrode 30b arranged on the first surface 12a is defined as the thickness.

[0052] The third external electrode 30c is connected to the second internal electrode layer 16b and is formed on the fifth surface 12e. Preferably, it is disposed on a portion of the first surface 12a and a portion of the second surface 12b. Alternatively, it may be disposed on either a portion of the first surface 12a or a portion of the second surface 12b, continuing from the fifth surface 12e.

[0053] The fourth external electrode 30d is connected to the second internal electrode layer 16b and is formed on the sixth surface 12f. Preferably, it is disposed on a portion of the first surface 12a and a portion of the second surface 12b. Alternatively, it may be disposed continuously from the sixth surface 12f on a portion of either the first surface 12a or the second surface 12b.

[0054] The third external electrode 30c and the fourth external electrode 30d may be directly joined together.

[0055] The first external electrode 30a has a first base electrode layer 32a containing a conductive metal that is arranged on the first laminate 12, and has a first plating layer 34a that is arranged to cover the first base electrode layer 32a. The second external electrode 30b has a second base electrode layer 32b containing a conductive metal that is arranged on the first laminate 12, and has a second plating layer 34b that is arranged to cover the second base electrode layer 32b. The third external electrode 30c has a third base electrode layer 32c containing a conductive metal that is arranged on the first laminate 12, and has a third plating layer 34c that is arranged to cover the third base electrode layer 32c. The fourth external electrode 30d has a fourth base electrode layer 32d containing a conductive metal that is arranged on the first laminate 12, and has a fourth plating layer 34d that is arranged to cover the fourth base electrode layer 32d.

[0056] The base electrode layer 32 includes a first base electrode layer 32a, a second base electrode layer 32b, a third base electrode layer 32c, and a fourth base electrode layer 32d. The first base electrode layer 32a, the second base electrode layer 32b, the third base electrode layer 32c, and the fourth base electrode layer 32d each include at least one selected from a baked layer, a conductive resin layer, a thin film layer, and the like.

[0057] The baking layer includes a glass component and a metal. The baking layer may be a multi-layered layer.

[0058] The glass component of the baking layer contains at least one selected from B, Si, Ba, Mg, Al, Li, and the like.

[0059] The metal of the baking layer includes, for example, at least one selected from Cu, Ni, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0060] The baked layer is formed by applying a conductive paste containing glass and metal to the first laminate 12 and baking it, and may be baked simultaneously with the internal electrode layer 16 or may be baked after the internal electrode layer 16 has been baked.

[0061] When a baked layer is provided as the first base electrode layer 32a and the second base electrode layer 32b, the thickness of the baked layer at the center in the stacking direction x of the first base electrode layer 32a and the second base electrode layer 32b located on the third surface 12c and the fourth surface 12d is preferably, for example, 20 μm or more and 50 μm or less.

[0062] Furthermore, when baked layers are provided on the first surface 12a and the second surface 12b, the fifth surface 12e and the sixth surface 12f as the first base electrode layer 32a and the second base electrode layer 32b, the thickness of the baked layer at the center in the first direction y of the first base electrode layer 32a and the second base electrode layer 32b located on the first surface 12a and the second surface 12b, the fifth surface 12e and the sixth surface 12f is preferably, for example, 5 μm or more and 20 μm or less.

[0063] When a baked layer is provided as the third base electrode layer 32c and the fourth base electrode layer 32d, the thickness of the baked layer at the center in the stacking direction x of the third base electrode layer 32c and the fourth base electrode layer 32d located on the fifth surface 12e and the sixth surface 12f is preferably, for example, 20 μm or more and 50 μm or less.

[0064] Furthermore, when baked layers are provided on the first surface 12a and the second surface 12b as the third base electrode layer 32c and the fourth base electrode layer 32d, the thickness of the baked layer at the center in the first direction y of the third base electrode layer 32c and the fourth base electrode layer 32d located on the first surface 12a and the second surface 12b is preferably, for example, 5 μm or more and 20 μm or less.

[0065] Next, a case where the base electrode layer 32 is formed by a conductive resin layer will be described. The conductive resin layer may be disposed on the baked layer so as to cover the baked layer, or may be disposed directly on the first laminate 12 without providing a baked layer. The conductive resin layer may also completely cover the baked layer, or may cover only a portion of the baked layer. Furthermore, the conductive resin layer may be a multi-layer structure.

[0066] The conductive resin layer contains a thermosetting resin and a metal. Because the conductive resin layer contains a thermosetting resin, it is more flexible than a baked layer made of, for example, a plating film or a baked conductive paste. Therefore, even if the multilayer ceramic capacitor 10 is subjected to a physical impact or an impact due to a thermal cycle, the conductive resin layer functions as a buffer layer and can prevent cracks in the multilayer ceramic capacitor 10.

[0067] The metal contained in the conductive resin layer can be Ag, Cu, Ni, Sn, Bi, or an alloy containing these. It is also possible to use a metal powder whose surface is coated with Ag. When using a metal powder whose surface is coated with Ag, it is preferable to use Cu, Ni, Sn, Bi, or an alloy powder thereof as the metal powder. The reason for using Ag conductive metal powder as the conductive metal is that Ag has the lowest resistivity of all metals, making it suitable as an electrode material, and Ag is a noble metal that does not oxidize and has high weather resistance. The reason for using Ag-coated metal is that it allows the base metal to be made inexpensively while maintaining the above-mentioned properties of Ag.

[0068] The metal contained in the conductive resin layer is mainly responsible for the electrical conductivity of the conductive resin layer. Specifically, when the metals (conductive fillers) contained in the conductive resin layer come into contact with each other, an electrical path is formed inside the conductive resin layer.

[0069] The metal contained in the conductive resin layer may be spherical or flat, but it is preferable to use a mixture of spherical metal powder and flat metal powder. The average particle size of the metal contained in the conductive resin layer is not particularly limited. The average particle size of the metal (conductive filler) contained in the conductive resin layer may be, for example, about 0.3 μm or more and 10 μm or less.

[0070] The metal contained in the conductive resin layer is preferably contained in an amount of 35 vol % or more and 75 vol % or less with respect to the volume of the entire conductive resin.

[0071] The resin for the conductive resin layer may be any of various known thermosetting resins, such as epoxy resin, phenol resin, urethane resin, silicone resin, polyimide resin, etc. Among these, epoxy resin is one of the most suitable resins, as it has excellent heat resistance, moisture resistance, adhesion, etc.

[0072] The resin contained in the conductive resin layer is preferably contained in an amount of 25 vol % or more and 65 vol % or less with respect to the volume of the entire conductive resin.

[0073] The conductive resin layer preferably contains a curing agent together with the thermosetting resin. When an epoxy resin is used as the base resin, various known compounds such as phenol-based, amine-based, acid anhydride-based, imidazole-based, active ester-based, and amide-imide-based compounds can be used as the curing agent for the epoxy resin.

[0074] When conductive resin electrode layers are provided as the first and second base electrode layers 32a and 32b, the thickness of the conductive resin electrode layers at the center in the stacking direction x of the first and second base electrode layers 32a and 32b located on the third and fourth surfaces 12c and 12d is preferably, for example, approximately 20 μm or more and 70 μm or less.

[0075] Furthermore, when conductive resin electrode layers are provided as the first base electrode layer 32a and the second base electrode layer 32b on the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f, the thickness of the conductive resin electrode layer at the center in the first direction y of the first base electrode layer 32a and the second base electrode layer 32b located on the first surface 12a, the second surface 12b, the fifth surface 12e, and the sixth surface 12f is preferably, for example, approximately 5 μm or more and 20 μm or less.

[0076] When conductive resin electrode layers are provided as the third and fourth base electrode layers 32c and 32d, the thickness of the conductive resin electrode layers at the center in the stacking direction x of the third and fourth base electrode layers 32c and 32d located on the fifth and sixth surfaces 12e and 12f is preferably, for example, approximately 20 μm or more and 70 μm or less.

[0077] Furthermore, when conductive resin electrode layers are provided on the first surface 12a and the second surface 12b as the third base electrode layer 32c and the fourth base electrode layer 32d, the thickness of the conductive resin electrode layer at the center in the first direction y of the third base electrode layer 32c and the fourth base electrode layer 32d located on the first surface 12a and the second surface 12b is preferably, for example, approximately 5 μm or more and 20 μm or less.

[0078] In addition, only conductive resin electrode layers may be arranged as the first base electrode layer 32a and the second base electrode layer 32b, and only conductive resin electrode layers may be arranged as the third base electrode layer 32c and the fourth base electrode layer 32d.

[0079] (plating layer) The plating layer 34 includes a first plating layer 34a, a second plating layer 34b, a third plating layer 34c, and a fourth plating layer 34d.

[0080] The first plating layer 34a is disposed so as to cover the first base electrode layer 32a. The second plating layer 34b is disposed so as to cover the second base electrode layer 32b. The third plating layer 34c is disposed so as to cover the third base electrode layer 32c. The fourth plating layer 34d is disposed so as to cover the fourth base electrode layer 32d.

[0081] The plating layer 34 includes, for example, at least one selected from Cu, Ni, Sn, Ag, Pd, an Ag—Pd alloy, Au, and the like.

[0082] The plating layer 34 may also be formed of multiple layers. The plating layer 34 preferably has a two-layer structure consisting of Ni plating and Sn plating in that order. The Ni plating layer can prevent the base electrode layer 32 from being eroded by solder when mounting the multilayer ceramic capacitor 10. The Sn plating layer also improves the wettability of the solder when mounting the multilayer ceramic capacitor 10, facilitating mounting. When the plating layer 34 has a three-layer structure, it is preferably Sn plating, Ni plating, and Sn plating from the first laminate 12 side.

[0083] The thickness of each plating layer 34 is preferably 1 μm or more and 6 μm or less.

[0084] Any one or each of the first external electrode 30a, the second external electrode 30b, the third external electrode 30c, and the fourth external electrode 30d may have a plating layer formed directly on the surface of the first laminate 12. That is, the multilayer ceramic capacitor 10 may have a structure including plating layers that are directly and electrically connected to the first internal electrode layers 16a and the second internal electrode layers 16b. In such a case, a catalyst may be disposed on the surface of the first laminate 12 as a pretreatment, and then the plating layer may be formed directly.

[0085] The first direct plating layer is disposed on the third surface 12c and is formed to be joined to the first internal electrode layer 16a. The second direct plating layer is disposed on the fourth surface 12d and is formed to be joined to the first internal electrode layer 16a. The third direct plating layer is disposed on the fifth surface 12e and is formed to be joined to the second internal electrode layer 16b. The fourth direct plating layer is disposed on the sixth surface 12f and is formed to be joined to the second internal electrode layer 16b.

[0086] Each of the directly plated layers preferably contains at least one metal selected from Cu, Ni, Sn, Pb, Au, Ag, Pd, Bi, Zn, etc., or an alloy containing such a metal.

[0087] For example, when the first internal electrode layer 16a and the second internal electrode layer 16b are formed using Ni, it is preferable that the direct plating layer be formed using Cu, which has good bonding properties with Ni.

[0088] When the plating layer 34 is formed directly on the first laminate 12, the thickness of each plating layer 34 is preferably 1 μm or more and 15 μm or less.

[0089] When the plating layer 34 is formed directly on the first laminate 12, it is preferable that the plating layer 34 does not contain glass. In addition, the metal content per unit volume of the plating layer 34 is preferably 99% by volume or more.

[0090] A case will be described in which the base electrode layer 32 is formed as a thin film layer and the plating layer 34 is formed directly on the thin film layer.

[0091] The first thin film layer disposed on the first surface 12a is connected to the first direct plating layer disposed around from the third surface 12c. The second thin film layer disposed on the first surface 12a is connected to the second direct plating layer disposed around from the fourth surface 12d. The third thin film layer disposed on the first surface 12a is connected to the third direct plating layer disposed around from the fifth surface 12e. The fourth thin film layer disposed on the first surface 12a is connected to the fourth direct plating layer disposed around from the sixth surface 12f.

[0092] Similarly, the first thin film layer disposed on the second surface 12b is connected to the first direct plating layer disposed around from the third surface 12c. The second thin film layer disposed on the second surface 12b is connected to the second direct plating layer disposed around from the fourth surface 12d. The third thin film layer disposed on the second surface 12b is connected to the third direct plating layer disposed around from the fifth surface 12e. The fourth thin film layer disposed on the second surface 12b is connected to the fourth direct plating layer disposed around from the sixth surface 12f.

[0093] The dimension in the first direction y of the multilayer ceramic capacitor 10 including the first laminate 12 and the external electrodes 30 is defined as dimension L. The dimension L is preferably 1.0 mm or more and 3.2 mm or less. The dimension in the lamination direction x of the multilayer ceramic capacitor 10 including the first laminate 12 and the external electrodes 30 is defined as dimension T. Dimension T is preferably 0.3 mm or more and 2.5 mm or less. The dimension in the second direction z of the multilayer ceramic capacitor 10 including the first laminate 12 and the external electrodes 30 is defined as dimension W. The dimension W is preferably 0.5 mm or more and 2.5 mm or less.

[0094] (b) Conductor Next, the conductor portion 40 will be described. As shown in FIG. 1, the conductor portion 40 is electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 via a conductive adhesive 70.

[0095] The conductor portion 40 can be configured as a chip-type coil component.

[0096] The conductor section 40 has a second laminate 42 and a conductor electrode 60. The configuration of each will be described below in the order of the second laminate 42 and the conductor electrode 60.

[0097] The second laminate 42 includes a plurality of stacked ferrite layers 44. These ferrite layers 44 are sintered together in a stacked state. The second laminate 42 also includes a first surface 42a and a second surface 42b facing the stacking direction x, a third surface 42c and a fourth surface 42d facing a first direction y perpendicular to the stacking direction x, and a fifth surface 42e and a sixth surface 42f facing a second direction z perpendicular to the stacking direction x and the first direction y. The second laminate 42 has a rectangular parallelepiped shape. It is preferable that the corners and ridges of the second laminate 42 be rounded. Note that the corners refer to the intersections of three adjacent surfaces of the second laminate 42, and the ridges refer to the intersections of two adjacent surfaces of the second laminate 42.

[0098] As shown in FIGS. 5 and 10 , the second laminate 42 includes a coil 46. The coil 46 is made of, for example, Cu or Ag. The coil 46 includes patterned conductors 48. These patterned conductors 48 are formed on the ferrite layers 44. The patterned conductors 48 are connected in a coil shape by via holes 50 formed in the ferrite layers 44. One end of the coil 46 is led out to the third surface 42c of the second laminate 42 as a first lead conductor 52a. The other end of the coil 46 is led out to the fourth surface 42d of the second laminate 42 as a second lead conductor 52b. The coil 46 may be a conductor wound in a coil shape.

[0099] (Conductor electrodes) The conductor electrode 60 includes a first conductor electrode 60a and a second conductor electrode 60b. The conductor electrode 60 is also composed of a conductor base electrode 62 and a conductor plating layer 64.

[0100] A first conductor electrode 60a is formed on the third surface 42c side of the second laminate 42. Furthermore, a second conductor electrode 60b is formed on the fourth surface 42d side of the second laminate 42.

[0101] The first conductor electrode 60a is formed from the third surface 12c to the first and second surfaces 42a, 42b and the fifth and sixth surfaces 42e, 42f of the second laminate 42. In this case, the first conductor electrode 60a is electrically connected to the first lead conductor 52a of the coil 46.

[0102] The second conductor electrode 60b is formed from the fourth surface 12d to the first and second surfaces 42a, 42b and the fifth and sixth surfaces 42e, 42f of the second laminate 42. In this case, the second conductor electrode 60b is electrically connected to the second lead conductor 52b of the coil 46.

[0103] The first conductor electrode 60a includes, in order from the second laminate 42 side, a conductor base electrode 62 and a conductor plating layer 64a. The first conductor base electrode 62a is made of a conductor such as Ag or an Ag alloy. The first conductor base electrode 62a is formed on the surface of the second laminate 42, i.e., on the third surface 12c. In this case, the first conductor base electrode 62a is electrically connected to the first lead conductor 52a. The first conductor plating layer 64a has a two-layer structure including a Ni plating film and a Sn plating film. The Ni plating film is formed on the first conductor base electrode 62a. The Sn plating film is formed on the Ni plating film.

[0104] The second conductor electrode 60b, like the first conductor electrode 60a, includes, in order from the second laminate 42 side, a second conductor base electrode 62b and a conductor plating layer 64b. The second conductor base electrode 62b is made of a conductor such as Ag or an Ag alloy. The second conductor base electrode 62b is formed on the surface of the second laminate 42, i.e., on the fourth surface 12d, etc. In this case, the second conductor base electrode 62b is electrically connected to the second lead conductor 52b. The second conductor plating layer 64b has a two-layer structure including a Ni plating film and a Sn plating film. The Ni plating film is formed on the second conductor base electrode 62b. The Sn plating film is formed on the Ni plating film.

[0105] The first conductor electrode 60a is electrically connected to the first external electrode 30a via a first conductive adhesive 70a, and the second conductor electrode 60b is electrically connected to the second external electrode 30b via a second conductive adhesive 70b.

[0106] More specifically, the first conductive adhesive 70a is disposed on the surface of the first conductor electrode 60a and from the first region 36a to the second region 36b of the first external electrode 30a. As a result, the first conductive adhesive 70a is disposed on the ridge portion formed by the first surface 12a and the third surface 12c of the first laminate 12. The second conductive adhesive 70b is disposed across the third region 36c to the fourth region 36d of the second conductor electrode 60b and the second external electrode 30b, so that the second conductive adhesive 70b is disposed on the ridgeline formed by the first surface 12a and the fourth surface 12d of the first laminate 12.

[0107] 6(a), in a cross section parallel to the fifth surface 12e or the sixth surface 12f of the first laminate 12 and cut at half the length of the dimension of the first laminate 12 in the second direction z, the total thickness t3 (thickness of the ridge line) of the thickness t1 of the first external electrode 30a along the extension line l1 of the first surface 12a in this cross section and the thickness t2 of the first conductive adhesive 70a is 7 μm or more. The total thickness (thickness of the ridge line) t3 is preferably 12 μm or more, and more preferably 62 μm or more.

[0108] 6(b), in a cross section parallel to the fifth surface 12e or the sixth surface 12f of the first laminate 12 and cut at half the length of the dimension of the first laminate 12 in the second direction z, the total thickness t6 (thickness of the ridge line) of the thickness t4 of the second external electrode 30b along the extension line l2 of the first surface 12a in this cross section and the thickness t5 of the second conductive adhesive 70b is 7 μm or more. The total thickness (thickness of the ridge line) t6 is preferably 12 μm or more, and more preferably 62 μm or more.

[0109] The conductive adhesive 70 used to connect the conductor portion 140 and the multilayer ceramic capacitor 10 is, for example, a material containing a metal component, such as high-temperature solder.

[0110] It is preferable that voids are contained in the conductive adhesive 70. This allows the voids to function as cushion portions when the composite electronic component 1 is bent.

[0111] When the DC resistance of the multilayer ceramic capacitor 10 is Rdc1 and the DC resistance of the conductor portion 40 is Rdc2, Rdc2≦Rdc1.

[0112] When the DC resistance of the multilayer ceramic capacitor 10 is Rdc1 and the DC resistance of the conductor portion 40 is Rdc2, Rdc2≦Rdc1 holds. This allows AC current to flow preferentially to the multilayer ceramic capacitor 10 with low impedance, and DC current to flow to the one with low DC resistance. Furthermore, noise that did not flow to the multilayer ceramic capacitor 10 can be removed by the conductor portion 40, which is a chip-type coil component, thereby improving the noise removal effect.

[0113] The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured and compared after removing the conductive adhesive 70 that bonds them together. The DC resistance values ​​of the conductor portion 40 and the multilayer ceramic capacitor 10 are measured using the four-terminal method with a current of 100 mA applied, in accordance with JIS C2139.

[0114] An insulating resin may be disposed between the conductor portion 40 and the multilayer ceramic capacitor 10. In this case, it is preferable that the insulating resin covers at least a portion of the multilayer ceramic capacitor 10. It is also preferable that the insulating resin covers at least a portion of the conductor portion 40. It is further preferable that the insulating resin covers at least a portion of the multilayer ceramic capacitor 10 and at least a portion of the conductor portion 40.

[0115] 2. Mounting structure of composite electronic components Next, a mounting structure 500 for the composite electronic component 1 according to the first embodiment of the present invention will be described.

[0116] 1 is a cross-sectional view in the stacking direction showing a mounting structure of a composite electronic component according to a first embodiment of the present invention.

[0117] 11, a composite electronic component mounting structure 500 according to this embodiment includes a composite electronic component 1 according to this embodiment and a mounting substrate 80. The mounting substrate 80 includes a substrate core material 82 and connecting conductors (conductor lands) 84.

[0118] The core material 82 of the substrate is, for example, a substrate made of a material in which a base material made of a mixture of glass cloth and nonwoven glass cloth is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramic and glass. The core material 82 of the substrate may be a single-layer substrate or a substrate made of multiple laminated layers. The thickness of the core material 82 of the substrate is not particularly limited, but is preferably, for example, 200 μm to 800 μm.

[0119] One main surface of the core material 82 of the substrate is provided with conductor lands 84 and constitutes a substrate-side mounting surface 82a on which the composite electronic component 1 is mounted.

[0120] The conductor lands 84 include a first conductor land 84a, a second conductor land 84b, a third conductor land 84c, and a fourth conductor land 84d.

[0121] The first conductor land 84a is a portion that is electrically connected and mechanically joined to the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 86. The second conductor land 84b is a portion that is electrically connected and mechanically joined to the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 86. The third conductor land 84c is a portion that is electrically connected and mechanically joined to the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 86. The fourth conductor land 84d is a portion that is electrically connected and mechanically joined to the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 86.

[0122] The conductor land 84 may be provided on the main surface of the core material 82 of the substrate opposite to the substrate-side mounting surface 82a.

[0123] The material of the conductor lands 84 is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. The thickness of the conductor lands 84, i.e., the dimension in the stacking direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less, for example. The bonding material 86 can be, for example, a high-heat-resistant epoxy adhesive or solder.

[0124] In the above description, the mounting substrate 80 corresponds to the mounting substrate of the present invention. The core material 82 of the substrate corresponds to the core material of the substrate of the present invention. The substrate-side mounting surface 82a corresponds to the mounting surface of the present invention. The multiple conductor lands 84 correspond to the multiple connecting conductors of the present invention. However, the connecting conductors of the present invention are not limited to so-called lands or other conductors that are provided between the multilayer ceramic capacitor 10 and the mounting substrate 80 and can electrically connect the two, and are not limited by other uses, functions, shapes, names, etc.

[0125] In the composite electronic component mounting structure 500 shown in FIG. 11, the composite electronic component 1 is preferably mounted so that the conductor portion 40 of the composite electronic component 1 is disposed facing away from the mounting substrate 80. That is, the conductor portion 40 of the composite electronic component 1 is preferably disposed on the first surface side (non-mounting surface side) of the multilayer ceramic capacitor 10, and the multilayer ceramic capacitor 10 of the composite electronic component 1 is preferably mounted on the mounting substrate 80 side. Mounting in this manner eliminates the need to increase the distance between the multilayer ceramic capacitor 10 and the mounting substrate 80, making it easier to achieve a low ESL effect. Furthermore, mounting can be performed without affecting the mounting of the composite electronic component 1 to the mounting substrate.

[0126] 3. Manufacturing method for composite electronic components A method for manufacturing the composite electronic component 1 according to the first embodiment of the present invention will now be described.

[0127] (a) Manufacturing method of multilayer ceramic capacitor First, a method for manufacturing the multilayer ceramic capacitor 10 will be described. First, a dielectric sheet for the dielectric layers and a conductive paste for the internal electrode layers are prepared. The dielectric sheet and the conductive paste for the internal electrode layers contain a binder and a solvent. Known binders and solvents can be used.

[0128] Next, a conductive paste for the internal electrode layers is printed in a predetermined pattern on the dielectric sheet by, for example, screen printing or gravure printing. This prepares a dielectric sheet on which the patterns of the first internal electrode layer 16a and the second internal electrode layer 16b are formed. More specifically, for example, a screen plate for printing the first internal electrode layer 16a and a screen plate for printing the second internal electrode layer 16b are separately prepared, and the internal electrode layers 16 of this embodiment can be printed using a printer capable of printing the two types of screen plates separately. Here, a sheet on which the first internal electrode layer 16a is printed and a sheet on which the second internal electrode layer 16b is printed are stacked to obtain a desired structure, thereby forming a portion that becomes the internal layer portion 15a. In this embodiment, the internal electrode layer 16 is printed by screen printing.

[0129] Next, a predetermined number of dielectric sheets without a printed internal electrode layer pattern are stacked to form the portion that will become the first outer layer portion 15b1 on the first surface 12a side. After that, the portion that will become the internal layer portion 15a prepared above is stacked, and a predetermined number of dielectric sheets without a printed internal electrode layer pattern are stacked on top of this portion that will become the internal layer portion 15a to form the portion that will become the second outer layer portion 15b2 on the second surface 12b side. In this way, a laminated sheet is produced.

[0130] Next, the laminated sheets are pressed in the lamination direction by means of a hydrostatic press or the like to produce a laminated block.

[0131] The laminated block is then cut to a predetermined size to produce laminated chips, which may have rounded corners and ridges by barrel polishing or the like.

[0132] Next, the laminated chip is fired to produce the first laminate 12. The firing temperature depends on the materials of the dielectric layers 14 and the internal electrode layers 16, but is preferably 900°C or higher and 1400°C or lower.

[0133] A third base electrode layer 32c of the third external electrode 30c and a fourth base electrode layer 32d of the fourth external electrode 30d are formed on the fifth surface 12e and the sixth surface 12f of the first laminate 12 obtained by firing.

[0134] When a baked layer is formed as the base electrode layer 32, a conductive paste containing a glass component and a metal component is applied, followed by baking to form the base electrode layer 32. The baking temperature at this time is preferably 700° C. or higher and 900° C. or lower. In this embodiment, the base electrode layer 32 is formed as a baked layer.

[0135] Various methods can be used to form the baked layers as the third and fourth base electrode layers 32c and 32d. For example, the third and fourth base electrode layers 32c and 32d can be formed by extruding a conductive paste through a slit. With this method, by increasing the amount of conductive paste extruded, the third and fourth base electrode layers 32c and 32d can be formed not only on the fifth surface 12e and the sixth surface 12f, but also on a portion of the first surface 12a and a portion of the second surface 12b.

[0136] Alternatively, they may be formed using a roller transfer method. In the case of the roller transfer method, when the third and fourth base electrode layers 32c and 32d are formed not only on the fifth surface 12e and the sixth surface 12f but also on a part of the first surface 12a and a part of the second surface 12b, it is possible to form the third and fourth base electrode layers 32c and 32d on a part of the first surface 12a and a part of the second surface 12b by increasing the pressing pressure during the roller transfer.

[0137] Next, the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b are formed on the third surface 12c and the fourth surface 12d of the fired first laminate 12. When forming baked layers as the first base electrode layer 32a and the second base electrode layer 32b, as with the third base electrode layer 32c and the fourth base electrode layer 32d, a conductive paste containing a glass component and a metal component is applied, followed by a baking process to form the first base electrode layer 32a and the second base electrode layer 32b. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0138] Regarding the baking process, the first base electrode layer 32a of the first external electrode 30a, the second base electrode layer 32b of the second external electrode 30b, the third base electrode layer 32c of the third external electrode 30c, and the fourth base electrode layer 32d of the fourth external electrode 30d may be baked simultaneously, or the third base electrode layer 32c of the third external electrode 30c and the fourth base electrode layer 32d of the fourth external electrode 30d on the side surface side may be baked separately from the first base electrode layer 32a of the first external electrode 30a and the second base electrode layer 32b of the second external electrode 30b on the end surface side.

[0139] When the base electrode layer 32 is formed of a conductive resin layer, the conductive resin layer can be formed by the following method. The conductive resin layer may be formed on the surface of a baked layer, or the conductive resin layer may be formed directly on the first laminate 12 without forming a baked layer.

[0140] The conductive resin layer is formed by applying a conductive resin paste containing a thermosetting resin and a metal component onto the baking layer or the first laminate 12, followed by heat treatment at a temperature of 250°C to 550°C to thermally cure the resin and form the conductive resin layer. The heat treatment is preferably performed in an N2 atmosphere. To prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably kept below 100 ppm.

[0141] The conductive resin paste can be applied by, for example, a method of applying the conductive resin paste by extruding it through a slit or a roller transfer method, similar to the method of forming the base electrode layer 32 as a baked layer.

[0142] When forming the base electrode layer 32 as a thin film layer, masking or the like is performed, and the base electrode layer 32 can be formed in the desired location by a thin film formation method such as sputtering or vapor deposition. The base electrode layer 32 formed as a thin film layer is a layer of deposited metal particles having a thickness of 1 μm or less.

[0143] Finally, a plating layer 34 is formed. The plating layer 34 may be formed on the surface of the base electrode layer 32, or may be formed directly on the first laminate 12. In this embodiment, the plating layer 34 is formed on the surface of the base electrode layer 32. More specifically, a Ni plating layer and a Sn plating layer are formed on the base electrode layer 32. Either electrolytic plating or electroless plating may be used for the plating process. However, electroless plating has the disadvantage of requiring pretreatment using a catalyst or the like to improve the plating deposition rate, which complicates the process. Therefore, it is usually preferable to use electrolytic plating.

[0144] In this manner, the multilayer ceramic capacitor 10 shown in FIG. 1 can be manufactured.

[0145] (b) Manufacturing method of the conductor part

[0146] Next, an example of a method for manufacturing the conductor 40, which is a chip-type coil component, will be described.

[0147] First, the process of preparing the ceramic body will be described. For example, ferric oxide (Fe2O3), zinc oxide (ZnO), nickel oxide (NiO), and copper oxide (CuO) are weighed out in a predetermined ratio and placed in a ball mill as raw materials, and wet-mixed for a predetermined time to obtain a mixture. This mixture is dried and pulverized to obtain a powder, which is then calcined, for example, at 700°C for 1 hour to obtain a calcined powder. This calcined powder is then wet-pulverized in a ball mill for a predetermined period of time, and then dried and crushed to obtain a ferrite powder.

[0148] A binder resin, a plasticizer, a wetting agent, and a dispersant are added to the ferrite powder, and the mixture is mixed in a ball mill for a predetermined time, and then degassed under reduced pressure to obtain a slurry. This slurry is applied onto a peelable film using a lip coater or multi-coater and dried to obtain a long ferrite green sheet having a desired film thickness.

[0149] This long ferrite green sheet is cut to a predetermined size, and via holes are formed in it by a method such as laser processing, thereby obtaining a ferrite sheet with via holes in predetermined positions. A conductive paste containing Ag or an Ag alloy as a main component is applied to this ferrite sheet in a predetermined pattern by a method such as screen printing, and the ferrite sheet is then heated and dried to obtain an electrode-formed ferrite sheet equipped with a coil conductor.

[0150] These electrode-formed ferrite sheets are stacked so that the coil conductors are connected between the layers to form a coil, forming a laminate, and ferrite green sheets that have not been coated with conductor paste are stacked on top and bottom of the laminate to obtain an unfired laminate. When the electrode-formed ferrite sheets having the coil conductors are stacked, the coil conductors are connected between the layers in a coil shape through the above-mentioned via holes, and a coil is formed inside the unsintered laminate.

[0151] Then, this unfired laminate is heated at, for example, 45°C and 1.0 t / cm 2 The laminated and compressed body is then cut to a predetermined size by a method such as dicing with a dicer or cutting with a cutting blade to obtain an unfired ceramic body.

[0152] Next, the green ceramic body is debindered under predetermined conditions and then fired. Debindering is performed, for example, in a low-oxygen atmosphere at 500°C for two hours. Firing is performed, for example, in an air atmosphere at 870°C for 150 minutes. This results in a second laminate 42 (see FIG. 10 ). The second laminate 42 includes multiple ferrite layers 44. These ferrite layers 44 are sintered together in a stacked state. A coil 46 is formed inside the second laminate 42. The coil 46 includes patterned conductors 48. Each patterned conductor 48 is formed on each ferrite layer 44. The patterned conductors 48 are connected in a coil shape by via holes 50.

[0153] Next, the process of forming the conductor electrodes will be described. First, an electrode material paste for forming external electrodes is applied by a dipping method to the third surface 42c and the fourth surface 42d of the second laminate 42, where the lead conductors 52a, 52b of the coil 46 are exposed, and after drying at 120°C for 10 minutes, for example, the electrode material paste is baked at 800°C for 15 minutes to form the conductor base electrodes 62a, 62b of the conductor electrodes 60a, 60b.

[0154] Then, conductor plating layers 64a, 64b having a two-layer structure consisting of a lower layer of Ni plating film and an upper layer of Sn plating film are formed on the conductor base electrodes 62a, 62b of the conductor electrodes 60a, 60b. As a result, the conductor portion 40 shown in FIG. 1 is obtained.

[0155] (c) Manufacturing method of composite electronic components Next, the conductor portion 40 fabricated by the above method is mounted on the multilayer ceramic capacitor 10 fabricated by the above method.

[0156] More specifically, a cutting support tape is attached to the assembly of conductor portions 40. Next, the assembly of conductor portions 40 is cut into individual pieces to a predetermined size. Next, the individual conductor portions 40 are transferred to a heat-resistant plate. Note that heat-resistant tape, adhesive, etc. may be placed on the heat-resistant plate during transfer. Next, a conductive adhesive 70 (solder) is printed on the transferred individual conductor portions 40, and the multilayer ceramic capacitor 10 is mounted using a mounter.

[0157] Next, soldering is performed in a reflow furnace. Finally, the individual conductor portions 40 are removed from the heat-resistant plate, and the flux is washed away.

[0158] In this manner, the composite electronic component 1 shown in FIG. 1 is manufactured.

[0159] B. Second Embodiment In the composite electronic component 1A according to the second embodiment, the conductor 40 which is a chip-type coil component in the composite electronic component 1 according to the first embodiment is also configured as a conductor 140, for example, as an interposer substrate.

[0160] Fig. 12 is an external perspective view showing a composite electronic component according to a second embodiment of the present invention, Fig. 13 is a front view of the composite electronic component according to the second embodiment of the present invention, and Fig. 14 is a cross-sectional view taken along line XIV-XIV in Fig. 12.

[0161] As shown in FIGS. 12 and 13, a composite electronic component 1A according to the second preferred embodiment of the present invention includes a multilayer ceramic capacitor 10 and a conductor portion 140. As shown in FIG.

[0162] The multilayer ceramic capacitor 10 included in the composite electronic component 1A according to the second embodiment is the same as the multilayer ceramic capacitor 10 included in the composite electronic component 1 according to the first embodiment, and therefore a description thereof will be omitted.

[0163] 1. Conductor Next, the conductor portion 140 will be described.

[0164] 15 is a cross-sectional view showing an example of a conductor portion. Conductor portion 140 is composed of a single-sided substrate. Specifically, conductor portion 140 includes an insulating substrate 150 and a conductive pattern 152 disposed on one main surface of insulating substrate 150. A protective layer 154 is disposed on the surface of conductive pattern 152 so as to expose a portion of conductive pattern 152. The exposed portions of conductive pattern 152 are a pair of exposed electrode portions 153a, 153b. In addition, protective layer 154 is disposed on the entire other main surface of insulating substrate 150. Note that protective layer 154 does not necessarily have to be formed on the other main surface of insulating substrate 150.

[0165] The exposed electrode portion 153a is electrically connected to the first external electrode 30a via a first conductive adhesive 70a, and the exposed electrode portion 153b is electrically connected to the second external electrode 30b via a second conductive adhesive 70b.

[0166] More specifically, the first conductive adhesive 70a is disposed on the exposed electrode portion 153a and the first external electrode 30a from the first region 36a to the second region 36b, so that the first conductive adhesive 70a is disposed on the ridge portion defined by the first surface 12a and the third surface 12c of the first laminate 12. The second conductive adhesive 70b is disposed on the exposed electrode portion 153b and the second external electrode 30b from the third region 36c to the fourth region 36d, so that the second conductive adhesive 70b is disposed on the ridge portion defined by the first surface 12a and the fourth surface 12d of the first laminate 12.

[0167] The conductor portion 140 may be rectangular or disk-shaped, and the shape is not limited. However, when the conductor portion 140 is disposed on the first surface 12a or the second surface 12b, increasing the thickness of the conductor portion 140 in the stacking direction x increases the dimension of the composite electronic component 1A in the stacking direction x. Therefore, when the conductor portion 140 is disposed on the first surface 12a or the second surface 12b of the composite electronic component 1A, it is preferable to reduce the thickness of the conductor portion 140.

[0168] 2. Modification of the conductor part The conductor section 140 is configured as a single-sided substrate as an interposer substrate as described above, but may also be configured as a double-sided substrate or a multi-layer substrate. Modified examples of the conductor section 140 will be described below.

[0169] A conductor portion 140A, which is a first modified example of the conductor portion 140, will be described. 16a is a cross-sectional view showing a first modified example of the conductor portion 140. The conductor portion 140A is formed of a double-sided substrate. Specifically, the conductor portion 140A includes an insulating substrate 150, a conductive pattern 152a disposed on one main surface of the insulating substrate 150, and a conductive pattern 152b disposed on the other main surface of the insulating substrate 150. Land electrode portion 156a is arranged on the surface of conductive pattern 152a on one end side of insulating substrate 150, and land electrode portion 156b is arranged on the surface of conductive pattern 152a on the other end side of insulating substrate 150. On one main surface of insulating substrate 150, protective layer 154 is arranged on portions of conductive pattern 152a where land electrodes 156a, 156b are not arranged. Land electrode portion 156c is arranged on the surface of conductive pattern 152b on one end side of insulating substrate 150, and land electrode portion 156d is arranged on the surface of conductive pattern 152b on the other end side of insulating substrate 150. On the other main surface of insulating substrate 150, a protective layer 154 is disposed on the portions of conductive pattern 152b where land electrode portions 156c and 156d are not disposed. An interlayer connection conductor (end face through hole) 158a for electrically connecting the land electrode portion 156a and the land electrode portion 156c is arranged on one end side of the insulating substrate 150. An interlayer connection conductor (end face through hole) 158b for electrically connecting the land electrode portion 156b and the land electrode portion 156d is arranged on the other end side of the insulating substrate 150.

[0170] The land electrode portion 156a is electrically connected to the first external electrode 30a via a first conductive adhesive 70a, and the land electrode portion 156b is electrically connected to the second external electrode 30b via a second conductive adhesive 70b.

[0171] Next, a conductor portion 140B, which is a second modified example of the conductor portion 140, will be described. 16b is a cross-sectional view showing a second modified example of the conductor portion. The conductor portion 140B is composed of a double-sided substrate. Specifically, the conductor portion 140B includes an insulating substrate 150, a conductive pattern 152a disposed on one main surface of the insulating substrate 150, and a conductive pattern 152b disposed on the other main surface of the insulating substrate 150. A protective layer 154 is disposed on the surface of conductive pattern 152a so as to expose a portion of conductive pattern 152a. The exposed portion of conductive pattern 152a is a pair of exposed electrode portions 153a and 153b. A protective layer 154 is disposed on the surface of conductive pattern 152b so as to expose a portion of conductive pattern 152b. The exposed portion of conductive pattern 152b is a pair of exposed electrode portions 153c and 153d. To electrically connect exposed electrode portion 153a and exposed electrode portion 153c, an interlayer connection conductor (penetrating through-hole) 160a is disposed so as to penetrate insulating substrate 150 from one main surface to the other main surface. To electrically connect exposed electrode portion 153b and exposed electrode portion 153d, an interlayer connection conductor (penetrating through-hole) 160b is disposed so as to penetrate insulating substrate 150 from one main surface to the other main surface.

[0172] The exposed electrode portion 153a is electrically connected to the first external electrode 30a via a first conductive adhesive 70a, and the exposed electrode portion 153b is electrically connected to the second external electrode 30b via a second conductive adhesive 70b.

[0173] Next, a conductor portion 140C, which is a third modified example of the conductor portion 140, will be described. 16c is a cross-sectional view showing a third modified example of the conductor portion. The conductor portion 140C is composed of a multilayer substrate. Specifically, the conductor portion 140C includes a plurality of insulating substrates 150a-150c and conductive patterns 152a, 152b arranged alternately with the insulating substrates 150a-150c interposed therebetween. The conductive patterns 152a, 152b are arranged so as to be exposed from both end faces of the insulating substrates 150a-150c. A land electrode portion 156a is arranged on the surface of one end of the insulating substrate 150a located on one main surface side of the conductor portion 140C, and a land electrode portion 156b is arranged on the surface of the other end of the insulating substrate 150c located on the other main surface side of the conductor portion 140C. A protective layer 154 is arranged on the surface of the insulating substrate 150a in areas where the land electrodes 156a, 156b are not arranged. A land electrode portion 156c is arranged on the surface of one end of the insulating substrate 150c located on the other main surface side of the conductor portion 140C, and a land electrode portion 156d is arranged on the surface of the other end of the insulating substrate 150c located on the other main surface side of the conductor portion 140C. A protective layer 154 is arranged on the surface of the insulating substrate 150c in areas where the land electrodes 156c, 156d are not arranged. An interlayer connection conductor (end face through hole) 158a is disposed on one end of each of the insulating substrates 150a-150c to electrically connect the land electrode portion 156a to the land electrode portion 156c. The interlayer connection conductor 158a is also electrically connected to the conductive patterns 152a and 152b. An interlayer connection conductor (end face through hole) 158b is disposed on the other end of each of the insulating substrates 150a-150c to electrically connect the land electrode portion 156b to the land electrode portion 156d. The interlayer connection conductor 158b is also electrically connected to the conductive patterns 152a and 152b.

[0174] The land electrode portion 156a is electrically connected to the first external electrode 30a via a first conductive adhesive 70a, and the land electrode portion 156b is electrically connected to the second external electrode 30b via a second conductive adhesive 70b.

[0175] Next, a conductor portion 140D, which is a fourth modified example of the conductor portion 140, will be described. 16d is a cross-sectional view showing a fourth modified example of the conductor portion. The conductor portion 140D is composed of a multilayer substrate. Specifically, it includes a plurality of insulating substrates 150a-150c and conductive patterns 152a, 152b alternately arranged between the insulating substrates 150a-150c and the insulating substrates 150a-150c interposed therebetween. A protective layer 154 is arranged on the surface of insulating substrate 150a located on one main surface side of conductor portion 140C, exposing a portion of insulating substrate 150a. A pair of land electrodes 156a, 156b are arranged on the exposed portion of insulating substrate 150a. A protective layer 154 is arranged on the surface of insulating substrate 150c located on the other main surface side of conductor portion 140D, exposing a portion of insulating substrate 150c. A pair of land electrodes 156c, 156d are arranged on the exposed portion of insulating substrate 150c. To electrically connect land electrode portion 156a and land electrode portion 156c, an interlayer connection conductor (penetrating through-hole) 160a is disposed so as to penetrate from the surface of insulating substrate 150a to the surface of insulating substrate 150c. At this time, interlayer connection conductor 160a is also electrically connected to conductive patterns 152a and 152b. To electrically connect land electrode portion 156b and land electrode portion 156d, an interlayer connection conductor (penetrating through-hole) is disposed so as to penetrate from the surface of insulating substrate 150a to the surface of insulating substrate 150c. At this time, interlayer connection conductor 160b is also electrically connected to conductive patterns 152a and 152b.

[0176] The land electrode portion 156a is electrically connected to the first external electrode 30a via a first conductive adhesive 70a, and the land electrode portion 156b is electrically connected to the second external electrode 30b via a second conductive adhesive 70b.

[0177] The insulating substrates 150, 150a to 150c are formed, for example, from a substrate made of a material in which a base material made of a mixture of glass cloth and nonwoven glass cloth is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramic and glass. The insulating substrates 150, 150a to 150c may be formed as a single-layer substrate or a substrate made of a laminate of multiple layers. The thickness of the insulating substrates 150, 150a to 150c is not particularly limited, but is preferably set to, for example, 200 μm or more and 800 μm or less.

[0178] The material of the conductive patterns 152, 152a, and 152b is not particularly limited, but may be, for example, a metal such as Cu, Au, Pd, or Pt. The thickness of the conductive patterns 152, 152a, and 152b, i.e., the dimension in the stacking direction x, is not particularly limited, but is preferably, for example, 20 μm or more and 200 μm or less.

[0179] The conductive adhesive 70 used to connect the conductor portion 140 and the multilayer ceramic capacitor 10 is, for example, a material containing a metal component, such as high-temperature solder.

[0180] As described above, the conductive adhesive 70 is arranged so as to be electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10. In other words, the conductor portion 140 is electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 via the conductive adhesive 70. By arranging the conductor portion 140 so as to be electrically connected to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10 in this manner, a direct current flows through the conductor portion 140, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing a temperature rise.

[0181] When the DC resistance of the multilayer ceramic capacitor 10 is Rdc1 and the DC resistance of the conductor portion 140 is Rdc2, Rdc2≦Rdc1 holds.

[0182] By making the DC resistance Rdc2 of the conductor portion 140 less than or equal to the DC resistance Rdc1 of the multilayer ceramic capacitor 10, the DC current flows preferentially through the conductor portion 140, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing temperature rise.

[0183] On the other hand, if the DC resistance Rdc2 of the conductor portion 140 becomes larger than the DC resistance Rdc1 of the multilayer ceramic capacitor 10, current will flow more to the multilayer ceramic capacitor 10 than to the conductor portion 140, making it difficult to achieve the effect of handling large currents.

[0184] The conductor portion 140 is not electrically connected to the third external electrode 30c and the fourth external electrode 30d. By arranging the conductor portion 140 so that it is electrically connected only to the first external electrode 30a and the second external electrode 30b of the multilayer ceramic capacitor 10, a direct current flows through the conductor portion 140, reducing the current flowing through the multilayer ceramic capacitor 10 and suppressing a temperature rise.

[0185] The DC resistance values ​​of the conductor portion 140 and the multilayer ceramic capacitor 10 are measured and compared after removing the conductive adhesive 70 that bonds them together. The DC resistance values ​​of the conductor portion 140 and the multilayer ceramic capacitor 10 are measured using the four-terminal method with a current of 100 mA applied, in accordance with JIS C2139.

[0186] In the composite electronic component 1A shown in FIG. 12 , the DC resistance Rdc2 of the conductor portion 140 connected to the multilayer ceramic capacitor 10 is equal to or less than the DC resistance Rdc1 of the multilayer ceramic capacitor 10. This allows DC current to flow through the conductor portion and AC current to escape to the multilayer ceramic capacitor 10. More specifically, DC current tends to flow toward a lower DC resistance, so it tends to flow toward the conductor portion 140, which has a lower DC resistance than the multilayer ceramic capacitor 10. On the other hand, AC current tends to flow toward a lower impedance, so it tends to flow toward the multilayer ceramic capacitor 10, which has a lower impedance. This configuration prevents the capacitance and DC resistance of the multilayer ceramic capacitor 10 from increasing. Furthermore, simply attaching the conductor portion 40 to an existing multilayer ceramic capacitor 10 allows it to handle large currents, without requiring a new internal structure for each unique capacitance of the multilayer ceramic capacitor 10. This also enhances the flexibility of the product lineup.

[0187] 3. Mounting structure of composite electronic components Next, a mounting structure 500A of a composite electronic component 1A according to a second embodiment of the present invention will be described.

[0188] FIG. 17 is a cross-sectional view in the lamination direction showing the mounting structure of a composite electronic component 1A according to the second embodiment of the present invention.

[0189] 12 and 13, a composite electronic component mounting structure 500A according to the second embodiment includes a composite electronic component 1 according to the second embodiment and a mounting substrate 80. The mounting substrate 80 includes a substrate core material 82 and connecting conductors (conductor lands) 84.

[0190] The core material 82 of the substrate is, for example, a substrate made of a material in which a base material made of a mixture of glass cloth and nonwoven glass cloth is impregnated with epoxy resin or polyimide resin, or a ceramic substrate manufactured by baking a sheet made of a mixture of ceramic and glass. The core material 82 of the substrate may be a single-layer substrate or a substrate made of multiple laminated layers. The thickness of the core material 82 of the substrate is not particularly limited, but is preferably, for example, 200 μm to 800 μm.

[0191] One main surface of the core material 82 of the substrate is provided with conductor lands 84 and constitutes a substrate-side mounting surface 82a on which the composite electronic component 1 is mounted.

[0192] The conductor lands 84 include a first conductor land 84a, a second conductor land 84b, a third conductor land 84c, and a fourth conductor land 84d.

[0193] The first conductor land 84a is a portion that is electrically connected and mechanically joined to the first external electrode 30a of the multilayer ceramic capacitor 10 by the bonding material 86. The second conductor land 84b is a portion that is electrically connected and mechanically joined to the second external electrode 30b of the multilayer ceramic capacitor 10 by the bonding material 86. The third conductor land 84c is a portion that is electrically connected and mechanically joined to the third external electrode 30c of the multilayer ceramic capacitor 10 by the bonding material 86. The fourth conductor land 84d is a portion that is electrically connected and mechanically joined to the fourth external electrode 30d of the multilayer ceramic capacitor 10 by the bonding material 86.

[0194] The conductor land 84 may be provided on the main surface of the core material 82 of the substrate opposite to the substrate-side mounting surface 82a.

[0195] The material of the conductor lands 84 is not particularly limited, but metals such as Cu, Au, Pd, and Pt can be used. The thickness of the conductor lands 84, i.e., the dimension in the stacking direction x, is not particularly limited, but is preferably 20 μm or more and 200 μm or less, for example. The bonding material 86 can be, for example, a high-heat-resistant epoxy adhesive or solder.

[0196] In the above description, the mounting substrate 80 corresponds to the mounting substrate of the present invention. The core material 82 of the substrate corresponds to the core material of the substrate of the present invention. The substrate-side mounting surface 82a corresponds to the mounting surface of the present invention. The multiple conductor lands 84 correspond to the multiple connecting conductors of the present invention. However, the connecting conductors of the present invention are not limited to so-called lands or other conductors that are provided between the multilayer ceramic capacitor 10 and the mounting substrate 80 and can electrically connect the two, and are not limited by other uses, functions, shapes, names, etc.

[0197] In the composite electronic component mounting structure 500A shown in FIG. 17, the composite electronic component 1A is preferably mounted so that the conductor portion 140 of the composite electronic component 1A is disposed facing away from the mounting substrate 80. That is, the conductor portion 140 of the composite electronic component 1A is preferably disposed on the first surface side (non-mounting surface side) of the multilayer ceramic capacitor 10, and the multilayer ceramic capacitor 10 of the composite electronic component 1A is preferably mounted on the mounting substrate 80 side. Mounting in this manner eliminates the need to increase the distance between the multilayer ceramic capacitor 10 and the mounting substrate 80, making it easier to achieve a low ESL effect. Furthermore, mounting can be performed without affecting the mounting of the composite electronic component 1A to the mounting substrate.

[0198] 4. Manufacturing method for composite electronic components A method for manufacturing the composite electronic component 1A according to the second embodiment of the present invention will now be described.

[0199] (a) Manufacturing method of multilayer ceramic capacitor The method for manufacturing the multilayer ceramic capacitor 10 is the same as that for the multilayer ceramic capacitor 10 of the first embodiment, and therefore the description thereof will be omitted.

[0200] (b) Manufacturing method of the conductor part Next, a method for manufacturing the conductor portion 140 of the composite electronic component 1A according to the second embodiment of the present invention will be described.

[0201] The conductor portion 140 can be manufactured by first manufacturing an assembly of the conductor portions 140 and then dividing the assembly of the conductor portions 140 into individual pieces.

[0202] The assembly of conductor portions 140 is manufactured in the same manner as a general printed circuit board.

[0203] The conductor portion 140, which is a single-sided substrate, is manufactured as follows. That is, first, a material having copper foil disposed on one main surface of an insulating substrate is prepared, and the material is cut to a predetermined size. Next, an etching resist is printed on the portion where the copper foil is to remain (e.g., the conductive pattern). Next, the copper foil other than the portion where the etching resist is applied is removed by etching. The etching resist on the remaining portion is then peeled off, and the conductive pattern is formed. Next, a solder resist is printed and UV-cured to form a protective layer to insulate the conductive patterns and prevent solder from adhering to unnecessary portions during the soldering process. Finally, the exposed electrode portion, where the conductive pattern is exposed, is subjected to surface treatment such as solder plating, electroless gold plating, or water-soluble flux treatment to improve solderability and prevent rusting of the copper foil portion. In this way, an assembly of conductor parts 140, which is a single-sided substrate, is manufactured.

[0204] The conductor portion 140B, which is an example of a double-sided substrate, is manufactured as follows. First, a base material with copper foil on both main surfaces of an insulating substrate is prepared and cut to the specified dimensions. Next, through-holes and via holes are drilled at the specified locations in the cut material. Next, interlayer connection conductors (penetrating through-holes) are formed by through-hole plating to electrically connect the copper foil surfaces on both main surfaces of the insulating substrate. Next, dry film (etching resist) is laminated onto both main surfaces of the insulating substrate. After exposure and development, the dry film is baked onto only the inner layer patterns. Next, the dry film is removed from unnecessary areas other than the conductive pattern, completing the resist for forming the conductive pattern. Next, the copper foil outside the conductive pattern is removed by etching. The remaining etching resist is then peeled off, forming the conductive pattern. After the conductive pattern is formed, a protective layer is formed by forming solder resist to insulate the conductive patterns and prevent solder from adhering to unnecessary areas during the soldering process. Finally, the exposed conductive pattern is subjected to surface treatments such as solder plating, electroless gold plating, and water-soluble flux treatment to improve solderability and prevent rust on the copper foil. In this way, an assembly of conductor parts 140B, which is an example of a double-sided substrate, is manufactured.

[0205] The conductor portion 140D, which is an example of a multilayer substrate, is manufactured as follows. First, the inner layer substrate and the outer layer substrate, which has copper foil arranged on the surface of an insulating base material, are cut to specified dimensions. Next, a dry film (etching resist) is laminated on both main surfaces of the cut material. Next, the material is exposed and developed, and the dry film is baked only on the inner layer pattern. Next, unnecessary parts other than the conductive pattern are removed, completing the resist for forming the conductive pattern. Next, the copper foil other than the conductive pattern is removed by etching. Next, the etching resist from the remaining parts is peeled off, forming the conductive pattern. Next, the inner layer substrate and the outer layer substrate, with the conductive pattern already formed, are pressed together using a prepreg (insulating base material) to produce a multilayer substrate. Next, holes such as through holes and via holes are drilled at specified locations on the manufactured multilayer substrate. Next, interlayer connection conductors (penetrating through holes) are formed by through-hole plating to electrically connect the copper foil surfaces arranged on both main surfaces of the multilayer substrate. Next, a dry film (etching resist) is laminated on both main surfaces of the multilayer substrate. Next, the substrate is exposed to light and developed, and a dry film is baked onto only the outer layer pattern. Next, unnecessary parts other than the conductive pattern are removed, completing the resist for forming the conductive pattern. Next, the copper foil is removed from parts other than the conductive pattern by etching. Next, the etching resist from the remaining parts is peeled off, forming the conductive pattern. Next, after the conductive pattern is formed, a protective layer is formed by forming solder resist to insulate between the conductive patterns and to prevent solder from adhering to unnecessary parts during the soldering process. Finally, surface treatments such as solder plating, electroless gold plating, and water-soluble flux treatment are performed on the parts where the conductive pattern is exposed to improve solderability and prevent rusting of the copper foil parts. In this way, an assembly of conductor parts 140D, which is an example of a multilayer substrate, is manufactured.

[0206] (c) Manufacturing method of composite electronic components Next, the assembly of the conductor parts 140 produced by the above method is divided into individual pieces, and the multilayer ceramic capacitor 10 produced by the above method is mounted on the individual pieces. The same applies to the conductor parts 140A to 140D.

[0207] More specifically, a cutting support tape is attached to the assembly of conductor portions 140. Next, the assembly of conductor portions 140 is cut into individual pieces to a predetermined size. Next, the individual conductor portions 140 are transferred to a heat-resistant plate. Note that heat-resistant tape, adhesive, or the like may be placed on the heat-resistant plate during transfer. Next, a conductive adhesive 70 is printed on the transferred individual conductor portions 140, and the multilayer ceramic capacitor 10 is mounted using a mounter.

[0208] Next, soldering is performed in a reflow furnace. Finally, the individual conductor portions 140 are removed from the heat-resistant plate, and the flux is washed away.

[0209] In this manner, the composite electronic component 1A shown in FIG. 1 is manufactured.

[0210] C. Third embodiment In the composite electronic component 1B according to the third embodiment, the conductor 140 that serves as an interposer substrate in the composite electronic component 1A according to the second embodiment is also configured as a conductor 140E described below.

[0211] Fig. 18 is an external perspective view showing a composite electronic component according to a third embodiment of the present invention, Fig. 19(a) is a front view of the composite electronic component according to the third embodiment of the present invention, and Fig. 19(b) is a rear view of the composite electronic component according to the third embodiment of the present invention.

[0212] A conductor portion 140E included in a composite electronic component 1B according to the third preferred embodiment further includes a first side electrode 162a and a second side electrode 162b in addition to the conductor portion 140. The conductor portion 140E includes a first side electrode 162a connected to the third external electrode 30c by a third conductive adhesive 70c, and a second side electrode 162b connected to the fourth external electrode 30d by a fourth conductive adhesive 70d. The exposed electrode portions 153a and 153b are insulated from the first side electrode 162a, and the exposed electrode portions 153a and 153b are insulated from the second side electrode 162b.

[0213] The composite electronic component 1B according to the modified example of the third embodiment shown in FIG. 18 has the same effects as the composite electronic component 1A of FIG. 12, and also has the following effects. That is, the first side electrode 162a and the second side electrode 162b make it easier to dissipate heat generated in the conductor portion 140E to the outside. Furthermore, the connection between the first side electrode 162a and the third external electrode 30c, and the connection between the second side electrode 162b and the fourth external electrode 30d makes it even easier to dissipate heat.

[0214] D. Fourth embodiment In the composite electronic component 1C according to the fourth embodiment, the conductor 40 which is a chip-type coil component in the composite electronic component 1 according to the first embodiment is configured as a conductor 140A, for example, as an interposer substrate.

[0215] Fig. 20 is an external perspective view showing a composite electronic component according to a fourth embodiment of the present invention, and Fig. 21 is a front view of the composite electronic component according to the fourth embodiment of the present invention.

[0216] The conductor portion 140A included in the composite electronic component 1C according to the fourth embodiment has the following features. That is, the dimension of the conductor portion 140A in the first direction y is larger than the dimension (L dimension) of the multilayer ceramic capacitor 10 in the first direction y.

[0217] The composite electronic component 1C according to the modified example of the fourth embodiment shown in FIG. 20 has the same effects as the composite electronic component 1A of FIG. 12, and also has the following effects. In other words, if the dimension of the conductor portion 140A in the first direction y is larger than the dimension of the multilayer ceramic capacitor 10 in the first direction y and the dimension of the multilayer ceramic capacitor 10 in the second direction z, it becomes easier for the conductive adhesive 70 to sufficiently wrap around the multilayer ceramic capacitor 10.

[0218] E. Modifications of the Multilayer Ceramic Capacitor According to the Present Embodiment Hereinafter, various modified examples (first and second modified examples) of the multilayer ceramic capacitor in the composite electronic component according to the present embodiment will be described. In addition, in these modified examples, components corresponding to those in the above-described embodiment will be given the same reference numerals, and detailed description thereof will be omitted.

[0219] (a) First Modification The multilayer ceramic capacitor 10A according to the first modified example of this embodiment differs from the multilayer ceramic capacitor 10 according to the first embodiment only in the structure of the first laminate 12A of the multilayer ceramic capacitor 10A. Therefore, the same parts as those in the multilayer ceramic capacitor 10 are denoted by the same reference numerals, and their description will be omitted.

[0220] Fig. 22 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. Fig. 23 is a cross-sectional view showing a first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. Fig. 24 is a cross-sectional view showing a dielectric layer on which a first internal electrode layer is arranged in the first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention. Fig. 25 is a cross-sectional view showing a dielectric layer on which a second internal electrode layer is arranged in the first modified example of the multilayer ceramic capacitor according to the embodiment of the present invention.

[0221] The multilayer ceramic capacitor 10A includes a first laminate 12A and external electrodes 30.

[0222] The first laminate 12A includes a plurality of stacked dielectric layers 14. The first laminate 12A further includes a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0223] At the ends (L gap) 24a, 24b of the first laminate 12A, a first dummy electrode 25a is arranged so as to be exposed on the third surface 12c, and a second dummy electrode 25b is arranged so as to be exposed on the fourth surface 12d.

[0224] The first dummy electrode 25a and the second dummy electrode 25b are preferably arranged on the same plane as the second internal electrode layer 16b, and have the same thickness as the second internal electrode layer 16b.

[0225] The current path can be shortened by reducing the coverage of the first dummy electrode 25a and the second dummy electrode 25b.

[0226] The first dummy electrode 25a and the second dummy electrode 25b may be disposed on the first outer layer portion 15b1 and the second outer layer portion 15b2. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the ends (L gaps) 24a and 24b of the first laminate 12A in the lamination direction x. By disposing them in this manner, when the plating layer 34 is provided without providing the base electrode layer 32, the plating layer 34 can be easily formed.

[0227] In addition, when the first dummy electrode 25a and the second dummy electrode 25b are provided on the same plane as the second internal electrode layer 16b, the first dummy electrode 25a and the second dummy electrode 25b can be arranged on the same plane as the second internal electrode layer 16b by printing the first dummy electrode 25a and the second dummy electrode 25b together with the second internal electrode layer 16b when printing the second internal electrode layer 16b.

[0228] In addition, a third dummy electrode 25c may be arranged on the side portions (W gap) 22a, 22b of the first laminate 12A so as to be exposed on the fifth surface 12e, and a fourth dummy electrode 25d may be arranged so as to be exposed on the sixth surface 12f.

[0229] The third dummy electrode 25c and the fourth dummy electrode 25d are preferably arranged on the same plane as the first internal electrode layer 16a and have the same thickness as the first internal electrode layer 16a.

[0230] The current path can be shortened by reducing the coverage of the third dummy electrode 25c and the fourth dummy electrode 25d.

[0231] The third dummy electrode 25c and the fourth dummy electrode 25d may be disposed on the first outer layer portion 15b1 and the second outer layer portion 15b2. In this case, they are preferably disposed on portions corresponding to positions obtained by translating the side portions (W gaps) 22a and 22b of the first laminate 12A in the stacking direction x. By disposing them in this manner, when the plating layer 34 is provided without providing the base electrode layer 32, it becomes easier to form the plating layer 34.

[0232] In addition, when the third dummy electrode 25c and the fourth dummy electrode 25d are provided on the same plane as the first internal electrode layer 16a, the third dummy electrode 25c and the fourth dummy electrode 25d can be arranged on the same plane as the first internal electrode layer 16a by printing the third dummy electrode 25c and the fourth dummy electrode 25d together with the second internal electrode layer 16b when printing the first internal electrode layer 16a.

[0233] In the multilayer ceramic capacitor 10A shown in Figures 22 to 25, first dummy electrodes 25a, second dummy electrodes 25b, third dummy electrodes 25c, and fourth dummy electrodes 25d are arranged on the side portions (W gaps) 22a, 22b of the first laminate 12A and the end portions (L gaps) 24a, 24b of the first laminate 12A, thereby preventing distortion during pressing.

[0234] (b) Second Modification The multilayer ceramic capacitor 10B according to the second modification of this embodiment differs from the multilayer ceramic capacitor 10 according to the first embodiment only in the structure of the first laminate 12B of the multilayer ceramic capacitor 10B. Therefore, the same parts as those in the multilayer ceramic capacitor 10 are denoted by the same reference numerals and their description will be omitted.

[0235] Fig. 26 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the preferred embodiment of the present invention. Fig. 27 is a cross-sectional view showing a second modified example of the multilayer ceramic capacitor according to the preferred embodiment of the present invention.

[0236] The first laminate 12B includes a plurality of stacked dielectric layers 14. The first laminate 12B further includes a first surface 12a and a second surface 12b facing in a stacking direction x, a third surface 12c and a fourth surface 12d facing in a first direction y perpendicular to the stacking direction x, and a fifth surface 12e and a sixth surface 12f facing in a second direction z perpendicular to the stacking direction x and the first direction y.

[0237] The first laminate 12B has an inner layer portion 15a, and a first outer layer portion 15b1 and a second outer layer portion 15b2 arranged so as to sandwich the inner layer portion 15a in the stacking direction x.

[0238] The dielectric layer 14 of the inner layer portion 15a may be disposed so as to be sandwiched between the first inner electrode layers 16a and 16a. In this case, the first inner electrode layers 16a and 16a are disposed continuously with the dielectric layer 14 of the inner layer portion 15a interposed therebetween.

[0239] The dielectric layer 14 of the inner layer portion 15a may be disposed so as to be sandwiched between the second internal electrode layers 16b. In this case, the second internal electrode layers 16b are disposed continuously with the dielectric layer 14 of the inner layer portion 15a interposed therebetween. The dielectric layer 14 of the inner layer portion 15a is composed of dielectric ceramic particles having a perovskite structure, with a perovskite-type compound containing, for example, Ba and Ti as the main component. At least one of Si, Mg, Ba, and Mn may be added as an additive to these main components. The additive is present between the ceramic particles.

[0240] The inner layer portion 15a of the first laminate 12B has a capacitance forming portion 26 where the first internal electrode layer 16a and the second internal electrode layer 16b face each other with the dielectric layer 14 interposed therebetween to form a capacitance, and an internal electrode laminate portion 28 which is a region where two or more first internal electrode layers 16a are continuously laminated. The capacitance forming portion 26 is what allows the multilayer ceramic capacitor 10B to exhibit its capacitor characteristics.

[0241] Moreover, the internal electrode laminate portion 28 is arranged so as to be divided by the second internal electrode layer 16b into a plurality of internal electrode laminate portions 28. This disperses the aggregate of the first internal electrode layers 16a, thereby improving the heat dissipation effect and obtaining the effect of suppressing a temperature rise.

[0242] As shown in Figures 26 and 27, in the multilayer ceramic capacitor 10B, the internal electrode laminate portion 28 is divided by two second internal electrode layers 16b, and the internal electrode laminate portion 28 is divided into a first internal electrode laminate portion 28a, a second internal electrode laminate portion 28b, and a third internal electrode laminate portion 28c.

[0243] The second internal electrode layer 16b arranged so as to divide the internal electrode laminated portion 28, which is a region where two or more first internal electrode layers 16a are continuously laminated, may be arranged singly. This makes it possible to laminate more first internal electrode layers 16a, thereby obtaining the effect of reducing DC resistance.

[0244] Furthermore, the second internal electrode layers 16b arranged so as to divide the internal electrode laminated portion 28, which is a region where two or more first internal electrode layers 16a are continuously laminated, may be arranged by continuously laminating two or more. This makes it possible to ensure more sufficient connectivity between the second internal electrode layers 16b and the external electrodes 30 even if the number of second internal electrode layers 16b is reduced.

[0245] The second internal electrode layer 16b may be disposed in the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the first surface 12a side of the first laminate 12B are continuously laminated, i.e., between the first internal electrode laminate portion 28a and the first surface 12a, and in the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the second surface 12b side of the first laminate 12B are continuously laminated, i.e., between the third internal electrode laminate portion 28c and the second surface 12b. This allows the capacitance forming portion 26 to be formed also in the vicinity of the first outer layer portion 15b1 and the second outer layer portion 15b2, thereby obtaining part of the capacitance, shortening the current path to the mounting board and achieving the effect of low ESL.

[0246] Furthermore, the second internal electrode layer 16b does not have to be disposed in the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the first surface 12a side of the first laminate 12B are continuously laminated, i.e., between the first internal electrode laminate portion 28a and the first surface 12a, or in the internal electrode laminate portion 28, which is a region where two or more first internal electrode layers 16a located on the second surface 12b side of the first laminate 12B are continuously laminated, i.e., between the third internal electrode laminate portion 28c and the second surface 12b. This increases the distance from the surface of the first laminate 12B to the capacitance forming portion 26 where capacitance is formed, and makes it less likely that insulation resistance will deteriorate even if a crack occurs from the surface of the first laminate 12B due to an external load.

[0247] The thickness of the dielectric layer 14 adjacent to the second internal electrode layer 16b is preferably greater than the thickness of the dielectric layer 14 sandwiched between the first internal electrode layers 16a. This makes it possible to stack more first internal electrode layers 16a, thereby further increasing the effect of reducing DC resistance.

[0248] Furthermore, it is preferable that the thickness of the second internal electrode layer 16b be greater than the thickness of the first internal electrode layer 16a. This ensures connectivity between the third lead electrode portion 20c of the second internal electrode layer 16b and the third external electrode 30c arranged on the fifth surface 12e, and also ensures connectivity between the fourth lead electrode portion 20d of the second internal electrode layer 16b and the fourth external electrode 30d arranged on the sixth surface 12f, even when the capacitance is further reduced.

[0249] F. Experimental Example Next, in order to confirm the effect of the composite electronic component according to the present invention described above, composite electronic components were fabricated as experimental samples according to the manufacturing method described above, with the thickness of the ridge line portion being varied, and the temperature rise of the composite electronic component due to the difference in the thickness of the ridge line portion was evaluated.

[0250] (1) Specifications of the multilayer ceramic capacitor fabricated as a sample for the experiment Using the manufacturing method according to the above embodiment, multilayer ceramic capacitors provided in multilayer ceramic electronic components, which are samples Nos. 1 to 11, were fabricated. - Dimensions of multilayer ceramic capacitor (design value): L x W x T = 1.6 mm x 0.8 mm x 0.8 mm Ceramic material: BaTiO3 Internal electrode layer material: Ni Number of first internal electrode layers: 16 Number of second internal electrode layers: 16 · Base electrode layer of external electrode: Conductive metal (Cu) and glass component Plating layer Two-layer formation of Ni plating layer and Sn plating layer Ni plating layer thickness: approx. 3 μm Sn plating layer thickness: approx. 5 μm

[0251] (2) Specifications of the conductor used as the sample in the experiment In this experimental example, the conductor portion 140 of the above-described embodiment was used. Conductor dimensions (design values): L x W x T = 1.7 mm x 0.9 mm x 0.4 mm

[0252] As shown in Table 1, samples No. 1 to No. 11 were prepared with the thickness t3 of the ridge line portion varied.

[0253] (3) Temperature rise measurement method When a direct current was applied, the temperature generated by the composite electronic component itself (each sample) was measured, and the temperature rise ΔT was calculated by subtracting the room temperature from the measured temperature. Specifically, a thermocouple was attached to the surface of the composite electronic component (sample). The temperature rise was evaluated as follows: ΔT ≥ 40°C was evaluated as "x", 30°C ≤ ΔT < 40°C was evaluated as "△", 20°C ≤ ΔT < 30°C was evaluated as "◯", and ΔT < 20 was evaluated as "◎". The temperature of the composite electronic component can also be measured using a thermal camera. The increase in temperature rise when a direct current flows is due to the increased DC resistance of the multilayer ceramic capacitor. Furthermore, the increase in temperature rise of the composite electronic component leads to a decrease in high-temperature load reliability. Therefore, in this experiment, the effects of the present invention were confirmed by measuring the temperature rise of the composite electronic component (sample).

[0254] (4) Results Table 1 shows the evaluation results of the temperature rise with respect to the change in thickness of the ridge line portion in the composite electronic components of each sample, sample No. 1 to sample No. 11.

[0255] [Table 1]

[0256] According to Table 1, when the results of the adhesion test were noted, when the ridgeline thickness was 5 μm, as in sample No. 1, the result was "×," but when the ridgeline thickness was 7 μm, as in sample No. 2, the result was "△." Furthermore, when the ridgeline thickness was 12 μm or more and 49 μm or less, as in samples Nos. 3 to 6, the result was "◯," and when the ridgeline thickness was 62 μm or more and 103 μm or less, as in samples Nos. 7 to 11, the result was "◎," resulting in favorable results. This confirmed that increasing the ridgeline thickness suppresses the temperature rise of composite electronic components.

[0257] The above results suggest that, in this invention, the conductive adhesive is disposed from the first region to the second region of the first external electrode, and by setting the thickness of at least one ridge portion of the multilayer ceramic capacitor within a predetermined range, the volume of the metal component in that ridge portion can be increased. Therefore, it is suggested that increasing the thickness of the ridge portion of the multilayer ceramic capacitor can suppress the temperature rise of the composite electronic component, and as a result, the increase in the electrical resistance of the composite electronic component is suppressed.

[0258] As described above, the embodiment of the present invention has been disclosed in the above description, but the present invention is not limited to this.

[0259] In other words, various modifications can be made to the above-described embodiments in terms of mechanism, shape, material, quantity, position, arrangement, etc. without departing from the scope of the technical idea and purpose of the present invention, and these modifications are included in the present invention.

[0260] <1> a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the fourth surface; a third external electrode disposed on the fifth surface and the first surface; a fourth external electrode disposed on the sixth surface and the first surface; a multilayer ceramic capacitor comprising: a conductor portion electrically connected to the first external electrode and the second external electrode; A composite electronic component comprising: the first external electrode has a first region disposed on a surface on the first surface side and a second region disposed on a surface on the third surface side, The conductor portion is a first electrode connected to the first external electrode by the first conductive adhesive; a second electrode connected to the second external electrode by the second conductive adhesive; and When the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the conductor portion is Rdc2, Rdc2≦Rdc1; A composite electronic component, wherein the first conductive adhesive is disposed across the first region and the second region of the first external electrode.

[0261] <2> the second external electrode has a third region disposed on a surface on the first surface side and a fourth region disposed on a surface on the fourth surface side, the second conductive adhesive is disposed across the second external electrode from the third region to the fourth region. <1> The composite electronic component according to claim 1.

[0262] <3> In a cross section of the laminate parallel to the fifth surface or the sixth surface, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the first external electrode and the thickness of the first conductive adhesive along an extension line of the first surface in the cross section is 7 μm or more. <1> or <2> The composite electronic component according to claim 1.

[0263] <4> In a cross section of the laminate parallel to the fifth surface or the sixth surface, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the second external electrode along an extension line of the first surface in the cross section and the thickness of the second conductive adhesive is 7 μm or more. <2> or <3> 10. The composite electronic component according to claim 9, wherein

[0264] <5> In a cross section of the laminate parallel to the fifth surface or the sixth surface, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the first external electrode along an extension line of the first surface in the cross section and the thickness of the first conductive adhesive is 12 μm or more. <1> The composite electronic component according to claim 1.

[0265] <6> In a cross section of the laminate parallel to the fifth surface or the sixth surface, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the second external electrode and the second conductive adhesive along an extension line of the first surface in the cross section is 12 μm or more. <2> Or <5> 10. The composite electronic component according to claim 9, wherein

[0266] <7> In a cross section of the laminate parallel to the fifth surface or the sixth surface, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the first external electrode along an extension line of the first surface in the cross section and the thickness of the first conductive adhesive is 62 μm or more. <1> The composite electronic component according to claim 1.

[0267] <8> In a cross section of the laminate parallel to the fifth surface or the sixth surface, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the second external electrode and the second conductive adhesive along an extension line of the first surface in the cross section is 62 μm or more. <2> Or <7> The composite electronic component according to claim 1.

[0268] <9> The conductor portion is a chip-type coil component. <1> Or <8> 10. The composite electronic component according to claim 9, wherein

[0269] <10> an insulating resin is disposed between the conductor portion and the multilayer ceramic capacitor; The insulating resin covers at least a portion of the multilayer ceramic capacitor. <1> Or <9> 10. The composite electronic component according to claim 9, wherein

[0270] <11> an insulating resin is disposed between the conductor portion and the multilayer ceramic capacitor; The insulating resin covers at least a part of the conductor portion. <1> Or <9> 10. The composite electronic component according to claim 9, wherein

[0271] <12> an insulating resin is disposed between the conductor portion and the multilayer ceramic capacitor; the insulating resin covers at least a portion of the multilayer ceramic capacitor and at least a portion of the conductor portion; <1> Or <9> 10. The composite electronic component according to claim 9, wherein

[0272] <13> The laminate is a first internal electrode connected to the first external electrode and the second external electrode; a second internal electrode connected to the third external electrode and the fourth external electrode; <1> Or <12> 10. The composite electronic component according to claim 9, wherein

[0273] <14> The conductor portion is a third electrode connected to the third external electrode by a third conductive adhesive; a fourth electrode connected to the fourth external electrode by a fourth conductive adhesive; Equipped with the first electrode is insulated from at least one of the third electrode and the fourth electrode; the second electrode is insulated from at least one of the third electrode and the fourth electrode; <1> Or <13> 10. The composite electronic component according to claim 9, wherein

[0274] <15> A gap is disposed inside the first conductive adhesive or the second conductive adhesive. <1> Or <14> 10. The composite electronic component according to claim 9, wherein [Explanation of symbols]

[0275] 1, 1A, 1B, 1C Composite Electronic Components 10, 10A, 10B Multilayer Ceramic Capacitors 500, 500A composite electronic component mounting structure 12, 12A, 12B First laminate 12a First Side 12b Second Side 12c Third Face 12d Fourth Face 12e The Fifth Side 12th floor, 6th floor 14 Dielectric layer 15a Inner layer 15b1 First outer layer 15b2 Second outer layer 16 Internal electrode layer 16a First internal electrode layer 16b Second internal electrode layer 18a first opposing electrode portion 18b Second opposing electrode portion 20a First extraction electrode portion 20b Second extraction electrode portion 20c Third extraction electrode portion 20d Fourth extraction electrode part 22a, 22b Side (W gap) 24a, 24b Ends (L gap) 30 External electrode 30a First outer electrode 30b Second external electrode 30c Third external electrode 30d Fourth external electrode 32 Base electrode layer 32a First base electrode layer 32b Second base electrode layer 32c Third base electrode layer 32d Fourth base electrode layer 34 plating layer 34a First plating layer 34b Second plating layer 34c Third plating layer 34d Fourth plating layer 40 Conductor part (chip type coil component) 42 Second laminate 42a First Face 42b Second Side 42c Third Face 42d The Fourth Side 42e The Fifth Side 42f Sixth Side 44 ferrite layer 46 Coil 48 Patterned Conductors 50 Beer 52a, 52b Lead conductor 60 Conductor electrodes 60a First conductor electrode 60b Second conductor electrode 62 Conductor base electrode 62a First conductor base electrode 62b Second conductor base electrode 64 Conductor plating layer 64a First conductor plating layer 64b Second conductor plating layer 70 Conductive adhesive 70a First conductive adhesive 70b Second conductive adhesive 70c Third Conductive Adhesive 70d 4th conductive adhesive 140, 140A~140E Conductor part 150, 150a~150c Insulating substrate 152, 152a, 152b Conductive patterns 153a~153d Exposed electrode part 154 Protective layer 156a to 156d Land electrode part 158a, 158b Interlayer connection conductor (end face through hole) 160a, 160b Interlayer connection conductor (penetrating through hole) 162a first side electrode 162b second side electrode 80 Mounting board 82 Core material 82a PCB mounting surface 84a, 84b, 84c, 84d Connecting conductors (lands) 86 Joining material (solder) 25a First dummy electrode 25b Second dummy electrode 25c Third dummy electrode 25d Fourth dummy electrode 26 Capacity forming part 28 Internal electrode laminate 28a First internal electrode laminate 28b Second internal electrode laminate 28c Third internal electrode laminate x stacking direction y primary direction z second direction

Claims

1. a laminate having a first surface and a second surface facing each other in a stacking direction, a third surface and a fourth surface facing each other in a first direction perpendicular to the stacking direction, and a fifth surface and a sixth surface facing each other in a second direction perpendicular to the stacking direction and the first direction; a first external electrode disposed on the first surface and the third surface; a second external electrode disposed on the first surface and the fourth surface; a third external electrode disposed on the fifth surface and the first surface; a fourth external electrode disposed on the sixth surface and the first surface; a multilayer ceramic capacitor comprising: a conductor portion electrically connected to the first external electrode and the second external electrode; A composite electronic component comprising: the first external electrode has a first region disposed on a surface on the first surface side and a second region disposed on a surface on the third surface side, The conductor portion is a first electrode connected to the first external electrode by the first conductive adhesive; a second electrode connected to the second external electrode by the second conductive adhesive; and When the DC resistance of the multilayer ceramic capacitor is Rdc1 and the DC resistance of the conductor portion is Rdc2, Rdc2≦Rdc1; The composite electronic component, wherein the first conductive adhesive is disposed across the first region and the second region of the first external electrode.

2. the second external electrode has a third region disposed on a surface facing the first surface and a fourth region disposed on a surface facing the fourth surface, 2. The composite electronic component according to claim 1, wherein the second conductive adhesive is disposed across the second external electrode from the third region to the fourth region.

3. 2. The composite electronic component according to claim 1, wherein in a cross section parallel to the fifth surface or the sixth surface of the laminate, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the first external electrode along an extension line of the first surface in the cross section and the thickness of the first conductive adhesive is 7 μm or more.

4. 3. The composite electronic component according to claim 2, wherein in a cross section parallel to the fifth surface or the sixth surface of the laminate, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the second external electrode along an extension line of the first surface in the cross section and the thickness of the second conductive adhesive is 7 μm or more.

5. 2. The composite electronic component according to claim 1, wherein in a cross section parallel to the fifth surface or the sixth surface of the laminate, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the first external electrode along an extension line of the first surface in the cross section and the thickness of the first conductive adhesive is 12 μm or more.

6. 3. The composite electronic component according to claim 2, wherein in a cross section parallel to the fifth surface or the sixth surface of the laminate, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the second external electrode along an extension line of the first surface in the cross section and the thickness of the second conductive adhesive is 12 μm or more.

7. 2. The composite electronic component according to claim 1, wherein in a cross section parallel to the fifth surface or the sixth surface of the laminate, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the first external electrode along an extension line of the first surface in the cross section and the thickness of the first conductive adhesive is 62 μm or more.

8. 3. The composite electronic component according to claim 2, wherein in a cross section parallel to the fifth surface or the sixth surface of the laminate, cut at a length that is half the dimension of the laminate in the second direction, the total thickness of the thickness of the second external electrode along an extension line of the first surface in the cross section and the thickness of the second conductive adhesive is 62 μm or more.

9. 3. The composite electronic component according to claim 1, wherein the conductor portion is a chip-type coil component.

10. an insulating resin is disposed between the conductor portion and the multilayer ceramic capacitor; 3. The composite electronic component according to claim 1, wherein the insulating resin covers at least a part of the multilayer ceramic capacitor.

11. an insulating resin is disposed between the conductor portion and the multilayer ceramic capacitor; 3. The composite electronic component according to claim 1, wherein the insulating resin covers at least a part of the conductor portion.

12. an insulating resin is disposed between the conductor portion and the multilayer ceramic capacitor; 3. The composite electronic component according to claim 1, wherein the insulating resin covers at least a part of the multilayer ceramic capacitor and at least a part of the conductor portion.

13. The laminate is a first internal electrode layer connected to the first external electrode and the second external electrode; 3. The composite electronic component according to claim 1, further comprising a second internal electrode layer connected to the third external electrode and the fourth external electrode.

14. The conductor portion is a third electrode connected to the third external electrode by a third conductive adhesive; a fourth electrode connected to the fourth external electrode by a fourth conductive adhesive; Equipped with the first electrode is insulated from at least one of the third electrode and the fourth electrode; 3. The composite electronic component according to claim 1, wherein the second electrode is insulated from at least one of the third electrode and the fourth electrode.

15. 3. The composite electronic component according to claim 1, wherein a gap is disposed inside the first conductive adhesive or the second conductive adhesive.

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