Semiconductor device

Abstract

To provide a semiconductor device having excellent transistor characteristics.SOLUTION: A semiconductor device includes: a substrate; a first region and a second region disposed side by side on one side in a first direction with respect to the substrate; and a first insulating layer and a metal oxide layer disposed at a position farther from the substrate than the first region, on the one side in the first direction with respect to the substrate. The first region includes: a first transistor having a first semiconductor layer containing Si; and a second insulating layer disposed between the first insulating layer and the first transistor and between the metal oxide layer and the first transistor. The second region includes: a second transistor having a second semiconductor layer containing an oxide semiconductor; and a third insulating layer disposed between the first insulating layer and the second transistor and between the metal oxide layer and the second transistor. The metal oxide layer contains: at least one element selected from the group consisting of Al, Hf, Zr, La, and Y; and oxygen (O). Each of the second insulating layer and the third insulating layer contains Si and oxygen (O). A density of the third insulating layer is higher than a density of the second insulating layer.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present embodiment relates to a semiconductor device. [Background technology]

[0002] BACKGROUND ART A semiconductor device is known that includes an oxide semiconductor layer, a first wiring that faces the oxide semiconductor layer, and a gate insulating film that is provided between the oxide semiconductor layer and the first wiring. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-169490 Summary of the Invention [Problem to be solved by the invention]

[0004] A semiconductor device having excellent transistor characteristics is provided. [Means for solving the problem]

[0005] A semiconductor device according to one embodiment includes a substrate, a first region disposed on one side of the substrate in a first direction intersecting the surface of the substrate, a second region disposed on one side of the substrate in the first direction and parallel to the first region in the first direction or a second direction intersecting the first direction, and a first insulating layer and a metal oxide layer disposed on one side of the substrate in the first direction, farther from the first and second regions. The first region includes a first transistor having a first semiconductor layer containing silicon (Si) and a second insulating layer disposed between the first insulating layer and the metal oxide layer and the first transistor. The second region includes a second transistor having a second semiconductor layer containing an oxide semiconductor and a third insulating layer disposed between the first insulating layer and the metal oxide layer and the second transistor. The metal oxide layer includes at least one element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), and yttrium (Y), and oxygen (O). The second insulating layer and the third insulating layer each contain silicon (Si) and oxygen (O). The density of the third insulating layer is higher than the density of the second insulating layer. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a schematic circuit diagram showing a configuration of a portion of a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor device. [Figure 3] FIG. 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor device. [Figure 4] FIG. 2 is a schematic plan view showing a configuration of a part of the semiconductor device. [Figure 5] FIG. 2 is a schematic plan view showing a configuration of a part of the semiconductor device. [Figure 6] FIG. 2 is a schematic plan view showing a configuration of a part of the semiconductor device. [Figure 7] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor device. [Figure 8] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 9]5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 10] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 11] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 12] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 13] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 14] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 15] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 16] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 17] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 18] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 19] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 20] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 21] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 22] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 23] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 24] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 25] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 26] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 27] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 28] FIG. 10 is a schematic cross-sectional view for explaining a semiconductor device according to a comparative example. [Figure 29] FIG. 2 is a schematic cross-sectional view for explaining the effect of the semiconductor device according to the first embodiment. [Figure 30] 1 is a schematic cross-sectional view showing a partial configuration of a first modified example of the semiconductor device according to the first embodiment. [Figure 31] FIG. 10 is a schematic cross-sectional view showing a partial configuration of a second modified example of the semiconductor device according to the first embodiment. [Figure 32] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor device according to a second embodiment. [Figure 33] 5A to 5C are schematic cross-sectional views for explaining a manufacturing method of the semiconductor device. [Figure 34] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 35] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 36] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 37] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 38] 5A to 5C are schematic cross-sectional views for explaining the manufacturing method. [Figure 39] FIG. 10 is a schematic cross-sectional view for explaining the effect of the semiconductor device according to the second embodiment. [Figure 40] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor device according to a third embodiment. [Figure 41] 10A and 10B are schematic cross-sectional views for explaining the effect of the semiconductor device. [Figure 42] FIG. 10 is a schematic cross-sectional view showing a configuration of a portion of a semiconductor device according to a fourth embodiment. [Figure 43] 10A and 10B are schematic cross-sectional views for explaining the effect of the semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0007] Next, semiconductor devices according to embodiments will be described in detail with reference to the drawings. Note that the following embodiments are merely examples and are not intended to limit the present invention. Furthermore, the following drawings are schematic, and for the sake of convenience, some configurations may be omitted. Furthermore, parts common to multiple embodiments are given the same reference numerals, and descriptions thereof may be omitted.

[0008] Furthermore, in this specification, when a first component is said to be "electrically connected" to a second component, the first component may be directly connected to the second component, or the first component may be connected to the second component via wiring, a semiconductor member, a transistor, etc. For example, when three transistors are connected in series, the first transistor is "electrically connected" to the third transistor even if the second transistor is in the OFF state.

[0009] In this specification, a predetermined direction parallel to the upper surface of the substrate is called the X direction, a direction parallel to the upper surface of the substrate and perpendicular to the X direction is called the Y direction, and a direction perpendicular to the upper surface of the substrate is called the Z direction.

[0010] In addition, in this specification, a direction along a predetermined plane may be referred to as the first direction, a direction along this predetermined plane that intersects with the first direction may be referred to as the second direction, and a direction that intersects with this predetermined plane may be referred to as the third direction. These first, second, and third directions may or may not correspond to any of the X, Y, and Z directions.

[0011] Furthermore, in this specification, expressions such as "upper" and "lower" are based on a specific substrate. For example, the direction away from the specific substrate along the Z direction is referred to as "up," and the direction approaching the specific substrate along the Z direction is referred to as "lower." Furthermore, when referring to a certain configuration, the lower surface or lower end refers to the surface or end of the configuration facing the specific substrate, and when referring to the upper surface or upper end, refers to the surface or end of the configuration facing away from the specific substrate. Furthermore, surfaces that intersect with the X or Y direction are referred to as side surfaces, etc.

[0012] Furthermore, in this specification, when referring to a configuration, member, etc., "width," "length," or "film thickness" in a specific direction, this may mean the width, length, or thickness in a cross section observed by SEM (Scanning Electron Microscopy), TEM (Transmission Electron Microscopy), or the like.

[0013] [First embodiment] [Circuit configuration] The semiconductor device according to the first embodiment includes, for example, a memory cell array MCA and a peripheral circuit PC as shown in FIG.

[0014] The memory cell array MCA includes a plurality of bit lines BL, a plurality of word lines WL, a plurality of plate lines PL, and a plurality of memory cells MC connected to the plurality of bit lines BL, the plurality of word lines WL, and the plurality of plate lines PL. The plurality of memory cells MC connected to one word line WL are each connected to a different bit line BL. Also, the plurality of memory cells MC connected to one bit line BL are each connected to a different word line WL.

[0015] Each memory cell MC includes a select transistor ST and a capacitor Cap connected in series between a bit line BL and a plate line PL.

[0016] The select transistors ST are field-effect transistors that include a semiconductor layer that functions as a channel region, a gate insulating film, and a gate electrode. The gate electrodes of the select transistors ST are each connected to a word line WL.

[0017] The capacitor Cap includes a pair of electrodes and an insulating film, and includes a memory section.

[0018] The peripheral circuit PC includes, for example, a voltage generation circuit that generates an operating voltage and outputs it to a voltage supply line, a decode circuit that connects the desired voltage supply line to each wiring (bit line BL, word line WL, and plate line PL) in the memory cell array MCA, and a sense amplifier circuit that detects the current or voltage of the bit line BL.

[0019] [Memory area R MC , the surrounding area R PC ] 2 is a schematic cross-sectional view showing a configuration of a part of the semiconductor device according to the first embodiment. As shown in FIG. 2, the semiconductor device according to the first embodiment includes a substrate Sub and a transistor layer L spaced apart from the substrate Sub in the Z direction. Tr and the transistor layer L Tr The wiring layer L provided above ML and the wiring layer L ML The wiring layer L provided above UL and the transistor layer L Tr The capacitor layer L CP and the capacitor layer L CP The plate line layer L PT and the plate line layer L PT A peripheral circuit layer L provided on the substrate Sub below PC The substrate Sub includes, for example, P-type silicon (Si) containing P-type impurities such as boron (B).

[0020] As shown in FIG. 2, the semiconductor device according to the first embodiment includes a memory region R provided on a substrate Sub. MC and the surrounding area R PC The memory area R MC and the surrounding area R PC are aligned in the Y direction.

[0021] [Memory area R MC Structure of Next, referring to FIGS. 2 to 6, the memory area R MC The structure of the memory area R is explained in Figure 3. MCFig. 4 is a schematic cross-sectional view showing a part of the configuration of Fig. 3, taken along line AA' and viewed in the direction of the arrows. Fig. 5 is a schematic cross-sectional view of the configuration of Fig. 3, taken along line BB' and viewed in the direction of the arrows. Fig. 6 is a schematic cross-sectional view of the configuration of Fig. 3, taken along line CC' and viewed in the direction of the arrows.

[0022] Memory area R MC Transistor layer L Tr For example, as shown in FIGS. 2 to 4, the capacitor layer L CP an insulating layer 111H provided on the upper surface of the insulating layer 111H, an insulating layer 113H provided above the insulating layer 111H, a plurality of insulating layers 112H and a plurality of conductive layers 150 (FIG. 4) provided between the insulating layer 111H and the insulating layer 113H and arranged alternately in the X direction, and an electrode 151 (FIG. 2) connected to the lower end of the conductive layer 150. The insulating layer 111H, the insulating layer 112H, and the insulating layer 113H will be described later.

[0023] Also, memory area R MC Transistor layer L Tr 4, the transistor structure Tr10 includes a plurality of semiconductor layers 130 aligned in the Y direction corresponding to the plurality of conductive layers 150 and aligned in the X direction along the plurality of conductive layers 150, and a plurality of insulating layers 140 provided on the outer peripheral surfaces of the plurality of semiconductor layers 130. Hereinafter, a structure including the semiconductor layers 130, the insulating layers 140, and parts of the conductive layers 150 may be referred to as a transistor structure Tr10 (FIG. 2). The transistor structure Tr10 functions as a select transistor ST (FIG. 1).

[0024] The semiconductor layer 130 extends in, for example, the Z direction and has a substantially cylindrical shape. The semiconductor layer 130 functions as, for example, a channel region of the select transistor ST (FIG. 1). The semiconductor layer 130 includes an oxide semiconductor. The semiconductor layer 130 includes, for example, at least one element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), calcium (Ca), titanium (Ti), manganese (Mn), cadmium (Cd), and tin (Sn), zinc (Zn), and oxygen (O). The semiconductor layer 130 includes, for example, indium (In), gallium (Ga), zinc (Zn), and oxygen (O).

[0025] The insulating layer 140 extends in, for example, the Z direction and has a substantially cylindrical shape. A portion of the insulating layer 140 is provided between the conductive layer 150 and the semiconductor layer 130. The insulating layer 140 functions, for example, as a gate insulating film of the select transistor ST (FIG. 1). The insulating layer 140 includes, for example, silicon oxide (SiO2) or the like. The insulating layer 140 may have a stacked structure of silicon oxide (SiO2) and silicon nitride (SiN) or other insulating layers with a high dielectric constant.

[0026] The conductive layer 150 extends in, for example, the Y direction. The conductive layer 150 surrounds a portion of the outer periphery of each of the semiconductor layers 130 aligned in the Y direction and faces a portion of the outer periphery of the semiconductor layer 130. The conductive layer 150 functions as the gate electrodes of the select transistors ST aligned in the Y direction and the word lines WL (FIG. 1) of the memory cell array MCA. The conductive layer 150 may include, for example, tungsten (W) or a stacked structure of titanium nitride (TiN) and tungsten (W).

[0027] The electrode 151 extends in, for example, the Z direction and has a substantially cylindrical shape. The electrode 151 includes, for example, tungsten (W) or a laminated structure of titanium nitride (TiN) and tungsten (W).

[0028] Memory area R MC Wiring layer L ML For example, as shown in FIG. TrThe plug layer L PL and plug layer L PL The bit line layer L BL and the bit line layer L BL and a metal oxide layer 191 and an insulating layer 196 provided on the upper surface of the insulating layer 190H. The insulating layer 190H will be described later.

[0029] Plug Layer L PL 3 and 5, the transistor layer L Tr The semiconductor layer 130 includes a conductive layer 170, a conductive layer 171, and a conductive layer 172, which are provided in this order on the upper surface of the semiconductor layer 130. The conductive layer 170, the conductive layer 171, and the conductive layer 172 are electrically connected to the semiconductor layer 130.

[0030] 3 and 5, the structure including the conductive layer 170, the conductive layer 171, and the conductive layer 172 has a generally cylindrical shape extending in the Z direction, and a plurality of such structures are arranged side by side in the X direction and the Y direction. The conductive layer 170, the conductive layer 171, and the conductive layer 172 function as, for example, the source electrode of the select transistor ST. Between the structures including the conductive layer 170, the conductive layer 171, and the conductive layer 172, for example, an insulating layer 173H is provided. The insulating layer 173H will be described later.

[0031] The conductive layer 170 contains, for example, at least one element selected from the group consisting of indium (In), tin (Sn), niobium (Nb), titanium (Ti), tungsten (W), ruthenium (Ru), tantalum (Ta), iridium (Ir), and molybdenum (Mo), and oxygen (O). The conductive layer 170 may be, for example, indium tin oxide (InSnO).

[0032] The conductive layer 171 includes, for example, titanium nitride (TiN).

[0033] The conductive layer 172 includes, for example, tungsten (W), aluminum (Al), molybdenum (Mo), or the like.

[0034] Bit line layer L BL 3 and 6, the plug layer L is formed at a position corresponding to the conductive layer 172. PL The conductive layer 181, the conductive layer 182, and the conductive layer 184 are provided in this order on the upper surface of the conductive layer 172. The conductive layer 181, the conductive layer 182, and the conductive layer 184 are electrically connected to the plurality of conductive layers 172 arranged in the X direction.

[0035] 3 and 6, a structure including the conductive layer 181, the conductive layer 182, and the conductive layer 184 extends in the X direction and is arranged in a plurality of layers in the Y direction. The conductive layer 181, the conductive layer 182, and the conductive layer 184 function as, for example, the bit lines BL (FIG. 1) of the memory cell array MCA. Between the structures including the conductive layer 181, the conductive layer 182, and the conductive layer 184, for example, an insulating layer 183H is provided. The insulating layer 183H will be described later.

[0036] The conductive layer 181 and the conductive layer 184 include, for example, titanium nitride (TiN).

[0037] The conductive layer 182 includes, for example, tungsten (W), aluminum (Al), molybdenum (Mo), or the like.

[0038] The metal oxide layer 191 and the insulating layer 196 extend in the X and Y directions, for example, as shown in FIG. MC and the surrounding area R PC At least a portion of the metal oxide layer 191 functions as a layer that increases the efficiency of oxygen introduction into the semiconductor layer 130, for example, in a first oxidation treatment (FIG. 25) described later. The metal oxide layer 191 also functions as a layer that prevents hydrogen (H) from diffusing from the insulating layer 196 and prevents the semiconductor layer 130 from being reduced (deoxidized), for example, in a post-annealing treatment described later.

[0039] The metal oxide layer 191 contains a metal element ME and oxygen (O). The metal element ME is, for example, at least one metal element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), and yttrium (Y).

[0040] The metal oxide layer 191 is mainly composed of, for example, a metal element ME and oxygen (O). The metal oxide layer 191 may contain, for example, a metal oxide such as aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), lanthanum oxide (LaO), or yttrium oxide (YO). When the metal oxide layer 191 contains aluminum oxide (AlO), hafnium oxide (HfO), zirconium oxide (ZrO), lanthanum oxide (LaO), or yttrium oxide (YO), the insulating properties of the metal oxide layer are improved.

[0041] The metal oxide layer 191 has a thickness d191 in the Z direction (FIG. 3). The thickness d191 is, for example, 5 nm or more and 20 nm or less. By forming the metal oxide layer 191 with such a thickness, the semiconductor layer 130 is more effectively prevented from being reduced (deoxidized) in the post-annealing treatment described later.

[0042] The insulating layer 196 is provided, for example, on the upper surface of the metal oxide layer 191 in contact with the metal oxide layer 191. The insulating layer 196 contains, for example, nitrogen (N) and silicon (Si). The insulating layer 196 may be silicon nitride (Si3N4). Note that the insulating layer 196 may contain a large amount of hydrogen (H) in its material and may serve as a hydrogen supply source. For example, in a post-annealing process described below, hydrogen (H) may be released from the insulating layer 196 and diffuse to the surrounding area. The insulating layer 196 has a thickness d196 in the Z direction (FIG. 3). The thickness d196 is, for example, 5 nm or more and 100 nm or less.

[0043] Memory area R MC Wiring layer L UL2, includes a wiring 301 provided on the upper surface of the insulating layer 196, a wiring 302 provided on the upper surface of the wiring 301 and connected to the wiring 301, and a wiring 303 provided on the upper surface of the wiring 302 and connected to the wiring 302. An insulating layer 304H is provided between the wiring 301, the wiring 302, and the wiring 303. The insulating layer 304H will be described later.

[0044] The wiring 301, the wiring 302, and the wiring 303 function as wirings that supply voltage and current to the bit lines BL, for example. The wiring 301, the wiring 302, and the wiring 303 include, for example, copper (Cu), tungsten (W), aluminum (Al), or the like.

[0045] Memory area R MC The capacitor layer L CP 2 and 3, includes a plurality of capacitor structures CP10 arranged in the X and Y directions. The plurality of capacitor structures CP10 are provided corresponding to the plurality of transistor structures Tr10, respectively.

[0046] The capacitor structure CP10 includes a conductive layer 120 connected to the lower end of the semiconductor layer 130, a conductive layer 201 connected to the lower end of the conductive layer 120, a conductive layer 121 provided on the outer peripheral surface of the conductive layer 120 and on the outer peripheral surface and lower surface of the conductive layer 201, an insulating layer 202 provided on the outer peripheral surface and lower surface of the conductive layer 121, and a conductive layer 203 provided on the outer peripheral surface and lower surface of the insulating layer 202. The capacitor structure CP10 functions as a capacitor Cap (FIG. 1). For example, an insulating layer 100H is provided between the plurality of capacitor structures CP10. The insulating layer 100H will be described later.

[0047] The conductive layer 120 functions as, for example, a drain electrode of the select transistor ST (FIG. 1) and part of one electrode of the capacitor Cap (FIG. 1). The conductive layer 120 is substantially circular in the XY cross section and may have a plug shape. The conductive layer 120 includes, for example, the same material as the conductive layer 170. The conductive layer 120 may be, for example, indium tin oxide (InSnO) or the like.

[0048] The conductive layer 121 functions as, for example, a part of one electrode of a capacitor Cap (FIG. 1). The conductive layer 121 may be, for example, titanium nitride (TiN).

[0049] The conductive layer 201 functions as a part of one electrode of the capacitor Cap (FIG. 1). The conductive layer 201 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0050] The insulating layer 202 functions as an insulating layer between the electrodes of the capacitor Cap (FIG. 1). The insulating layer 202 includes, for example, aluminum oxide (AlO). The insulating layer 202 may also be, for example, silicon oxide (SiO2) or other insulating metal oxides.

[0051] The conductive layer 203 functions as, for example, the other electrode of the capacitor Cap (FIG. 1). The conductive layer 203 includes, for example, a stacked structure of titanium nitride (TiN) and tungsten (W).

[0052] Memory area R MC Plate line layer L PT For example, as shown in FIG. CP The conductive layer 204 is electrically connected to the plurality of conductive layers 203. The conductive layer 204 functions as, for example, a plate line PL (FIG. 1). The conductive layer 204 may include, for example, tungsten (W) or a stacked structure of titanium nitride (TiN) and tungsten (W).

[0053] [Surrounding Area R PC Structure of Next, referring to FIG. 2, the peripheral region R PC The structure of is explained below.

[0054] Surrounding area R PC Transistor layer L Tr For example, as shown in FIG. CP the top surface of the wiring layer L MLThe insulating layer 110L is provided in contact with the lower surface of the substrate 110. The insulating layer 110L will be described later.

[0055] Surrounding area R PC Wiring layer L ML For example, as shown in FIG. Tr The semiconductor device includes an insulating layer 180L provided on the upper surface of the insulating layer 180L, wiring 185 provided inside the insulating layer 180L, an electrode 192 connected to the upper surface of the wiring 185, an insulating layer 190L provided on the upper surface of the insulating layer 180L, and a metal oxide layer 191 and an insulating layer 196 provided on the upper surface of the insulating layer 190L. The insulating layer 180L and the insulating layer 190L will be described later.

[0056] The wiring 185 includes, for example, copper (Cu), tungsten (W), aluminum (Al), or the like.

[0057] 2, the electrode 192 extends in the Z direction and has a generally cylindrical shape. The upper surface of the electrode 192 is provided at the same position as the upper surface of the insulating layer 196, for example. The electrode 192 is provided so as to penetrate the insulating layer 190L, the metal oxide layer 191, and the insulating layer 196, for example. The electrode 192 may include, for example, tungsten (W) or a stacked structure of titanium nitride (TiN) and tungsten (W).

[0058] Surrounding area R PC Wiring layer L UL is basically a memory area R MC Wiring layer L UL However, the surrounding area R PC Wiring layer L UL In this example, an insulating layer 304L, rather than an insulating layer 304H, is provided between the wiring 301, the wiring 302, and the wiring 303. The insulating layer 304L will be described later.

[0059] Surrounding area R PC The capacitor layer L CP For example, as shown in FIG. 2, PTand an electrode CC provided so as to penetrate the insulating layer 100L. The insulating layer 100L will be described later.

[0060] The electrode CC extends in the Z direction, for example, and is connected at its upper end to the electrode 151 and at its lower end to the plate line layer L PT The electrode CC is electrically connected to some of the plurality of conductive layers 205 described later. The electrode CC may include, for example, tungsten (W) or a stacked structure of titanium nitride (TiN) and tungsten (W).

[0061] Surrounding area R PC Plate line layer L PT For example, as shown in FIG. CP The conductive layer 205 may include, for example, the same material as the conductive layer 204.

[0062] Surrounding area R PC Peripheral circuit layer L PC For example, as shown in FIG. 2, the semiconductor device includes a plurality of peripheral transistors TrP1 provided on a substrate Sub, and a plurality of electrodes 210 connected to the plurality of peripheral transistors TrP1.

[0063] The peripheral transistor TrP1 has a part of the substrate Sub as a channel region. The peripheral transistors TrP1 constitute, for example, at least a part of the peripheral circuit PC (FIG. 1).

[0064] For example, the upper end of the electrode 210 is connected to the conductive layer 205. For example, the lower end of the electrode 210 is connected to the source regions, drain regions, gate electrodes, etc. of the multiple peripheral transistors TrP1. The electrode 210 may include, for example, copper (Cu), tungsten (W), or a stacked structure of titanium nitride (TiN) and tungsten (W).

[0065] An insulating layer 200L is provided between the peripheral transistors TrP1, the electrodes 210, and the conductive layers 205. The insulating layer 200L will be described later.

[0066] [Memory area R MC , the surrounding area R PC insulating layer] The insulating layer 100H, the insulating layer 111H, the insulating layer 112H (FIG. 4), the insulating layer 113H, the insulating layer 173H, the insulating layer 183H, the insulating layer 190H, and the insulating layer 304H may be hereinafter referred to as insulating layers belonging to the insulating layer group H, or simply as the insulating layer group H. MC Peripheral circuit layer L PC As shown in FIGS. 2 and 3, insulating layers belonging to insulating layer group H are formed on the other layers.

[0067] The insulating layer group H includes a material through which diffusion of hydrogen (H) does not easily occur. The insulating layer group H includes, for example, a material with a relatively high density. The insulating layer group H includes, for example, a film with high crystallinity, and diffusion of hydrogen (H) through grain boundaries or highly amorphous portions does not easily occur. Hydrogen (H) does not easily permeate the insulating layer group H.

[0068] The insulating layer group H includes, for example, silicon (Si) and oxygen (O). The insulating layer group H includes, for example, relatively high-density silicon oxide (SiO 2 ).

[0069] The insulating layer group H is formed by, for example, CVD (Chemical Vapor Deposition). When the insulating layer group H is formed by CVD, it is formed at a relatively high temperature, for example, with a stage temperature of about 400° C. Hereinafter, forming the insulating layer group H by CVD may be referred to as high-temperature CVD.

[0070] The insulating layer group H prevents hydrogen (H) and the like that are released from the insulating layer 196 from diffusing through the insulating layer group H and reaching the semiconductor layer 130, for example, during a post-annealing process described later.

[0071] The insulating layer 200L, the insulating layer 100L, the insulating layer 110L, the insulating layer 180L, the insulating layer 190L, and the insulating layer 304L may hereinafter be referred to as insulating layers belonging to the insulating layer group L, or simply as the insulating layer group L. PC , and memory region R MC Peripheral circuit layer L PC As shown in FIG. 2, an insulating layer belonging to an insulating layer group L is formed on the insulating layer.

[0072] The insulating layer group L includes a material through which hydrogen (H) diffusion easily occurs. The insulating layer group L includes, for example, a material with a relatively low density. The insulating layer group L includes, for example, a film with low crystallinity, and hydrogen (H) is likely to diffuse through grain boundaries and highly amorphous portions. Hydrogen (H) easily permeates the insulating layer group L.

[0073] The insulating layer group L includes, for example, silicon (Si) and oxygen (O). The insulating layer group L includes, for example, relatively low-density silicon oxide (SiO2).

[0074] The insulating layer group L is formed by, for example, CVD. When the insulating layer group L is formed by CVD, it is formed at a relatively low temperature, for example, with a stage temperature of about 300° C. Hereinafter, forming the insulating layer group L by CVD may be referred to as low-temperature CVD.

[0075] The insulating layer group L allows hydrogen (H) and the like released from the insulating layer 196 to diffuse through the insulating layer group L and easily reach the peripheral transistor TrP1 during, for example, a post-annealing process described later.

[0076] The density of insulating layer group H is greater than the density of insulating layer group L. For example, the average density of the multiple materials constituting insulating layer group H is greater than the average density of the multiple materials constituting insulating layer group L. The densities of the materials contained in insulating layer group H and insulating layer group L can be measured by, for example, electron energy loss spectroscopy, X-ray reflectivity, etc.

[0077] Insulating layer group H and insulating layer group L may contain, for example, hydrogen (H). When insulating layer group H and insulating layer group L contain hydrogen (H), the hydrogen concentration of insulating layer group H is lower than the hydrogen concentration of insulating layer group L. For example, the average hydrogen concentration of the multiple materials that make up insulating layer group H is lower than the average hydrogen concentration of the multiple materials that make up insulating layer group L. The hydrogen (H) concentrations of insulating layer group H and insulating layer group L can be measured, for example, by SIMS (Secondary Ion Mass Spectrometry) or the like.

[0078] [Manufacturing method of the first embodiment] Next, a method for manufacturing a semiconductor device according to this embodiment will be described with reference to Figures 7 to 27. Figures 7 to 27 are schematic cross-sectional views for explaining the method for manufacturing a semiconductor device according to the first embodiment. Note that the drawings relating to the manufacturing method are schematic, and for the sake of explanation, some components may be omitted.

[0079] In this manufacturing method, for example, as shown in FIG. 7, a peripheral circuit layer L including a peripheral transistor TrP1 is formed on a substrate Sub. PC (Fig. 2), and then the plate line layer L PT In this process, for example, a peripheral transistor TrP1 including an element isolation and well (not shown), a gate insulating film, a gate electrode, a source / drain (not shown), etc. is formed on the surface of the substrate Sub, and electrodes, wiring, etc. are formed.

[0080] Next, as shown in FIG. 8, for example, the plate line layer L PT An insulating layer 100L' is formed on the upper surface of the insulating layer 100L. The insulating layer 100L' includes, for example, the same material as the insulating layer 100L. This step is performed, for example, by the above-mentioned low-temperature CVD or the like.

[0081] 9, an opening is formed at a position corresponding to the electrode CC, a film of the same material as the electrode CC is formed in the opening, and unnecessary material formed on the upper surface of the insulating layer 100L' is removed to form the electrode CC. This process is performed by RIE (Reactive Ion Etching), CVD, CMP (Chemical Mechanical Planarization), or the like.

[0082] Next, as shown in FIG. CP The surrounding area R PC A mask material 400 is formed at a position corresponding to the insulating layer 100L by photolithography or the like, and the insulating layer 100L is formed by removing the portion of the insulating layer 100L' that is not covered by the mask material 400. This step is performed by, for example, RIE, wet etching, or the like.

[0083] Next, as shown in FIG. 11, the capacitor layer L CP Memory region R MC The same material as the insulating layer 100H is formed at the position corresponding to the insulating layer 100L, and unnecessary material formed on the upper surface of the insulating layer 100L is removed to form the insulating layer 100H. This process is performed by, for example, the above-mentioned high-temperature CVD and CMP.

[0084] Next, for example, as shown in FIG. 12, memory area R MC A capacitor structure CP10 is formed on the insulating layer 202. The capacitor structure CP10 is formed by forming an opening at a position corresponding to the capacitor structure CP10 and sequentially depositing a conductive layer 203, an insulating layer 202, a conductive layer 121, a conductive layer 201, and a conductive layer 120 in the opening. This process is performed by, for example, RIE, CVD, CMP, or the like.

[0085] Next, as shown in FIG. 13, the capacitor layer L CPAn insulating layer 111H' containing the same material as the insulating layer 111H is formed on the upper surface of the insulating layer 111H. This process is performed, for example, by the high-temperature CVD described above. An electrode 151 is also formed in the insulating layer 111H', and a conductive layer 150' containing the same material as the conductive layer 150 is formed on the upper surfaces of the insulating layer 111H' and the electrode 151. This process is performed, for example, by RIE, CVD, CMP, etc.

[0086] Next, as shown in Fig. 14, a conductive layer 150 is formed. This process is performed by, for example, photolithography and RIE. Furthermore, an insulating layer 112H' containing the same material as the insulating layer 112H is formed between the multiple conductive layers 150, and an insulating layer 113H' containing the same material as the insulating layer 113H is formed on the upper surfaces of the conductive layer 150 and the insulating layer 112H'. This process is performed by, for example, the above-mentioned high-temperature CVD and CMP.

[0087] 15, openings are formed at positions corresponding to the insulating layer 140 and the semiconductor layer 130, and materials similar to the insulating layer 140 and the semiconductor layer 130 are formed on the inner surfaces and in the openings, respectively, and unnecessary material formed on the upper surface of the insulating layer 113H' is removed to form the insulating layer 140 and the semiconductor layer 130. This process is performed by RIE, CVD, CMP, or the like.

[0088] Next, as shown in FIG. 16, the transistor layer L Tr Memory region R MC A mask material 401 is formed by photolithography or the like at positions corresponding to the insulating layers 111H', 112H', and 113H', and portions of the insulating layer 111H', the insulating layer 112H', and the insulating layer 113H' that are not covered by the mask material 401 are removed to form the insulating layers 111H, 112H, and 113H. This step is performed by, for example, RIE, wet etching, or the like.

[0089] Next, as shown in FIG. 17, the transistor layer L Tr The surrounding area R PCAn insulating layer containing the same material as the insulating layer 110L is formed at a position corresponding to the insulating layer 113H, and unnecessary material formed on the upper surface of the insulating layer 113H is removed to form the insulating layer 110L. This process is performed by, for example, the above-mentioned low-temperature CVD, CMP, or the like.

[0090] Next, as shown in FIG. 18, for example, the transistor layer L Tr On the upper surface of the conductive layer 170, a conductive layer 171', and a conductive layer 172' containing the same material as the conductive layer 170, the conductive layer 171, and the conductive layer 172 are formed in this order. This process is performed by, for example, CVD or the like.

[0091] Next, as shown in FIG. 19, a mask material is formed by photolithography or the like, and portions not covered by the mask material are removed to form conductive layers 170, 171, and 172. This process is performed by, for example, RIE or the like. Furthermore, an insulating layer containing the same material as insulating layer 173H is formed between the plurality of conductive layers 170, 171, and 172, and unnecessary material formed on the upper surface of conductive layer 172 is removed to form insulating layer 173H'. This process is performed by, for example, the aforementioned high-temperature CVD, CMP, or the like.

[0092] 20, conductive layers 181′, 182′, and 184′ containing the same materials as the conductive layers 181, 182, and 184 are formed in this order on the upper surfaces of the insulating layer 173H′ and the conductive layer 172. This process is performed by, for example, CVD or the like.

[0093] 21, a mask material is formed by photolithography or the like, and portions not covered by the mask material are removed to form conductive layers 181, 182, and 184. This process is performed by, for example, RIE or the like. Furthermore, an insulating layer containing the same material as insulating layer 183H is formed between the plurality of conductive layers 181, 182, and 184, and unnecessary material formed on the upper surface of conductive layer 184 is removed to form insulating layer 183H'. This process is performed by, for example, the aforementioned high-temperature CVD, CMP, or the like.

[0094] Next, as shown in FIG. ML Memory region R MC A mask material 402 is formed by photolithography or the like at positions corresponding to the insulating layers 173H and 183H, and the insulating layers 173H′ and 183H′ are formed by removing portions that are not covered by the mask material 402. This step is performed by, for example, RIE or wet etching.

[0095] Next, as shown in FIG. 23, for example, the wiring layer L ML The surrounding area R PC An insulating layer containing the same material as the insulating layer 180L is formed in a portion of the position corresponding to the insulating layer 183H, and unnecessary material formed on the upper surfaces of the insulating layer 183H and the conductive layer 184 is removed to form the insulating layer 180L. This process is performed by, for example, the above-mentioned low-temperature CVD, CMP, or the like. Furthermore, a portion of the insulating layer 180L is removed to form the wiring 185. This process is performed by, for example, RIE, CVD, CMP, or the like.

[0096] 24, for example, an insulating layer 190H is formed on the upper surfaces of the insulating layer 183H and the conductive layer 184, and an insulating layer 190L is formed on the upper surfaces of the insulating layer 180L and the wiring 185. In this process, first, an insulating layer containing the same material as the insulating layer 190H is formed on the upper surface of the structure shown in FIG. PC Next, an insulating layer containing the same material as the insulating layer 190L is formed in the memory region R. MC The insulating layer 190L is formed by, for example, the above-described low-temperature CVD and RIE or wet etching. The insulating layer 190H is formed by, for example, the above-described high-temperature CVD and RIE or wet etching.

[0097] 25, a metal oxide layer 191' containing the same material as the metal oxide layer 191 is formed on the upper surfaces of the insulating layers 190L and 190H. The metal oxide layer 191' may have a thickness of, for example, 1 nm to 5 nm. This process is performed by, for example, ALD (Atomic Layer Deposition), CVD, or the like.

[0098] Next, with the metal oxide layer 191' exposed, a first oxidation treatment, which will be described later, is performed to introduce oxygen into the semiconductor layer 130, for example, via the insulating layer 190H, the insulating layer 183H, the insulating layer 173H, the insulating layer 113H, the insulating layer 112H, and the insulating layer 111H. Note that, if there is no need to increase the efficiency of introducing oxygen into the semiconductor layer 130, the formation of the metal oxide layer 191' and the first oxidation treatment may be omitted.

[0099] 26, a similar material is deposited on the upper surface of the metal oxide layer 191′ to form a metal oxide layer 191, and then an insulating layer 196 is formed. This process is performed by, for example, ALD, PVD (Physical Vapor Deposition), CVD, or the like.

[0100] 27, an opening is formed at a position corresponding to the electrode 192, a film of the same material as the electrode 192 is formed in the opening, and unnecessary material formed on the upper surface of the insulating layer 196 is removed to form the electrode 192. This process is performed by RIE, CVD, CMP, or the like.

[0101] Next, a wiring layer L UL (Fig. 2) is formed. UL In the formation of (Figure 2), the memory region R MC The insulating layer 304H is formed in the peripheral region R. PC An insulating layer 304L is formed on each of the insulating layers 304A and 304B in the same manner as in the process described with reference to FIG.

[0102] Wiring layer L ULDuring or after the formation of the layer, a post-annealing treatment, which will be described later, is performed. In this manner, the semiconductor device according to the first embodiment is manufactured.

[0103] [First oxidation treatment] The first oxidation treatment (FIG. 25) is, for example, radical oxidation.

[0104] Radical oxidation is carried out in an atmosphere containing oxygen radicals or hydroxyl radicals. Radical oxidation is carried out, for example, in an atmosphere of oxygen gas (O2), hydrogen gas (H2), and argon gas (Ar) in plasma form. Radical oxidation is carried out, for example, in an atmosphere of water vapor in plasma form.

[0105] The method for generating oxygen radicals or hydroxyl radicals used in radical oxidation is not particularly limited, and oxygen radicals or hydroxyl radicals may be generated using, for example, an inductively coupled plasma method, a microwave plasma method, an electron cyclotron resonance method, a helicon wave method, or a hot filament method.

[0106] The radical oxidation atmosphere contains, for example, hydrogen (H) and oxygen (O). The atomic ratio (H / (H+O)) of the hydrogen (H) contained in the radical oxidation atmosphere to the sum of hydrogen (H) and oxygen (O) is, for example, 40% or less. The atomic ratio (H / (H+O)) of the hydrogen (H) contained in the radical oxidation atmosphere to the sum of hydrogen (H) and oxygen (O) is, for example, 2% or more and 5% or less.

[0107] The atomic ratio (H / (H+O)) of hydrogen (H) contained in the radical oxidation atmosphere to the sum of hydrogen (H) and oxygen (O) is adjusted, for example, by the flow rates of hydrogen gas (H2) and oxygen gas (O2) introduced into the radical oxidation atmosphere. The molar ratio (H2 / (H2+O2)) of hydrogen gas (H2) introduced into the radical oxidation atmosphere to the sum of hydrogen gas (H2) and oxygen gas (O2) is, for example, 40% or less. The molar ratio (H2 / (H2+O2)) of hydrogen gas (H2) introduced into the radical oxidation atmosphere to the sum of hydrogen gas (H2) and oxygen gas (O2) is, for example, 2% or more and 5% or less.

[0108] The temperature of the radical oxidation is, for example, 300° C. or more and 900° C. or less. The pressure of the radical oxidation is, for example, 50 Pa or more and 3000 Pa or less.

[0109] When the first oxidation treatment (FIG. 25) is performed by radical oxidation, the metal oxide layer 191' preferably contains at least one element selected from the group consisting of nitrogen (N), carbon (C), hydrogen (H), and chlorine (Cl). When the metal oxide layer 191' contains any of the above elements, crystallization of the metal oxide layer 191' is suppressed and the rate of oxygen introduction is increased.

[0110] When the first oxidation treatment (FIG. 25) is performed by radical oxidation, the radical oxidation atmosphere contains hydrogen (H) and oxygen (O), and the atomic ratio (H / (H+O)) of the contained hydrogen (H) to the sum of hydrogen (H) and oxygen (O) is preferably 40% or less, and more preferably 2% or more and 5% or less. By satisfying the above range of atomic ratio (H / (H+O)), the speed of oxygen introduction increases.

[0111] In the above description, radical oxidation is performed as the first oxidation treatment, but the method of the first oxidation treatment can be adjusted as appropriate.

[0112] For example, as the first oxidation treatment (FIG. 25), a film containing oxygen (O) may be formed on the upper surface of the metal oxide layer 191' by plasma CVD or the like. Plasma CVD is a film formation method performed in an atmosphere where oxygen gas, hydrogen gas, argon gas, or the like is converted into plasma. The film containing oxygen (O) is, for example, silicon oxide (SiO2).

[0113] Furthermore, for example, oxygen plasma ashing may be performed as the first oxidation treatment (FIG. 25). Oxygen plasma ashing is a treatment in which the metal oxide layer 191' is irradiated with oxygen plasma in a high-energy state, for example.

[0114] [Post-annealing treatment] The post-annealing process is an annealing process performed near the final process on a peripheral transistor TrP1 or the like having a semiconductor layer containing silicon (Si) as a channel. The post-annealing process is performed, for example, at about 400°C. The post-annealing process supplies hydrogen to the gate insulating film and channel interface of the peripheral transistor TrP1, reducing the interface state density of the gate insulating film. This improves carrier mobility within the peripheral transistor TrP1 and results in good switching characteristics.

[0115] In the post-annealing process of this embodiment, the insulating layer 196 (FIG. 2) containing a large amount of hydrogen (H) may become a supply source of hydrogen to the peripheral transistor TrP1.

[0116] [Comparative Example] Next, a semiconductor device according to a comparative example will be described with reference to Fig. 28. Fig. 28 is a schematic cross-sectional view for describing a method for manufacturing a semiconductor device according to the comparative example.

[0117] The semiconductor device according to the comparative example has a memory region R MC Even in the surrounding area R PC In the manufacturing method of the semiconductor device according to the comparative example, the insulating layer group L is formed in the memory region R MC , the surrounding area R PCIn this case, the insulating layer group H and the insulating layer group L are not separately formed. Furthermore, the metal oxide layer 191 is not formed in the semiconductor device according to the comparative example.

[0118] In the manufacturing process of the semiconductor device according to the comparative example, the metal oxide layer 191 functioning as a hydrogen barrier layer is not formed, and further, the memory region R MC Insulating layer group L, into which hydrogen (H) easily diffuses, is formed in insulating layer 196. As a result, a large amount of hydrogen (H) in insulating layer 196 may reach semiconductor layer 130 during post-annealing (FIG. 28). As a result, for example, donor-type OH defects may occur in semiconductor layer 130 including an oxide semiconductor, causing the threshold voltage of select transistor ST to shift negatively, and good switching characteristics may not be obtained.

[0119] [effect] Next, the effects of the semiconductor device according to this embodiment will be described with reference to Fig. 29. Fig. 29 is a schematic cross-sectional view for explaining the effects of the semiconductor device according to this embodiment.

[0120] The memory region R of the semiconductor device according to this embodiment MC In the semiconductor device manufacturing method according to this embodiment, an insulating layer group H in which diffusion of hydrogen (H) does not easily occur is formed in the memory region R. MC , the surrounding area R PC In this step, insulating layer group H and insulating layer group L are separately formed. Furthermore, a metal oxide layer 191 is formed in the semiconductor device according to this embodiment.

[0121] In manufacturing the semiconductor device according to this embodiment, the metal oxide layer 191 that functions as a hydrogen barrier layer is formed, and further, the memory region R MCInsulating layer group H, into which hydrogen (H) is less likely to diffuse, is formed in the peripheral region R. This prevents hydrogen (H) in the insulating layer 196 from reaching the semiconductor layer 130 during post-annealing (FIG. 29). This prevents the threshold voltage of the select transistor ST including an oxide semiconductor from shifting negatively, resulting in good switching characteristics. PC In this case, since the insulating layer group L in which hydrogen (H) easily diffuses is formed, hydrogen (H) can be effectively supplied to the peripheral transistor TrP1 (FIG. 29).

[0122] In manufacturing the semiconductor device according to this embodiment, an oxidation treatment is performed in a state where the metal oxide layer 191′ is exposed, thereby enabling efficient introduction of oxygen into the semiconductor layer 130. This allows good switching characteristics to be obtained in the select transistor ST including the oxide semiconductor.

[0123] Therefore, in this configuration, the peripheral region R PC a peripheral transistor TrP1 formed in the memory region R MC In this way, it is possible to provide a semiconductor device having excellent transistor characteristics in both the first and second select transistors ST formed on the first and second gate electrodes.

[0124] [Modification 1 of the First Embodiment] Next, a first modification of the semiconductor device according to the first embodiment will be described with reference to Fig. 30. Fig. 30 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to this modification.

[0125] The semiconductor device according to this modification is basically configured in the same manner as the semiconductor device according to the first embodiment (FIG. 2). However, the semiconductor device according to this modification (FIG. 30) does not include the metal oxide layer 191, but instead includes a metal oxide layer 191a.

[0126] The metal oxide layer 191a extends in the X and Y directions as shown in FIG. 30, for example, and MC and the peripheral region R PCIt cannot be set up.

[0127] The metal oxide layer 191a basically contains the same material and has the same function as the metal oxide layer 191. At least a portion of the metal oxide layer 191a functions as a layer that increases the efficiency of oxygen introduction into the semiconductor layer 130, for example, in the first oxidation treatment (FIG. 25) described above. In addition, the metal oxide layer 191a, together with the insulating layer group H, functions as a hydrogen barrier layer that prevents hydrogen from diffusing from the insulating layer 196 to the semiconductor layer 130, for example, in the post-annealing treatment described above.

[0128] [Modification 2 of the First Embodiment] Next, a second modification of the semiconductor device according to the first embodiment will be described with reference to Fig. 31. Fig. 31 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to this modification.

[0129] The semiconductor device according to this modification is basically configured in the same manner as the semiconductor device according to the first embodiment (FIG. 2). However, the semiconductor device according to this modification (FIG. 31) has a peripheral region R PC In the plate line layer L PT On top of this, a metal oxide layer 191b and an insulating layer 196b are provided.

[0130] The metal oxide layer 191b basically contains the same material as the metal oxide layer 191.

[0131] The insulating layer 196b basically contains the same material as the insulating layer 196. The insulating layer 196b may contain a large amount of hydrogen (H) in its material and may serve as a source of hydrogen (H). For example, in the post-annealing process described above, hydrogen (H) is released not only from the insulating layer 196 but also from the insulating layer 196b. In such a case, hydrogen (H) can be supplied from the insulating layer 196b to the peripheral transistor TrP1 via the insulating layer 200L, which easily diffuses hydrogen (H). The insulating layer 196b may have the same film thickness as the insulating layer 196.

[0132] [Second embodiment] Next, a semiconductor device according to a second embodiment will be described with reference to Fig. 32. Fig. 32 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to this embodiment. In the following description, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.

[0133] The semiconductor device according to this embodiment is basically configured in the same manner as the semiconductor device according to the first embodiment (FIGS. 2 to 6). However, the semiconductor device according to this embodiment (FIG. 32) does not include the metal oxide layer 191 and the insulating layer 196, and the capacitor layer L CP An insulating layer 196_2 is provided on the top layer, and a metal oxide layer 191_2 is provided on the upper surface of the insulating layer 196_2.

[0134] Memory area R MC The capacitor layer L CP In this example, an insulating layer 100L_2 is provided instead of the insulating layer 100H.

[0135] Surrounding area R PC The capacitor layer L CP In the embodiment, an insulating layer 100L_2 is provided instead of the insulating layer 100L. The insulating layer 100L_2 is provided in the peripheral region R PC and memory region R MC It is integrally formed in

[0136] Memory area R MC Transistor layer L Tr In this example, the insulating layer 111H, the insulating layer 112H, and the insulating layer 113H are not provided, and instead, the insulating layer 111H_2, the insulating layer 112H_2, and the insulating layer 113H_2 are provided.

[0137] Surrounding area R PC Transistor layer L Tr The insulating layer 110L is not provided in the peripheral region R, but instead, insulating layers 111H_2, 112H_2, and 113H_2 are provided. PC and memory region R MC It is integrally formed in

[0138] Memory area R MC Wiring layer L ML The insulating layer 173H, the insulating layer 183H, and the insulating layer 190H are not provided, and instead, the insulating layer 173H_2, the insulating layer 183H_2, and the insulating layer 190H_2 are provided.

[0139] Surrounding area R PC Wiring layer L ML The insulating layer 180L and the insulating layer 190L are not provided in the peripheral region R, and instead, the insulating layer 173H_2, the insulating layer 183H_2, and the insulating layer 190H_2 are provided. PC and memory region R MC It is integrally formed in

[0140] Memory area R MC Wiring layer L UL The insulating layer 304H is not provided, and instead an insulating layer 304H_2 is provided.

[0141] Surrounding area R PC Wiring layer L UL The insulating layer 304L is not provided in the peripheral region R, but instead an insulating layer 304H_2 is provided. PC and memory region R MC It is integrally formed in

[0142] The insulating layer 111H_2, the insulating layer 112H_2, the insulating layer 113H_2, the insulating layer 173H_2, the insulating layer 183H_2, the insulating layer 190H_2, and the insulating layer 304H_2 are insulating layers belonging to the insulating layer group H described above.

[0143] The insulating layer 100L_2 is an insulating layer that belongs to the insulating layer group L described above.

[0144] As described above, the semiconductor device according to this embodiment has a transistor layer L Tr , wiring layer L ML , and the wiring layer L ULIn the region including the insulating layer group H, an insulating layer belonging to the insulating layer group H is formed, and the capacitor layer L CP , plate line layer L PT , and the peripheral circuit layer L PC In the region including the insulating layer group L, an insulating layer belonging to the insulating layer group L is formed.

[0145] The metal oxide layer 191_2 basically contains the same material and has the same function as the metal oxide layer 191. For example, in the above-described post-annealing treatment, the metal oxide layer 191_2, together with the insulating layer group H, functions as a hydrogen barrier layer that prevents diffusion of hydrogen (H) from the insulating layer 196_2 to the semiconductor layer 130. Note that the metal oxide layer 191_2 is not used in the above-described first oxidation treatment (FIG. 25).

[0146] The insulating layer 196_2 basically contains the same material as the insulating layer 196. The insulating layer 196_2 may contain a large amount of hydrogen (H) in its material and may serve as a source of hydrogen (H). For example, in the post-annealing process described above, hydrogen (H) is released from the insulating layer 196_2. In such a case, hydrogen (H) can be supplied to the peripheral transistor TrP1 through the insulating layers 100L_2 and 200L, which are easily permeable to hydrogen (H). The insulating layer 196_2 may have the same film thickness as the insulating layer 196.

[0147] [Manufacturing method of the second embodiment] Next, a method for manufacturing the semiconductor device according to this embodiment will be described with reference to Figures 33 to 38. The semiconductor device according to this embodiment is basically manufactured in the same manner as the semiconductor device according to the first embodiment. However, in the method for manufacturing the semiconductor device according to this modification, the steps shown in Figures 33 to 38 are performed after the steps described with reference to Figures 7 and 8.

[0148] 8, an insulating layer 100L_2 is formed instead of the insulating layer 100L'. This step is performed by, for example, the above-mentioned low-temperature CVD or the like.

[0149] Next, for example, as shown in Fig. 33, an insulating layer 196_2 is formed on the upper surface of the insulating layer 100L_2. This step is performed by, for example, CVD or the like.

[0150] Next, as shown in FIG. 34, openings are formed at positions corresponding to the electrode CC and the capacitor structure CP10. A film of the same material as the electrode CC is formed in the corresponding opening, and unnecessary material formed on the upper surface of the insulating layer 196_2 is removed to form the electrode CC. A conductive layer 203, an insulating layer 202, a conductive layer 121, a conductive layer 201, and a conductive layer 120 are sequentially formed in the corresponding openings to form the capacitor structure CP10. This process is performed by, for example, RIE, CVD, CMP, or the like.

[0151] Next, as shown in FIG. 35, the capacitor layer L CP A metal oxide layer 191_2 is formed on the upper surface of the insulating layer 111H_2. This process is performed by, for example, ALD, CVD, or the like. An insulating layer 111H_2 is also formed on the upper surface of the metal oxide layer 191_2. This process is performed by, for example, the above-mentioned high-temperature CVD. An electrode 151 is also formed penetrating the insulating layer 111H_2 and the metal oxide layer 191_2, and a conductive layer 150' containing the same material as the conductive layer 150 is formed on the upper surfaces of the insulating layer 111H_2 and the electrode 151. This process is performed by, for example, RIE, CVD, CMP, or the like.

[0152] Next, as shown in Fig. 36, a conductive layer 150 is formed by photolithography or the like. This process is performed by, for example, RIE or the like. Furthermore, an insulating layer 112H_2 is formed in the same layer as the plurality of conductive layers 150, and an insulating layer 113H_2 is formed on the upper surfaces of the conductive layer 150 and the insulating layer 112H_2. This process is performed by, for example, the above-mentioned high-temperature CVD and CMP or the like.

[0153] 37, openings are formed at positions corresponding to the insulating layer 140 and the semiconductor layer 130, and the same materials as the insulating layer 140 and the semiconductor layer 130 are deposited in the openings, respectively, and unnecessary material formed on the upper surface of the insulating layer 113H_2 is removed to form the insulating layer 140 and the semiconductor layer 130. This process is performed by RIE, CVD, CMP, or the like.

[0154] Next, as shown in Fig. 38, for example, conductive layers 170, 171, 172, and an insulating layer 173H_2 are formed in the same manner as in the steps described with reference to Figs. 18 to 21. Note that the layer shown as insulating layer 173H' in Figs. 19 to 21 corresponds to the insulating layer 173H_2. Also, conductive layers 181, 182, 184, and an insulating layer 183H_2 are formed. Note that the layer shown as insulating layer 183H' in Fig. 21 corresponds to the insulating layer 183H_2.

[0155] 23, the wiring 185 may be formed by removing a portion of the insulating layer 173H_2 and the insulating layer 183H_2. This step is performed by, for example, RIE, CVD, CMP, or the like. The wiring 185 may be formed simultaneously in the steps of forming the conductive layer 170, the conductive layer 171, and the conductive layer 172, and the conductive layer 181, the conductive layer 182, and the conductive layer 184.

[0156] Next, an insulating layer 190H_2 is formed on the upper surface of the structure shown in Fig. 38. This process is performed, for example, by the high-temperature CVD described above. An opening is formed at a position corresponding to the electrode 192, and a film of the same material as the electrode 192 is formed in the opening. Unnecessary material formed on the upper surface of the insulating layer 190H_2 is removed to form the electrode 192. This process is performed by RIE, CVD, CMP, or the like.

[0157] Next, the wiring layer L UL (Fig. 32) is formed. UL In the formation of (Figure 32), the memory region R MC and the surrounding area R PCThe insulating layer 304H_2 is formed on the insulating layer 304H_2 by, for example, the above-mentioned high-temperature CVD.

[0158] Wiring layer L UL During or after the formation of the semiconductor device, the above-described post-annealing treatment is performed. In this manner, the semiconductor device according to the second embodiment is manufactured.

[0159] [effect] Next, the effects of the semiconductor device according to this embodiment will be described with reference to Fig. 39. Fig. 39 is a schematic cross-sectional view for explaining the effects of the semiconductor device according to this embodiment.

[0160] The semiconductor device according to this embodiment includes a transistor layer L above the insulating layer 196_2 and the metal oxide layer 191_2. Tr , wiring layer L ML , and the wiring layer L UL In the region including the insulating layer group H, the diffusion of hydrogen (H) is difficult to occur.

[0161] In manufacturing the semiconductor device according to this embodiment, a metal oxide layer 191_2 functioning as a hydrogen barrier layer is formed on the upper surface of an insulating layer 196_2 containing a large amount of hydrogen, and an insulating layer group H through which hydrogen (H) is difficult to diffuse and a semiconductor layer 130 are formed above the metal oxide layer 191_2. This prevents hydrogen (H) in the insulating layer 196_2 from reaching the semiconductor layer 130 during post-annealing (FIG. 39). This prevents the threshold voltage of the select transistor ST including an oxide semiconductor from shifting negatively, thereby achieving good switching characteristics. Furthermore, an insulating layer group L through which hydrogen (H) is easily diffused is formed below the insulating layer 196_2, so that hydrogen (H) can be effectively supplied to the peripheral transistor TrP1 (FIG. 39).

[0162] Therefore, in this configuration, the peripheral region R PC a peripheral transistor TrP1 formed in the memory region R MCIn this way, it is possible to provide a semiconductor device having excellent transistor characteristics in both the first and second select transistors ST formed on the first and second gate electrodes.

[0163] [Third embodiment] Next, a semiconductor device according to a third embodiment will be described with reference to Fig. 40. Fig. 40 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to this embodiment. In the following description, the same components as those in the first and second embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0164] The semiconductor device according to this embodiment is basically configured in the same manner as the semiconductor device according to the second embodiment (FIG. 32), and is manufactured by the same manufacturing method as the first and second embodiments. However, the semiconductor device according to this embodiment (FIG. 40) has memory regions R aligned in the Y direction. MC and the surrounding area R PC (Fig. 32), but instead has memory areas R arranged in the Z direction on the substrate Sub. MC3 and the surrounding area R PC3 (Fig. 40) Memory area R MC3 and the surrounding area R PC3 Between them, there is a connection layer L CN will be established.

[0165] Memory area R MC3 In the semiconductor device according to the second embodiment (FIG. 32), a transistor layer L Tr and the wiring layer L ML and the wiring layer L UL and the capacitor layer L CP and the plate line layer L PT However, the capacitor layer L CP The insulating layer 100L_2 is not provided on the transistor layer L, but an insulating layer 100H_3 is provided instead. Tr and capacitor layer L CP The metal oxide layer 191_2 and the insulating layer 196_2 are not provided on the upper surface of the insulating layer 190H_2, and instead, a metal oxide layer 191_3b and an insulating layer 196_3b are provided on the upper surface of the insulating layer 190H_2.

[0166] The insulating layer 100H_3 is an insulating layer belonging to the insulating layer group H described above.

[0167] Surrounding area R PC3 In the semiconductor device according to the second embodiment (FIG. 32), a peripheral circuit layer L PC However, the peripheral region R PC3 Peripheral circuit layer L PC In this example, a plurality of peripheral transistors TrP1 are also provided at positions overlapping with the transistor structure Tr10 when viewed from the Z direction.

[0168] Connection layer L CN For example, the connection layer L is provided with a wiring 211 connected to the electrode 210, and a metal oxide layer 191_3a and an insulating layer 196_3a provided on the upper surface of the wiring 211 and the insulating layer 200L. CN 2, an electrode 221 connected to the wiring 211, a wiring 220 connected to the electrode 221, an electrode 222 connected to the wiring 220 and the conductive layer 205, and an insulating layer 230H_3 are provided therebetween.

[0169] The wiring 211, the electrode 221, the wiring 220, and the electrode 222 may include, for example, copper (Cu), tungsten (W), or a laminated structure of titanium nitride (TiN) and tungsten (W). PC3 and memory region R MC3 It functions as a connection layer that electrically connects

[0170] The insulating layer 230H_3 is an insulating layer belonging to the insulating layer group H described above.

[0171] The metal oxide layer 191_3a and the metal oxide layer 191_3b basically contain the same material as the metal oxide layer 191 and have the same function. However, the metal oxide layer 191_3a is not used in the first oxidation treatment (FIG. 25) described above. A part of the metal oxide layer 191_3b may be used in the first oxidation treatment (FIG. 25) described above. In addition, the metal oxide layer 191_3b, together with the insulating layer group H, functions as a hydrogen barrier layer that prevents diffusion of hydrogen (H) from the insulating layer 196_3b to the semiconductor layer 130, for example, in the post-annealing treatment described above. The metal oxide layer 191_3a and the metal oxide layer 191_3b may have the same film thickness as the metal oxide layer 191.

[0172] The insulating layer 196_3a and the insulating layer 196_3b basically contain the same material as the insulating layer 196. The insulating layer 196_3a and the insulating layer 196_3b may contain a large amount of hydrogen (H) in their materials and may serve as a source of hydrogen (H). For example, in the above-mentioned post-annealing treatment, hydrogen (H) is released from the insulating layer 196_3a and the insulating layer 196_3b. In such a case, hydrogen (H) can be supplied from the insulating layer 196_3a to the peripheral transistor TrP1 via the insulating layer 200L, which easily diffuses hydrogen (H). Note that the insulating layer 196_3a and the insulating layer 196_3b may have the same film thickness as the insulating layer 196.

[0173] [Manufacturing method of the third embodiment] The semiconductor device according to this embodiment is basically manufactured in the same manner as the semiconductor device according to the first and second embodiments. However, in the manufacturing method of the semiconductor device according to this modification, in the process described with reference to FIG. 7, a plurality of peripheral transistors TrP1 are also formed at positions overlapping with the transistor structure Tr10 when viewed from the Z direction. In addition, the peripheral circuit layer L PC After the formation of the connecting layer L CN Next, a connection layer L CN On top of the plate line layer L PT Next, similarly to the steps described with reference to FIGS. 33 to 38, the memory region R MC3 Form.

[0174] 33, an insulating layer 100H_3 is formed instead of the insulating layer 100L_2, and an insulating layer 196_2 is not formed. In the process corresponding to FIG. 35, a metal oxide layer 191_2 is not formed. After the process corresponding to FIG. 38, a metal oxide layer 191_3b and an insulating layer 196_3b are formed before the electrode 192 is formed. After a portion of the metal oxide layer 191_3b is formed, the first oxidation treatment described above may be performed, similar to the process described with reference to FIG. 25.

[0175] [effect] Next, the effects of the semiconductor device according to this embodiment will be described with reference to Fig. 41. Fig. 41 is a schematic cross-sectional view for explaining the effects of the semiconductor device according to this embodiment.

[0176] The semiconductor device according to this embodiment has a connection layer L above the metal oxide layer 191_3a and the insulating layer 196_3a. CN and memory region R MC3 In this case, an insulating layer group H in which diffusion of hydrogen (H) is difficult to occur is formed.

[0177] In manufacturing the semiconductor device according to this embodiment, a metal oxide layer 191_3b functioning as a hydrogen barrier layer is formed on the lower surface of an insulating layer 196_3b containing a large amount of hydrogen, and an insulating layer group H through which hydrogen (H) is difficult to diffuse and a semiconductor layer 130 are formed below the metal oxide layer 191_3b. This prevents hydrogen (H) in the insulating layer 196_3b from reaching the semiconductor layer 130 during post-annealing (FIG. 41). This prevents the threshold voltage of the select transistor ST including an oxide semiconductor from shifting negatively, thereby achieving good switching characteristics. Furthermore, an insulating layer group L through which hydrogen (H) is easily diffused is formed below the insulating layer 196_3a, so that hydrogen (H) can be effectively supplied to the peripheral transistor TrP1 (FIG. 41).

[0178] Therefore, in this configuration, the peripheral region R PC3 a peripheral transistor TrP1 formed in the memory region R MC3In this way, it is possible to provide a semiconductor device having excellent transistor characteristics in both the first and second select transistors ST formed on the first and second gate electrodes.

[0179] [Fourth embodiment] Next, a semiconductor device according to a fourth embodiment will be described with reference to Fig. 42. Fig. 42 is a schematic cross-sectional view showing the configuration of a portion of the semiconductor device according to this embodiment. In the following description, the same components as those in the first to third embodiments are denoted by the same reference numerals, and description thereof will be omitted.

[0180] The semiconductor device according to this embodiment is a chip C M And Chip C P Chip C M is a substrate Sub_4 and a memory region R formed on the substrate Sub_4. MC4 Chip C P is the peripheral region R formed on the substrate Sub. PC3 and the surrounding area R PC3 The connection layer L formed on the top surface of CN4 The substrate Sub_4 or the substrate Sub may be removed.

[0181] The substrate Sub_4 may contain, for example, P-type silicon (Si) containing P-type impurities such as boron (B), or may be a substrate containing a material other than a glass substrate.

[0182] Chip C M A plurality of bonding electrodes PI1 are provided on the upper surface of the chip C. P A plurality of bonding electrodes PI2 are provided on the underside of the chip C. M Regarding the chip C, the surface on which the plurality of bonding electrodes PI1 are provided is called the front surface, and the surface on the substrate Sub_4 side is called the back surface. P In the example shown in the figure, the surface on which the plurality of bonding electrodes PI2 are provided is called the front surface, and the surface on the substrate Sub side is called the back surface. P The back side of the chip C P and the chip C M The surface of the chip C MThe back surface of the substrate is provided above the substrate.

[0183] Chip C M and Chip C P is Chip C M Surface and chip C P The plurality of bonded electrodes PI1 are provided corresponding to the plurality of bonded electrodes PI2, respectively, and are arranged at positions where they can be bonded to the plurality of bonded electrodes PI2. The bonded electrodes PI1 and the bonded electrodes PI2 are arranged on the chip C. M and Chip C P and functions as a bonding electrode for electrically connecting them.

[0184] The plurality of laminated electrodes PI1 and the plurality of laminated electrodes PI2 may include, for example, a laminated film of a barrier conductive film such as titanium nitride (TiN) and a metal film such as copper (Cu).

[0185] Memory area R MC4 In the third embodiment, the memory area R MC3 Similar to (Figure 40), transistor layer L Tr and the wiring layer L ML and the capacitor layer L CP and the plate line layer L PT However, the memory area R MC4 The wiring layer L UL (Fig. 40) instead of the wiring layer L UL4 (Figure 42) is provided.

[0186] Wiring layer L UL4 is basically the wiring layer L UL However, the wiring layer L UL4 is provided with a plurality of laminated electrodes PI1 on the surface farther from the substrate Sub_4.

[0187] Connection layer L CN4 is basically a connection layer L CN (Fig. 40). However, the connection layer L CN4 On the surface of the substrate Sub, a plurality of laminated electrodes PI2 are provided.

[0188] Furthermore, memory area R MC4 The word line WL(150) is connected to the peripheral region R via, for example, the electrode 151_4 and the like and the laminated electrodes PI1, PI2 and the like. PC3 The electrode 151_4 includes, for example, the same material as the electrode 151.

[0189] [Manufacturing method of the fourth embodiment] The semiconductor device according to this embodiment is, for example, a chip C M Wafer on which the chip C is formed P After manufacturing the wafers on which the bonding electrodes PI1 and PI2 are formed, the bonding electrodes PI1 and PI2 of the two wafers are bonded together by, for example, direct bonding.

[0190] Furthermore, Chip C M The step of forming the memory region R of the third embodiment (FIG. 40) on the substrate Sub_4, for example, MC3 Similarly to the process of forming the memory region R MC4 After forming the chip C M A laminated electrode PI1 is formed on the top layer.

[0191] Furthermore, Chip C P The process of forming the peripheral region R of the third embodiment (FIG. 40) on the substrate Sub may be carried out, for example. PC3 Similarly to the process of forming the peripheral region R PC3 After forming the chip C P A laminated electrode PI2 is formed on the top layer.

[0192] In the manufacturing method of the semiconductor device according to this embodiment, the post-annealing treatment is performed on the chip C. M and Chip C P Before laminating, chip C P Alternatively, chip C M and Chip C P After laminating the substrates, a post-annealing treatment may be performed.

[0193] [effect] Next, the effects of the semiconductor device according to this embodiment will be described with reference to Fig. 43. Fig. 43 is a schematic cross-sectional view for explaining the effects of the semiconductor device according to this embodiment.

[0194] The semiconductor device according to this embodiment includes an insulating layer 196_3a containing a large amount of hydrogen (H) and a connecting layer L below the metal oxide layer 191_3a. CN4 and memory region R MC4 In the insulating layer group H, the diffusion of hydrogen (H) is difficult to occur. In addition, a metal oxide layer 191_3b functioning as a hydrogen barrier layer is formed on the lower surface of an insulating layer 196_3b containing a large amount of hydrogen, and the insulating layer group H and the semiconductor layer 130, in which the diffusion of hydrogen (H) is difficult to occur, are formed below that.

[0195] This allows chip C M and Chip C P Even when post-annealing is performed after lamination, hydrogen (H) in the insulating layers 196_3a and 196_3b can be prevented from reaching the semiconductor layer 130 (FIG. 43). This prevents the threshold voltage of the select transistor ST including an oxide semiconductor from shifting negatively, thereby achieving good switching characteristics. Furthermore, above the insulating layer 196_3a, an insulating layer group L through which hydrogen (H) easily diffuses is formed, so that hydrogen (H) can be effectively supplied to the peripheral transistor TrP1.

[0196] Therefore, in this configuration, the peripheral region R PC3 a peripheral transistor TrP1 formed in the memory region R MC4 In this way, it is possible to provide a semiconductor device having excellent transistor characteristics in both the first and second select transistors ST formed on the first and second gate electrodes.

[0197] [Modification of the fourth embodiment] Chip C of the fourth embodiment M and Chip C P The upper position is chip C. M ,The bottom side is chip C P But that's okay. Chip C Mis located on the upper side, the upper substrate Sub_4 may be removed after fabrication.

[0198] [Other embodiments] The semiconductor devices according to the first to fourth embodiments have been described above. However, the semiconductor devices according to these embodiments are merely examples, and the specific configurations, operations, etc. can be adjusted as appropriate.

[0199] For example, in the above description, the metal oxide layer 191 and the insulating layer 196 (FIGS. 2 and 31), the metal oxide layer 191a and the insulating layer 196 (FIG. 30), the metal oxide layer 191b and the insulating layer 196b (FIG. 31), the metal oxide layer 191_2 and the insulating layer 196_2 (FIG. 32), the metal oxide layer 191_3a and the insulating layer 196_3a (FIGS. 40 and 42), and the metal oxide layer 191_3b and the insulating layer 196_3b (FIGS. 40 and 42) are provided in contact with each other, respectively. However, they may not be provided in contact with each other, and another insulating layer may be provided between them. The other insulating layer may be, for example, an insulating layer containing silicon oxide (SiO), silicon nitride (SiN), or another material. Note that when the other insulating layer contains silicon nitride (SiN), the silicon nitride (SiN) is provided by, for example, PVD, and its hydrogen (H) content is 1×10 or less. 19 / cm 3 The following is the result.

[0200] For example, in the above description, an example has been described in which the capacitor Cap (FIG. 1) is connected to the select transistor ST (FIG. 1). In such an example, the shape, structure, etc. of the capacitor Cap can be adjusted as appropriate.

[0201] In the above description, an example has been described in which a capacitor Cap (FIG. 1) is used as the memory unit connected to the select transistor ST (FIG. 1). However, the memory unit does not have to be a capacitor Cap. For example, the memory unit may include a ferroelectric material, a ferromagnetic material, a chalcogen material such as GeSbTe, or other material, and may record data using the properties of these materials. For example, in any of the structures described above, the insulating layer between the electrodes that forms the capacitor Cap may include one of these materials.

[0202] In the above description, the semiconductor layer 130 that functions as the channel region of the select transistor ST (FIG. 1) has been described as having a generally cylindrical shape extending in the Z direction, for example. However, the semiconductor layer 130 may have a generally cylindrical shape extending in the Z direction, for example. Furthermore, an insulating layer that has a generally cylindrical shape extending in the Z direction and contains silicon oxide (SiO2) or the like may be provided inside the semiconductor layer 130.

[0203] The above description has been given of an example in which the memory cell MC (FIG. 1) includes a select transistor ST including an oxide semiconductor and a capacitor Cap. However, the memory cell MC may also include, for example, a semiconductor layer including silicon (Si), a gate insulating film including a charge storage film, and a gate electrode. The threshold voltage of such a memory cell MC varies depending on the amount of charge in the charge storage film. Furthermore, if a large amount of hydrogen is supplied to the gate insulating film in such a memory cell MC, the threshold voltage of the memory cell MC may easily shift, potentially reducing the reliability of the memory cell MC. In such an example, an insulating layer group H may be provided in the region where the memory cell MC is provided, and an insulating layer group L may be provided in the region where the peripheral circuit PC is provided. In this configuration, hydrogen (H) is less likely to permeate through the insulating layer group H during post-annealing, thereby preventing the hydrogen (H) from reaching the gate insulating film of the memory cell MC. Furthermore, hydrogen (H) easily diffuses through the insulating layer group L, allowing the hydrogen (H) to be efficiently supplied to the peripheral transistor TrP1 in the peripheral circuit PC.

[0204] [others] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0205] R MC …memory area, R PC ...peripheral region, ST...selection transistor, Sub...substrate, TrP1...peripheral transistor, 130...semiconductor layer, 140...insulating layer, 150...conductive layer, 191...metal oxide layer, 196...insulating layer.

Claims

1. A substrate; a first region provided on one side of the substrate in a first direction intersecting with a surface of the substrate; a second region provided on the one side of the substrate in the first direction, and arranged alongside the first region in the first direction or a second direction intersecting the first direction; a first insulating layer and a metal oxide layer provided on the substrate at a position farther from the first region on the one side in the first direction; Equipped with The first region is a first transistor having a first semiconductor layer including silicon (Si); a second insulating layer provided between the first insulating layer and the metal oxide layer and the first transistor; Including, The second region is a second transistor having a second semiconductor layer including an oxide semiconductor; a third insulating layer provided between the first insulating layer and the metal oxide layer and the second transistor; Including, the metal oxide layer contains at least one element selected from the group consisting of aluminum (Al), hafnium (Hf), zirconium (Zr), lanthanum (La), and yttrium (Y), and oxygen (O); the second insulating layer and the third insulating layer each contain silicon (Si) and oxygen (O); The density of the third insulating layer is higher than the density of the second insulating layer. Semiconductor device.

2. The oxide semiconductor contains at least one element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), magnesium (Mg), aluminum (Al), calcium (Ca), titanium (Ti), manganese (Mn), cadmium (Cd), and tin (Sn), zinc (Zn), and oxygen (O). The semiconductor device according to claim 1.

3. The first insulating layer includes nitrogen (N) and silicon (Si). The semiconductor device according to claim 1.

4. a first wiring extending in the second direction and facing a part of the second semiconductor layer; a gate insulating film provided between the second semiconductor layer and the first wiring; Furthermore, The second semiconductor layer extends in the first direction. The semiconductor device according to claim 1.

5. The third insulating layer surrounds a portion of the second semiconductor layer in the second direction and in a third direction intersecting the first direction and the second direction.

5. The semiconductor device according to claim 4.

6. a second wiring extending in a third direction intersecting the first direction and the second direction; The second wiring is electrically connected to the second semiconductor layer.

5. The semiconductor device according to claim 4.

7. the first region and the second region are aligned in the second direction, The metal oxide layer is provided on the one side of the substrate in the first direction, at a position farther than the second region. The semiconductor device according to claim 1.

8. the second insulating layer is in contact with the first insulating layer; The metal oxide layer is provided between the third insulating layer and the first insulating layer.

8. The semiconductor device according to claim 7.

9. When viewed from the first direction, the metal oxide layer is provided between the second insulating layer and the first insulating layer; The metal oxide layer is provided between the third insulating layer and the first insulating layer.

8. The semiconductor device according to claim 7.

10. the first region and the second region are aligned in the first direction, The first insulating layer and the metal oxide layer are provided between the first region and the second region. The semiconductor device according to claim 1.

11. The first insulating layer is in contact with the metal oxide layer. The semiconductor device according to claim 1.

12. The hydrogen (H) concentration of the third insulating layer is lower than the hydrogen (H) concentration of the second insulating layer. The semiconductor device according to claim 1.

13. a capacitor electrically connected to the second semiconductor layer; The semiconductor device according to claim 1.

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