Sub-substrate structure and electronic control device

Abstract

To provide a sub-substrate structure capable of avoiding loss of communication function between electronic components on a sub-substrate and the outside of the sub-substrate, and also avoiding an increase in the size of the sub-substrate.SOLUTION: A sub-substrate structure is equipped with a sub-substrate 4 where an SoC 5 is surface-mounted on an upper surface, a plurality of solder balls 12 arranged on the periphery of the underside of the sub-substrate 4 for mounting the sub-substrate 4 to a motherboard 2, and a side fill 8 arranged on the periphery of the SoC 5 to reinforce the state in which the SoC 5 is mounted on the sub-substrate 4. The solder balls 12 are electrically connected to the terminals of the SoC 5 by a wiring 10 inside the sub-substrate 4. The SoC 5 has multiple communication functions and multiple terminal groups corresponding to the multiple communication functions, and performs data communication with external devices using the communication functions via communication ICs 17 and 18 mounted on the motherboard 2 and the motherboard 2.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a sub-substrate on whose upper surface sub-side electronic components are surface-mounted, a sub-substrate structure that is arranged on the outer periphery of the lower surface of the sub-substrate and has a plurality of solder balls for mounting and electrically connecting the sub-substrate to a motherboard, and an electronic control device that has the sub-substrate structure. [Background technology]

[0002] In multi-chip modules (MCMs), such as ball grid array (BGA) modules, which are composed of a sub-substrate surface-mounted and electrically connected to a motherboard, thermosetting underfill or sidefill materials may be used as reinforcement materials when mounting electronic components such as ICs on the sub-substrate. When solder balls are arranged on the backside of the sub-substrate to connect the sub-substrate to the motherboard, etc., located directly below these reinforcement materials, the stress generated by the shrinkage of the reinforcement material during hardening can cause the solder balls to become open. If the electronic components on the MCM have the function of communicating with the outside world via the solder balls, this can disrupt communication, leading to a loss of MCM functionality.

[0003] To avoid the above situation, attempts to avoid placing terminals connected via solder balls directly below the reinforcing material would result in an increase in the size of the board. For example, in an IC such as an SoC (System on Chip), terminals for high-speed communication are placed on the periphery. To shorten the wiring length from these terminals to the motherboard, there is a demand to place the SoC on the edge of the sub-board, and also to place the solder balls connected to the sub-board terminals on the edge of the sub-board. In this case, the solder balls tend to overlap in the area directly below the reinforcing material injected around or below the IC. To avoid this, it would be necessary to place the solder balls further outward from the center of the sub-board, directly below the reinforcing material, which would increase the size of the sub-board. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-38943 Summary of the Invention [Problem to be solved by the invention]

[0005] Furthermore, because ICs such as SoCs consume a relatively large amount of current, it is desirable to mount the power supply bypass capacitor, which is used to absorb load fluctuations, on the back surface of the sub-board, directly below the center of the IC. However, since solder balls cannot be placed on the back surface of the sub-board, the outer edge of the IC, where the reinforcing material is applied, tends to overlap with the solder balls, causing the effects of the stress mentioned above to become a problem.

[0006] The present invention has been made in consideration of the above circumstances, and its purpose is to provide a sub-substrate structure that can avoid the loss of communication function between the electronic components on the sub-substrate and the outside of the sub-substrate, while also avoiding an increase in the size of the sub-substrate, and an electronic control device that is equipped with this sub-substrate structure. [Means for solving the problem]

[0007] The sub-substrate structure according to claim 1 includes a sub-substrate (4) having sub-side electronic components (5, 6) surface-mounted on its upper surface, a plurality of solder balls (12) arranged on the outer periphery of the underside of the sub-substrate for mounting the sub-substrate to a motherboard (2), and reinforcing members (8, 24) arranged on at least a portion of the outer periphery of the sub-substrate to reinforce the state in which the sub-side electronic component (5) is mounted on the sub-substrate. The solder balls are electrically connected to terminals of the sub-side electronic component by wiring (10) within the sub-substrate. The sub-side electronic component has multiple communication functions and multiple terminal groups corresponding to the multiple communication functions, and performs data communication with motherboard electronic components (17, 18, 21-23) mounted on the motherboard or with an external device via the motherboard.

[0008] If the terminal groups connected to the solder balls on the outer periphery of the sub-board are designated as connection terminal groups (15, 16, 25, 26), at least one of the terminal groups (15, 25) is arranged in an overlapping area on the sub-board where the reinforcing material is arranged, while the other connection terminal groups (16, 26) are arranged in non-overlapping areas not related to the areas where the reinforcing material is arranged.

[0009] To improve signal quality in high-speed communications, it is necessary to shorten the wiring length from the terminals of electronic components with high-speed communication capabilities to the solder balls electrically connected to those terminals. Therefore, it is desirable to arrange the electronic components on the outer edge of the front surface of the sub-board and the solder balls on the outer edge of the back surface of the sub-board. In this case, the reinforcing material arranged on the outer edge of the electronic components tends to overlap with the solder balls. Therefore, avoiding the placement of the solder balls in the overlapping area leads to an increase in the size of the sub-board. In contrast, by configuring as in claim 1, it is possible to avoid the loss of communication function between the electronic components on the sub-board and the outside of the sub-board without increasing the size of the sub-board. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a plan view of an electronic control device according to a first embodiment. [Figure 2] Schematic longitudinal cross-sectional view of an electronic control device [Figure 3] Model diagram (part 1) explaining the tensile stress acting when side fill is thermally cured [Figure 4] Model diagram (part 2) explaining the tensile stress acting when side fill is thermally cured [Figure 5] Model diagram (part 3) explaining the tensile stress acting when side fill is thermally cured [Figure 6] FIG. 10 is a plan view of an electronic control device according to a second embodiment. [Figure 7] FIG. 10 is a plan view of an electronic control device according to a third embodiment. [Figure 8] FIG. 10 is a plan view of an electronic control device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] (First embodiment) As shown in Figures 1 to 3, the electronic control device of this embodiment is an ECU (Electronic Control Unit) 1 mounted on a vehicle, and is configured by mounting an MCM 3, which is a sub-substrate structure, on a motherboard 2. The MCM 3 has an SoC 5 and a power supply IC 6, which are sub-side electronic components, surface-mounted on the upper surface of a sub-substrate 4, which is a multilayer substrate, by solder balls 7. In other words, the packages of the SoC 5 and the power supply IC 6 are BGA type. Side fills 8, which are thermosetting resin reinforcing materials, are arranged at the four corners of the SoC 5 to reinforce the mounted state of the SoC 5.

[0012] Each terminal on the underside of SoC 5 is electrically connected to a pad 9 on the upper surface of sub-substrate 4 via solder balls 7. Pad 9 is connected to pad 11, which is a connection terminal on the underside of sub-substrate 4, via internal wiring 10 consisting of through-holes and pads in sub-substrate 4. Pad 11 is electrically connected to a pad (not shown) on the upper surface of motherboard 2 via solder balls 12.

[0013] 1 and 2, a chip capacitor 13, which is a bypass capacitor for the power supply, is surface-mounted on the underside of the sub-board 4 in a region located in the center of the SoC 5. For this reason, an area 14 indicated by a dashed line in Fig. 2 is an area where pads 11 and solder balls 12 connected to those pads 11 cannot be placed.

[0014] 1, the two connection terminal groups 15 and 16 are indicated by being surrounded by dashed lines. The pads 11 included in the connection terminal group 15 are arranged in an overlapping region related to the position where the side fill 8 is arranged on the upper surface of the sub-substrate 4. On the other hand, the pads 11 included in the connection terminal group 16 are arranged in a non-overlapping region not related to the position where the side fill 8 is arranged.

[0015] The connection terminal groups 15 and 16 are respectively connected to communication ICs 17 and 18, which are mother-side electronic components mounted on the motherboard 2. The SoC 5 performs duplication and redundancy of communications with external devices using the two communication ICs 17 and 18. These communication protocols may be, for example, Ethernet (registered trademark) or CAN (Controller Aria Network; registered trademark), or each protocol may be provided in one system.

[0016] Next, the operation of this embodiment will be described. FIG. 3 shows a simplified model of the ECU 1. As shown in FIG. 4, when the side fill 8 is applied between the SoC 5 and the sub-board 4 and heated to harden, the side fill 8 shrinks. This causes upward tensile stress on the sub-board 4, as shown in an enlarged partial view in FIG. 5, which may cause solder cracks or resin cracks in the areas where the stress is concentrated. This may lead to signal interruptions in the SoC 5.

[0017] 1, two connection terminal groups 15 and 16 are provided, and communication ICs 17 and 18 are connected to them, respectively, to achieve duplication and redundancy. Connection terminal group 15, which is located in the overlapping area, is more likely to be affected by the above-mentioned stress than terminal group 16. However, even if communication is interrupted due to a break in the connection terminal group 15, communication can be continued by using communication IC 18 connected to terminal group 16, which is less likely to be affected by stress.

[0018] As described above, this embodiment includes a sub-substrate 4 on whose upper surface the SoC 5 is surface-mounted, a plurality of solder balls 12 arranged on the periphery of the underside of the sub-substrate 4 for mounting the sub-substrate 4 to the motherboard 2, and side fill 8 arranged on the periphery of the SoC 5 to reinforce the state in which the SoC 5 is mounted on the sub-substrate 4. The solder balls 12 are electrically connected to the terminals of the SoC 5 by wiring 10 inside the sub-substrate 4. The SoC 5 has multiple communication functions and multiple terminal groups corresponding to the multiple communication functions, and performs data communication with an external device using the communication functions via communication ICs 17 and 18 mounted on the motherboard 2 and the motherboard 2.

[0019] Corresponding to each of the terminal groups of SoC 5, there are connection terminal groups 15 and 16 connected to solder balls 12 on the periphery of sub-substrate 2, with connection terminal group 15 arranged in the overlapping region and connection terminal group 16 arranged in the non-overlapping region. In this way, by arranging connection terminal groups 15 and 16 on the periphery of sub-substrate 2, high-speed communication can be achieved. Furthermore, an increase in the size of sub-substrate 2 can be suppressed, and even if stress affects solder balls 12 of connection terminal group 15 in the overlapping region, causing a connection failure and communication to be interrupted, communication via connection terminal group 16 in the non-overlapping region can continue, so loss of communication function between SoC 5 on sub-substrate 2 and the outside of sub-substrate 2 can be avoided.

[0020] (Second embodiment) Hereinafter, the same parts as those in the first embodiment are denoted by the same reference numerals, and a description thereof will be omitted, and only the differences will be described. As shown in Fig. 6, in the second embodiment, two memories 21 and 22 are connected to connection terminal groups 15 and 16 instead of communication ICs 17 and 18. The memories 21 and 22 are, for example, NAND-type or NOR-type flash memories, and both may be NAND-type or NOR-type, or one may be NAND-type and the other NOR-type. These memories 21 and 22 store the same data that is read by the SoC 5.

[0021] SoC5 initially uses memory 21. If a disconnection occurs on the connection terminal group 15 side and data cannot be read from memory 21, SoC5 switches to using memory 22. This allows SoC5 to continue reading data.

[0022] (Third embodiment) As shown in Fig. 7, in the third embodiment, an IC 23 is connected to connection terminal groups 15 and 16. The IC 23 is, for example, an Octal SPI flash memory or a GMII (Gigabit Media-Independent Interface). The Octal SPI flash memory can switch its communication mode between an Octal mode, which uses eight data lines and transmits eight bits at a time per clock, and a Quad mode, which uses four data lines and transmits four bits at a time per clock. The same is true for the GMII.

[0023] SoC5 initially accesses IC23 in octal mode. If a break occurs on the connection terminal group 15 side, SoC5 switches IC23 to quad mode and switches to using only the 4-bit data lines of connection terminal group 16. This allows SoC5 to continue reading data.

[0024] (Fourth embodiment) 8, in the fourth embodiment, the state of application of the side fill differs from that of the above-described embodiments, and the side fill 24 is applied over the entire periphery of the SoC 5. In this case, the connection terminal group 25 arranged in the overlapping region and the connection terminal group 26 arranged in the non-overlapping region are as shown in the figure.

[0025] (Other embodiments) The reinforcing material is not limited to a thermosetting type, and other types, such as an ultraviolet curing type, may also be used. The electronic control device is not necessarily limited to the MCM 3, but may include at least one sub-side electronic component, or may include three or more sub-side electronic components. The number of connection terminal groups may be three or more. The communication system may also be multiplexed into three or more systems.

[0026] Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and equivalent modifications. In addition, various combinations and forms, including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure. [Explanation of symbols]

[0027] In the drawing, 1 indicates an ECU, 2 indicates a motherboard, 3 indicates an MCM, 4 indicates a sub-board, 5 indicates an SoC, 6 indicates a power supply IC, 7 indicates solder balls, 8 indicates a side fill, 10 indicates internal wiring, 11 indicates pads, 12 indicates solder balls, 15 and 16 indicate connection terminal groups, and 17 and 18 indicate communication ICs.

Claims

1. a sub-substrate (4) on whose upper surface sub-side electronic components (5, 6) are surface-mounted; a plurality of solder balls (12) arranged on the outer periphery of the lower surface of the sub-substrate for mounting the sub-substrate to the motherboard (2); and a reinforcing member (8, 24) disposed at least partially on the outer periphery of the sub-side electronic component (5) to reinforce the state in which the sub-side electronic component (5) is mounted on the sub-substrate. the solder balls are electrically connected to terminals of the sub-side electronic component by wiring within the sub-substrate; The sub-side electronic component has a plurality of communication functions and a plurality of terminal groups corresponding to the plurality of communication functions, and executes data communication with the mother-side electronic components (17, 18, 21 to 23) mounted on the motherboard by the communication functions, or with an external device via the motherboard, If the terminal groups connected to the solder balls on the outer periphery of the sub-board are defined as a plurality of connection terminal groups (15, 16, 25, 26), A sub-substrate structure in which at least one (15, 25) of the plurality of connection terminal groups is arranged in an overlapping area related to the area where the reinforcing material is arranged on the sub-substrate, and the other connection terminal groups (16, 26) are arranged in non-overlapping areas not related to the area where the reinforcing material is arranged.

2. An electronic control device comprising the sub-substrate structure according to claim 1 and the motherboard.

Images