Method for manufacturing nitride semiconductor device

Abstract

To provide a method for manufacturing a nitride semiconductor device that reduces electron traps to improve MOSFET mobility and realizes GaN-MOSFETs that combine high mobility and high threshold voltage.SOLUTION: A method for manufacturing a nitride semiconductor device includes the steps of forming a silicon-based film 2 on a surface 1a of a gallium nitride substrate 1, nitriding the silicon-based film 2 to form a nitride film 3, and forming a gate insulating film 4 on the nitride film 3.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a nitride semiconductor device. [Background technology]

[0002] Patent Document 1 discloses that when a silicon oxide film is formed on the upper surface of a gallium nitride semiconductor substrate, a nitrogen source gas containing nitrogen is introduced into a film formation chamber to form a high-nitrogen concentration region. Non-Patent Document 1 discloses that by depositing a thin Si film before SiN film formation, N2 plasma exposure to the GaN surface during SiN film formation can be avoided, resulting in good interface characteristics. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2020-35931 [Non-patent literature]

[0004] [Non-Patent Document 1] T. Watanabe et. al., IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 63, NO. 4, APRIL 2016 Summary of the Invention [Problem to be solved by the invention]

[0005] The Si film formed on the GaN surface becomes a source of electron traps. In the method disclosed in Non-Patent Document 1, the Si film is nitrided by N2 plasma during SiN film formation, but as SiN film formation progresses, the Si film is no longer exposed to N2 plasma, which may result in insufficient nitridation of the Si film. The present disclosure aims to provide a method for manufacturing a nitride semiconductor device that can reduce electron traps. [Means for solving the problem]

[0006] In order to solve the above problems, a method for manufacturing a nitride semiconductor device according to one aspect of the present disclosure includes the steps of forming a silicon-based film on a gallium nitride substrate, performing a nitriding process on the silicon-based film to form a nitride film, and forming a gate insulating film on the nitride film. [Effects of the Invention]

[0007] According to one aspect of the present disclosure, it is possible to provide a method for manufacturing a nitride semiconductor device capable of reducing electron traps. [Brief explanation of the drawings]

[0008] [Figure 1] 1A to 1C are cross-sectional views illustrating a first example of a manufacturing method for a GaN semiconductor device according to an embodiment of the present disclosure in the order of steps. [Figure 2] 2A to 2C are cross-sectional views illustrating a second manufacturing method of a GaN semiconductor device according to an embodiment of the present disclosure in the order of steps. [Figure 3] FIG. 3 is a cross-sectional view showing a third example of a manufacturing method of a GaN semiconductor device according to an embodiment of the present disclosure. [Figure 4] FIG. 4 is a diagram illustrating a process flow according to an embodiment of the present disclosure. [Figure 5] FIG. 5 is a diagram showing a process flow according to a comparative example of the present disclosure. [Figure 6] FIG. 6 is a graph showing the electron trap density ratios of the examples and the comparative examples. [Figure 7] FIG. 7 is a graph showing the relationship between the deposition time of the Si film and the electron trap density ratio. [Figure 8] FIG. 8 is a plan view showing a configuration example of a GaN semiconductor device according to an embodiment of the present disclosure. [Figure 9] FIG. 9 is a cross-sectional view showing a configuration example of a GaN semiconductor device according to an embodiment of the present disclosure. DETAILED DESCRIPTION OF THE INVENTION

[0009] An embodiment of the present disclosure will be described below. In the following description of the drawings, identical or similar parts are designated by identical or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the thickness ratio of each device or component, etc., may differ from the actual ones. Therefore, specific thicknesses and dimensions should be determined with reference to the following description. Furthermore, it goes without saying that the drawings may include parts with different dimensional relationships and ratios.

[0010] In the following description, directions may be described using the terms X-axis direction, Y-axis direction, and Z-axis direction. For example, the X-axis direction and Y-axis direction are directions parallel to the surface 1a of the GaN substrate 1 described below. The X-axis direction and Y-axis direction are also referred to as horizontal directions. The Z-axis direction is a direction perpendicular to the surface 1a of the GaN substrate 1. The X-axis direction, Y-axis direction, and Z-axis direction are orthogonal to each other.

[0011] In the following description, the positive direction of the Z axis may be referred to as "up" and the negative direction of the Z axis may be referred to as "down." "Up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of regions, layers, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0012] In the following description, + or - attached to p or n indicating the conductivity type means that the semiconductor region has a relatively high or low impurity concentration, respectively, compared to a semiconductor region without + or -. However, even if the same p and p (or n and n) are attached to semiconductor regions, this does not mean that the impurity concentrations of the respective semiconductor regions are strictly the same.

[0013] <Embodiment> (GaN semiconductor device manufacturing method) A method for manufacturing a GaN semiconductor device (an example of a "nitride semiconductor device" of the present disclosure) according to an embodiment of the present disclosure will be described. The GaN semiconductor device is manufactured using various types of equipment, such as a film formation apparatus (e.g., a plasma CVD (Chemical Vapor Deposition) apparatus, a thermal CVD apparatus, or a thermal oxidation apparatus), a heat treatment apparatus, an ion implantation apparatus, an exposure apparatus, an etching apparatus, or a CMP (Chemical Mechanical Polishing) apparatus. Hereinafter, these apparatuses will be collectively referred to as manufacturing apparatuses.

[0014] (1) Manufacturing method example 1 1 is a cross-sectional view showing a process sequence of a first example of a manufacturing method for a GaN semiconductor device according to an embodiment of the present disclosure. In step ST1 of FIG. 1, the manufacturing equipment forms a silicon (Si) film 2 (an example of a "silicon-based film" of the present disclosure) on a surface 1a of a gallium nitride (GaN) substrate 1. The Si film 2 may be a film mainly composed of Si (e.g., having the highest composition ratio of Si in atomic % (at %)), and may contain carbon (C), nitrogen (N), oxygen (O), etc.

[0015] The deposition conditions for the Si film 2 are, for example, as follows: The deposition method for the Si film 2 is a plasma CVD method. The source gas contains monosilane (SiH4) as a reactive gas and argon (Ar) as a dilution gas. The supply rate of SiH4 is 0.001 sccm or more and 0.5 sccm or less. The supply rate of Ar is 100 sccm. The deposition pressure in the plasma atmosphere is 12 mTorr or more and 1200 mTorr or less. In this way, the manufacturing apparatus deposits the Si film 2 by a plasma CVD method in a source gas atmosphere containing Si but not containing oxygen (O) or nitrogen (N).

[0016] The thickness of the Si film 2 after deposition is preferably 1 nm or less. If the thickness of the Si film 2 is 1 nm or less, it is easy to nitride the entire Si film 2 in the nitriding process described below. As a result, as will be described later with reference to FIG. 7, the electron trap density can be reduced.

[0017] 1, the manufacturing equipment performs a nitriding process on the Si film 2 to form a SiN film 3 (an example of the "nitride film" of the present disclosure) from the Si film 2. In this nitriding process, it is preferable to nitride the entire Si film 2 to form the SiN film 3 from the Si film 2 so that no Si film 2 remains on the GaN substrate 1.

[0018] The conditions for the nitriding treatment in step ST2 are, for example, as follows: The nitriding treatment is performed by N2 plasma nitriding. The N2 supply rate is 10 sccm or more and 200 sccm or less. The pressure in the plasma atmosphere is 12 mm or more and 1200 mmTorr or less. In this way, the manufacturing equipment performs the nitriding treatment by plasma irradiation in an atmosphere containing nitrogen gas (N2). The thickness of the SiN film 3 formed by the nitriding treatment of the Si film 2 is 1 nm or less.

[0019] It is preferable that the deposition of the Si film 2 shown in step ST1 of FIG. 1 and the nitriding treatment of the Si film 2 shown in step ST2 of FIG. 1 are performed consecutively in the same chamber without being exposed to the atmosphere.

[0020] 1, the manufacturing equipment deposits a gate insulating film 4 on the SiN film 3 formed by nitriding. The gate insulating film 4 is a film composed of at least one of an oxide of silicon (Si) and an oxide of aluminum (Al), such as a silicon oxide film (SiO2 film) or an aluminum oxide film (Al2O3 film). The gate insulating film 4 is deposited by, for example, a plasma CVD method. The deposited thickness of the gate insulating film 4 is, for example, 100 nm.

[0021] (2) Manufacturing method example 2 FIG. 2 is a cross-sectional view showing a second manufacturing method of a GaN semiconductor device according to an embodiment of the present disclosure in the order of steps. In step ST11 of FIG. 2, the steps up to the step of forming a SiN film 3 by nitriding are the same as those in the first manufacturing method. In the second manufacturing method, after forming the SiN film 3 by nitriding, the manufacturing equipment forms a first gate insulating film 4A (an example of a "part of the gate insulating film" of the present disclosure) on the SiN film 3. The first gate insulating film 4A is, for example, a silicon oxynitride film (SiON film) and is formed by a plasma CVD method. The first gate insulating film 4A has a thickness of, for example, 3 nm.

[0022] Next, in step ST12 of FIG. 2, the manufacturing equipment deposits a second gate insulating film 4B (an example of "another part of the gate insulating film" in the present disclosure) on the first gate insulating film 4A. The second gate insulating film 4B is a film composed of at least one of an oxide of silicon and an oxide of aluminum, such as an SiO2 film or an Al2O3 film. The second gate insulating film 4B is deposited by, for example, a plasma CVD method. The deposited thickness of the second gate insulating film 4B is, for example, 100 nm.

[0023] (3) Manufacturing method example 3 3 is a cross-sectional view showing a third manufacturing method of a GaN semiconductor device according to an embodiment of the present disclosure. In step ST21 of FIG. 3, the steps up to the step of forming the gate insulating film 4 are the same as those in the first manufacturing method. In the third manufacturing method, after the gate insulating film 4 is formed, the manufacturing equipment applies a heat treatment at 400°C or higher to the entire substrate including the gate insulating film 4, the SiN film 3, and the GaN substrate 1. For example, the manufacturing equipment applies a heat treatment to the entire substrate up to a maximum temperature of 800°C. This allows the gate insulating film 4 to be densified.

[0024] The heat treatment of Manufacturing Method Example 3 may be applied not only to Manufacturing Method Example 1 but also to Manufacturing Method Example 2. That is, in Manufacturing Method Example 2, the manufacturing apparatus may perform a heat treatment at 400° C. or higher on the entire substrate including the first gate insulating film 4A, the second gate insulating film 4B, the SiN film 3, and the GaN substrate 1. This makes it possible to densify the first gate insulating film 4A and the second gate insulating film 4B.

[0025] (Experiment and results) (1) Nitriding Regarding the nitridation process for a silicon-based film (e.g., Si film 2), an experiment was conducted to investigate the relationship between the N2 plasma treatment time and the composition ratio of elements in the nitrided film. The results of the investigation (experimental results) are shown in Table 1. [Table 1]

[0026] As shown in Table 1, in this experiment, a sample was prepared in which a Si film was deposited on a substrate to a thickness of 2 nm to 3 nm. This sample was then subjected to nitriding treatment using N2 plasma, and the composition ratio (at%) of the elements that make up the film after nitriding treatment was measured. The nitriding treatment conditions were N2 plasma treatment times of 0 seconds (sec), 10 seconds, 30 seconds, and 40 seconds. A treatment time of 0 seconds means that no nitriding treatment using N2 plasma was performed.

[0027] Each sample contained carbon (C) and oxygen (O), but this was not due to the gas supplied to the chamber, but was thought to be due to unintentional contamination within the device (for example, intake from the atmosphere when opening and closing the chamber, or degassing from the chamber). Only N2 gas was supplied to the chamber when performing N2 plasma.

[0028] As shown in Table 1, as the N2 plasma treatment time increases, the composition ratio of Si in the film decreases and the composition ratio of N increases, and it was confirmed that the film approaches a SiN film from a Si film. As shown in Table 1, it was confirmed that the nitriding treatment (N2 plasma) increases the composition ratio of nitrogen in the silicon-based film.

[0029] (2) Electron trap density (2-1) Examples and Comparative Examples In order to investigate the relationship between the Si film deposition and nitridation process (e.g., steps ST1 and ST2 in FIG. 1 ) and the electron trap density at the MOS (Metal Oxide Semiconductor) interface, an n-type MOS capacitor fabricated using a process flow according to an example (hereinafter referred to as the MOS capacitor according to the example) and an n-type MOS capacitor fabricated using a process flow according to a comparative example (hereinafter referred to as the MOS capacitor according to the comparative example) were prepared. Note that the MOS interface refers to the interface between the GaN substrate and the insulating film and its vicinity.

[0030] Fig. 4 is a diagram showing a process flow according to an example of the present disclosure. The process flow according to the example includes the process flow described in embodiment 2 (steps ST1 and ST2 in Fig. 1, and steps ST11 and ST12 in Fig. 2). Fig. 5 is a diagram showing a process flow according to a comparative example of the present disclosure. The process flow according to the comparative example does not include Si film formation and nitridation treatment (steps ST1 and ST2 in Fig. 1).

[0031] (2-2) Calculation method for electron trap density The electron trap density was calculated as follows: A stress voltage of 3 MV / cm was applied to each of the MOS capacitors according to the example and the comparative example, and the electron trap density was calculated from the difference in flat band voltage of the CV curve before and after the application.

[0032] (2-3) Calculation results of electron trap density FIG. 6 is a graph showing the electron trap density ratios of the example and the comparative example. In FIG. 6, the comparative example refers to the MOS capacitor according to the comparative example. The example refers to the MOS capacitor according to the example. The electron trap density ratio on the vertical axis is the ratio when the electron trap density of the MOS capacitor according to the comparative example is set to 1. As shown in FIG. 6, the electron trap density ratio of the MOS capacitor according to the example was 0.3. The MOS capacitor according to the example had an electron trap density reduced by approximately 70% compared to the MOS capacitor according to the comparative example. This result confirmed that the electron trap density could be reduced by performing the process flow according to the example (i.e., a process flow including Si film formation and nitridation treatment).

[0033] (2-4) Relationship with Si film deposition time The relationship between the deposition time of the Si film and the electron trap density was investigated. The results are shown in FIG. 7. FIG. 7 is a graph showing the relationship between the deposition time of the Si film and the electron trap density ratio. The deposition time ratio of the Si film, which is the horizontal axis of FIG. 7, is the ratio when the deposition time of the Si film when creating the MOS capacitor according to the example shown in FIG. 6 is set to 1. The Si deposition time ratio of 1 is the data of the example shown in FIG. 6, and the Si deposition time ratio of 0 (zero) is the data of the comparative example shown in FIG. 6. Note that since the Si deposition time is proportional to the Si film thickness, the "Si film deposition time ratio" may be replaced with the "Si film thickness ratio."

[0034] The left vertical axis in Fig. 7 represents the electron trap density ratio, similar to the vertical axis in Fig. 6. The electron trap density was calculated as described above in (2-2). A stress voltage of 3 MV / cm was applied, and the electron trap density was calculated from the difference in flat band voltage of the CV curve before and after the application.

[0035] The right-hand vertical axis in Figure 7 represents the Dit density ratio. Dit refers to electron traps at a very shallow level at the MOS interface, and in this evaluation refers to electron traps located quite close to the conduction band, 0.2 eV toward the valence band from the conduction band.

[0036] As shown in Figure 7, it was confirmed that both the electron trap density ratio and the Dit density ratio are correlated with the Si film formation time ratio. From this result, it was confirmed that it is possible to control the electrical characteristics of MOS by adjusting the Si film formation conditions (for example, the Si film formation time (or Si film thickness)).

[0037] Note that for each of the deposition time ratios of 0.5, 1, and 2 shown in Figure 7, the nitriding conditions (plasma nitriding conditions) for the Si film were fixed at one condition, and the electron trap density and Dit density were calculated. However, the electron trap density and Dit density are affected not only by the Si film deposition conditions, but also by the plasma nitriding conditions for the Si film. Therefore, by adjusting the plasma nitriding conditions in addition to the Si film deposition conditions, it becomes possible to more precisely control the electrical characteristics of the MOS.

[0038] (GaN semiconductor device) Next, an example of a GaN semiconductor device to which a manufacturing method according to an embodiment of the present disclosure can be applied will be described. FIGS. 8 and 9 are a plan view and a cross-sectional view showing an example configuration of a GaN semiconductor device 100 according to an embodiment of the present disclosure. FIG. 9 shows a cross-section taken along line X1-X'1 in FIG. 8. The GaN semiconductor device 100 shown in FIGS. 8 and 9 is manufactured using, for example, manufacturing method example 1 described above.

[0039] The GaN semiconductor device 100 includes a GaN substrate 1 and a lateral MOSFET (Metal Oxide Semiconductor Field Effect Transistor) 20 provided on the GaN substrate 1.

[0040] The GaN substrate 1 includes, for example, a GaN single crystal substrate 11, an n-type GaN layer 12 provided on the GaN single crystal substrate 11, and a p-type GaN layer 13 provided on the n-type GaN layer 12.

[0041] The GaN single crystal substrate 11 is, for example, an n+ type c-plane GaN single crystal substrate. The n-type impurities contained in the GaN single crystal substrate 11 are one or more of Si, oxygen (O), and germanium (Ge). The GaN single crystal substrate 11 has a dislocation density of 1×10 7 cm -2 The substrate may be a freestanding substrate with a low dislocation density of less than 1000 nm.

[0042] GaN layer 12 is a layer epitaxially grown on the surface of GaN single crystal substrate 11, and contains, for example, Si as an n-type impurity. Si is doped during the epitaxial growth of GaN layer 12. The thickness of GaN layer 12 is, for example, 1 μm or less.

[0043] GaN layer 13 is a layer epitaxially grown on the surface of GaN layer 12, and contains magnesium (Mg) as a p-type impurity. Mg is doped during the epitaxial growth of GaN layer 13. The thickness of GaN layer 13 is, for example, 4 μm.

[0044] The configuration of GaN substrate 1 is not limited to the above. For example, there may be no n-type GaN layer 12, and p-type GaN layer 13 may be provided directly on n+-type GaN single crystal substrate 11. GaN substrate 1 may also be composed of only a Mg-doped p-type single crystal GaN layer. That is, GaN substrate 1 may be a Mg-doped p-type GaN single crystal substrate.

[0045] The lateral MOSFET 20 includes a SiN film 3 provided on a p-type GaN layer 13 doped with Mg, a gate insulating film 4 provided on the SiN film 3, a gate electrode 22 provided on the gate insulating film 4, an n+ type source region 23 provided in the GaN layer 13, an n+ type drain region 24 provided in the GaN layer 13, a source electrode 25 provided above the GaN layer 13 and in contact with the source region 23, and a drain electrode 26 provided above the GaN layer 13 and in contact with the drain region 24.

[0046] The SiN film 3 is a film formed by nitriding a Si film with N2 plasma, as described in Manufacturing Method Example 1. The thickness of the SiN film 3 is, for example, 1 nm or less.

[0047] The gate insulating film 4 is, for example, an SiO2 film or an Al2O3 film, as described in Manufacturing Method Example 1. The thickness of the SiO2 film that is the gate insulating film 4 is, for example, 100 nm.

[0048] The gate electrode 22 is adjacent to the channel region via the gate insulating film 4 and the SiN film 3. The gate electrode 22 is made of, for example, aluminum (Al) and has a thickness of 200 nm. The gate electrode 22 may also be made of a material other than Al.

[0049] The source region 23 and the drain region 24 are provided in the GaN layer 13 below both sides of the gate electrode 22. The source region 23 and the drain region 24 are, for example, n+ type impurity-implanted layers.

[0050] 9, the source electrode 25 is in contact with the source region 23 and the p-type GaN layer 13 through an opening h1 provided in the gate insulating film 4. This allows the potential of the p-type GaN layer 13 to be fixed to the potential of the source electrode 25. The drain electrode 26 is in contact with the drain region 24 through an opening h2 provided in the gate insulating film 4. The drain electrode 26 is not in contact with the p-type GaN layer 13.

[0051] The source electrode 25 and the drain electrode 26 are made of Al or an Al-Si alloy, nickel (Ni), a Ni alloy, a titanium (Ti)-Al alloy, a Ni-gold (Au) alloy, or the like. The source electrode 25 may have a barrier metal layer between it and the source region 23. The drain electrode 26 may have a barrier metal layer between it and the drain region 24. The barrier metal layer may be made of Ti.

[0052] The source electrode 25 may be directly connected to the p-type GaN layer 13 or may be indirectly connected via a p-type layer (not shown). In this way, the potential of the p-type GaN layer 13 may be fixed to the potential of the source electrode 25.

[0053] (Effects of the embodiment) As described above, the method for manufacturing a GaN semiconductor device according to an embodiment of the present disclosure includes the steps of forming a Si film 2 on a GaN substrate 1, nitriding the Si film 2 to form a SiN film 3, and forming a gate insulating film 4 on the SiN film 3. In the step of nitriding the Si film 2, it is preferable to nitride the entire Si film 2 to form the SiN film 3 from the Si film 2 so that no Si film 2 remains on the GaN substrate 1.

[0054] According to the manufacturing method of the embodiment of the present disclosure, a Si film 2 is formed on a GaN substrate 1, instead of an SiO2 film. Because the source gas for forming the Si film 2 does not contain oxygen (O), it is possible to suppress the formation of GaOx on the surface 1a of the GaN substrate 1. It is known that GaOx undergoes a reduction reaction during heat treatment, turning into a positive fixed charge, which shifts the threshold voltage of an n-type MOSFET in the negative direction. However, according to the manufacturing method of the present embodiment, the formation of GaOx is suppressed, and therefore a decrease in the threshold voltage caused by GaOx can be prevented.

[0055] Furthermore, according to the manufacturing method of this embodiment, a SiN film 3 is formed by nitriding the Si film 2 formed on the GaN substrate 1. This makes it possible to suppress irradiation of the surface 1a of the GaN substrate 1 with N2 plasma, compared to when a nitrogen (N)-containing insulating film (e.g., a SiN film or a SiON film) is directly formed on the GaN substrate by plasma CVD. Irradiation of the surface 1a of the GaN substrate 1 with N2 plasma can cause electron trapping, but according to the manufacturing method of this embodiment, N2 plasma irradiation is suppressed as described above, and therefore electron trapping can be reduced.

[0056] Furthermore, not only the irradiation of N2 plasma but also the Si film 2 formed on the GaN substrate 1 can become a source of electron traps if left as is on the GaN substrate 1. For this reason, in the nitriding treatment of the Si film 2, it is preferable to nitride the entire Si film 2. According to the manufacturing method of this embodiment, the nitriding treatment is performed on the Si film 2 in a state where no other film is formed on the Si film 2 (i.e., in a state where the Si film 2 is exposed), so that it is easy to nitride the entire Si film 2 and it is possible to reduce the source of electron traps.

[0057] For example, consider a process in which an insulating film containing N is deposited on a Si film using plasma CVD. In this process, it is possible to nitride the underlying Si film by utilizing the plasma atmosphere (N2 plasma) used when depositing the N-containing insulating film (e.g., SiON film). However, with this method, the N2 plasma exposure to the Si film is limited to the initial stage of SiON film deposition, and the Si film is quickly covered by the SiON film, making it difficult to nitride the entire Si film.

[0058] As described above, the manufacturing method according to this embodiment can reduce electron traps at the MOS interface, thereby improving the mobility of the MOSFET. A GaN-MOSFET (e.g., a lateral MOSFET 20) that achieves both high mobility and a high threshold voltage can be realized.

[0059] Furthermore, as explained with reference to FIG. 7, for example, it is possible to control the electrical characteristics of the GaN-MOSFET by adjusting the film formation conditions of the Si film 2 and the conditions of the nitriding treatment.

[0060] (Variation) In the above embodiment, the Si film 2 is formed by plasma CVD. However, in the embodiments of the present disclosure, the formation of the Si film 2 is not limited to plasma CVD. For example, the Si film 2 may be formed by thermal CVD, sputtering, or atomic deposition. Even in such a case, the formation of GaOx on the surface 1a of the GaN substrate 1 can be suppressed, thereby preventing a decrease in threshold voltage due to GaOx. Furthermore, by forming a SiN film 3 by nitriding the Si film 2 formed by these methods, electron traps at the MOS interface can be reduced.

[0061] (Other embodiments) As described above, the present disclosure has been described by the embodiments, examples, and modifications, but the descriptions and drawings that form part of this disclosure should not be understood to limit the present disclosure. Various alternative embodiments will become apparent to those skilled in the art from this disclosure.

[0062] 8 and 9 may be manufactured using the above-described manufacturing method example 2. In that case, the gate insulating film 4 is composed of a first gate insulating film 4A exemplified by a silicon oxynitride film and a second gate insulating film 4B exemplified by a silicon oxide film.

[0063] In the above embodiment, the GaN semiconductor device 100 has been described as having a horizontal MOSFET 20. However, the MOSFET included in the GaN semiconductor device 100 is not limited to a horizontal type in which a current flows horizontally relative to the GaN substrate 1, and may be a vertical type in which a current flows vertically relative to the GaN substrate 1. The vertical MOSFET may have a planar structure or a trench gate structure.

[0064] In either structure, a thin Si film 2 is formed, and then the formed Si film 2 is subjected to nitriding treatment using N2 plasma or the like, after which the gate insulating film 4 is formed. This reduces electron traps at the MOS interface, thereby improving the mobility of the MOSFET. A vertical GaN-MOSFET that combines high mobility and high threshold voltage can be realized.

[0065] As such, the present technology naturally includes various embodiments not described herein. At least one of various omissions, substitutions, and modifications of components can be made without departing from the spirit of the above-described embodiments, examples, and modifications. Furthermore, the effects described in this specification are merely examples and are not intended to be limiting, and other effects may also be present.

[0066] The present disclosure can also be configured as follows. (1) forming a silicon-based film on a gallium nitride substrate; a step of forming a nitride film by subjecting the silicon-based film to a nitriding treatment; and forming a gate insulating film on the nitride film. (2) In the step of subjecting the silicon-based film to the nitriding treatment, The method for manufacturing a nitride semiconductor device according to (1), wherein the silicon-based film is entirely nitrided to form the nitride film from the silicon-based film, so that no silicon-based film remains on the gallium nitride substrate. (3) In the step of forming a silicon-based film, The method for manufacturing a nitride semiconductor device according to (1) or (2) above, wherein the silicon-based film is formed to a thickness of 1 nm or less. (4) In the step of forming a silicon-based film, The method for manufacturing a nitride semiconductor device according to any one of (1) to (3), wherein the silicon-based film is formed by thermal CVD, plasma CVD, sputtering, or atomic deposition. (5) In the step of forming a silicon-based film, The method for manufacturing a nitride semiconductor device according to any one of (1) to (3), wherein the silicon-based film is formed by a plasma CVD method in a source gas atmosphere containing silicon and not containing oxygen or nitrogen. (6) The method for manufacturing a nitride semiconductor device according to any one of (1) to (5), wherein the nitriding treatment increases a composition ratio of nitrogen in the silicon-based film. (7) The method for manufacturing a nitride semiconductor device according to any one of (1) to (6), wherein the nitriding treatment is performed by plasma irradiation in an atmosphere containing nitrogen gas. (8) In the step of forming the gate insulating film, The method for manufacturing a nitride semiconductor device according to any one of (1) to (7), wherein the gate insulating film is a film made of at least one of an oxide of silicon and an oxide of aluminum. (9) The step of forming the gate insulating film includes: forming a silicon oxynitride film on the nitride film as part of the gate insulating film; and forming a film composed of at least one of an oxide of silicon or an oxide of aluminum on the silicon oxynitride film as another part of the gate insulating film. (10) The method for manufacturing a nitride semiconductor device according to any one of (1) to (9), further comprising the step of, after forming the gate insulating film, subjecting the entire substrate including the gate insulating film, the nitride film, and the gallium nitride substrate to a heat treatment at 400°C or higher. [Explanation of symbols]

[0067] 1. GaN substrate 1a surface 2. Si film 3 SiN film 4 Gate insulating film 4A First gate insulating film 4B Second gate insulating film 11 GaN single crystal substrate 12 GaN layers 13 GaN layer 20 MOSFET 22 gate electrode 23 Source Region 24 Drain region 25 Source electrode 26 Drain electrode 100 GaN semiconductor devices h1, h2 opening

Claims

1. forming a silicon-based film on a gallium nitride substrate; a step of forming a nitride film by subjecting the silicon-based film to a nitriding treatment; and forming a gate insulating film on the nitride film.

2. In the step of subjecting the silicon-based film to the nitriding treatment, 2. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the silicon-based film is entirely nitrided to form the nitride film from the silicon-based film, so that no silicon-based film remains on the gallium nitride substrate.

3. In the step of forming a silicon-based film, The method for manufacturing a nitride semiconductor device according to claim 1 or 2, wherein the silicon-based film is formed to a thickness of 1 nm or less.

4. In the step of forming a silicon-based film, 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said silicon-based film is formed by thermal CVD, plasma CVD, sputtering, or atomic deposition.

5. In the step of forming a silicon-based film, 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said silicon-based film is formed by plasma CVD in a source gas atmosphere containing silicon but not containing oxygen or nitrogen.

6. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein said nitriding treatment increases a composition ratio of nitrogen in said silicon-based film.

7. 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the nitriding treatment is performed by plasma irradiation in an atmosphere containing nitrogen gas.

8. In the step of forming the gate insulating film, 3. The method for manufacturing a nitride semiconductor device according to claim 1, wherein the gate insulating film is a film made of at least one of an oxide of silicon and an oxide of aluminum.

9. The step of forming the gate insulating film includes: forming a silicon oxynitride film on the nitride film as part of the gate insulating film; 3. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising the step of: depositing a film composed of at least one of an oxide of silicon and an oxide of aluminum on the silicon oxynitride film as another part of the gate insulating film.

10. 3. The method for manufacturing a nitride semiconductor device according to claim 1, further comprising the step of: after forming the gate insulating film, performing a heat treatment at 400° C. or higher on the entire substrate including the gate insulating film, the nitride film, and the gallium nitride substrate.

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