Semiconductor storage device

Abstract

To suppress a decrease in the yield of a semiconductor storage device.SOLUTION: A semiconductor storage device of an embodiment comprises a memory cell array, a first member W1, and a first conductor portion 30B-2 crossing the first member W1. The memory cell array includes a source line, a plurality of word lines located on one side in a Z direction relative to the source line, and a memory pillar. The first conductor portion 30B-2 is included in the same layer as the source line, and the surface on the other side in the Z direction has the same height as the height of the surface on the other side in the Z direction of the source line. The first member W1 extends in the Z direction so as to surround the plurality of word lines, reaches the other side in the Z direction relative to a first height of the other side surface of the first conductive portion 30B-2, and includes a first contact LI2 integrally provided along the Z direction, and a first insulating film SP2 covering the portion from a second height at one end of the first contact LI2 on one side in the Z direction to a third height on one side in the Z direction relative to the other end of the first contact LI2 in the Z direction among the side surfaces of the first contact LI2.SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] The embodiments relate to a semiconductor memory device. [Background technology]

[0002] NAND flash memory is a well-known semiconductor memory device capable of storing data nonvolatilely. NAND flash memory employs a three-dimensional memory structure to achieve high integration and large capacity. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-160922 [Patent Document 2] Japanese Patent Publication No. 2022-050233 [Patent Document 3] Japanese Patent Publication No. 2022-147748 Summary of the Invention [Problem to be solved by the invention]

[0004] This suppresses a decrease in the yield of semiconductor memory devices. [Means for solving the problem]

[0005] a first conductive portion provided in the second region so as to intersect with the first member within the second region, the memory cell array including a source line provided above the substrate, a plurality of word lines provided above the substrate and on one side in a first direction intersecting with a surface of the substrate from the source line, the plurality of word lines being spaced apart in the first direction, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the memory pillar having one end in the first direction connected to the source line, the first conductive portion being included in the same layer as the source line, and a surface on the other side in the first direction being connected to the source line; the first member has a height equivalent to that of the surface on the other side in the first direction of the first conductive portion, and is electrically insulated from the source line; the first member extends in the first direction to surround the plurality of word lines over at least an area equivalent to that of the plurality of word lines in the first direction while being spaced apart from the plurality of word lines, and extends from a first height of the surface on the other side of the first conductive portion to the other side in the first direction, and is integrally provided along the first direction; and a first insulating film covering a side surface of the first contact from a second height of one end of the first contact on the one side in the first direction to a third height from the other end of the first contact in the first direction on the one side, and forming an end on the other side in the first direction at the third height. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to a first embodiment. [Figure 2] FIG. 2 is a circuit diagram showing an example of the circuit configuration of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 3] FIG. 1 is a plan view showing an example of a planar layout of a semiconductor memory device according to a first embodiment. [Figure 4]FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 5] FIG. 2 is a plan view showing an example of a planar layout of a memory cell array included in the semiconductor memory device according to the first embodiment. [Figure 6] 6 is a cross-sectional view taken along line VI-VI in FIG. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the first embodiment. [Figure 7] 7 is a cross-sectional view taken along line VII-VII in FIG. 6, showing an example of the cross-sectional structure of a memory pillar of the semiconductor memory device according to the first embodiment. [Figure 8] 3 is a cross-sectional view showing an example of the cross-sectional structure in the circuit region and wall region of the semiconductor memory device according to the first embodiment. [Figure 9] 3 is a cross-sectional view showing an example of the cross-sectional structure of a sealing portion and a member of the semiconductor memory device according to the first embodiment. [Figure 10] FIG. 2 is a cross-sectional view showing an example of the cross-sectional structure of a connection pad according to the first embodiment. [Figure 11] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 12] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 13] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 14] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 15] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 16] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 17] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 18] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 19]3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 20] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 21] 3A to 3C are cross-sectional views illustrating an example of a method for manufacturing the semiconductor memory device according to the first embodiment. [Figure 22] FIG. 10 is a plan view showing an example of a planar layout of a semiconductor memory device according to a first modified example of the first embodiment. [Figure 23] 23 is a cross-sectional view taken along line XXIII-XXIII in FIG. 22, showing an example of the cross-sectional structure of the sealing portion of the semiconductor memory device according to the first modification of the first embodiment. [Figure 24] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region and a wall region of a semiconductor memory device according to a second modification of the first embodiment. [Figure 25] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of the sealing portion of the semiconductor memory device according to a third modification of the first embodiment. [Figure 26] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a third modification of the first embodiment. [Figure 27] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a third modification of the first embodiment. [Figure 28] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a third modification of the first embodiment. [Figure 29] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a third modification of the first embodiment. [Figure 30] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of the sealing portion of the semiconductor memory device according to a fourth modification of the first embodiment. [Figure 31] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a fourth modification of the first embodiment. [Figure 32] FIG. 10 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array in a semiconductor memory device according to a second embodiment. [Figure 33] 10 is a cross-sectional view showing an example of the cross-sectional structure in a circuit region and a wall region of a semiconductor memory device according to a second embodiment. [Figure 34] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 35] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a second embodiment. [Figure 36] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure of a memory cell array in a semiconductor memory device according to a modified example of the second embodiment. [Figure 37] FIG. 10 is a cross-sectional view showing an example of a cross-sectional structure in a circuit region and a wall region of a semiconductor memory device according to a modified example of the second embodiment. [Figure 38] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a modified example of the second embodiment. [Figure 39] 10A and 10B are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to a modified example of the second embodiment. [Figure 40] FIG. 10 is a plan view showing an example of a planar layout of a semiconductor memory device according to another embodiment. [Figure 41] 41 is a cross-sectional view taken along line XLI-XLI in FIG. 40, showing an example of a cross-sectional structure in a circuit region and a wall region of a semiconductor memory device according to another embodiment. [Figure 42] 10A to 10C are cross-sectional views illustrating an example of a method for manufacturing a semiconductor memory device according to another embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings. Note that the dimensions and proportions of the drawings are not necessarily the same as those in reality. In the following description, components having substantially the same functions and configurations are designated by the same reference numerals. Furthermore, when elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0008] 1. First embodiment The semiconductor memory device according to the first embodiment will be described below.

[0009] 1.1 Configuration The configuration of the semiconductor memory device according to the first embodiment will be described.

[0010] 1.1.1 Memory System First, an example of the configuration of a memory system will be described with reference to Fig. 1. Fig. 1 is a block diagram showing an example of the configuration of a memory system including a semiconductor memory device according to the first embodiment.

[0011] The memory system 3 is, for example, an SSD (solid state drive) or SD TM The memory system 3 is a card. The memory system 3 is connected to, for example, an external host device (not shown). The memory system 3 stores data from the host device. The memory system 3 also reads data to the host device.

[0012] The memory system 3 includes a semiconductor memory device 1 and a memory controller 2.

[0013] The semiconductor memory device 1 is, for example, a NAND flash memory. The semiconductor memory device 1 stores data in a non-volatile manner. In the following, an example will be described in which the semiconductor memory device 1 is a NAND flash memory.

[0014] The memory controller 2 is configured by an integrated circuit such as a system-on-a-chip (SoC). The memory controller 2 writes data to the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also reads data from the semiconductor memory device 1 based on a request from the host device, for example. The memory controller 2 also transmits the data read from the semiconductor memory device 1 to the host device.

[0015] The communication between the semiconductor memory device 1 and the memory controller 2 complies with, for example, an SDR (single data rate) interface, a toggle DDR (double data rate) interface, or an ONFI (Open NAND flash interface).

[0016] 1.1.2 Semiconductor memory devices Continuing with the description of the internal configuration of the semiconductor memory device 1, the semiconductor memory device 1 includes, for example, a memory cell array 10 and a peripheral circuit PERI. The peripheral circuit PERI includes, for example, a command register 11, an address register 12, a sequencer 13, a driver module 14, a row decoder module 15, and a sense amplifier module 16.

[0017] The memory cell array 10 includes a plurality of blocks BLK0 to BLK(m-1) (m is an integer equal to or greater than 2). A block BLK is a set of a plurality of memory cells capable of storing data in a non-volatile manner. A block BLK is used, for example, as a unit for erasing data. The memory cell array 10 is also provided with a plurality of bit lines and a plurality of word lines. For example, one memory cell is associated with one bit line and one word line.

[0018] The command register 11 holds the command CMD that the semiconductor memory device 1 receives from the memory controller 2. The command CMD includes, for example, an instruction to make the sequencer 13 execute a read operation, a write operation, an erase operation, and the like.

[0019] The address register 12 holds address information ADD that the semiconductor memory device 1 receives from the memory controller 2. The address information ADD includes, for example, a page address PA, a block address BA, and a column address CA. For example, the page address PA, the block address BA, and the column address CA are used to select a word line, a block BLK, and a bit line, respectively.

[0020] The sequencer 13 controls the overall operation of the semiconductor memory device 1. Based on the command CMD stored in the command register 11, the sequencer 13 executes a read operation, a write operation, and an erase operation.

[0021] The driver module 14 generates voltages used in read operations, write operations, erase operations, etc. Then, the driver module 14 applies the generated voltages to a signal line corresponding to a selected word line based on, for example, a page address PA held in the address register 12.

[0022] The row decoder module 15 selects one block BLK in the corresponding memory cell array 10 based on the block address BA held in the address register 12. Then, the row decoder module 15 transfers, for example, a voltage applied to a signal line corresponding to the selected word line to the selected word line in the selected block BLK.

[0023] In a write operation, the sense amplifier module 16 transfers write data DAT received from the memory controller 2 to the memory cell array 10. In a read operation, the sense amplifier module 16 determines the data stored in the memory cell based on the voltage of the bit line. The sense amplifier module 16 transfers the result of this determination to the memory controller 2 as read data DAT.

[0024] 1.1.3 Memory cell array circuit configuration An example of the circuit configuration of the memory cell array 10 will be described with reference to Fig. 2. Fig. 2 is a circuit diagram showing an example of the circuit configuration of the memory cell array included in the semiconductor memory device according to the first embodiment. Fig. 2 shows one block BLK among multiple blocks BLK included in the memory cell array 10. In the example shown in Fig. 2, the block BLK includes four string units SU0, SU1, SU2, and SU3.

[0025] Each string unit SU includes a plurality of NAND strings NS associated with bit lines BL0 to BL(n-1) (n is an integer equal to or greater than 2). Each NAND string NS includes, for example, memory cell transistors MT0 to MT7 and select transistors ST1 and ST2. Each of the memory cell transistors MT0 to MT7 includes a control gate and a charge storage film. Each of the memory cell transistors MT0 to MT7 stores data in a non-volatile manner. The select transistors ST1 and ST2 are used to select the string unit SU during various operations. In the following description, when the bit lines BL0 to BL(n-1) are not distinguished from one another, each of the bit lines BL0 to BL(n-1) will simply be referred to as a bit line BL. When the memory cell transistors MT0 to MT7 are not distinguished from one another, each of the memory cell transistors MT0 to MT7 will simply be referred to as a memory cell transistor MT.

[0026] In each NAND string NS, the memory cell transistors MT0 to MT7 are connected in series. One end of the select transistor ST1 is connected to the bit line BL associated with the select transistor ST1. The other end of the select transistor ST1 is connected to one end of the memory cell transistors MT0 to MT7 connected in series. One end of the select transistor ST2 is connected to the other end of the memory cell transistors MT0 to MT7 connected in series. The other end of the select transistor ST2 is connected to a source line SL.

[0027] In the same block BLK, the control gates of memory cell transistors MT0 to MT7 are connected to word lines WL0 to WL7, respectively. The gates of select transistor ST1 in string units SU0 to SU3 are connected to select gate lines SGD0 to SGD3, respectively. In contrast, the gates of multiple select transistors ST2 are commonly connected to a select gate line SGS. However, this is not a limitation, and the gates of multiple select transistors ST2 may be connected to multiple select gate lines SGS that are different for each string unit SU. In the following description, when the word lines WL0 to WL7 are not distinguished, each of the word lines WL0 to WL7 will simply be referred to as a word line WL. Furthermore, when the select gate lines SGD0 to SGD3 are not distinguished, each of the select gate lines SGD0 to SGD3 will simply be referred to as a select gate line SGD.

[0028] A different column address is assigned to each of the bit lines BL0 to BL(n-1). Each bit line BL is shared by NAND strings NS that are assigned the same column address among multiple blocks BLK. Word lines WL0 to WL7 are provided for each block BLK. A source line SL is shared, for example, among multiple blocks BLK.

[0029] A set of memory cell transistors MT connected to a common word line WL within one string unit SU is called a cell unit CU. For example, the storage capacity of a cell unit CU including multiple memory cell transistors MT, each storing one bit of data, is defined as "one page of data." A cell unit CU may have a storage capacity of two or more pages of data depending on the number of bits of data stored in the memory cell transistors MT.

[0030] The circuit configuration of the memory cell array 10 is not limited to the configuration described above. For example, each block BLK may include any number of string units SU. Each NAND string NS may include any number of memory cell transistors MT and select transistors ST1 and ST2.

[0031] 1.1.4 Structure of semiconductor memory device An example of the structure of the semiconductor memory device 1 according to the first embodiment will be described.

[0032] In the following description, the X direction is approximately parallel to the semiconductor substrate of the semiconductor memory device 1. The X direction corresponds to the extension direction of the word lines WL. The Y direction is approximately parallel to the semiconductor substrate and perpendicular to the X direction. The Y direction corresponds to the extension direction of the bit lines BL. The Z1 and Z2 directions are approximately perpendicular to the semiconductor substrate. The Z1 direction corresponds to the direction from the semiconductor substrate of the semiconductor memory device 1 toward the electrode pads. The Z2 direction corresponds to the direction from the electrode pads toward the semiconductor substrate. When the Z1 and Z2 directions are not distinguished, each of the Z1 and Z2 directions will be simply referred to as the Z direction. Hereinafter, the Z2 direction side of a certain component will be referred to as one side in the Z direction (or simply one side), and the Z1 direction side will be referred to as the other side in the Z direction (or simply the other side). Furthermore, the surface of a certain component facing the electrode pads will be referred to as the first surface, and the surface of a certain component facing the semiconductor substrate will be referred to as the second surface. The first surface and the second surface can also be called the surface on the other side in the Z direction and the surface on one side in the Z direction, respectively.

[0033] 1.1.4.1 Planar Configuration of Semiconductor Memory Devices An example of the planar configuration of the semiconductor memory device 1 will be described with reference to Fig. 3. Fig. 3 is a plan view showing an example of the planar layout of the semiconductor memory device according to the first embodiment.

[0034] The semiconductor memory device 1 is divided into a circuit region CR, a wall region WR, and a kerf region KR in the planar layout shown in FIG.

[0035] The circuit region CR is an area in which elements that constitute the semiconductor memory device 1, such as the memory cell array 10, the command register 11, the address register 12, the sequencer 13, the driver module 14, the row decoder module 15, and the sense amplifier module 16, are provided. The circuit region CR is, for example, a rectangular area.

[0036] The wall region WR is, for example, a region provided to surround the outer periphery of the circuit region CR. One or more sealing portions ES are provided in the wall region WR so that each of them surrounds the outer periphery of the circuit region CR when viewed from above. In the first embodiment, an example is shown in which sealing portions ES1 and ES2 are provided. Furthermore, a plurality of conductor layers 208 are provided in the wall region WR so that each of them surrounds the outer periphery of the circuit region CR when viewed from above. Each of the plurality of conductor layers 208 may have an intermittent annular pattern or a continuous annular pattern. The example of FIG. 3 shows a case in which each of the plurality of conductor layers 208 has an intermittent annular pattern. Furthermore, one of the sealing portions ES1 and ES2 may have an intermittent annular pattern. The plurality of conductor layers 208 are provided, for example, closer to the outer periphery of the semiconductor memory device 1 than the sealing portion ES. In FIG. 3, the regions where the sealing portion ES and each of the plurality of conductor layers 208 are provided are indicated by dotted lines.

[0037] The sealing portion ES is a structure that can release electric charges generated inside and outside the wall region WR to the semiconductor substrate. Each sealing portion ES suppresses the accumulation of electric charges that may occur during etching, for example, in the manufacturing process of the semiconductor memory device 1. Each sealing portion ES can also function as a crack stopper or edge seal. That is, when a crack occurs in the peripheral portion of the chip on which the semiconductor memory device 1 is formed, each sealing portion ES prevents the crack from reaching the inside of the semiconductor memory device 1 beyond the sealing portion ES. Furthermore, each sealing portion ES suppresses the penetration of moisture and the like from the outer periphery of the wall region WR to the inside. The configuration of the sealing portion ES will be described later.

[0038] Similar to the sealing portion ES, the plurality of conductive layers 208 are structures that allow charges generated inside and outside the wall region WR to escape to the semiconductor substrate. Each of the plurality of conductive layers 208 suppresses charge accumulation that may occur during etching, for example, in a manufacturing process different from the manufacturing process in which charge accumulation is suppressed by the sealing portion ES. The cross-sectional configuration of the plurality of conductive layers 208 will be described later.

[0039] The sealing portion ES and the suppression of charge accumulation by the plurality of conductive layers 208 will be described later.

[0040] The kerf region KR is a region provided to surround the outer periphery of the wall region WR. The kerf region KR is located at the outermost periphery of the semiconductor memory device 1. For example, alignment marks used during manufacturing of the semiconductor memory device 1 and circuits for performance testing of the semiconductor memory device 1 are provided in the kerf region KR.

[0041] 1.1.4.2 Memory Cell Array Structure First, an example of the structure of the memory cell array 10 provided in the circuit region CR will be described.

[0042] 1.1.4.2.1 Overall Configuration of Memory Cell Array The overall configuration of the memory cell array 10 will be described with reference to Fig. 4. Fig. 4 is a plan view showing an example of a planar layout of the memory cell array included in the semiconductor memory device according to the first embodiment. Fig. 4 shows areas corresponding to four blocks BLK0 to BLK3.

[0043] The memory cell array 10 includes a stacked wiring structure and a plurality of components SLT and SHE. The stacked wiring structure includes select gate lines SGD and SGS and word lines WL. The stacked wiring structure is a structure in which the select gate lines SGD and SGS and the word lines WL are stacked along the Z direction according to the number of layers. In the following description, the select gate lines SGD and SGS and the word lines WL are also collectively referred to as stacked wiring.

[0044] The stacked wiring structure is provided across the memory area MA and the lead-out area HA in the X direction, for example.

[0045] The memory area MA is essentially an area where data is stored.

[0046] The lead-out area HA is an area used for connecting the stacked wiring to the peripheral circuits PERI such as the row decoder module 15.

[0047] Each member SLT extends in the X direction. Each member SLT crosses the stacked wiring structure in the X direction across the memory region MA and the lead-out region HA. Each member SLT has a structure in which, for example, an insulator or a plate-shaped contact is embedded therein. Each member SLT separates adjacent stacked wirings via that member SLT. Each area separated by multiple members SLT corresponds to one block BLK. In the following description, the end of the blocks BLK0 to BLK3 on the block BLK0 side along the Y direction is referred to as one end in the Y direction.

[0048] Each member SHE extends in the X direction. In the first embodiment, a case will be described in which three members SHE are provided between adjacent members SLT. Each member SHE crosses the stacked wiring structure in the X direction across the memory area MA. Each member SHE has, for example, a structure in which an insulator is embedded. Each member SHE separates adjacent select gate lines SGD via the member SHE, for example. Each area partitioned by multiple members SLT and SHE corresponds to one string unit SU.

[0049] In the memory cell array 10, for example, the planar layout shown in FIG. 4 is repeatedly arranged in the Y direction.

[0050] Note that the planar layout of the memory cell array 10 is not limited to the layout described above. For example, the number of components SHE arranged between adjacent components SLT can be designed to be any number depending on the number of string units SU.

[0051] 1.1.4.2.2 Memory Cell Array Structure in the Memory Area The structure of the memory area MA of the memory cell array 10 will be described.

[0052] 1.1.4.2.2.1 Planar structure The planar structure of the memory area MA of the memory cell array 10 will be described with reference to Fig. 5. Fig. 5 is a plan view showing an example of the planar layout of the memory cell array included in the semiconductor memory device according to the first embodiment.

[0053] In the memory region MA, the memory cell array 10 includes a plurality of memory pillars MP, a plurality of contacts CV, and a plurality of bit lines BL. Also, each member SLT includes a contact LI1 and a spacer SP1.

[0054] Each memory pillar MP functions as, for example, one NAND string NS. The memory pillars MP are arranged in a staggered pattern of, for example, 19 rows in the region between two adjacent members SLT. Then, for example, counting from one end in the Y direction, one member SHE overlaps with the fifth memory pillar MP, the tenth memory pillar MP, and the fifteenth memory pillar MP.

[0055] Each of the multiple bit lines BL extends in the Y direction. The multiple bit lines BL are also aligned in the X direction. Each bit line BL is arranged so as to overlap at least one memory pillar MP for each string unit SU. In the example of FIG. 5, each bit line BL is arranged so as to overlap two memory pillars MP for each string unit SU. One of the multiple bit lines BL overlapping with a memory pillar MP is electrically connected to the memory pillar MP via a contact CV. The contact CV between the memory pillar MP overlapping with the member SHE and the bit line BL is, for example, omitted (not provided).

[0056] The contact LI1 is a conductor having a portion extending in the X direction. The spacer SP1 is an insulator provided on the side of the contact LI1. The contact LI1 is sandwiched between the spacers SP1. The contact LI1 and the stacked wiring adjacent to the contact LI1 in the Y direction are electrically separated by the spacer SP1. As a result, the contact LI1 and the stacked wiring adjacent to the contact LI1 in the Y direction are insulated from each other.

[0057] 1.1.4.2.2.2 Cross-sectional structure The cross-sectional structure of the memory region MA of the memory cell array 10 will be described with reference to Fig. 6. Fig. 6 is a cross-sectional view taken along line VI-VI in Fig. 5, showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the first embodiment.

[0058] The memory cell array 10 further includes conductor layers 30A, 31, and 33, multiple conductor layers 32, 34, 35, and 36, insulator layers 40, 41, 43, 44, and 45, and multiple insulator layers 42. FIG. 6 shows five memory pillars MP out of the multiple memory pillars MP. FIG. 6 also shows a case where the multiple conductor layers 32 and multiple insulator layers 42 include eight conductor layers 32 and eight insulator layers 42. The memory cell array 10 is provided between the electrode pads and the semiconductor substrate of the semiconductor memory device 1 in the Z direction.

[0059] The conductor layer 30A is formed, for example, in a plate shape extending along the XY plane. The conductor layer 30A is used as the source line SL. The conductor layer 30A is made of a conductive material. The conductive material is, for example, an N-type semiconductor doped with impurities or a metal material.

[0060] An insulating layer 40 is stacked on the second surface of the conductive layer 30A. A conductive layer 31 is stacked on the second surface of the insulating layer 40. The conductive layer 31 is formed, for example, in the shape of a plate extending along the XY plane. The conductive layer 31 is used as a select gate line SGS. The conductive layer 31 includes, for example, tungsten.

[0061] An insulator layer 41 is stacked on the second surface of the conductor layer 31. Eight conductor layers 32 and eight insulator layers 42 are stacked on the second surface of the insulator layer 41 in the Z1 direction in the order of conductor layer 32, insulator layer 42, ..., conductor layer 32, and insulator layer 42. The conductor layer 32 is formed, for example, in a plate shape extending along the XY plane. The eight conductor layers 32 are used as word lines WL0 to WL7 in order from the conductor layer 31 side along the Z2 direction. The conductor layer 32 contains, for example, tungsten.

[0062] A conductor layer 33 is stacked on the second surface of the insulator layer 42 that is furthest to one side in the Z direction among the eight insulator layers 42. The conductor layer 33 is formed, for example, in a plate shape extending along the XY plane. The conductor layer 33 is used as the select gate line SGD. The conductor layer 33 includes, for example, tungsten. The conductor layer 33 is electrically insulated for each string unit SU by, for example, a plurality of members SHE.

[0063] An insulating layer 43 is stacked on the second surface of the conductive layer 33. A conductive layer 34 is stacked on the second surface of the insulating layer 43. The conductive layer 34 is provided to extend along the Y direction. The conductive layer 34 functions as a bit line BL.

[0064] The laminated structure including the above-described conductor layers 30A, 31, 33, and 34, the eight conductor layers 32, the insulator layers 40, 41, and 43, and the eight insulator layers 42 is provided so as to be surrounded by insulators. FIG. 6 shows the insulator layer 44 in contact with the first surface of the conductor layer 30A and the insulator layer 45 in contact with the second surface of the conductor layer 34. Although not shown in FIG. 6, as will be described later, the conductor layer 30A is electrically connected to the peripheral circuit PERI, for example, via a conductor layer on the other side of the conductor layer 30A. Although not shown in FIG. 6, as will be described later, the conductor layer 34 is electrically connected to the peripheral circuit PERI, for example, via a conductor layer on one side of the conductor layer 34.

[0065] On the other side of the conductive layer 34, a plurality of memory pillars MP are provided extending along the Z direction. The plurality of memory pillars MP penetrate the conductive layers 31 and 33 and the eight conductive layers 32.

[0066] Each of the multiple memory pillars MP includes, for example, a core member 50, a semiconductor film 51, and a stacked film 52. The core member 50 is provided extending along the Z direction. The semiconductor film 51 covers the periphery of the core member 50. The semiconductor film 51 contacts the conductor layer 30A. The stacked film 52 covers the side surface and first surface of the semiconductor film 51 except for the portion where the semiconductor film 51 contacts the conductor layer 30A. The core member 50 includes an insulator such as silicon oxide. The semiconductor film 51 includes, for example, silicon. The configuration of the stacked film 52 will be described later.

[0067] A conductor layer 35 is provided on the second surface of the semiconductor film 51. The conductor layer 35 functions, for example, as a columnar contact. A conductor layer 36 is provided on the second surface of the conductor layer 35. The conductor layer 35 functions, for example, as a contact CV. With the above configuration, the conductor layers 35 and 36 connect the semiconductor film 51 and the conductor layer 34. One conductor layer 34 is connected to one conductor layer 35 and one conductor layer 36 in each of the spaces partitioned by the members SLT and SHE.

[0068] The member SLT divides the conductive layers 31 to 33. The contact LI1 in the member SLT is provided along the member SLT. The second surface of the contact LI1 is located between the conductive layer 33 and the conductive layer 34. The first surface of the contact LI1 is located between the insulating layers 40 and 44. This allows the contact LI1 to be connected to the conductive layer 30A. The contact LI1 is used, for example, as part of the source line SL. A spacer SP1 is provided between the contact LI1 and the conductive layers 31 to 33. The contact LI1 and the conductive layers 31 to 33 are separated and insulated by the spacer SP1. Although not shown in FIG. 6, the contact LI1 may include a barrier metal. That is, the contact LI1 may have a structure in which the barrier metal covers the first surface and side surfaces of a member containing metal, for example.

[0069] The intersection of each of the memory pillars MP and the conductive layer 31 functions as a select transistor ST2. The intersection of each of the memory pillars MP and the conductive layer 32 functions as a memory cell transistor MT. The intersection of each of the memory pillars MP and the conductive layer 33 functions as a select transistor ST1.

[0070] 1.1.4.2.2.3 Cross-sectional structure of memory pillar The structure of the memory pillar MP will be described with reference to Fig. 7. Fig. 7 is a cross-sectional view taken along line VII-VII in Fig. 6, showing an example of the cross-sectional structure of the memory pillar of the semiconductor memory device according to the first embodiment.

[0071] The stacked film 52 includes a tunnel insulating film 53, a charge storage film 54, and a block insulating film 55. The tunnel insulating film 53 covers the side surface and first surface of the semiconductor film 51 except for the portion where the semiconductor film 51 and the conductor layer 30A contact each other. The charge storage film 54 covers the side surface and first surface of the tunnel insulating film 53. The block insulating film 55 covers the side surface and first surface of the charge storage film 54.

[0072] The tunnel insulating film 53 and the block insulating film 55 include, for example, silicon oxide. The charge storage film 54 includes, for example, silicon nitride. The charge storage film 54 is a film that can store electric charges.

[0073] In the above configuration, the semiconductor film 51 functions as the channels of the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2. The charge storage film 54 functions as the charge storage film of the memory cell transistor MT. By turning on the memory cell transistors MT0 to MT7 and the select transistors ST1 and ST2, the semiconductor memory device 1 causes a current to flow between the conductor layers 34 and 30 (between the bit line BL and the source line SL) via the memory pillar MP and the conductor layers 35 and 36.

[0074] 1.1.4.3 Overall cross-sectional structure of semiconductor memory device The overall cross-sectional structure of the semiconductor memory device 1 will be described with reference to Fig. 8. Fig. 8 is a cross-sectional view showing an example of the cross-sectional structure of the circuit region and wall region of the semiconductor memory device according to the first embodiment. Fig. 8 shows the cross-sectional structure of a portion of the semiconductor memory device 1.

[0075] The semiconductor memory device 1 has a structure in which a circuit chip 1-1 and a memory chip 1-2 are bonded together.

[0076] 1.1.4.3.1 Circuit Chip The cross-sectional structure of the circuit chip 1-1 will be described.

[0077] The circuit chip 1-1 includes, for example, a semiconductor substrate 70, multiple conductor layers 101, 102, 103, 104, 105, and 106 that constitute part of the peripheral circuit PERI, and insulator layers 48 and 60. The semiconductor substrate 70 is made of, for example, a P-type semiconductor doped with impurities. The multiple conductor layers 101, 102, 103, 104, 105, and 106 each function as, for example, columnar contacts or wiring. In FIG. 8 , the multiple conductor layers 103 include conductor layers 103-1, 103-2, 103-3, and 103-4. The multiple conductor layers 104 include conductor layers 104-1, 104-2, 104-3, and 104-4. The multiple conductor layers 105 include conductor layers 105-1, 105-2, 105-3, and 105-4. The plurality of conductive layers 106 includes conductive layers 106-1, 106-2, 106-3, and 106-4.

[0078] An insulator layer 48 is provided on the first surface of the semiconductor substrate 70. The insulator layer 48 includes, for example, silicon oxide. A plurality of conductor layers 101, 102, 103, 104, and 105 are provided within the insulator layer 48.

[0079] A peripheral circuit PERI is provided in a circuit region CR on the first surface of the semiconductor substrate 70. In FIG. 8, transistors Tr1 and Tr2 are shown as examples of components included in the peripheral circuit PERI. In the following description, when there is no need to distinguish between the transistors Tr1 and Tr2, the transistors Tr1 and Tr2 will simply be referred to as transistors Tr. Each transistor Tr includes a gate insulating film, a gate electrode, and a source and a drain (not shown) provided in the semiconductor substrate 70.

[0080] A P-type impurity diffusion region PW and an N-type impurity diffusion region NW are provided in the wall region WR of the semiconductor substrate 70. The P-type impurity diffusion region PW and the N-type impurity diffusion region NW may each have an annular pattern that is provided discontinuously or continuously when viewed from above.

[0081] A plurality of conductor layers 101 are provided on first surfaces of the gate electrode, source, and drain of transistor Tr1, the gate electrode, source, and drain of transistor Tr2, the P-type impurity diffusion region PW, and the N-type impurity diffusion region NW. A plurality of conductor layers 102 are connected to the first surfaces of the plurality of conductor layers 101, respectively.

[0082] Each of the plurality of conductor layers 103 is connected to a first surface of the conductor layer 102 corresponding to that conductor layer 103 among the plurality of conductor layers 102. The conductor layers 103-1, 103-2, 103-3, and 103-4 are electrically connected to the transistors Tr1 and Tr2, the P-type impurity diffusion region PW, and the N-type impurity diffusion region NW, respectively.

[0083] Conductive layers 104-1, 104-2, 104-3, and 104-4 are connected to the first surfaces of conductive layers 103-1, 103-2, 103-3, and 103-4, respectively.

[0084] The conductive layers 105-1, 105-2, 105-3, and 105-4 are connected to the first surfaces of the conductive layers 104-1, 104-2, 104-3, and 104-4, respectively. The first surfaces of the plurality of conductive layers 105 are provided so as to be flush with the first surface of the insulating layer 48.

[0085] An insulator layer 60 is provided on the insulator layer 48 and the first surfaces of the plurality of conductor layers 105. The insulator layer 60 includes, for example, silicon oxide.

[0086] A plurality of conductor layers 106 are provided on the same layer as the insulator layer 60. The conductor layers 106-1, 106-2, 106-3, and 106-4 are connected to the first surfaces of the conductor layers 105-1, 105-2, 105-3, and 105-4, respectively. The first surfaces of the plurality of conductor layers 106 are provided so as to be flush with the first surface of the insulator layer 60. The plurality of conductor layers 106 include, for example, copper. The plurality of conductor layers 106 function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. The connection pads are also called bonding pads.

[0087] 1.1.4.3.2 Memory Chips The cross-sectional structure of the memory chip 1-2 will be described with reference to FIG.

[0088] The memory chip 1-2 includes, for example, a plurality of conductor layers 201, 202, 203, 204, 205, 206, and 208, conductor layers 37 and 207, insulator layers 46, 47, and 61, a member 171, a memory cell array 10, and a plurality of members W. Each of the plurality of members W includes a contact LI2 and a spacer SP2. The contact LI2 is a conductor. The spacer SP2 is an insulator provided on a side portion of the contact LI2, as described below.

[0089] The plurality of conductive layers 201, 202, 203, 204, 205, 206, and 208, and the conductive layer 207 each function as, for example, a columnar contact or wiring. In FIG. 8 , the plurality of conductive layers 201 includes conductive layers 201-1, 201-2, 201-3, and 201-4. The plurality of conductive layers 202 includes conductive layers 202-1, 202-2, 202-3, and 202-4. The plurality of conductive layers 203 includes conductive layers 203-1, 203-2, 203-3, and 203-4. The plurality of conductive layers 204 includes conductive layers 204-1, 204-2, 204-3, and 204-4. The plurality of conductive layers 205 includes conductive layers 205-1, 205-2, and 205-3. The plurality of conductive layers 206 includes conductive layers 206-1, 206-2, and 206-3. Also, in FIG. 8, the plurality of members W includes members W1 and W2. Member W1 includes contact LI2-1 and spacer SP2-1 as contact LI2 and spacer SP2, respectively. Member W2 includes contact LI2-2 and spacer SP2-2 as contact LI2 and spacer SP2, respectively.

[0090] In the memory chip 1-2, an insulating layer 61 is provided on the first surface of the circuit chip 1-1. The insulating layer 61 includes, for example, silicon oxide.

[0091] A plurality of conductor layers 201 are provided on the same layer as the insulator layer 61. The conductor layers 201-1, 201-2, 201-3, and 201-4 are connected to the first surfaces of the conductor layers 106-1, 106-2, 106-3, and 106-4, respectively. The first surfaces of the plurality of conductor layers 201 are provided so as to be flush with the first surface of the insulator layer 61. The plurality of conductor layers 201 include, for example, copper. The plurality of conductor layers 201 function as a plurality of connection pads for electrically connecting the circuit chip 1-1 and the memory chip 1-2. With the above-described configuration, the circuit chip 1-1 and the memory chip 1-2 are electrically connected by the plurality of conductor layers 106 and 201.

[0092] An insulator layer 45 is provided on the first surfaces of the insulator layer 61 and the plurality of conductor layers 201. In the insulator layer 45, the plurality of conductor layers 202, 203, 204, 205, and 206, a portion of the conductor layer 207, a portion of the memory cell array 10, a portion of the plurality of contacts LI2, and a portion of the plurality of spacers SP2 are provided.

[0093] The memory cell array 10 is provided so that the conductive layer 34 is disposed on one side in the Z direction and the conductive layer 30A is disposed on the other side in the Z direction.

[0094] Conductor layer 202-1 is provided on a first surface of conductive layer 201-1. Conductor layer 203-1 is connected to the first surface of conductive layer 202-1. Conductor layer 204-1 is connected to the first surface of conductive layer 203-1. The first surface of conductive layer 204-1 is connected to conductive layer 34. With the above configuration, the bit line BL and transistor Tr1 can be connected.

[0095] A conductor layer 202-2 is provided on the first surface of the conductor layer 201-2. A conductor layer 203-2 is provided on the first surface of the conductor layer 202-2. A conductor layer 204-2 is provided on the first surface of the conductor layer 203-2. A conductor layer 205-1 is provided on the first surface of the conductor layer 204-2. A conductor layer 206-1 is provided on the first surface of the conductor layer 205-1. A conductor layer 207 is provided on the first surface of the conductor layer 206-1. The conductor layer 207 functions as, for example, a columnar contact. The conductor layer 207 penetrates the insulator layer 45 in the Z direction. The conductor layer 207 has, for example, a portion on the other side that protrudes from the insulator layer 45.

[0096] The conductor layer 37 is provided on the other side of the insulator layer 45. The conductor layer 37 functions as a wiring layer. The conductor layer 37 includes, for example, aluminum. In FIG. 8, the conductor layer 37 extends in the Y direction. The conductor layer 37 includes a portion in contact with the conductor layer 30A and a portion in contact with the conductor layer 207. With the above configuration, the source line SL and the transistor Tr2 can be connected. In the portion in contact with the conductor layer 207, the conductor layer 37 is provided, for example, so as to cover the portion of the conductor layer 207 on the other side that protrudes from the insulator layer 45. The conductor layer 37 also includes a portion exposed on the first surface of the semiconductor memory device 1. This portion functions, for example, as an electrode pad PD that is connected to an external device of the semiconductor memory device 1.

[0097] In a region other than the portion where the memory cell array 10 is provided, a conductor layer 30B is provided on the first surface of the insulator layer 45. The conductor layer 30B is included at the same height as the conductor layer 30A of the memory cell array 10. The conductor layer 30B is electrically insulated from the conductor layer 30A. An insulator layer 62 is provided inside the conductor layer 30B. In the following description, the portion of the conductor layer 30B included on one side of the insulator layer 62 is referred to as a conductor portion 30B-1. In the following description, the portion of the conductor layer 30B included on the other side of the insulator layer 62 is referred to as a conductor portion 30B-2. The conductor portion 30B-2 is made of, for example, an N-type semiconductor doped with impurities. The second surface of the conductor portion 30B-1 and the second surface of the conductor layer 30A are located at, for example, the same height as each other. The first surface of the conductor portion 30B-2 and the first surface of the conductor layer 30A are located, for example, at the same first height. The conductor layer 30B includes a portion that overlaps in the Z direction with an area where the plurality of conductor layers 208 are provided. In the portion that overlaps with the plurality of conductor layers 208 in the Z direction, the insulator layer 62 is divided by the conductor layer 30B. This dividing portion of the conductor layer 30B is referred to as the conductor portion 30B-3. The conductor portions 30B-1 and 30B-2 are electrically connected by the conductor portion 30B-3.

[0098] A plurality of conductor layers 208 are provided on the first surface of the conductor layer 30B so as to contact the conductor portion 30B-2 of the conductor layer 30B. The plurality of conductor layers 208 are, for example, composed of an N-type semiconductor doped with impurities, similar to the conductor portion 30B-2. The insulator layer 44 is provided on the first surfaces of the conductor layers 30A and 30B, excluding the portion of the conductor layer 30B where the plurality of conductor layers 208 are provided and the portion of the conductor layer 30A in contact with the conductor layer 37. The insulator layer 44 and the plurality of conductor layers 208 are provided at the same height. The first surface of each conductor layer 208 is configured to be flush with the first surface of the insulator layer 44. The second surface of each conductor layer 208 is configured to be flush with the second surface of the insulator layer 44. As described below, the plurality of conductor layers 208 function as an antistatic member for dissipating positive charges generated during the manufacturing process.

[0099] A conductor layer 202-3 is provided on the first surface of the conductor layer 201-3. A conductor layer 203-3 is provided on the first surface of the conductor layer 202-3. A conductor layer 204-3 is provided on the first surface of the conductor layer 203-3. A conductor layer 205-2 is provided on the first surface of the conductor layer 204-3. A conductor layer 206-2 is provided on the first surface of the conductor layer 205-2. A contact LI2-1 of the member W1 is provided on the first surface of the conductor layer 206-2. The contact LI2-1 penetrates the insulator layers 44, 45, and 62 and the conductor layer 30B in the Z direction. The first surface of the contact LI2-1 is configured to be flush with the first surface of the insulator layer 44. The second surface of the contact LI2-1 is located, for example, on one side of the second surface of the memory pillar MP. The second surface of the contact LI2-1 and the second surface of the member SLT are located, for example, at the same height. Although not shown, the contact LI2-1 extends in the X and Y directions so as to surround the circuit region CR, corresponding to the sealing portion ES1 in FIG. 3. A spacer SP2-1 is provided on a side surface of the contact LI2-1. The spacer SP2-1 is provided in a range excluding the other side of the contact LI2-1 in the Z direction. The configurations of the contact LI2 and the spacer SP2 will be described further below. The conductor layers 201-3, 202-3, 203-3, 204-3, 205-2, and 206-2, the contact LI2-1, and the spacer SP2-1, together with the conductor layers 101 and 102 connected to the P-type impurity diffusion region PW of the circuit chip 1-1, and the conductor layers 103-3, 104-3, 105-3, and 106-3, are formed in a ring-shaped pattern when viewed from above and function as the sealing portion ES1. Note that the contact LI2-1 may have a structure in which a first surface and a side surface of a metal-containing member are covered with a barrier metal, similar to the contact LI1.

[0100] A conductor layer 202-4 is provided on the first surface of the conductor layer 201-4. A conductor layer 203-4 is provided on the first surface of the conductor layer 202-4. A conductor layer 204-4 is provided on the first surface of the conductor layer 203-4. A conductor layer 205-3 is provided on the first surface of the conductor layer 204-4. A conductor layer 206-3 is provided on the first surface of the conductor layer 205-3. A contact LI2-2 of the member W2 is provided on the first surface of the conductor layer 206-3. The contact LI2-2 penetrates the insulator layers 44, 45, and 62 and the conductor layer 30B in the Z direction. The first surface of the contact LI2-2 is configured to be flush with the first surface of the insulator layer 44. The second surface of the contact LI2-2 is located at, for example, the same height as the second surface of the contact LI2-1. Although not shown, the contact LI2-2 extends in the X and Y directions to surround the circuit region CR, similar to the contact LI2-1. A spacer SP2-2 is provided on the side surface of the contact LI2-2. The spacer SP2-2 is provided in an area excluding the other side of the contact LI2-1. The conductive layers 201-4, 202-4, 203-4, 204-4, 205-3, and 206-3, the contact LI2-2, and the spacer SP2-2, together with the conductive layers 101 and 102 connected to the N-type impurity diffusion region NW of the circuit chip 1-1 and the conductive layers 103-4, 104-4, 105-4, and 106-4, form a ring-shaped pattern when viewed from above and function as the sealing portion ES2. The contact LI2-2 has, for example, the same structure as the contact LI2-1.

[0101] For example, a member 171 is provided on the first surfaces of the insulating layer 44, the plurality of contacts LI2, and the plurality of conductive layers 208. The member 171 is a portion of a semiconductor substrate that is used to form the memory chip 1-2 in the manufacturing process, as will be described later.

[0102] The insulator layer 46 is provided on the first surface of the member 171 to a height equivalent to that of the second surface of the conductor layer 37. The insulator layer 46 is provided so as to electrically insulate the conductor layers 37 and 30B. In Fig. 8, the insulator layer 46 is provided, for example, between the portion of the conductor layer 37 that contacts the conductor layer 207 and the conductor layer 30B as well as the insulator layers 44 and 62.

[0103] An insulator layer 47 is provided on the first surfaces of the conductor layer 37 and the insulator layer 46, except for the portions that function as the electrode pads PD. The insulator layer 47 functions as a passivation film. The insulator layer 47 includes, for example, silicon nitride or a resin material.

[0104] 8 shows the case where the semiconductor memory device 1 includes the member 171, but this is not limiting. The semiconductor memory device 1 does not have to include the member 171. That is, the semiconductor substrate used to form the memory chip 1-2 in the manufacturing process may be completely removed. In this case, the second surface of the insulator layer 46 contacts, for example, the first surface of the insulator layer 44, the first surfaces of the plurality of contacts LI2, and the first surfaces of the plurality of conductor layers 208.

[0105] 1.1.4.3.3 Sealing The configuration of the contact LI2 and spacer SP2 included in the sealing portion ES of the semiconductor memory device 1 will be further described with reference to Fig. 9. Fig. 9 is a cross-sectional view showing an example of the cross-sectional structure of the sealing portion and members of the semiconductor memory device according to the first embodiment. Fig. 9 shows the cross-sectional structure of the portion of the contact LI2 and spacer SP2 of the member W, along with the cross-sectional structure of the portion of the contact LI1 and spacer SP1 of the member SLT, in a cross section equivalent to that of Fig. 8.

[0106] The contact LI2 reaches the other side of the first surface of the conductor portion 30B-2 beyond the first height in the Z direction. The spacer SP2 covers the side surface of the contact LI2 so that the contact LI2 is connected to the conductor portion 30B-2. That is, the spacer SP2 covers the side surface of the contact LI2 from the second (fifth) height of the second surface of the contact LI2 to the third (sixth) height between the second surface of the conductor portion 30B-1 and the first surface of the conductor portion 30B-2. This electrically connects the contact LI2 and the conductor layer 30B to the other side of the other end of the spacer SP2 in the Z direction formed at the third height.

[0107] 1.1.4.3.4 Cross-sectional structure of connection pads The cross-sectional structure of the connection pad will be described with reference to Fig. 10. Fig. 10 is a cross-sectional view showing an example of the cross-sectional structure of the connection pad according to the first embodiment. Note that, although the following describes the portion where the conductor layer 106-1 and the conductor layer 201-1 are connected, the same applies to the portions where each of the other conductor layers 106 and the conductor layer 201 corresponding to that conductor layer 106 are connected.

[0108] On the bonding surface where the circuit chip 1-1 and the memory chip 1-2 are bonded together, the area of ​​the conductor layer 106-1 and the area of ​​the conductor layer 40-1 are, for example, equal. If the conductor layers 106-1 and 201-1 are copper, they may become integrated, making it difficult to identify the boundary between the copper layers. However, for example, the bonding can be confirmed by the distortion of the bonded shape of the conductor layers 106-1 and 201-1 due to misalignment during bonding. Furthermore, the bonding can be confirmed by the misalignment of the copper barrier metal, for example. That is, the bonding can be confirmed by the occurrence of discontinuities on the side surfaces.

[0109] Furthermore, when the conductive layers 106-1 and 201-1 are formed by the damascene method, their respective side surfaces have a tapered shape. As a result, the sidewalls of the conductive layers 106-1 and 201-1 are not linear. As a result, the cross section along the Z direction at the bonded portion of the conductive layers 106-1 and 201-1 is non-rectangular.

[0110] Furthermore, when the conductive layers 106-1 and 201-1 are bonded together, the first, second, and side surfaces of the copper that forms them are covered with a barrier metal. In contrast, in a typical wiring layer using copper, an insulating layer (such as silicon nitride or silicon carbide containing nitrogen) that functions to prevent oxidation of copper is provided on the top surface of the copper, and no barrier metal is provided. Therefore, even if there is no misalignment in the bonding, it is possible to distinguish it from a typical wiring layer.

[0111] 1.2 Manufacturing method of semiconductor memory device A method for manufacturing the semiconductor memory device 1 will be described with reference to Figures 11 to 21. Figures 11 to 21 are cross-sectional views for explaining an example of a method for manufacturing the semiconductor memory device according to the first embodiment. The cross-sectional views shown in Figures 11 to 21 show the region corresponding to Figure 8.

[0112] 11, the transistors Tr1 and Tr2 included in the peripheral circuit PERI, the plurality of conductor layers 101 to 106, and the insulator layers 48 and 60 are formed on the semiconductor substrate 70. That is, the circuit chip 1-1 is formed.

[0113] Next, parts of memory chip 1-2 are formed.

[0114] First, on the second surface of the semiconductor substrate 71 made of an impurity-doped P-type semiconductor, a plurality of conductor layers 208, a conductor layer 30 corresponding to conductor layers 30A and 30B, sacrificial layers Sc1 and Sc3 corresponding to conductor layers 31 and 33, a plurality of sacrificial layers Sc2 corresponding to the plurality of conductor layers 32, a sacrificial layer Sc4 provided in the same layer as the insulator layer 62 in the circuit region CR, insulator layers 40, 41, 43, 44, and 62, a plurality of insulator layers 42, a plurality of memory pillars MP, and a portion of the insulator layer 45 covering these are formed. In this process, the portion of the conductor layer 30 corresponding to the conductor layer 30A and the portion of the conductor layer 30 corresponding to the conductor layer 30B are electrically connected to each other. Then, a plurality of slits SH1 and SH2 are formed, as shown in FIG. 12 . More specifically, anisotropic etching is performed using a mask including openings corresponding to the plurality of members SLT and the plurality of members W, and the regions where the plurality of members SLT and the plurality of members W are to be formed are simultaneously removed. This forms multiple slits SH1 and SH2. The anisotropic etching is performed, for example, so that portions corresponding to the conductor portions 30B-2 remain in the regions overlapping with the openings corresponding to the multiple members W. The anisotropic etching in this process is, for example, RIE. Thereafter, the mask is removed.

[0115] In the above steps, most of the large amount of positive charges generated in the step of forming holes corresponding to the memory pillars MP and the step of forming the plurality of slits SH1 and SH2 are released to the semiconductor substrate 71, for example, via the conductive layers 30 and 208. This prevents arcing from occurring around the conductive layers 30A and 30B.

[0116] Then, as shown in FIG. 13, the sacrificial layers Sc1, Sc3, and Sc4 and the plurality of sacrificial layers Sc2 are replaced with the conductor layers 31, 33, conductors corresponding to the portions of the conductor layer 30A, and the plurality of conductor layers 32, respectively.

[0117] First, the sacrificial layer Sc4 is selectively removed through the multiple slits SH1 by, for example, wet etching using hot phosphoric acid. In this process, the wall surfaces within the multiple slits SH1 above the sacrificial layer Sc4 are protected from the wet etching by, for example, a protective film. Then, a portion of the stacked film 52 of each memory pillar MP is removed through the space where the sacrificial layer Sc4 was removed. Then, a conductor is embedded in the space where the sacrificial layer Sc4 was removed. This electrically connects the portion of the conductor layer 30 corresponding to the conductor layer 30A and the semiconductor film 51 of each memory pillar MP.

[0118] Further, for example, by wet etching using hot phosphoric acid, the sacrificial layers Sc1 and Sc3 and the plurality of sacrificial layers Sc2 are selectively removed through the plurality of slits SH1. In this process, the portion of the conductor layer 30 corresponding to the conductor layer 30A formed as described above is protected from the wet etching by, for example, a protective film. Then, a conductor is filled in the spaces where the sacrificial layers Sc1 and Sc3 and the plurality of sacrificial layers Sc2 have been removed. This results in the formation of conductor layers 31 and 33 and the plurality of conductor layers 32.

[0119] Then, as shown in FIG. 14, an insulating film SP corresponding to the spacer SP1 and a spacer SP2 are formed. More specifically, first, an insulating film SP corresponding to the spacers SP1 and SP2 is formed so as to cover the side surfaces and the first surface of the plurality of slits SH1 and SH2. Then, a mask MS1 is formed, the mask MS1 having openings in areas corresponding to the plurality of slits SH2. Then, the portions of the insulating film SP provided on the other side of the plurality of slits SH2, as well as the portions of the conductor layer 30 and the insulator layer 44 overlapping with these portions in the Z direction, are removed. This exposes portions of the semiconductor substrate 71 on the other side of the plurality of slits SH2. Furthermore, spacers SP2 are formed in the plurality of slits SH2.

[0120] Then, after the mask MS1 is removed, the portions of the insulating film SP provided on the other side of the plurality of slits SH1 are removed as shown in Fig. 15. This exposes the portions of the conductor layer 30A on the other side of the plurality of slits SH1. Also, spacers SP1 are formed in the plurality of slits SH1.

[0121] Next, as shown in FIG. 15, a plurality of members W and SLT are formed. More specifically, first, conductors corresponding to a plurality of contacts LI1 and LI2 are formed in a plurality of slits SH1 and SH2. Then, the conductors formed outside the plurality of slits SH1 and SH2 are removed by, for example, CMP (Chemical Mechanical Polishing). As a result, a plurality of members W and SLT are formed.

[0122] Next, as shown in FIG. 17 , for example, regions on the memory pillars MP where the plurality of conductor layers 35 are to be formed are collectively removed by anisotropic etching using a mask including openings corresponding to the plurality of conductor layers 35. The anisotropic etching in this process is, for example, RIE. In this process, positive charges generated by the anisotropic etching are released to the semiconductor substrate 71 via, for example, the semiconductor film 51 of the memory pillars MP, the conductor layer 30, and the plurality of members W. Thereafter, the conductor layers 35 are formed in the removed portions.

[0123] 18, the conductor layer 207, the plurality of conductor layers 34, 36, and 201 to 206, the portions of the insulator layer 45 that fill these, and the insulator layer 61 are formed. More specifically, the conductor layer 207 and the plurality of conductor layers 34, 36, and 201 to 206 are each formed by anisotropic etching using a mask, similar to the plurality of conductor layers 35. In the step of forming the plurality of conductor layers 34, 36, and 201 to 206, positive charges generated by the anisotropic etching are released to the semiconductor substrate 71 via, for example, the conductor layer 35, the semiconductor film 51 of the memory pillar MP, the conductor layer 30, and the plurality of members W.

[0124] Through the above steps, the memory chip 1-2 portion is formed.

[0125] Then, portions of the circuit chip 1-1 and the memory chip 1-2 are bonded together by a bonding process. More specifically, a plurality of conductor layers 106 functioning as connection pads on the circuit chip 1-1 and a plurality of conductor layers 201 functioning as connection pads on the memory chip 1-2 are arranged to face each other. The facing connection pads are then bonded to each other by heat treatment. Thereafter, at least a portion of the semiconductor substrate 71 is removed by, for example, CMP. The portion of the semiconductor substrate 71 not removed by CMP is designated as the member 171. As shown in FIG. 18 , for example, in the region surrounding the conductor layer 207, portions of the conductor layer 30, the insulator layer 62, the insulator layer 44, and the member 171 are removed. This exposes a portion of the first surface of the insulator layer 45. The conductor layer 30 is then divided into conductor layers 30A and 30B. This electrically insulates the conductor layers 30A and 30B from each other.

[0126] Next, as shown in FIG. 20, the insulating layer 46 is formed, for example, on the first surface of the member 171, on the exposed portion of the first surface of the insulating layer 45, and on the first surface of the conductive layer 207.

[0127] Then, as shown in FIG. 21, the portions of the insulating layer 46 where the conductive layer 37 is connected to the conductive layer 30A and the conductive layer 207 are removed by, for example, processing using lithography and etching.

[0128] Then, a conductive layer 37 and an insulating layer 47 are formed.

[0129] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0130] It should be noted that the manufacturing process described above is merely an example, and other processes may be inserted between the respective manufacturing processes, or the order of the manufacturing processes may be changed. For example, since the circuit chip 1-1 and the memory chip 1-2 portions are formed using different semiconductor substrates 70 and 71, the process of forming the circuit chip 1-1 shown in Fig. 11 and the process of forming the memory chip 1-2 portions shown in Figs. 12 to 18 may be carried out in parallel.

[0131] 1.3 Effects According to the embodiment, it is possible to suppress a decrease in yield of the semiconductor memory device 1. The effects of the embodiment will be described below.

[0132] According to the embodiment, the semiconductor memory device 1 includes a semiconductor substrate 70, a memory cell array 10, a member W, and a conductor portion 30B-2. The semiconductor substrate 70 has a circuit region CR and a wall region WR surrounding the circuit region CR. The memory cell array 10 is provided in the circuit region CR. The conductor portion 30B-2 is included in the same layer as the source lines SL, and its first surface has a first height equal to that of the first surfaces of the source lines SL. The conductor portion 30B-2 is electrically insulated from the source lines SL. The member W includes a contact LI2 and a spacer SP2. The contact LI2 is spaced apart from the word lines WL and is provided to surround the word lines WL. The contact LI2 extends in the Z direction over a range at least equal to the height of the word lines WL. The contact LI2 reaches the other side of the first height of the first surface of the conductor portion 30B-2 in the Z direction. The contact LI2 is integrally provided along the Z direction. The spacer SP2 covers the side surface of the contact LI2 from the second height on the second surface of the contact LI2 to the third height on one side of the first surface of the contact LI2. With the above-described configuration, for example, in the memory chip 1-2, it is possible to suppress the occurrence of defects due to dissolution of conductors such as electrodes provided on one side of the conductor layer 35. Therefore, it is possible to suppress a decrease in the yield of the semiconductor memory device 1.

[0133] Additionally, during the manufacturing process of a semiconductor memory device, when holes for forming contacts and wiring are formed by anisotropic etching, positive charges may accumulate at the bottom of the holes. This may cause conductors formed near the holes to become positively charged. In such cases, the conductors may dissolve. For example, in a configuration in which a circuit chip and a memory chip are bonded together, if the sealing portion included in the memory chip is located lower than the first surface of the source line, the contacts and wiring on one side of the memory pillar may become positively charged. That is, when forming the memory chip portion before bonding the circuit chip and the memory chip, the positive charges generated during the process of forming these contacts and wiring may not be able to dissipate to the semiconductor substrate by the antistatic member. Therefore, in the above case, the contacts and wiring on one side of the memory pillar may dissolve.

[0134] According to the first embodiment, when forming the memory chip 1-2 portion before bonding the circuit chip 1-1 and the memory chip 1-2, positive charges generated in the process of forming contacts and wiring on one side of the memory pillar MP are released to the semiconductor substrate 71 via the contact LI2 of the member W, as shown in FIG. 17. This prevents the contacts and wiring on one side of the memory pillar MP from becoming positively charged. This makes it possible to prevent defects from occurring in the semiconductor memory device 1.

[0135] 2. Modification of the First Embodiment The first embodiment described above can be modified in various ways, and semiconductor memory devices according to modifications of the first embodiment will be described below.

[0136] 2.1 First Modification of the First Embodiment In the first embodiment described above, the contacts LI2 of the member W penetrate the insulator layer 44 over the entire region where each sealing portion ES is provided, but this is not limited to this. In each sealing portion ES, the contacts LI2 of the member W may include a portion that does not penetrate the insulator layer 44. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the first modification of the first embodiment will be described, focusing on the differences from the configuration and manufacturing method of the semiconductor memory device according to the first embodiment.

[0137] The configuration of a semiconductor memory device 1 according to a first modification of the first embodiment will be described with reference to Figures 22 and 23. Figure 22 is a plan view showing an example of a planar layout of the semiconductor memory device according to the first modification of the first embodiment. Figure 23 is a cross-sectional view taken along line XXIII-XXIII in Figure 22, showing an example of a cross-sectional structure of the sealing part of the semiconductor memory device according to the first modification of the first embodiment.

[0138] 22, in the semiconductor memory device 1 according to the first modification of the first embodiment, each sealing portion ES is divided into a plurality of regions ES_A and ES_B. In addition, in each sealing portion ES, the plurality of regions ES_A and ES_B are, for example, arranged alternately. That is, the plurality of regions ES_A and ES_B are each provided intermittently so as to surround the circuit region CR.

[0139] FIG. 23 shows the structure of the other side of the sealing portion ES1 in the region ES_A and the structure of the other side of the sealing portion ES2 in the region ES_B.

[0140] The structure of the sealing portion ES in the region ES_A is equivalent to the structure of the sealing portion ES in the first embodiment. That is, the contact LI2 in the region ES_A reaches the other side in the Z direction beyond the first height of the first surface of the conductor portion 30B-2.

[0141] In region ES_B, the structure of the spacer SP2 is equivalent to the structure of the spacer SP2 in region ES_A. The height of the first surface of the contact LI2 in region ES_B is lower than the second surface of the insulator layer 44. That is, the contact LI2 in region ES_B is provided exclusively on one side in the Z direction of the first height of the first surface of the conductor portion 30B-2. The height of the first surface of the contact LI2 in region ES_B is, for example, equivalent to the height of the first surface of the spacer SP2.

[0142] With the above configuration, the semiconductor memory device 1 includes a portion of the contact LI2 that penetrates the insulator layer 44 in the region ES_A, and a portion of the contact LI2 that has a first surface that is lower than the second surface of the insulator layer 44 in the region ES_B.

[0143] 14 of the first embodiment, the manufacturing method of the semiconductor memory device 1 according to the first modification of the first embodiment is substantially the same as that of the first modification of the first embodiment, except that the shape of the mask MS1 is different. In the first modification of the first embodiment, for example, while leaving the portions of the insulating film SP provided on the other side of the portions of the plurality of slits SH2 corresponding to the region ES_B, the portions of the insulating film SP provided on the other side of the portions of the plurality of slits SH2 corresponding to the region ES_A, as well as the portions of the conductor layer 30B and the insulator layer 44 overlapping with the portions in the Z direction, are removed. Also, in the step corresponding to FIG. 15 of the first embodiment, in addition to removing the portions of the insulating film SP provided on the other side of the portions of the plurality of slits SH1, for example, the portions of the insulating film SP provided on the other side of the portions of the plurality of slits SH2 corresponding to the region ES_B are removed.

[0144] The first modification of the first embodiment also provides the same effects as the first embodiment.

[0145] 2.2 Second Modification of the First Embodiment In the above-described first embodiment, the case where the contact LI2 of the member W is surrounded by the insulator layer 44 and the member 171 at one end on the other side of each sealing portion ES has been described, but this is not limiting. At one end on the other side of each sealing portion ES, the contact LI2 of the member W may be configured to contact, for example, a conductive layer. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the second modification of the first embodiment will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the first embodiment.

[0146] The configuration of a semiconductor memory device 1 according to a second modified example of the first embodiment will be described with reference to FIG. 24. FIG. 24 is a cross-sectional view showing an example of the cross-sectional structure in the circuit region and the wall region of a semiconductor memory device according to the second modified example of the first embodiment. FIG. 24 shows three members W in the sealing portion ES, which differ from the semiconductor memory device according to the first embodiment in the structure of the spacer SP2 and the structure around the periphery of the contact LI2. Note that the second modified example of the first embodiment shows an example in which the semiconductor substrate 71 is completely removed in the manufacturing process, and therefore the member 171 is not provided.

[0147] In a second modification of the first embodiment, the semiconductor memory device 1 further includes a sealing portion ES3. That is, the semiconductor memory device 1 includes three sealing portions ES in the wall region WR. The sealing portion ES3 includes a member W3. The member W3 includes contacts LI2-3 and spacers SP2-3 as the contact LI2 and the spacer SP2, respectively. The semiconductor memory device 1 also includes a conductive layer 38. Note that the contacts LI2-3 are electrically connected to the semiconductor substrate 70, for example, in a region not shown.

[0148] The conductive layer 38 connects, for example, contacts LI2-1, LI2-2, and LI2-3 included in the members W1, W2, and W3, respectively.

[0149] The contact LI2-1 of the member W1 is surrounded by the conductor layer 38 at a height equivalent to that of the insulator layer 44. The structure of the member W1 on one side of the insulator layer 44 in the Z direction is equivalent to the structure of the member W1 on one side of the insulator layer 44 in the first embodiment. The portion of the member W1 on one side of the second surface of the insulator layer 44 in the Z direction is surrounded by the conductor layer 30B and the insulator layer 62.

[0150] The other side portion of the member W2 is surrounded by the conductive layer 38 over a height equal to that of the insulator layers 44 and 62 and the conductive layer 30B. For example, the other side portion of the side surface of the contact LI2-2 that is not covered by the spacer SP2-2 that forms the other end near the height position of the first surface of the insulator layer 45 in the Z direction is surrounded by the conductive layer 38. In the portion surrounding the member W2, the conductive layer 38 may reach one side in the Z direction from the second surface of the conductive layer 30B. For example, in the portion surrounding the member W2, the conductive layer 38 may be provided so that the second surface of the conductive layer 38 is at the same height as the second surface of the conductive layer 37 around the conductive layer 207. The spacer SP2-2 is provided on the side surface of the contact LI2-2 from the second height of the second surface of the contact LI2-2 to the height of the second surface of the conductive layer 38 in the portion surrounding the member W2.

[0151] The other side portion of the member W3, for example, at a portion of its periphery, contacts the conductor layer 38, the conductor layer 30B, and the insulator layer 62, similar to the member W1. Similarly to the member W2, the other side portion of the member W3, for example, at another portion of its periphery, contacts the conductor layer 38 at a height equal to the insulator layers 44 and 62 and the conductor layer 30B. In the portion surrounding the member W3, the second surface of the conductor layer 38 may have a different height. More specifically, for example, in the portion surrounding the member W3, the conductor layer 38 is provided so that at least a first portion of the second surface of the conductor layer 38 is at the same height as the second surface of the conductor layer 37 around the conductor layer 207. Furthermore, for example, in the portion surrounding the member W3, the conductor layer 38 is provided so that a second portion of the second surface of the conductor layer 38, different from the first portion, is at the same height as the second surface of the conductor layer 38 in the portion surrounding the member W1. In a portion overlapping with the first portion in the Z direction, the spacer SP2-3 is provided on the side surface of the contact LI2-3 from the second height of the second surface of the contact LI2-3 to the height of the second surface of the conductor layer 38. In addition, in a portion overlapping with the second portion in the Z direction, the spacer SP2-3 is provided in the same manner as the spacer SP2-1.

[0152] 19 to 21 of the first embodiment, the manufacturing method of the semiconductor memory device 1 according to the second modification of the first embodiment is substantially the same except that the portions removed in the steps corresponding to those in Figures 19 to 21 of the first embodiment are different and a conductive layer 38 is formed. In the steps corresponding to those in Figures 19 and 21 of the first embodiment, the portions on the other side of the spacer SP2-2 of the member W2 and the spacer SP2-3 of the member W3 are removed, thereby forming the above-described structures of the spacer SP2-2 and the spacer SP2-3.

[0153] The second modification of the first embodiment also achieves the same effects as the first embodiment. In the second modification of the first embodiment, the multiple sealing portions ES are formed of members W1, W2, and W3, each having a different structure, but this is not limiting. For example, the multiple sealing portions ES may be formed of one or two of the three members W1, W2, and W3 shown in FIG. 24, or may be formed by combining the members W in the first embodiment and the second modification of the first embodiment.

[0154] 2.3 Third Modification of the First Embodiment In the third modified example of the first embodiment, the member W is manufactured by a process different from that of the first embodiment. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the third modified example of the first embodiment will be described, focusing on the differences from the configuration and manufacturing method of the semiconductor memory device according to the first embodiment.

[0155] The configuration of a semiconductor memory device 1 according to a third modification of the first embodiment will be described with reference to Fig. 25. Fig. 25 is a cross-sectional view showing an example of the cross-sectional structure of the sealing part of the semiconductor memory device according to the third modification of the first embodiment.

[0156] The portion of the contact LI2 provided on the other side of the spacer SP2 of each sealing portion ES may have a portion wider than the width D1 between the portion on one side of the spacer SP2 in the Y direction and the portion on the other side of the spacer SP2 in the Y direction in the YZ cross section. Of the portion of the contact LI2 provided on the other side of the spacer SP2 of each sealing portion ES, the width D2 of the contact LI2 on the most one side in the Z direction is, for example, wider than the width D1. Also, although not shown, each sealing portion ES may have a similar structure in the XZ cross section.

[0157] A method for manufacturing the semiconductor memory device 1 according to the third modified example of the first embodiment will be described with reference to Figures 26, 27, 28, and 29. Figures 26 to 29 are cross-sectional views for explaining an example of the method for manufacturing the semiconductor memory device according to the third modified example of the first embodiment.

[0158] In the third modification of the first embodiment, steps similar to those described with reference to FIGS. 12 and 13 are performed.

[0159] Furthermore, for example, by anisotropic etching using a mask including openings corresponding to the slits SH2, portions of the conductor layer 30B and the insulator layer 44 that overlap with the slits SH2 in the Z direction are removed. The anisotropic etching in this process is, for example, RIE. Thereafter, the mask is removed.

[0160] 26 and 27, for example, spacers SP3 and sacrificial materials S are formed in the other side portions of the plurality of slits SH2. The spacers SP3 and sacrificial materials S are formed to have the same height as the conductor portions 30B-2 and the insulator layer 44, for example.

[0161] Then, as shown in FIG. 28, after the spacers SP1 and SP2 are formed, the sacrificial material S in each slit SH2 is removed.

[0162] 29, the spacers SP3 in each slit SH2 are removed. The spacers SP3 are removed by, for example, CDE (Chemical Dry Etching).

[0163] The other steps are the same as those in the method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0164] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0165] The third modified example of the first embodiment also provides the same effects as the first embodiment.

[0166] 2.4 Fourth Modification of the First Embodiment In the first embodiment and the first to third modified examples of the first embodiment described above, the member W does not include a spacer in the same layer as the insulator layer 44, but this is not limiting. The member W may include a spacer in the same layer as the insulator layer 44. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the fourth modified example of the first embodiment will be described, focusing on differences from the configuration and manufacturing method of the semiconductor memory device according to the first embodiment.

[0167] The configuration of a semiconductor memory device 1 according to a fourth modification of the first embodiment will be described with reference to Fig. 30. Fig. 30 is a cross-sectional view showing an example of the cross-sectional structure of the sealing portion of the semiconductor memory device according to the fourth modification of the first embodiment. In Fig. 30, the cross-sectional structure of the contact LI2 and spacer SP2 portions of the member W is shown together with the cross-sectional structure of the contact LI1 and spacer SP1 portions of the member SLT.

[0168] The semiconductor memory device 1 according to the fourth modification of the first embodiment further includes a spacer SP4. The spacer SP4 is an insulator provided on the side of the contact LI2 on the other side of the spacer SP2, which is provided in the side of the contact LI2 of each sealing portion ES, excluding the portion on the other side of the contact LI2. The third height of the end of the other side of the spacer SP2 is equal to the fourth height of the first surface of the insulator layer 62 or is located on the other side of the fourth height. Furthermore, the outer diameter of the spacer SP4, as viewed in the Z direction, is, for example, smaller than the inner diameter of the spacer SP2. As a result, as shown by the dotted line in FIG. 30 , the contact LI2 is connected to the conductor portion 30B-2 between the spacer SP2 and the spacer SP4 along the Y direction. Although not shown, the contact LI2 is also connected to the conductor portion 30B-2 between the spacer SP2 and the spacer SP4 along the X direction.

[0169] The third height of the first surface at the other end of the spacer SP2 and the height of the second surface at one end of the spacer SP4 are, for example, approximately equal. In this case, even if the spacer SP2 and the spacer SP4 have a portion where they contact each other due to misalignment or the like, because they have a portion where the contact LI2 and the conductor portion 30B-2 are connected as described above, it is possible to distinguish the spacer SP2 from the spacer SP4, for example, by the other end of the spacer SP2.

[0170] A method for manufacturing the semiconductor memory device 1 according to the fourth modification of the first embodiment will be described with reference to Figure 31. Figure 31 is a cross-sectional view for explaining an example of the method for manufacturing the semiconductor memory device according to the fourth modification of the first embodiment.

[0171] In the fourth modified example of the first embodiment, steps similar to those described in Figures 26 to 28 for the third modified example of the first embodiment are performed. Note that in the fourth modified example of the first embodiment, an insulating film corresponding to the spacer SP4 is formed instead of the spacer SP3. Also, in the fourth modified example of the first embodiment, the spacers SP2 and SP4 are formed so that the contact LI2 and the conductor portion 30B-2 are connected between the spacer SP2 and the spacer SP4.

[0172] 31, anisotropic etching is performed using a mask including openings corresponding to the slits SH2 to remove portions of the insulator film corresponding to the spacers SP4 that are in contact with the semiconductor substrate 71. The anisotropic etching in this step is, for example, RIE. Thereafter, the mask is removed.

[0173] The other steps are the same as those in the method for manufacturing the semiconductor memory device 1 according to the third modification of the first embodiment.

[0174] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0175] The fourth modified example of the first embodiment also provides the same effects as the first embodiment.

[0176] 3 Second embodiment The semiconductor memory device according to the second embodiment will be described below. In the manufacturing process of the semiconductor memory device according to the second embodiment, instead of the contact LI2 of the member W contacting the semiconductor substrate 71 of the memory chip 1-2, the contact LI1 of the member SLT in the memory cell array 10 contacts the semiconductor substrate 71 of the memory chip 1-2. The following mainly describes the configuration and manufacturing method of the semiconductor memory device according to the second embodiment, focusing on the differences from the configuration and manufacturing method of the semiconductor memory device according to the first embodiment.

[0177] 3.1 Configuration The configuration of the semiconductor memory device 1 according to the second embodiment will be described below. The cross-sectional structure of the memory cell array 10 and the overall cross-sectional structure of the semiconductor memory device 1 will be described below.

[0178] First, the cross-sectional structure of the memory region MA of the memory cell array 10 will be described with reference to Fig. 32. Fig. 32 is a cross-sectional view showing an example of the cross-sectional structure of the memory cell array of the semiconductor memory device according to the second embodiment.

[0179] The contact LI1 of the semiconductor memory device 1 according to the second embodiment penetrates the conductor layer 30A and the insulator layer 44. The spacer SP1 covers the side surface of the contact LI1, for example, from the height of the second surface of the contact LI1 to the height on one side of the second surface of the insulator layer 44. This connects the contact LI1 to the conductor layer 30A.

[0180] Next, the overall cross-sectional structure of the semiconductor memory device 1 will be described with reference to Fig. 33. Fig. 33 is a cross-sectional view showing an example of the cross-sectional structure of the circuit region and wall region of the semiconductor memory device according to the second embodiment. Fig. 33 shows the cross-sectional structure of a portion of the semiconductor memory device 1 corresponding to Fig. 8.

[0181] In the memory chip 1-2, as described above, the contact LI1 penetrates the conductor layer 30A and the insulator layer 44. The first surface of the contact LI1 is provided so as to be flush with the first surface of the insulator layer 44. As a result, as shown in FIG. 33 , the first surface of the contact LI1 contacts the member 171. Note that if the semiconductor memory device 1 does not include the member 171, the first surface of the contact LI1 contacts, for example, the second surface of the insulator layer 46.

[0182] 3.2 Manufacturing method of semiconductor memory device A method for manufacturing the semiconductor memory device 1 according to the second embodiment will be described with reference to Figures 34 and 35. Figures 34 and 35 are cross-sectional views for explaining an example of the method for manufacturing the semiconductor memory device according to the second embodiment. The cross-sectional views shown in Figures 34 and 35 show the region corresponding to Figure 33.

[0183] In the second embodiment, steps similar to those of the first embodiment described with reference to FIGS. 12 and 13 are carried out.

[0184] Furthermore, in a process corresponding to the process of the first embodiment described with reference to FIG. 14, an insulating film SP corresponding to the spacer SP2 and a spacer SP1 are formed as shown in FIG. 34. More specifically, first, an insulating film SP corresponding to the spacers SP1 and SP2 is formed so as to cover the side surfaces and first surface of the plurality of slits SH1 and SH2. Then, a mask MS2 is formed, the mask MS2 having openings in areas corresponding to the plurality of slits SH1. Then, the portions of the insulating film SP provided on the other side of the plurality of slits SH1, as well as the portions of the conductor layer 30A and the insulator layer 44 overlapping with the portions in the Z direction, are removed. This exposes portions of the semiconductor substrate 71 on the other side of the plurality of slits SH1. Furthermore, spacers SP1 are formed within the plurality of slits SH1.

[0185] After the mask MS2 is removed, the portions of the insulating film SP on the other side of the slits SH2 are removed, thereby exposing the portions of the conductive layer 30B on the other side of the slits SH2. Also, spacers SP2 are formed in the slits SH2.

[0186] Then, a plurality of contacts LI1 and LI2 are formed by the same process as the process of the first embodiment described with reference to Fig. 16. As a result, a plurality of members W and SLT are formed.

[0187] 17, regions on the memory pillar MP where the plurality of conductor layers 35 are to be formed are collectively removed by anisotropic etching using a mask including openings corresponding to the plurality of conductor layers 35, as shown in Fig. 35. In the second embodiment, in this step, positive charges generated by anisotropic etching are released to the semiconductor substrate 71 via, for example, the semiconductor film 51 of the memory pillar MP, the conductor layer 30A, and the plurality of members SLT.

[0188] The other steps are the same as those in the method for manufacturing the semiconductor memory device 1 according to the first embodiment.

[0189] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0190] The second embodiment also provides the same effects as the first embodiment.

[0191] 4. Modification of the Second Embodiment The second embodiment described above can be modified in various ways, and semiconductor memory devices according to modifications of the second embodiment will be described below.

[0192] In the second embodiment described above, the case where the contact LI1 formed integrally along the Z direction contacts the semiconductor substrate 71 in the manufacturing process has been described, but this is not limiting. The member SLT may include, for example, a component different from the portion of the contact LI1 made of a material containing metal, at the same height as the insulator layer 44. Then, in the manufacturing process, the portion of the contact LI1 may contact the semiconductor substrate 71 via this component. Below, the configuration and manufacturing method of the semiconductor memory device 1 according to the modified example of the second embodiment will be described, focusing on the differences from the configuration and manufacturing method of the semiconductor memory device according to the second embodiment.

[0193] The configuration of a semiconductor memory device 1 according to a modification of the second embodiment will be described below. The cross-sectional structure of the memory cell array 10 and the overall cross-sectional structure of the semiconductor memory device 1 will be described below with reference to FIGS.

[0194] Fig. 36 is a cross-sectional view showing an example of the cross-sectional structure of a memory cell array of a semiconductor memory device according to a modification of the second embodiment. Fig. 37 is a cross-sectional view showing an example of the cross-sectional structure of a circuit region and a wall region of a semiconductor memory device according to a modification of the second embodiment. Fig. 37 shows the cross-sectional structure of a portion of the semiconductor memory device 1 corresponding to Figs. 8 and 33.

[0195] In a modification of the second embodiment, the first surface of the contact LI1 is located between the first surface and the second surface of the insulator layer 44. However, without being limited to this, the first surface of the contact LI1 may be located on one side in the Z direction of the second surface of the insulator layer 44 as long as sufficient conduction is obtained between the portion of the contact LI1 and the conductor layer 30A.

[0196] The member SLT further includes a contact portion BE. The contact portion BE is included in, for example, the same layer as the insulator layer 44. The first surface of the contact portion BE is provided so as to be flush with the first surface of the insulator layer 44. As a result, the contact portion BE contacts, for example, the member 171. Note that if the semiconductor memory device 1 does not include the member 171, the first surface of the contact portion BE contacts, for example, the second surface of the insulator layer 46. The second surface of the contact portion BE contacts the first surface of the contact LI1. The contact portion BE is, for example, a silicon layer. The contact portion BE is, for example, an epitaxial layer. The contact portion BE is formed by epitaxial growth on the second surface of the semiconductor substrate 71, as will be described later.

[0197] Next, a method for manufacturing the semiconductor memory device 1 according to the modified example of the second embodiment will be described with reference to Figures 38 and 39. Figures 38 and 39 are cross-sectional views for explaining an example of the method for manufacturing the semiconductor memory device according to the modified example of the second embodiment.

[0198] After the process of the second embodiment described with reference to FIG. 34 is performed and the mask MS2 is removed, but before the contacts LI1 and LI2 are formed, a protective film F is formed on the portion of the conductive layer 30A exposed in the slit SH1, as shown in FIG. 38. The protective film F is, for example, an oxide film formed by oxidizing the conductive layer 30A. This prevents an epitaxial layer from being formed on the conductive layer 30A.

[0199] Next, as shown in FIG. 39, contact portions BE are formed by epitaxial growth on the second surface of the semiconductor substrate 71.

[0200] Then, after the protective film F and the portion of the insulating film SP provided on the other side of the plurality of slits SH2 are removed, the plurality of contacts LI1 and LI2 are formed, thereby forming the plurality of members W and SLT.

[0201] The other steps are the same as those in the method for manufacturing the semiconductor memory device 1 according to the second embodiment.

[0202] Through the manufacturing process described above, the semiconductor memory device 1 is formed.

[0203] The modified example of the second embodiment also provides the same effects as the first embodiment.

[0204] Furthermore, according to a modification of the second embodiment, the semiconductor memory device 1 has a contact portion BE provided in contact with the first surface of the contact LI1. This prevents the contact LI1 from being ground, thereby suppressing the occurrence of scratches. Furthermore, by forming the contact portion BE between the contact LI1 and the semiconductor substrate 71 in the manufacturing process, when at least a portion of the semiconductor substrate 71 is removed by CMP after the circuit chip 1-1 and the memory chip 1-2 are bonded together, the contact LI1 is prevented from being partially removed along with the semiconductor substrate 71. Therefore, the contact LI1, which tends to be scratched by polishing such as CMP, is not polished, and the occurrence of scratches on the polished surface is suppressed.

[0205] 5. Other In the above-described first embodiment and the first to fourth modified examples of the first embodiment, the member W includes only the contact LI2 as a conductor, but this is not limited to this. For example, as in the modified example of the second embodiment, a configuration similar to the contact portion BE may be provided on the surface of the contact LI2 on the other side in the Z direction. That is, the member W may include a silicon layer such as an epitaxial layer. Furthermore, various combinations may be made in the first embodiment, the first to fourth modified examples of the first embodiment, the second embodiment, and the modified example of the second embodiment without departing from the spirit of the invention.

[0206] In the above-described first embodiment, the first to fourth modifications of the first embodiment, the second embodiment, and the modification of the second embodiment, the semiconductor memory device has a structure in which a circuit chip and a memory chip are bonded together, but this is not limited thereto. The semiconductor memory device may be formed, for example, from a single chip. Below, configurations of semiconductor memory devices according to other embodiments that differ from those of the first embodiment, the first to fourth modifications of the first embodiment, the second embodiment, and the modification of the second embodiment will be described.

[0207] The planar layout of a semiconductor memory device 1 according to another embodiment will be described with reference to FIG. 40. FIG. 40 is a plan view showing an example of the planar layout of a semiconductor memory device according to another embodiment. As described above, the semiconductor memory device according to another embodiment is formed by one chip. Hereinafter, the direction from the semiconductor substrate toward the memory cell array will be referred to as the upward direction. Also, the direction from the memory cell array toward the semiconductor substrate will be referred to as the downward direction.

[0208] A semiconductor memory device 1 according to another embodiment includes a circuit region CR, a contact region C3T, a wall region WR, and a kerf region KR. In another embodiment, the wall region WR is provided with sealing portions ES4 and ES5. The sealing portions ES4 and ES5 correspond to the sealing portions ES1 and ES2 of the first embodiment.

[0209] The contact region C3T is a region between the circuit region CR and the wall region WR. In the contact region C3T, for example, contacts for connecting the memory cell array 10 and the peripheral circuit PERI are arranged.

[0210] Furthermore, one or more bridge regions BR are provided in the contact region C3T. Each bridge region BR is provided with, for example, a wall region WR and a conductive layer that is included in the same layer as the source line SL. In FIG. 40, the area where the conductive layer and the source line SL are provided is indicated by diagonal lines.

[0211] Furthermore, the semiconductor memory device 1 according to the other embodiment further includes a separating portion KC. The separating portion KC separates the source line SL from the conductive layer included in the same layer as the source line SL in each bridge region BR. This electrically insulates the source line SL from the conductive layer in the wall region WR.

[0212] Next, the structure of a semiconductor memory device 1 according to another embodiment will be described with reference to Fig. 41. Fig. 41 is a cross-sectional view taken along line XLI-XLI in Fig. 40, showing an example of the cross-sectional structure of the circuit region and wall region of a semiconductor memory device according to another embodiment.

[0213] The semiconductor memory device 1 further includes a semiconductor substrate 70A, conductive layers 130A, 130B, 131, and 133, a plurality of conductive layers 132, 134, 135, 136, and 208A, insulator layers 140, 141, 143, 144, 145, and 162, and a plurality of insulator layers 142. The conductive layers 130A, 130B, 131, and 133, the plurality of conductive layers 132, 134, 135, and 136, the insulator layers 140, 141, 143, 145, and 162, and the plurality of insulator layers 142 correspond to the conductive layers 30A, 30B, 31, and 33, the plurality of conductive layers 32, 34, 35, and 36, the insulator layers 40, 41, 43, 45, and 62, and the plurality of insulator layers 42, respectively. The memory cell array 10 according to the other embodiment has substantially the same structure as the memory cell array according to the first embodiment.

[0214] An insulator layer 144 is provided on the upper surface of the semiconductor substrate 70A. A conductor layer 208A and a peripheral circuit PERI (not shown) are provided in the same layer as the insulator layer 144. The peripheral circuit PERI is provided in the circuit region CR. The conductor layer 208A penetrates the insulator layer 144 in the Z direction. The conductor layer 208A corresponds to the conductor layer 208.

[0215] The memory cell array 10 and the conductor layer 130B are provided on the upper surfaces of the insulating layer 144 and the conductor layer 208A. The memory cell array 10 is provided in the circuit region CR so that the conductor layer 130A (source line SL) is lower than the conductor layer 134 (bit line BL). The conductor layer 130B is provided in the same layer as the conductor layer 130A. An insulating layer 162 is provided in the same layer as the conductor layer 130B. A portion of the conductor layer 130B above the upper surface of the insulating layer 162 is referred to as a conductor portion 130B-1. A portion of the conductor layer 130B below the lower surface of the insulating layer 162 is referred to as a conductor portion 130B-2. The conductor layer 130B includes a portion that overlaps in the Z direction with a region where multiple conductor layers 208A are provided. In the portion where the insulating layer 162 overlaps with the plurality of conductor layers 208A in the Z direction, the insulating layer 162 is divided by a conductor portion 130B-3 that corresponds to the conductor portion 30B-3 in the first embodiment. The conductor portions 130B-1 and 130B-2 are electrically connected by the conductor portion 130B-3.

[0216] In another embodiment, each of the plurality of conductive layers 208A is composed of conductive layers 208A-1, 208A-2, 208A-3, 208A-4, 208A-5, and 208A-6. Each of the conductive layers 208A-1 to 208A-6 functions as, for example, an annular contact or wiring.

[0217] The encapsulating unit ES4 includes a contact LI2-4 and a spacer SP2-4 as the contact LI2 and the spacer SP2, respectively. The encapsulating unit ES5 includes a contact LI2-5 and a spacer SP2-5 as the contact LI2 and the spacer SP2, respectively. The lower surface of the contact LI2-4 contacts, for example, an N-type impurity diffusion region NW provided in the semiconductor substrate 70A. The lower surface of the contact LI2-5 contacts, for example, a P-type impurity diffusion region PW provided in the semiconductor substrate 70A. Each spacer SP2 is provided so as to cover the side surface of the portion of the contact LI2 corresponding to the spacer SP2. The spacer SP2 is included, for example, above the lower surface of the conductor portion 130B-2. As a result, each contact LI2 is connected to the conductor layer 130B. In each encapsulating unit ES, wiring and contacts may be provided on the upper surface of the contact LI2. In FIG. 41, in each sealing portion ES, a wiring M0, a contact V0, a ​​wiring M1, a contact V1, and a wiring M2 are provided in this order from bottom to top.

[0218] The dividing portion KC includes, for example, a conductor layer 150, a contact LI3, and a spacer SP5. The conductor layer 150 is included, for example, in the insulator layer 144. The contact LI3 is provided on the insulator layer 144. The contact LI3 is a conductor that penetrates the conductor layer 130B and the insulator layer 162. The spacer SP5 is an insulator that is provided so as to cover the side surface of the contact LI3. This electrically insulates the contact LI3 from the conductor layer 130B. Furthermore, with the above-described configuration, the dividing portion KC divides the conductor layer 130B from the insulator layer 162 in the bridge region BR. This electrically insulates the conductor layer 130A from the conductor layer 130B in the wall region WR.

[0219] Next, a method for manufacturing a semiconductor memory device 1 according to another embodiment will be described with reference to Figure 42. Figure 42 is a cross-sectional view for explaining an example of a method for manufacturing a semiconductor memory device according to another embodiment.

[0220] In a manufacturing process of a semiconductor memory device 1 according to another embodiment, insulator layers 144 and 145, a portion of the memory cell array 10, conductor layers 130B and 150, an insulator layer 162, a contact LI2, and a spacer SP2 are formed on a semiconductor substrate 70A. The portion of the memory cell array 10 includes conductor layers 130A, 131, and 133, a plurality of conductor layers 132, insulator layers 140 and 141, a plurality of insulator layers 142, a memory pillar MP, and a member SLT. Note that the contact LI2 and the spacer SP2 are formed by, for example, substantially the same process as the process described with reference to FIGS. 12 to 16 in the first embodiment. In this process, the conductor layer 130A and the conductor layer 130B in the wall region WR are electrically connected to each other.

[0221] 42, similar to the process described with reference to FIG. 17, regions on the memory pillars MP where the plurality of conductor layers 135 are to be formed are collectively removed by anisotropic etching using a mask including openings corresponding to the plurality of conductor layers 135. The anisotropic etching in this process is, for example, RIE. In this process, positive charges generated by the anisotropic etching are released to the semiconductor substrate 70A via, for example, the semiconductor film of the memory pillars MP, the conductor layers 130A and 130B, and the plurality of members W.

[0222] Then, for example, after forming the plurality of conductor layers 134-136, the contact LI3 and spacer SP5 of the dividing portion KC are formed. As a result, the conductor layer 130B is separated by the dividing portion KC. Furthermore, the conductor layer 130A and the conductor layer 130B of the wall region WR are electrically insulated from each other.

[0223] Even with this configuration, the same effects as those of the first embodiment can be achieved.

[0224] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, as well as within the scope of the invention described in the claims and their equivalents. [Explanation of symbols]

[0225] 1...semiconductor memory device, 2...memory controller, 3...memory system, 10...memory cell array, 11...command register, 12...address register, 13...sequencer, 14...driver module, 15...row decoder module, 16...sense amplifier module, BLK...block, SU...string unit, NS...NAND string, MT...memory cell transistor, ST1, ST2...select transistor, BL...bit line, WL...word line, SGS, SGD...select gate line, SHE...component.

Claims

1. a substrate having a first region and a second region provided so as to surround the periphery of the first region; a memory cell array provided in the first region; a first member provided in the second region; a first conductor portion disposed in the second region so as to intersect with the first member; Equipped with The memory cell array a source line provided above the substrate; a plurality of word lines provided above the substrate and on one side of the source line in a first direction intersecting the surface of the substrate, the word lines being spaced apart from each other in the first direction; a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the memory pillar having one end in the first direction connected to the source line; and the first conductor portion is included in the same layer as the source line, a surface on the other side in the first direction has the same height as a surface on the other side in the first direction of the source line, and is electrically insulated from the source line; The first member is a first contact that is spaced apart from the plurality of word lines, extends in the first direction to surround the plurality of word lines over at least an area equivalent to that of the plurality of word lines in the first direction, reaches the other side in the first direction from a first height of the surface on the other side of the first conductor portion, and is integrally provided along the first direction; a first insulating film covering a side surface of the first contact from a second height of one end of the first contact on the one side in the first direction to a third height from the other end of the first contact on the one side in the first direction, and forming an end on the other side in the first direction at the third height; Including, Semiconductor memory device.

2. the substrate is provided in a first chip; the memory cell array, the first member, and the first conductor portion are provided in a second chip that contacts the first chip in the first direction; The semiconductor device further includes a plurality of first connection pads provided in a boundary region between the first chip and the second chip.

2. The semiconductor memory device according to claim 1.

3. a first chip including a substrate; a second chip contacting the first chip in a first direction intersecting the surface of the substrate; Equipped with The second chip is a memory cell array including a source line, a plurality of word lines spaced apart from one another in the first direction below the source line, and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the upper end of which is connected to the source line; a first member extending within the plurality of word lines in a second direction within the surface of the substrate and dividing the plurality of word lines in a third direction within the surface of the substrate that intersects with the second direction; Including, The first member is a first contact extending in the first direction and including a portion located above the source line; a first insulating film provided to cover a side surface of the first contact from a height of a lower end of the first contact to a first height between an upper surface and a lower surface of the source line; Including, Semiconductor memory device.

4. the first contact includes a first portion and a second portion provided on the first portion and made of a different material than the first portion; the second portion is a silicon layer; 4. The semiconductor memory device according to claim 3.

5. a first chip including a substrate having a first region and a second region provided so as to surround the periphery of the first region; a second chip contacting the first chip in a first direction intersecting the surface of the substrate; Equipped with The second chip is a memory cell array in the first region, the memory pillars including: a source line; a plurality of word lines spaced apart from one another in the first direction below the source line; and a memory pillar extending in the first direction so as to intersect with the plurality of word lines, the memory pillars having upper ends connected to the source line; a first member including first contacts extending in the first direction over a range equal to that of the plurality of word lines; a first conductor portion included in the same layer as the source line, the first conductor portion having an upper surface at the same height as an upper surface of the source line, and the first conductor portion being electrically insulated from the source line; a second member provided in the second region on the outer periphery of the plurality of word lines and the first member in a direction parallel to the substrate, so as to surround the plurality of word lines when viewed from above, and in contact with an upper surface of the first conductor portion; Including, The first contact is a portion of the source line located above the top surface; Semiconductor memory device.

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