Transmitting device and semiconductor device

Abstract

To provide a transmitting device for generating an analog signal suitable for a receiving device, and a semiconductor device.SOLUTION: A transmitting device of one embodiment comprises: a digital processing circuit which generates an n-phase first digital signal and an n-phase second digital signal, which is phase-shifted from the first digital signal by a first phase, n being an integer of 2 or more; a delay circuit which generates an n-phase second clock signal phase-shifted from an n-phase first clock signal by a second phase; a first multiplexer which converts the first digital signal into a single-phase third digital signal on the basis of the first clock signal; a second multiplexer which converts the second digital signal into a single-phase fourth digital signal, which is phase-shifted from the third digital signal by the sum of the first and second phases on the basis of the second clock signal; and a first driver which outputs a composite signal of a first analog signal based on the third digital signal and a second analog signal based on the fourth digital signal. The second phase is greater than or equal to 0 and less than or equal to the first phase.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The embodiments relate to a transmitter and a semiconductor device. [Background technology]

[0002] The transmitting device and receiving device are connected via a transmission path. The transmitting device generates a digital signal on which data is superimposed. The transmitting device converts the digital signal into an analog signal. The transmitting device transmits the analog signal to the receiving device via the transmission path. The receiving device generates a digital signal based on the analog signal. The receiving device recovers data based on the generated digital signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2021-153231 Summary of the Invention [Problem to be solved by the invention]

[0004] A transmitting device and a semiconductor device are provided that generate an analog signal suitable for a receiving device. [Means for solving the problem]

[0005] A transmitter according to an embodiment includes a digital processing circuit that generates a first digital signal with n phases and a second digital signal with n phases that is shifted from the first digital signal by a first phase, where n is an integer greater than or equal to 2, a delay circuit that generates a second clock signal with n phases that is shifted from a first clock signal with n phases by a second phase, a first multiplexer that converts the first digital signal into a third digital signal with a single phase based on the first clock signal, a second multiplexer that converts the second digital signal into a fourth digital signal with a single phase that is shifted from the third digital signal by the sum of the first and second phases based on the second clock signal, and a first driver that outputs a composite signal of a first analog signal based on the third digital signal and a second analog signal based on the fourth digital signal, where the second phase is greater than or equal to 0 and less than the first phase. [Brief explanation of the drawings]

[0006] [Figure 1] FIG. 1 is a block diagram showing an example of the configuration of a transmission / reception system including a transmission device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device including a transmitting and receiving system according to an embodiment. [Figure 3] FIG. 1 is a block diagram showing an example of the configuration of a transmission device according to an embodiment. [Figure 4] FIG. 2 is a block diagram showing an example of the configuration of a feedforward equalizer included in the transmission device according to the embodiment. [Figure 5] FIG. 2 is a block diagram showing an example of the configuration of a buffer circuit included in the feedforward equalizer according to the embodiment. [Figure 6] FIG. 2 is a block diagram showing an example of the configuration of a delay circuit included in the feedforward equalizer according to the embodiment. [Figure 7] 4 is a timing chart showing an example of a generation operation of a signal Main in the transmission device according to the embodiment. [Figure 8] 6 is a timing chart showing an example of a generating operation of a signal Post in the transmitting device according to the embodiment. [Figure 9]FIG. 2 is a schematic diagram showing an example of the waveform of a signal TR output from a transmitting device according to the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0007] Hereinafter, embodiments will be described with reference to the drawings.

[0008] In the following description, components having substantially the same functions and configurations are denoted by the same reference numerals. When elements having similar configurations are to be particularly distinguished from one another, different letters or numbers may be added to the end of the same reference numerals.

[0009] 1. Configuration 1.1 Transmission and Reception System First, a configuration of a transmission / reception system including a transmission device according to an embodiment will be described. Fig. 1 is a block diagram showing an example of the configuration of a transmission / reception system including a transmission device according to an embodiment.

[0010] The transmission / reception system 1 is, for example, a transmission / reception system that realizes wired serial communication. The transmission / reception system 1 is configured to transmit data from one device or circuit to another device or circuit. Specifically, the transmission / reception system 1 includes a transmission device 2, a transmission path 3, and a reception device 4.

[0011] The transmitting device 2 is configured to transmit signals TR and / TR to the receiving device 4 via a transmission path 3. The signals TR and / TR are differential signals. The signals TR and / TR are, for example, signals including a plurality of pulse signals. Data is superimposed on each pulse signal of the signals TR and / TR. The voltage level of each pulse signal of the signals TR and / TR corresponds to one or more bits of data. The data superimposed on the pulse signals is transmitted from the transmitting device 2 to the receiving device 4 via the transmission path 3.

[0012] The transmission path 3 is a physical or spatial transmission medium for transmitting the signals TR and / TR to the receiving device 4. The transmission path 3 is, for example, a wiring that connects the transmitting device 2 and the receiving device 4. The transmission path 3 can have various transmission characteristics depending on the structure and material of the transmission medium. The transmission characteristics of the transmission path 3 include, for example, frequency characteristics that involve a loss of gain in a specific frequency band.

[0013] The signals TR and / TR transmitted by the transmitter 2 pass through the transmission path 3 and are subjected to loss according to the transmission characteristics of the transmission path 3. As a result, inter-symbol interference (ISI) occurs in the signals TR and / TR that have passed through the transmission path 3. For this reason, the signals TR and / TR that have passed through the transmission path 3 are processed as analog signals in the first-stage circuit of the receiver 4. Hereinafter, the signals TR and / TR that have passed through the transmission path 3 and suffered loss will be referred to as signals RV and / RV.

[0014] The receiving device 4 is configured to receive the signals RV and / RV from the transmitting device 2 via the transmission path 3. Based on the signals RV and / RV, the receiving device 4 decodes the data superimposed on the signals TR and / TR by the transmitting device 2. The receiving device 4 has a receiving circuit for correctly decoding the data superimposed on the signals TR and / TR.

[0015] 2 is a cross-sectional view showing an example of a cross-sectional structure of a semiconductor device including a transceiver system according to the embodiment. As shown in FIG. 2, the transceiver system 1 may be a semiconductor device including a wiring substrate 100, adhesive layers 101 and 103, semiconductor chips 102 and 104, pad electrodes 105, 106, and 107, wirings 108 and 109, bump electrodes 110, and a resin layer 111.

[0016] The wiring substrate 100 is, for example, a printed circuit board or an interposer made of glass epoxy resin. Pad electrodes 105 are provided on the upper surface of the wiring substrate 100. Bump electrodes 110 are provided on the lower surface of the wiring substrate 100.

[0017] A semiconductor chip 102 is provided on the upper surface of the wiring substrate 100 in an area that does not overlap with the pad electrodes 105, via an adhesive layer 101. For example, a receiving device 4 is formed on the semiconductor chip 102 as a semiconductor circuit. A pad electrode 106 is provided on the upper surface of the semiconductor chip 102. The pad electrodes 105 and 106 are electrically connected by, for example, a wiring 108. The wiring 108 is, for example, a bonding wire.

[0018] A semiconductor chip 104 is provided on the upper surface of the semiconductor chip 102 in an area that does not overlap with the pad electrodes 106, via an adhesive layer 103. For example, a transmitter 2 is formed as a semiconductor circuit on the semiconductor chip 104. A pad electrode 107 is provided on the upper surface of the semiconductor chip 104. The pad electrodes 106 and 107 are electrically connected by, for example, a wiring 109. The wiring 109 is, for example, a bonding wire that functions as a transmission path 3.

[0019] The resin layer 111 is a thermosetting resin, such as an epoxy resin or an acrylic resin, and seals the semiconductor chips 102 and 104, and also covers a portion of the wiring substrate 100.

[0020] 2, the transmitting and receiving system 1 is a semiconductor device configured by a plurality of semiconductor chips 102 and 104 provided on the same wiring board 100, but the present invention is not limited to this. For example, the transmitting device 2 and the receiving device 4 may be provided on different wiring boards.

[0021] 1.2 Transmitting equipment FIG. 3 is a block diagram illustrating an example of the configuration of the transmission device according to the embodiment.

[0022] The transmitting device 2 includes, for example, pads P1 and P2, a DSP 10, a CLKGEN 20, and an FFE 30.

[0023] Each of the pads P1 and P2 is a terminal connected to the transmission line 3. In the example of Fig. 3, the pads P1 and P2 of the transmitter 2 transmit signals TR and / TR to the transmission line 3, respectively.

[0024] The DSP 10 is a digital processing circuit. The DSP 10 generates signals Main<3:0> and / Main<3:0>, and signals Post<3:0> and / Post<3:0>. The DSP 10 outputs the signals Main<3:0> and / Main<3:0>, and signals Post<3:0> and / Post<3:0> to the FFE 30.

[0025] The signals Main<3:0> and / Main<3:0> are four-phase digital signals. Transmission data is superimposed on the signals Main<3:0> and / Main<3:0> in parallel at a cycle of 4 UI (unit interval). <1> and / Main <1> The phases of the signals are <0> and / Main <0> It is delayed by 1 UI. <2> and / Main <2> The phases of the signals are <1> and / Main <1> It is delayed by 1 UI. <3> and / Main <3> The phases of the signals are <2> and / Main <2> It is delayed by 1 UI. <0> and / Main <0> is a differential signal. <1> and / Main <1> is a differential signal. <2> and / Main <2> is a differential signal. <3> and / Main <3> is a differential signal.

[0026] The signals Post<3:0> and / Post<3:0> are four-phase digital signals. <1> and / Post <1> are differential signals, and the Main signal <0> and / Main <0> The signal Post is obtained by delaying the phase of <2> and / Post <2> are differential signals, and the Main signal <1> and / Main <1> The signal Post is obtained by delaying the phase of <3> and / Post <3> are differential signals, and the Main signal <2> and / Main <2> The signal Post is obtained by delaying the phase of <0> and / Post <0> are differential signals, and the Main signal <3> and / Main <3> is obtained by delaying the phase of by 1 UI.

[0027] The CLKGEN20 is a clock generation circuit. The CLKGEN20 generates the signals CLK000, CLK090, CLK180, and CLK270. The CLKGEN20 outputs the signals CLK000, CLK090, CLK180, and CLK270 to the FFE30.

[0028] The signals CLK000, CLK090, CLK180, and CLK270 are, for example, four-phase clock signals with a 4UI cycle. The signal CLK090 is delayed by 1UI relative to the signal CLK000. The signal CLK180 is delayed by 1UI relative to the signal CLK090. The signal CLK270 is delayed by 1UI relative to the signal CLK180. The signals CLK000, CLK090, CLK180, and CLK270 are respectively connected to the signal Main <0> and / Main <0> , Main <1> and / Main <1> , Main <2> and / Main <2> , and Main <3> and / Main <3> It is configured to start up at the timing when the data is confirmed.

[0029] The FFE30 is, for example, a feed forward equalizer. The FFE30 generates a signal TR based on the signals Main<3:0> and Post<3:0> and the signals CLK000, CLK090, CLK180, and CLK270. The FFE30 generates a signal / TR based on the signals / Main<3:0> and / Post<3:0> and the signals CLK000, CLK090, CLK180, and CLK270. The FFE30 outputs the signals TR and / TR to pads P1 and P2, respectively.

[0030] 1.3 Feedforward Equalizer Next, the internal configuration of a feedforward equalizer (FFE) included in the transmission device according to the embodiment will be described. Fig. 4 is a block diagram showing an example of the configuration of the feedforward equalizer included in the transmission device according to the embodiment.

[0031] The FFE 30 includes MUXes 31, 32, 33, and 34, a plurality of drivers 35, 36, 37, and 38, a BUF 40, and a DLY 60.

[0032] BUF40 is a buffer circuit. Signals CLK000, CLK090, CLK180, and CLK270 are input to BUF40 from CLKGEN20. BUF40 generates signals CKM000, CKM090, CKM180, and CKM270 based on signals CLK000, CLK090, CLK180, and CLK270, and outputs these signals to MUX31 and 33. The internal configuration of BUF40 will be described later.

[0033] The signals CKM000, CKM090, CKM180, and CKM270 are obtained by delaying the signals CLK000, CLK090, CLK180, and CLK270 by a predetermined phase, respectively. That is, the signals CKM000, CKM090, CKM180, and CKM270 are each a clock signal with a 4 UI period, and are shifted in phase by 1 UI in this order.

[0034] DLY60 is a delay circuit. Signals CLK000, CLK090, CLK180, and CLK270 are input to DLY60 from CLKGEN20. DLY60 generates signals CKD000, CKD090, CKD180, and CKD270 based on signals CLK000, CLK090, CLK180, and CLK270, and outputs these signals to MUX32 and 34. The internal configuration of DLY60 will be described later.

[0035] The signals CKD000, CKD090, CKD180, and CKD270 are obtained by further delaying the signals CKM000, CKM090, CKM180, and CKM270 by a phase Δ, respectively. That is, the signals CKD000, CKD090, CKD180, and CKD270 are each a clock signal with a 4 UI period, and are shifted in phase by 1 UI in this order. The phase Δ is preset to a predetermined value in the range of 0 to 1 UI (0≦Δ≦1 UI).

[0036] Each of MUX31 to 34 is a 4-to-1 multiplexer, and is configured to output data input in parallel from four signal lines in serial to one signal line using a clock signal as a trigger.

[0037] Specifically, the MUX 31 receives the signal Main<3:0> from the DSP 10. The MUX 31 receives the signals CKM000, CKM090, CKM180, and CKM270 from the BUF 40. The MUX 31 generates the signal Main from the signal Main<3:0> based on the signals CKM000, CKM090, CKM180, and CKM270. More specifically, the MUX 31 generates the signal Main in response to the rising edges of the signals CKM000, CKM090, CKM180, and CKM270. <0> , Main <1> , Main <2> , and Main <3> and outputs it as a single-phase signal Main. MUX 31 outputs signal Main to driver 35. Signal Main contains data obtained by serially converting data superimposed in parallel on signal Main<3:0>. Transmission data is superimposed serially on signal Main at a 1 UI cycle (i.e., 1 / 4 of the cycle of signal Main<3:0>).

[0038] The MUX 32 receives the signal Post<3:0> from the DSP 10. The MUX 32 receives the signals CKD000, CKD090, CKD180, and CKD270 from the DLY 60. The MUX 32 generates the signal Post from the signal Post<3:0> based on the signals CKD000, CKD090, CKD180, and CKD270. More specifically, the MUX 32 generates the signal Post in response to the rising edges of the signals CKD000, CKD090, CKD180, and CKD270. <0> , Post <1> , Post <2> , and Post <3> and outputs it as a single-phase signal Post. MUX 32 outputs signal Post to driver 36. Signal Post contains data obtained by serially converting data superimposed in parallel on signal Post<3:0>. Transmission data is serially superimposed on signal Post at a period of 1 UI (i.e., 1 / 4 of the period of signal Post<3:0>). Signal Post is output with an additional delay of a phase Δ with respect to signal Main. In other words, signal Post is output with a phase delay of (1 UI + Δ) with respect to signal Main.

[0039] The MUX 33 receives the signal / Main<3:0> from the DSP 10. The MUX 33 receives the signals CKM000, CKM090, CKM180, and CKM270 from the BUF 40. The MUX 33 generates the signal / Main from the signal / Main<3:0> based on the signals CKM000, CKM090, CKM180, and CKM270. More specifically, the MUX 33 generates the signal / Main in response to the rising edges of the signals CKM000, CKM090, CKM180, and CKM270. <0> , / Main <1> , / Main <2> , and / Main <3> and outputs it as a single-phase signal / Main. MUX 31 outputs signal / Main to driver 37. Signal / Main includes data obtained by serially converting data superimposed in parallel on signal / Main<3:0>. Signal / Main is a differential signal of signal Main.

[0040] The MUX 34 receives the signal / Post<3:0> from the DSP 10. The MUX 34 receives the signals CKD000, CKD090, CKD180, and CKD270 from the DLY 60. The MUX 34 generates the signal / Post from the signal / Post<3:0> based on the signals CKD000, CKD090, CKD180, and CKD270. More specifically, the MUX 34 generates the signal / Post in response to the rising edges of the signals CKD000, CKD090, CKD180, and CKD270. <0> , / Post <1> , / Post <2> , and / Post <3> and outputs it as a single-phase signal / Post. The MUX 34 outputs the signal / Post to the driver 38. The signal / Post includes data obtained by serially converting the data superimposed in parallel on the signal / Post<3:0>. The signal / Post is a differential signal of the signal Post.

[0041] Each of the drivers 35 to 38 may be an SST driver (source series termination driver). Each of the drivers 35 to 38 is configured to convert an input digital signal into an analog signal while adjusting the output impedance, and output the analog signal.

[0042] Specifically, a signal Main is input to the driver 35. The driver 35 converts the signal Main into an analog signal based on a control signal TAPm. The control signal TAPm determines the amplitude of the analog signal generated by the driver 35. A signal Post is input to the driver 36. The driver 36 converts the signal Post into an analog signal based on a control signal TAPd. The control signal TAPd determines the amplitude of the analog signal generated by the driver 36. The analog signal generated by the driver 35 and the analog signal generated by the driver 36 are combined and then output to the pad P1 as a signal TR.

[0043] A signal / Main is input to the driver 37. The driver 37 converts the signal / Main into an analog signal based on a control signal / TAPm. The control signal / TAPm determines the amplitude of the analog signal generated by the driver 37. A signal / Post is input to the driver 38. The driver 38 converts the signal / Post into an analog signal based on a control signal / TAPd. The control signal / TAPd determines the amplitude of the analog signal generated by the driver 38. The analog signal generated by the driver 37 and the analog signal generated by the driver 38 are combined and then output to the pad P2 as a signal / TR.

[0044] 1.4 Buffer circuit Next, the internal configuration of the buffer circuit (BUF40) included in the feedforward equalizer according to the embodiment will be described. Fig. 5 is a block diagram showing an example of the configuration of the buffer circuit included in the feedforward equalizer according to the embodiment.

[0045] BUF40 includes INV41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, and 56.

[0046] Each of the INVs 41 to 56 is an inverter, and is configured to invert an input signal and output the inverted signal.

[0047] Specifically, the signal CLK000 is input to the input terminal of INV41, and the output terminal of INV41 is connected to the node N1.

[0048] The input terminal of INV42 is connected to node N1, and the output terminal of INV42 is connected to node N2.

[0049] The signal CLK180 is input to the input terminal of INV43, and the output terminal of INV43 is connected to node N3.

[0050] The input terminal of INV44 is connected to node N3, and the output terminal of INV44 is connected to node N4.

[0051] The input terminal of INV45 is connected to node N3, and the output terminal of INV45 is connected to node N1.

[0052] The input terminal of INV46 is connected to node N1, and the output terminal of INV46 is connected to node N3.

[0053] The input terminal of INV47 is connected to node N4, and the output terminal of INV47 is connected to node N2.

[0054] The input terminal of INV48 is connected to node N2, and the output terminal of INV48 is connected to node N4.

[0055] In the above-described configuration of INV41 to 48, signals CKM000 and CKM180 are output from nodes N2 and N4, respectively.

[0056] Furthermore, the signal CLK090 is input to the input terminal of INV49, and the output terminal of INV49 is connected to node N5.

[0057] The input terminal of INV50 is connected to node N5, and the output terminal of INV50 is connected to node N6.

[0058] The signal CLK270 is input to the input terminal of INV51. The output terminal of INV51 is connected to node N7.

[0059] The input terminal of INV52 is connected to node N7, and the output terminal of INV52 is connected to node N8.

[0060] The input terminal of INV53 is connected to node N7, and the output terminal of INV53 is connected to node N5.

[0061] The input terminal of INV54 is connected to node N5, and the output terminal of INV54 is connected to node N7.

[0062] The input terminal of INV55 is connected to node N8, and the output terminal of INV55 is connected to node N6.

[0063] The input terminal of INV56 is connected to node N6, and the output terminal of INV56 is connected to node N8.

[0064] In the above-described configuration of INV49 to 56, signals CKM090 and CKM270 are output from nodes N6 and N8, respectively.

[0065] 1.5 Delay Circuit Next, the internal configuration of the delay circuit (DLY60) included in the feedforward equalizer according to the embodiment will be described. Fig. 6 is a block diagram showing an example of the configuration of the delay circuit included in the feedforward equalizer according to the embodiment.

[0066] DLY60 includes INV61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, and 76, and CAP77, 78, 79, 80, 81, 82, 83, and 84.

[0067] Each of INV61 to 76 is an inverter. Each of INV61 to 76 is configured to invert an input signal and output it. Each of CAP77 to 84 is a variable capacitance capacitor. Each of CAP77 to 84 can set the capacitance to a predetermined value based on a control signal CTRL.

[0068] Specifically, the signal CLK000 is input to the input terminal of INV61, and the output terminal of INV61 is connected to a node N9.

[0069] The input terminal of INV62 is connected to node N9, and the output terminal of INV62 is connected to node N10.

[0070] The signal CLK180 is input to the input terminal of INV63, and the output terminal of INV63 is connected to node N11.

[0071] The input terminal of INV64 is connected to node N11, and the output terminal of INV64 is connected to node N12.

[0072] The input terminal of INV65 is connected to node N11, and the output terminal of INV65 is connected to node N9.

[0073] The input terminal of INV66 is connected to node N9, and the output terminal of INV66 is connected to node N11.

[0074] The input terminal of INV67 is connected to node N12, and the output terminal of INV67 is connected to node N10.

[0075] The input terminal of INV68 is connected to node N10, and the output terminal of INV68 is connected to node N12.

[0076] CAP77 is connected to node N9. CAP78 is connected to node N10. CAP79 is connected to node N11. CAP80 is connected to node N12. Each of CAP77 to 80 is further connected to, for example, a wiring to which a reference potential is applied when DLY60 operates.

[0077] In the above-described configuration of INV61 to 68 and CAP77 to 80, signals CKD000 and CKD180 are output from nodes N10 and N12, respectively.

[0078] The signal CLK090 is input to the input terminal of INV69, and the output terminal of INV69 is connected to node N13.

[0079] The input terminal of INV70 is connected to node N13, and the output terminal of INV70 is connected to node N14.

[0080] The signal CLK270 is input to the input terminal of INV71, and the output terminal of INV71 is connected to node N15.

[0081] The input terminal of INV72 is connected to node N15, and the output terminal of INV72 is connected to node N16.

[0082] The input terminal of INV73 is connected to node N15, and the output terminal of INV73 is connected to node N13.

[0083] The input terminal of INV74 is connected to node N13, and the output terminal of INV74 is connected to node N15.

[0084] The input terminal of INV75 is connected to node N16, and the output terminal of INV75 is connected to node N14.

[0085] The input terminal of INV76 is connected to node N14, and the output terminal of INV76 is connected to node N16.

[0086] CAP81 is connected to node N13. CAP82 is connected to node N14. CAP83 is connected to node N15. CAP84 is connected to node N16. Each of CAP81 to 84 is further connected to, for example, a wiring to which a reference potential is applied when DLY60 operates.

[0087] In the above-described configuration of INV69 to 76 and CAP81 to 84, signals CKD090 and CKD270 are output from nodes N14 and N16, respectively.

[0088] 2. Operation Next, the operation of the transmitting device according to the embodiment will be described.

[0089] 2.1 Generation of the signal Main First, a description will be given of the operation of generating the signal Main in the transmitting device according to the embodiment. Fig. 7 is a timing chart showing an example of the operation of generating the signal Main in the transmitting device according to the embodiment. Fig. 7 shows the relationship between the signals Main<3:0> and data superimposed on Main, and the signals CKM000, CKM090, CKM180, and CKM270 in chronological order.

[0090] 7, the signal Main<3:0> contains different data every 4 UI. <0> contains data D0 over 4 UI from time T0 to time T4, contains data D4 over 4 UI from time T4 to time T8, and contains data D8 over 4 UI from time T8 onwards. <1> The signal Main includes data D1 over 4 UI from time T1 to time T5, data D5 over 4 UI from time T5 to time T9, and data D9 over 4 UI from time T9 onwards. Times T1, T5, and T9 are 1 UI after times T0, T4, and T8, respectively. <2> includes data D2 over 4 UI from time T2 to time T6, and Data D6 is included over 4 UI, and data D10 is included over the next 4 UI from time T10. Times T2, T6, and T10 are times 1 UI after times T1, T5, and T9, respectively. <3> includes data D3 over 4 UI from time T3 to time T7, and includes data D7 over 4 UI from time T7 onwards. Times T3 and T7 are 1 UI after times T2 and T6, respectively.

[0091] At time T2, MUX31 outputs the signal Main <0> MUX31 receives the signal Main <0> The data D0 contained in the signal is output as the signal Main.

[0092] At time T3, one UI after time T2, MUX31 outputs the signal Main <1> MUX31 receives the signal Main <1> The data D1 included in the signal is output as the signal Main.

[0093] At time T4, one UI after time T3, MUX31 outputs the signal Main <2> MUX31 receives the signal Main <2> The data D2 included in the signal is output as the signal Main.

[0094] At time T5, one UI after time T4, MUX31 outputs the signal Main <3> MUX31 receives the signal Main <3> The data D3 included in the signal is output as the signal Main.

[0095] Similarly, MUX 31 outputs the data included in signal Main<3:0> as signal Main every 1 UI, thereby enabling MUX 31 to output signal Main including data D0, D1, D2, D3, ... in a 1 UI cycle.

[0096] In the example of FIG. 7, the operation of generating the signal Main by MUX 31 has been described, but the operation of generating the signal / Main by MUX 33 is similar to the operation of generating the signal Main.

[0097] 2.2 Signal Post Generation Operation Next, a description will be given of a generation operation of the signal Post in the transmitting device according to the embodiment. Fig. 8 is a timing chart showing an example of a generation operation of the signal Post in the transmitting device according to the embodiment. Fig. 8 shows a time series of the relationship between the signal Post<3:0>, the data superimposed on Post, and the signals CKD000, CKD090, CKD180, and CKD270.

[0098] 8, the signal Post<3:0> contains different data every 4 UI. <1> The signal Post contains data D0 over 4 UI from time T1 to time T5, data D4 over 4 UI from time T5 to time T9, and data D8 over 4 UI from time T9 onwards. <2> The signal Post includes data D1 over 4 UI from time T2 to time T6, data D5 over 4 UI from time T6 to time T10, and data D9 over 4 UI from time T10 onwards. <3> The signal Post includes data D2 over 4 UI from time T3 to time T7, data D6 over 4 UI from time T7 to time T11, and data D10 over 4 UI from time T11 onwards. Time T11 is the time 1 UI after time T10. <0> includes data D3 over 4 UI from time T4 to time T8, and includes data D7 over 4 UI from time T8 onwards. Time T8 is the time 1 UI after time T7.

[0099] At time T2', which is (1 UI + Δ) after time T2, MUX33 outputs the signal Post <1> MUX33 is the signal Post <1> The data D0 contained in the signal is output as a signal Post.

[0100] At time T3', which is 1 UI after time T2' (i.e., (1 UI+Δ) after time T3), MUX33 outputs the signal Post <2> MUX33 is the signal Post <2> The data D1 included in the signal Post is output as the signal Post.

[0101] At time T4', which is 1 UI after time T3' (i.e., (1 UI+Δ) after time T4), MUX33 outputs the signal Post <3> MUX33 is the signal Post <3> The data D2 included in the signal Post is output as the signal Post.

[0102] At time T5', which is 1 UI after time T4' (i.e., (1 UI+Δ) after time T5), MUX33 outputs the signal Post <0> MUX33 is the signal Post <0> The data D3 included in the signal Post is output as the signal Post.

[0103] Similarly, MUX 33 outputs the data included in signal Post<3:0> as signal Post every 1 UI. This allows MUX 33 to output signal Post, which includes data D0, D1, D2, D3, ..., at a 1 UI period, delayed by (1 UI + Δ) from signal Main. In other words, MUX 33 can output signal Post delayed by any time within a range of 1 UI to 2 UI from signal Main.

[0104] In the example of FIG. 8, the operation of generating the signal Post by the MUX 33 has been described, but the operation of generating the signal / Post by the MUX 34 is similar to the operation of generating the signal Post.

[0105] 2.3 Output waveform of signal TR Next, a signal TR output from a transmitting device according to an embodiment will be described. Fig. 9 is a schematic diagram showing an example of the waveform of the signal TR output from a transmitting device according to an embodiment. Fig. 9 shows the waveform of a portion of the signal TR corresponding to one bit.

[0106] 9, the signal TR includes a portion corresponding to the signal Main at the main cursor (Cursor=0). The signal Main is output, for example, over 1 UI centered on the main cursor. The signal TR also includes a portion corresponding to the signal Post between post-cursor 1 (Cursor=1) and post-cursor 2 (Cursor=2). The signal Post is output, for example, over 1 UI centered at a time delayed by (1 UI+Δ) from the main cursor.

[0107] As described above, the FFE 30 can set Δ between 0 UI and 1 UI, which allows the signal Post to be delayed by any time between 1 UI and 2 UI from the main cursor and included in the signal TR.

[0108] 3. Effects of the embodiment According to an embodiment, the DSP 10 generates a four-phase signal Main<3:0> and a four-phase signal Post<3:0> that is shifted by 1 UI from the signal Main<3:0>. The DLY 60 in the FFE 30 generates four-phase signals CKD000, CKD090, CKD180, and CKD270 that are shifted by Δ from the four-phase signals CKM000, CKM090, CKM180, and CKM270, respectively. The MUX 31 in the FFE 30 converts the signal Main<3:0> into a single-phase signal Main based on the signals CKM000, CKM090, CKM180, and CKM270. The MUX 32 in the FFE 30 converts the signal Post<3:0> into a single-phase signal Post based on the signals CKD000, CKD090, CKD180, and CKD270. The signal Post is a signal shifted by (1 UI + Δ) from the signal Main. Drivers 35 and 36 output the signal TR to pad P1 as a composite signal of an analog signal based on the signal Main and an analog signal based on the signal Post. This makes it possible to add a corresponding waveform between post-cursors 1 and 2, as shown in FIG. 9. This makes it possible to generate an analog signal suitable for the receiving device 4.

[0109] Additionally, the receiving circuit in the receiving device 4 includes a CTLE (continuous time linear equalizer). The CTLE boosts the high-frequency components of the signals RV and / RV relative to the low-frequency components through Q-shaping. However, if the high-frequency components are strongly boosted through Q-shaping, the attenuation coefficient of the CTLE transfer function may become a complex pole. In this case, a component of opposite polarity to the component at the main cursor occurs between post-cursors 1 and 2 of the signal output from the CTLE, which may cause worsening inter-symbol interference (ISI).

[0110] According to the embodiment, as described above, the transmitting device 2 adds a corresponding waveform between post-cursors 1 and 2 of the signal TR. This makes it possible to compensate for waveform degradation in the CTLE on the receiving device 4 side. Therefore, even if high frequency components are strongly boosted by Q-shaping in the CTLE, it is possible to suppress ISI degradation. Therefore, it is possible to provide a transmitting device that generates an analog signal suitable for the receiving device 4.

[0111] The FFE30 also includes MUX33 and 34, which have the same configuration as MUX31 and 32. This allows the FFE30 to convert signals / Main<3:0> and / Post<3:0> into signals / Main and / Post, respectively, while converting signals Main<3:0> and Post<3:0> into signals Main and Post, respectively. Therefore, the FFE30 can output differential signals TR and / TR to pads P1 and P2, respectively.

[0112] 4. Modifications, etc. Various modifications can be applied to the above-described embodiment.

[0113] In the above embodiment, the DSP 10 outputs four-phase signals Main<3:0>, Post<3:0>, / Main<3:0>, and / Post<3:0> to the FFE 30, but this is not limiting. For example, the DSP 10 outputs n-phase signals Main <n-1:0>、Post <n-1:0>、 / Main <n-1:0>, and / Post <n-1:0>may be output to the FFE 30 (n is an integer of 2 or more).

[0114] In this case, the CLKGEN20 generates n-phase signals CLK000, CLK(360 / n), ..., and CLK(360×(n-1) / n) and outputs them to the FFE30. The BUF40 in the FFE30 generates signals CKM000, CKM(360 / n), ..., and CKM(360×(n-1) / n) based on the signals CLK000, CLK(360 / n), ..., and CLK(360×(n-1) / n). The DLY60 in the FFE30 generates signals CKD000, CKD(360 / n), ..., and CKD(360×(n-1) / n) based on the signals CLK000, CLK(360 / n), ..., and CLK(360×(n-1) / n).

[0115] MUX31 outputs the signal Main in response to the rising edges of the signals CKM000, CKM(360 / n), ..., and CKM(360×(n−1) / n). <0> , Main <1> , …, and Main <n-1>and outputs it as a single-phase signal Main. MUX32 outputs the signal Post in response to the rising edges of the signals CKD000, CKD(360 / n), ..., and CKD(360×(n-1) / n). <0> , Post <1> , …, and Post <n-1>and outputs it as a single-phase signal Post. The MUX 33 outputs the signal / Main in response to the rising edges of the signals CKM000, CKM(360 / n), ..., and CKM(360×(n-1) / n), respectively. <0> , / Main <1> , …, and / Main <n-1>and outputs it as a single-phase signal / Main. MUX34 outputs the signal / Post in response to the rising edges of the signals CKD000, CKD(360 / n), ..., and CKD(360×(n-1) / n). <0> , / Post <1> , …, and / Post <n-1>and output it as a single-phase signal / Post.

[0116] With the above configuration, the FFE 30 can generate signals Post and / Post that are shifted by (1 UI + Δ) relative to the signals Main and / Main, where n is an arbitrary integer equal to or greater than 2. This can achieve the same effects as those of the embodiment.

[0117] In the above embodiment, the signals TR and / TR each contain one bit of data per symbol, but this is not limiting. For example, the signals TR and / TR may each contain two or more bits of data per symbol.

[0118] Although several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments can be embodied in various other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the inventions and their equivalents as defined in the claims. [Explanation of symbols]

[0119] 1. Transmission and reception system 2...Transmitting device 3...Transmission path 4...Receiving device 10...DSP 20...CLKGEN 30...FFE 31, 32, 33, 34…MUX 35, 36, 37, 38...Driver 40…BUF 60…DLY 41,42,43,44,45,46,47,48,49,50,51,52,53,54,55,56,61,62,63,64,65,66,67,68,69,70,71,72,73,74,75,76...INV 77,78,79,80,81,82,83,84…CAP 100...Wiring board 101,103...adhesive layer 102, 104...Semiconductor chips 105, 106, 107...Pad electrodes 108,109...Wiring 110...bump electrode 111...Resin layer

Claims

1. a digital processing circuit that generates a first digital signal of n phases and a second digital signal of n phases that is shifted from the first digital signal by a first phase, where n is an integer equal to or greater than 2; a delay circuit that generates a second clock signal having n phases that is shifted by a second phase from the first clock signal having n phases; a first multiplexer that converts the first digital signal into a single-phase third digital signal based on the first clock signal; a second multiplexer that converts the second digital signal into a single-phase fourth digital signal that is shifted from the third digital signal by the sum of the first phase and the second phase, based on the second clock signal; a first driver that outputs a composite signal of a first analog signal based on the third digital signal and a second analog signal based on the fourth digital signal; Equipped with the second phase is greater than or equal to 0 and less than or equal to the first phase; Transmitting device.

2. the digital processing circuit further generates a fifth digital signal with n phases and a sixth digital signal with n phases that is shifted from the fifth digital signal by the first phase; the first digital signal and the fifth digital signal are differential signals, the second digital signal and the sixth digital signal are differential signals, a third multiplexer that converts the fifth digital signal into a single-phase seventh digital signal based on the first clock signal; a fourth multiplexer that converts the sixth digital signal into a single-phase eighth digital signal that is shifted from the seventh digital signal by the sum based on the second clock signal; a second driver that outputs a composite signal of a third analog signal based on the seventh digital signal and a fourth analog signal based on the eighth digital signal; Further comprising:

2. The transmitting device according to claim 1.

3. a period of the third digital signal is 1 / n of that of the first digital signal; the fourth digital signal has a period that is 1 / n of the second digital signal; 2. The transmitting device according to claim 1.

4. the conversion by the first multiplexer and the second multiplexer includes conversion from a parallel signal to a serial signal; 2. The transmitting device according to claim 1.

5. A wiring board; a semiconductor chip provided on the wiring substrate, the semiconductor chip having the transmitting device according to any one of claims 1 to 4 formed as a semiconductor circuit; a resin that encapsulates the semiconductor chip and covers a portion of the wiring substrate; A semiconductor device comprising:

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