Storage device

Abstract

To provide a storage device including a switching element having an excellent characteristic.SOLUTION: A storage device according to an embodiment includes a memory cell in which a first conductive layer, a switching layer, a third conductive layer, a resistance change layer, and a second conductive layer are stacked in this order. The switching layer includes a first region and a second region. The first region includes a first substance including a first element selected from Zr, Y, Ta, La, Ce, Ti, Hf, Mg, and Al and a second element selected from O, S, Se, and Te. The second region includes a second substance including a first element and a third element which is selected from S, Se, and Te and whose atomic number is larger than that of the second element, and a third substance including a fourth element selected from a group consisting of Zn, Sn, Ga, In, Bi, Mg, and Ca and a fifth element selected from a group consisting of S, Se, and Te. An atomic concentration of the fourth element in the second region is higher than that in the first region.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] FIELD OF THE INVENTION An embodiment of the present invention relates to a storage device. [Background technology]

[0002] Cross-point type two-terminal memory devices are a type of large-capacity nonvolatile memory device, which allows for easy miniaturization and high integration of memory cells.

[0003] A memory cell of a cross-point two-terminal memory device has, for example, a resistance change element and a switching element. By having a memory cell have a switching element, current flowing to memory cells other than the selected memory cell is suppressed.

[0004] The switching element is required to have excellent characteristics such as low leakage current, high on-state current, and high reliability. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] US Patent Application Publication No. 2010 / 0270588 Summary of the Invention [Problem to be solved by the invention]

[0006] An object of the present invention is to provide a memory device having a switching element with excellent characteristics. [Means for solving the problem]

[0007] A memory device according to an embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer provided between the first conductive layer and the second conductive layer, a switching layer provided between the first conductive layer and the third conductive layer, and a resistance change layer provided between the third conductive layer and the second conductive layer, wherein the switching layer includes at least one first region and at least one second region having a chemical composition different from a chemical composition of the first region, and the first region includes a first element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), and aluminum (Al), and oxygen (O), sulfur (S), selenium (Se), and the switching layer includes at least one first region and at least one second region having a chemical composition different from a chemical composition of the first region. and a second element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), and the second region includes a second material including the first element and a third element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and having an atomic number greater than that of the second element, and a third material including a fourth element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a fifth element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), the first region may or may not include the fourth element, and the atomic concentration of the fourth element in the second region is higher than the atomic concentration of the fourth element in the first region. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram of a storage device according to a first embodiment. [Figure 2] FIG. 2 is a schematic cross-sectional view of a memory cell of the memory device according to the first embodiment. [Figure 3] FIG. 2 is an explanatory diagram of a problem of the storage device of the first embodiment. [Figure 4] FIG. 3 is an explanatory diagram of current-voltage characteristics of the switching element according to the first embodiment. [Figure 5] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a first comparative example. [Figure 6] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a second comparative example. [Figure 7] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a first modified example of the first embodiment. [Figure 8] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a second modification of the first embodiment. [Figure 9] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a third modified example of the first embodiment. [Figure 10] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a fourth modified example of the first embodiment. [Figure 11] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a second embodiment. [Figure 12] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a third embodiment. [Figure 13] FIG. 10 is a schematic cross-sectional view of a memory cell of a memory device according to a fourth embodiment. [Figure 14] FIG. 10 is an explanatory diagram of current-voltage characteristics of the memory element according to the fourth embodiment. [Figure 15] FIG. 10 is an explanatory diagram of a first operation example of a memory operation of the storage device according to the fourth embodiment. [Figure 16] FIG. 13 is an explanatory diagram of a second example of memory operation of the storage device according to the fourth embodiment. [Figure 17] FIG. 13 is a graph showing current-voltage characteristics of a memory element according to a first modified example of the fourth embodiment. [Figure 18] FIG. 13 is an explanatory diagram of a third example of the memory operation of the storage device according to the first modified example of the fourth embodiment. [Figure 19] FIG. 13 is an explanatory diagram of a fourth operation example of the memory operation of the storage device according to the first modified example of the fourth embodiment. [Figure 20] FIG. 13 is a graph showing current-voltage characteristics of a memory element according to a second modified example of the fourth embodiment. [Figure 21] FIG. 13 is an explanatory diagram of a fifth operation example of the memory operation of the storage device according to the second modified example of the fourth embodiment. [Figure 22] FIG. 13 is an explanatory diagram of a sixth operation example of the memory operation of the storage device according to the second modified example of the fourth embodiment. [Figure 23]FIG. 13 is a graph showing current-voltage characteristics of a memory element according to a third modified example of the fourth embodiment. [Figure 24] FIG. 13 is an explanatory diagram of a seventh operation example of the memory operation of the storage device according to the third modified example of the fourth embodiment. [Figure 25] FIG. 13 is an explanatory diagram of an eighth operation example of the memory operation of the storage device according to the third modified example of the fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, an embodiment of the present invention will be described with reference to the drawings. In the following description, the same or similar components will be designated by the same reference numerals, and the description of components that have already been described will be omitted as appropriate.

[0010] The qualitative and quantitative analysis of the chemical composition constituting the memory device in this specification can be performed by, for example, Rutherford Backscattering Spectroscopy (RBS), Secondary Ion Mass Spectroscopy (SIMS), Energy Dispersive X-ray Spectroscopy (EDX), Electron Energy Loss Spectroscopy (EELS), etc. Furthermore, for example, a Transmission Electron Microscope (TEM) can be used to measure the thickness of the components constituting the memory device, the distance between the components, etc. Furthermore, for example, X-ray photoelectron spectroscopy (XPS), X-ray absorption fine structure (XAFS), Raman spectroscopy (Raman), or EELS can be used to identify the constituent materials of the memory device, and measure their abundance ratios, bonding states, local structures (atomic distances, coordination numbers), and chemical states. Furthermore, for example, EELS can be used to measure the band gaps of the components of the memory device.

[0011] (First embodiment) A memory device according to a first embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer disposed between the first and second conductive layers, a switching layer disposed between the first and third conductive layers, and a resistance change layer disposed between the third and second conductive layers. The switching layer includes at least one first region and at least one second region having a chemical composition different from that of the first region. The first region includes a first substance including a first element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), and aluminum (Al), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). The second region includes a second material including the first element, a third element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and having an atomic number greater than that of the second element, a fourth element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a fifth element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), and the first region may or may not include the fourth element, and the atomic concentration of the fourth element in the second region is greater than the atomic concentration of the fourth element in the first region.

[0012] The memory device of the first embodiment further includes a plurality of first wirings and a plurality of second wirings intersecting the plurality of first wirings, and the memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

[0013] FIG. 1 is a block diagram of a storage device according to the first embodiment.

[0014] A memory cell array 100 of the memory device of the first embodiment includes, for example, a plurality of word lines 102 and a plurality of bit lines 103 intersecting the word lines 102, disposed on a semiconductor substrate 101 via an insulating layer. The bit lines 103 are provided, for example, in an upper layer above the word lines 102. In addition, a first control circuit 104, a second control circuit 105, and a sense circuit 106 are provided around the memory cell array 100 as peripheral circuits.

[0015] The word line 102 is an example of a first wiring, and the bit line 103 is an example of a second wiring.

[0016] A plurality of memory cells MC are provided in the regions where the word lines 102 and the bit lines 103 intersect. The storage device of the first embodiment is a two-terminal magnetoresistive memory having a cross-point structure.

[0017] The plurality of word lines 102 are each connected to a first control circuit 104. The plurality of bit lines 103 are each connected to a second control circuit 105. The sense circuit 106 is connected to the first control circuit 104 and the second control circuit 105.

[0018] The first control circuit 104 and the second control circuit 105 have functions to, for example, select a desired memory cell MC and write data to the memory cell MC, read data from the memory cell MC, erase data from the memory cell MC, etc. When reading data, the data in the memory cell MC is read as the amount of current flowing between the word line 102 and the bit line 103 or as a change in potential on the bit line 103. The sense circuit 106 has a function to determine the amount of current or the change in potential and determine the polarity of the data. For example, it determines whether the data is "0" or "1."

[0019] The first control circuit 104, the second control circuit 105, and the sense circuit 106 are configured by electronic circuits using semiconductor devices formed on the semiconductor substrate 101, for example.

[0020] 2 is a schematic cross-sectional view of a memory cell in the memory device of Embodiment 1. Fig. 2 shows a cross-section of one memory cell MC indicated by a dotted circle, for example, in the memory cell array 100 of Fig. 1.

[0021] 2, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistance change layer 50. The switching layer 40 includes a first region 41, a second region 42, and a conductor 40x. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0022] The lower electrode 10 is an example of a first conductive layer, the upper electrode 20 is an example of a second conductive layer, and the intermediate electrode 30 is an example of a third conductive layer.

[0023] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute a switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute a resistance change element of the memory cell MC.

[0024] The bottom electrode 10 is connected to a word line 102. The bottom electrode 10 is, for example, a metal. The bottom electrode 10 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The bottom electrode 10 may be a part of the word line 102.

[0025] The upper electrode 20 is connected to the bit line 103. The upper electrode 20 is, for example, a metal. The upper electrode 20 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride. The upper electrode 20 may be a part of the bit line 103.

[0026] The intermediate electrode 30 is provided between the lower electrode 10 and the upper electrode 20. The intermediate electrode 30 is, for example, a metal. The intermediate electrode 30 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0027] The switching layer 40 is provided between the lower electrode 10 and the intermediate electrode 30. The thickness of the switching layer 40 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, not less than 5 nm and not more than 50 nm. It is more preferable that the thickness of the switching layer 40 in the first direction from the lower electrode 10 to the upper electrode 20 is, for example, not less than 5 nm and not more than 20 nm.

[0028] The switching layer 40 has a function of suppressing an increase in the semi-selected leakage current flowing through the semi-selected cells. The switching layer 40 has a non-linear current-voltage characteristic in which the current rises sharply at a specific threshold voltage.

[0029] The switching layer 40 includes at least one first region 41 and at least one second region 42. As shown in FIG. 2 , the first region 41 and the second region 42 are, for example, arranged alternately in a first direction. The first region 41 and the second region 42 are, for example, stacked alternately in the first direction. Either the first region 41 or the second region 42 may be provided adjacent to the lower electrode 10. Also, either the first region 41 or the second region 42 may be provided adjacent to the intermediate electrode 30.

[0030] 2 illustrates an example in which the first region 41 has two layers and the second region 42 has three layers, but the number of layers is not limited to these. For example, the first region 41 and the second region 42 may each be a single layer.

[0031] The switching layer 40 includes a first material, a second material, and a third material. The first material, the second material, and the third material are, for example, the main components of the switching layer 40. The fact that the first material, the second material, and the third material are the main components of the switching layer 40 means that no material exists in the switching layer 40 that is present in a higher proportion than any of the first material, the second material, and the third material. The proportions are, for example, molar ratios.

[0032] The first region 41 includes a first material. For example, the first material is the main component of the first region 41. The first region 41 may or may not include a third material.

[0033] The second region 42 includes a second material and a third material, for example, the second material and the third material are the main components of the second region 42.

[0034] The first material includes a first element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), and aluminum (Al), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te), where the second element is a Group 16 element.

[0035] The first substance is, for example, a compound of a first element and a second element. The first substance is an insulator.

[0036] The first material is, for example, zirconium oxide, yttrium oxide, tantalum oxide, lanthanum oxide, cerium oxide, titanium oxide, hafnium oxide, magnesium oxide, aluminum oxide, zirconium sulfide, yttrium sulfide, tantalum sulfide, lanthanum sulfide, cerium sulfide, titanium sulfide, hafnium sulfide, magnesium sulfide, aluminum sulfide, zirconium selenide, yttrium selenide, tantalum selenide, lanthanum selenide, cerium selenide, titanium selenide, hafnium selenide, magnesium selenide, aluminum selenide, zirconium telluride, yttrium telluride, tantalum telluride, lanthanum telluride, cerium telluride, titanium telluride, hafnium telluride, magnesium telluride, or aluminum telluride.

[0037] The second material contains the first element contained in the first material and a third element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te). The third element is a Group 16 element. The third element is different from the second element contained in the first material. The atomic number of the third element is greater than the atomic number of the second element contained in the first material.

[0038] The second substance is, for example, a compound of the first element and the third element. The second substance is an insulator.

[0039] The second material is, for example, zirconium sulfide, yttrium sulfide, tantalum sulfide, lanthanum sulfide, cerium sulfide, titanium sulfide, hafnium sulfide, magnesium sulfide, aluminum sulfide, zirconium selenide, yttrium selenide, tantalum selenide, lanthanum selenide, cerium selenide, titanium selenide, hafnium selenide, magnesium selenide, aluminum selenide, zirconium telluride, yttrium telluride, tantalum telluride, lanthanum telluride, cerium telluride, titanium telluride, hafnium telluride, magnesium telluride, or aluminum telluride.

[0040] The third material includes a fourth element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a fifth element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te).

[0041] The third substance is, for example, a compound of a fourth element and a fifth element. The third substance is an electrical conductor.

[0042] The third material is, for example, zinc sulfide, tin sulfide, gallium sulfide, indium sulfide, bismuth sulfide, magnesium sulfide, calcium sulfide, zinc selenide, tin selenide, gallium selenide, indium selenide, bismuth selenide, magnesium selenide, calcium selenide, zinc telluride, tin telluride, gallium telluride, indium telluride, bismuth telluride, magnesium telluride, or calcium telluride.

[0043] The first material is the first matrix of the switching layer 40. The second material is the second matrix of the switching layer 40.

[0044] The switching layer 40 includes a conductor 40x. The conductor 40x is included in the second region 42. The conductor 40x is, for example, dispersed in a second base material of the second region 42. The conductor 40x may or may not be included in the first region 41. The abundance ratio of the conductor 40x in the second region 42 is higher than the abundance ratio of the conductor 40x in the first region 41. The abundance ratio is, for example, a molar ratio.

[0045] The conductor 40x includes a third material. The conductor 40x is, for example, the third material. The conductor 40x includes a fourth element and a fifth element.

[0046] The first region 41 may or may not contain a fourth element. The atomic concentration of the fourth element in the second region 42 is higher than the atomic concentration of the fourth element in the first region 41. The atomic concentration of the fourth element in the second region 42 is, for example, 10 times or more and 100 times or less than the atomic concentration of the fourth element in the first region 41.

[0047] In the switching layer 40, the sum of the atomic concentrations of the first element, the second element, the third element, the fourth element, and the fifth element is, for example, not less than 80% and not more than 100%.

[0048] The band gap of the second material is smaller than the band gap of the first material. The band gap of the first material contained in the first region 41 and the band gap of the second material contained in the second region 42 can be measured using, for example, EELS.

[0049] In the case of compounds of metal elements and Group 16 elements, the compound in which the atomic number of the 16th element is higher has a smaller band gap. For example, when the metal element is zirconium (Zr), the band gap of zirconium sulfide is smaller than that of zirconium oxide. Also, the band gap of zirconium selenide is smaller than that of zirconium sulfide. Also, the band gap of zirconium telluride is smaller than that of zirconium selenide.

[0050] The atomic number of the third element contained in the second material, which is element 16, is greater than the atomic number of the second element contained in the first material, which is element 16. Therefore, when the first material and the second material are a compound containing element 16, the band gap of the second material is smaller than the band gap of the first material.

[0051] Furthermore, when a third material exists in a first material, the charge of the third material is greater than when the third material exists in a second material. The charge of the third material is thought to increase as the band gap of the base material increases. In other words, it is thought that the charge of the third material can be reduced by reducing the band gap of the base material. The charge of the third material can be calculated, for example, by first-principles calculations.

[0052] The switching layer 40 can be formed by, for example, a sputtering method. For example, the first region 41 is formed by a sputtering method using a target made of a first material. Also, for example, the second region 42 can be formed by a co-sputtering method using a target made of a second material and a target made of a third material. Also, the second region 42 can be formed by a sputtering method using a target made of a mixture of the second material and the third material.

[0053] The resistance change layer 50 is provided between the intermediate electrode 30 and the upper electrode 20. The resistance change layer 50 has a fixed layer 51, a tunnel layer 52, and a free layer 53. The resistance change layer 50 includes a magnetic tunnel junction configured of the fixed layer 51, the tunnel layer 52, and the free layer 53.

[0054] The resistance change layer 50 has a function of storing data by changing resistance, and has a characteristic that the electrical resistance of the resistance change layer 50 changes when a predetermined voltage is applied, for example.

[0055] The fixed layer 51 is made of a ferromagnetic material. In the fixed layer 51, the magnetization direction does not change with respect to a predetermined write voltage, and the magnetization direction is fixed in a specific direction.

[0056] The tunnel layer 52 is an insulator through which electrons pass by the tunnel effect.

[0057] The free layer 53 is a ferromagnetic material. The magnetization direction of the free layer 53 changes in response to a predetermined write voltage. The magnetization direction of the free layer 53 can be either parallel to the magnetization direction of the fixed layer 51 or antiparallel to the magnetization direction of the fixed layer 51. For example, the magnetization direction of the free layer 53 can be changed by applying a voltage and passing a current between the intermediate electrode 30 and the upper electrode 20.

[0058] Changing the magnetization direction of the free layer 53 changes the electrical resistance of the resistance change layer 50. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high resistance state is achieved where current does not easily flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low resistance state is achieved where current easily flows. The arrangement of the fixed layer 51 and the free layer 53 may be reversed. In other words, the intermediate electrode 30, free layer 53, tunnel layer 52, fixed layer 51, and upper electrode 20 may be stacked in this order.

[0059] Next, the operation and effects of the storage device of the first embodiment will be described.

[0060] As described above, in the memory device of the first embodiment, the resistance of the variable resistance layer 50 changes by changing the magnetization direction of the free layer 53. When the magnetization direction of the free layer 53 is antiparallel to the magnetization direction of the fixed layer 51, a high resistance state is achieved in which current does not easily flow. On the other hand, when the magnetization direction of the free layer 53 is parallel to the magnetization direction of the fixed layer 51, a low resistance state is achieved in which current easily flows.

[0061] For example, the high resistance state of the resistance change layer 50 is defined as data "1" and the low resistance state is defined as data "0." The memory cell MC can maintain different resistance states, allowing it to store one bit of data, "0" or "1." Writing to one memory cell MC is performed by applying a voltage between the bit line 103 and word line 102 connected to that memory cell MC, causing a current to flow.

[0062] 3 is an explanatory diagram of the problem of the memory device of the first embodiment. Fig. 3 shows the voltage applied to a memory cell MC when one memory cell MC in the memory cell array is selected for a write operation. The intersection of a word line and a bit line represents each memory cell MC.

[0063] The selected memory cell MC is memory cell A (selected cell). A write voltage Vwrite is applied to the word line connected to memory cell A. Also, 0 V is applied to the bit line connected to memory cell A.

[0064] Hereinafter, an example will be described in which a voltage (Vwrite / 2) that is half the write voltage is applied to the word line and bit line that are not connected to memory cell A.

[0065] The voltage applied to memory cells C (unselected cells) connected to word lines and bit lines not connected to memory cells A is 0 V. In other words, no voltage is applied.

[0066] On the other hand, a voltage (Vwrite / 2) that is half the write voltage Vwrite is applied to memory cell B (half-selected cell) connected to the word line or bit line connected to memory cell A. Therefore, a half-selection leakage current flows through memory cell B (half-selected cell).

[0067] In addition, as an alternative to the above, a voltage (Vwrite / 2) that is half the write voltage may be applied to the word line connected to memory cell A, a negative voltage (-Vwrite / 2) that is half the write voltage may be applied to the bit line, and 0V may be applied to the word line and bit line not connected to memory cell A.

[0068] 4 is an explanatory diagram of the current-voltage characteristics of the switching element of the first embodiment, in which the horizontal axis represents the voltage applied to the switching element and the vertical axis represents the current flowing through the switching element.

[0069] The switching element has a nonlinear current-voltage characteristic in which the current rises sharply at a threshold voltage Vth, which is, for example, 0.5V or more and 3V or less.

[0070] The write voltage Vwrite is set so that it is higher than the threshold voltage Vth and half the write voltage Vwrite (Vwrite / 2) is lower than the threshold voltage. The current that flows through the switching element when the write voltage Vwrite is applied is the on-current (Ion in Figure 4). The current that flows through the switching element when half the write voltage Vwrite (Vwrite / 2) is applied is the half-select leakage current (Ihalf in Figure 4).

[0071] The read voltage Vread of the memory cell MC is set to a voltage higher than the threshold voltage Vth and lower than the write voltage Vwrite, for example, as shown in Figure 4. Therefore, when reading from the memory cell MC, the half-selection leakage current flowing through the half-selected cells can also be suppressed.

[0072] A large half-selection leakage current, for example, leads to increased chip power consumption. Furthermore, for example, an increased voltage drop in the wiring prevents a sufficiently high voltage from being applied to the selected cell, making the write operation to the memory cell MC unstable. Furthermore, a small on-current, for example, leads to an insufficient current flowing through the selected cell, resulting in insufficient write to the memory cell MC. Therefore, the current-voltage characteristics of the switching element must achieve both a low half-selection leakage current and a high on-current.

[0073] Furthermore, the current-voltage characteristics of the switching element must be highly reliable, i.e., they must be able to suppress fluctuations in characteristics such as semi-selection leakage current and on-current when data is repeatedly written to the memory cell MC, thereby achieving high reliability.

[0074] 5 is a schematic cross-sectional view of a memory cell of a memory device of a first comparative embodiment, which corresponds to FIG. 2 of the first embodiment.

[0075] 5 , the memory cell MC of the first comparative example includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 140, and a resistance change layer 50. The switching layer 140 includes a conductor 40x. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0076] The memory cell MC of the memory device of the first comparative embodiment differs from the memory cell MC of the first embodiment in that the switching layer 140 does not contain the second material. The switching layer 140 of the memory cell MC of the memory device of the first comparative embodiment has conductors 40x, which are a third material, dispersed in a first base material, which is a first material.

[0077] The memory device of the first comparative example has a problem in that the characteristics fluctuate greatly when data is repeatedly written to the memory cell MC. The characteristic fluctuation of the memory device of the first comparative example is thought to be caused by the movement and aggregation of the conductors 40x in the switching layer 140. The aggregation of the conductors 40x is thought to be the cause of the formation of a leakage current path between the lower electrode 10 and the intermediate electrode 30.

[0078] 6 is a schematic cross-sectional view of a memory cell of a memory device of a second comparative embodiment, which corresponds to FIG. 2 of the first embodiment.

[0079] 6, the memory cell MC of the second comparative example includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 240, and a resistance change layer 50. The switching layer 240 includes a conductor 40x. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0080] The memory cell MC of the memory device of the second comparative embodiment differs from the memory cell MC of the first embodiment in that the switching layer 240 does not contain the first material. The switching layer 240 of the memory cell MC of the memory device of the second comparative embodiment has conductors 40x, which are a third material, dispersed in a second base material, which is a second material.

[0081] In the memory device of the second comparative example, the characteristic fluctuations caused by repeatedly writing data to the memory cells MC are suppressed compared to the memory device of the first comparative example. The suppression of the characteristic fluctuations in the memory device of the second comparative example is believed to be due to the suppression of movement of the conductors 40x in the switching layer 240.

[0082] The charge of the third substance when it exists in the first substance is greater than the charge of the third substance when it exists in the second substance, or in other words, the charge of the third substance when it exists in the second substance is less than the charge of the third substance when it exists in the first substance.

[0083] In the memory device of the second comparative example, the charge amount of the third substance is small, which is thought to suppress the movement of the third substance due to an electric field when a voltage is applied between the lower electrode 10 and the intermediate electrode 30. In other words, it is thought to suppress the movement of the conductor 40x within the switching layer 240. Therefore, it is thought that the aggregation of the conductor 40x is suppressed, and the formation of a path for leakage current between the lower electrode 10 and the intermediate electrode 30 is suppressed.

[0084] On the other hand, the band gap of the second material is smaller than the band gap of the first material. Therefore, the memory device of the second comparative embodiment has a larger semi-selection leakage current than the memory device of the first comparative embodiment. Therefore, the memory device of the second comparative embodiment has problems such as increased chip power consumption and unstable write operations to memory cells MC compared to the memory device of the first comparative embodiment.

[0085] In the memory device of the first embodiment, the switching layer 40 includes a first region 41 containing a first material and a second region 42 containing a second material. The second region 42 containing the second material includes a conductor 40x.

[0086] In the memory device of the first embodiment, the second region 42, which reduces the amount of charge on the conductor 40x, suppresses the movement and aggregation of the conductor 40x. Also, the first region 41, which has a large band gap, reduces the semi-select leakage current. Therefore, a highly reliable switching element with a small semi-select leakage current can be realized.

[0087] (First Modification) The memory device of the first variant of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer includes a first portion and a second portion, and the first portion includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0088] 7 is a schematic cross-sectional view of a memory cell of a memory device according to a first modification of the first embodiment, and corresponds to FIG. 2 of the first embodiment.

[0089] The bottom electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0090] The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0091] The second portion 12 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0092] In the memory device of the first modification of the first embodiment, the first portion 11 of the lower electrode 10 contains at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. Furthermore, the first portion 11 is not in contact with the switching layer 40, thereby suppressing desorption of oxygen (O) from the switching layer 40 and suppressing deterioration of the characteristics of the switching element.

[0093] As described above, according to the first modification of the first embodiment, a switching element that is highly reliable and has a small semi-selection leakage current can be realized, similar to the first embodiment.

[0094] (Second Modification) The memory device of the second variant of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer includes a first portion and a second portion, the first portion including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); the second conductive layer includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti); and the third conductive layer includes a third portion and a fourth portion, the fourth portion including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0095] 8 is a schematic cross-sectional view of a memory cell of a memory device according to a second modification of the first embodiment, and corresponds to FIG. 2 of the first embodiment.

[0096] The bottom electrode 10 includes a first portion 11 and a second portion 12. The second portion 12 is provided between the first portion 11 and the switching layer 40.

[0097] The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0098] The second portion 12 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0099] The upper electrode 20 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 includes, for example, a boride of the above element. The upper electrode 20 includes, for example, at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0100] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0101] The third portion 31 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0102] The fourth portion 32 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 includes, for example, a boride of the above element. The fourth portion 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0103] In the memory device of the second modification of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. Furthermore, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not in contact with the switching layer 40, thereby suppressing desorption of oxygen (O) from the switching layer 40 and suppressing deterioration of the characteristics of the switching element.

[0104] As described above, according to the second modification of the first embodiment, a switching element that is highly reliable and has a small semi-selection leakage current can be realized, similar to the first embodiment.

[0105] (Third Modification) A memory device of the third variant of the first embodiment differs from the memory device of the first embodiment in that the first conductive layer includes a first portion, a second portion, and a fifth portion, the first portion including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), the second conductive layer including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), and the third conductive layer includes a third portion and a fourth portion, the fourth portion including at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti).

[0106] 9 is a schematic cross-sectional view of a memory cell of a memory device according to a third modification of the first embodiment, and corresponds to FIG. 2 of the first embodiment.

[0107] The lower electrode 10 includes a first portion 11, a second portion 12, and a fifth portion 13. The second portion 12 is provided between the first portion 11 and the switching layer 40. The first portion 11 is provided between the fifth portion 13 and the second portion 12.

[0108] The first portion 11 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The first portion 11 includes, for example, a boride of the above element. The first portion 11 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0109] The second portion 12 and the fifth portion 13 include, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0110] The upper electrode 20 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The upper electrode 20 includes, for example, a boride of the above element. The upper electrode 20 includes, for example, at least one material selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0111] The intermediate electrode 30 includes a third portion 31 and a fourth portion 32. The third portion 31 is provided between the fourth portion 32 and the switching layer 40.

[0112] The third portion 31 includes, for example, at least one material selected from the group consisting of carbon, carbon nitride, tungsten, tungsten carbide, and tungsten nitride.

[0113] The fourth portion 32 includes at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti). The fourth portion 32 includes, for example, a boride of the above element. The fourth portion 32 includes, for example, at least one substance selected from the group consisting of hafnium, hafnium boride, aluminum magnesium boride, zirconium, zirconium boride, and titanium boride.

[0114] In the memory device of the third modification of the first embodiment, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 contain at least one element selected from hafnium (Hf), aluminum (Al), magnesium (Mg), zirconium (Zr), and titanium (Ti), thereby suppressing deterioration of the characteristics of the resistance change element. Furthermore, the first portion 11 of the lower electrode 10, the upper electrode 20, and the fourth portion 32 of the intermediate electrode 30 are not in contact with the switching layer 40, thereby suppressing desorption of oxygen (O) from the switching layer 40 and suppressing deterioration of the characteristics of the switching element.

[0115] As described above, according to the third modification of the first embodiment, a switching element that is highly reliable and has a small semi-selection leakage current can be realized, similar to the first embodiment.

[0116] (Fourth Modification)

[0117] 10 is a schematic cross-sectional view of a memory cell of a memory device according to a fourth modification of the first embodiment, and corresponds to FIG. 2 of the first embodiment.

[0118] 10 , the memory cell MC of the modification of the first embodiment includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 45, and a resistance change layer 50. The switching layer 45 includes a conductor 40x. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0119] The memory cell MC of the modification of the first embodiment differs from the memory cell MC of the first embodiment in that the second region 42 in the switching layer 45 is dispersed in the first region 41. The second region 42 is, for example, surrounded by the first region 41.

[0120] According to the fourth modification of the first embodiment, similarly to the first embodiment, a switching element with high reliability and small semi-selection leakage current can be realized.

[0121] According to the first embodiment and its modifications, a switching element having excellent characteristics such as high reliability and low semi-select leakage current can be realized. Therefore, according to the first embodiment and its modifications, a memory device having a switching element with excellent characteristics can be realized.

[0122] (Second embodiment) A memory device according to a second embodiment includes a memory cell including a first conductive layer, a second conductive layer, a third conductive layer disposed between the first and second conductive layers, a switching layer disposed between the first and third conductive layers, and a resistance change layer disposed between the third and second conductive layers. The switching layer includes at least one first region including a first material and at least one second region including a second material and a third material and having a chemical composition different from that of the first region. The third material includes zinc (Zn) and an element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te). The combination of the first material and the second material may be a first combination in which the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al) and oxygen (O); or a second combination in which the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of silicon (Si), aluminum (Al), and gallium (Ga) and nitrogen (N); or a first material includes silicon (Si) and nitrogen (N), and the second material includes zirconium (Zr), hafnium (Hf) a third combination including an element selected from the group consisting of silicon (Si) and nitrogen (N) and an element selected from the group consisting of aluminum (Al) and nitrogen (N); a fourth combination including a first material including silicon (Si) and nitrogen (N) and an element selected from the group consisting of aluminum (Al) and nitrogen (N); a fifth combination including a first material including aluminum (Al) and nitrogen (N) and an element selected from the group consisting of zirconium (Zr) and hafnium (Hf) and an element selected from the group consisting of oxygen (O); or a sixth combination including a first material including zirconium (Zr) and oxygen (O) and an element selected from the group consisting of hafnium (Hf) and oxygen (O). The first region may or may not include zinc (Zn), and the atomic concentration of zinc (Zn) in the second region is higher than the atomic concentration of zinc (Zn) in the first region.

[0123] The storage device of the second embodiment has a different combination of the first substance and the second substance from that of the storage device of the first embodiment. Hereinafter, some of the description overlapping with the first embodiment may be omitted.

[0124] Fig. 11 is a schematic cross-sectional view of a memory cell of a memory device according to the second embodiment, which corresponds to Fig. 2 of the first embodiment.

[0125] 11 , the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 48, and a resistance change layer 50. The switching layer 48 includes a first region 41, a second region 42, and a conductor 40x. The resistance change layer 50 includes a fixed layer 51, a tunnel layer 52, and a free layer 53.

[0126] The switching layer 48 includes at least one first region 41 and at least one second region 42. As shown in Fig. 11, the first region 41 and the second region 42 are, for example, arranged alternately in a first direction.

[0127] The switching layer 48 includes a first material, a second material, and a third material, which are the main components of the switching layer 48.

[0128] The first region 41 includes a first material, and the second region 42 includes a second material and a third material.

[0129] The combination of the first material and the second material of the switching layer 48 is one combination selected from the group consisting of the first combination, the second combination, the third combination, the fourth combination, the fifth combination, and the sixth combination shown below.

[0130] The first combination is a combination in which the first material includes silicon (Si) and oxygen (O), and the second material includes oxygen (O) and one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al). The first material is, for example, silicon oxide. The second material is, for example, zirconium oxide, hafnium oxide, titanium oxide, or aluminum oxide.

[0131] The second combination is a combination in which the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of silicon (Si), aluminum (Al), and gallium (Ga) and nitrogen (N). The first material is, for example, silicon oxide. The second material is, for example, silicon nitride, aluminum nitride, or gallium nitride.

[0132] The third combination is a combination in which the first material includes silicon (Si) and nitrogen (N), and the second material includes one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al) and oxygen (O). The first material is, for example, silicon nitride. The second material is, for example, zirconium oxide, hafnium oxide, titanium oxide, or aluminum oxide.

[0133] A fourth combination is a combination in which the first material includes silicon (Si) and nitrogen (N) and the second material includes aluminum (Al) and nitrogen (N). The first material is, for example, silicon nitride. The second material is, for example, aluminum nitride.

[0134] A fifth combination is a combination in which the first material includes aluminum (Al) and nitrogen (N), and the second material includes an element selected from the group consisting of zirconium (Zr) and hafnium (Hf) and oxygen (O). The first material is, for example, aluminum nitride. The second material is, for example, zirconium oxide or hafnium oxide.

[0135] A sixth combination is a combination in which the first material includes zirconium (Zr) and oxygen (O), and the second material includes hafnium (Hf) and oxygen (O). The first material is, for example, zirconium oxide. The second material is, for example, hafnium oxide.

[0136] The first substance includes oxygen (O) or nitrogen (N). The first substance is, for example, an oxide or a nitride.

[0137] The second material includes oxygen (O) or nitrogen (N). The second material is, for example, an oxide or a nitride.

[0138] The third substance includes one element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and zinc (Zn).

[0139] The third material is an electrical conductor, such as zinc sulfide, zinc selenide, or zinc telluride.

[0140] The first material is a first matrix of the switching layer 40. The second material is a second matrix of the switching layer 40.

[0141] The switching layer 40 includes a conductor 40x. The conductor 40x is included in the second region 42. The conductor 40x is, for example, dispersed in a second base material of the second region 42. The conductor 40x may or may not be included in the first region 41. The abundance ratio of the conductor 40x in the second region 42 is higher than the abundance ratio of the conductor 40x in the first region 41. The abundance ratio is, for example, a molar ratio.

[0142] The conductor 40x includes a third material, and is, for example, zinc sulfide, zinc selenide, or zinc telluride.

[0143] The first region 41 may or may not contain zinc (Zn). The atomic concentration of zinc (Zn) in the second region 42 is higher than the atomic concentration of zinc (Zn) in the first region 41. The atomic concentration of zinc (Zn) in the second region 42 is, for example, 10 times or more and 100 times or less than the atomic concentration of zinc (Zn) in the first region 41.

[0144] In the switching layer 40, the sum of the atomic concentrations of the first element, the second element, the third element, zinc (Zn), and one element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) is, for example, 80% or more and 100% or less.

[0145] The band gap of the second material is smaller than the band gap of the first material. The band gap of the first material contained in the first region 41 and the band gap of the second material contained in the second region 42 can be measured using, for example, EELS.

[0146] Furthermore, when a third substance exists in a first substance, the charge amount of the third substance is greater than the charge amount of the third substance when the third substance exists in a second substance. The charge amount of the third substance can be calculated, for example, by first-principles calculation.

[0147] According to the second embodiment, a switching element having excellent characteristics such as high reliability and low semi-select leakage current can be realized, similar to the first embodiment, and therefore, according to the second embodiment, a memory device having a switching element with excellent characteristics can be realized.

[0148] (Third embodiment) The storage device of the third embodiment differs from the storage device of the first embodiment in that it is a resistance change memory (ReRAM). In the following, some of the description overlapping with the first embodiment will be omitted.

[0149] 12 is a schematic cross-sectional view of a memory cell in a memory device according to Embodiment 3. Fig. 12 shows a cross section of one memory cell MC indicated by a dotted circle, for example, in the memory cell array 100 of Fig. 1.

[0150] 12, the memory cell MC includes a lower electrode 10, an upper electrode 20, an intermediate electrode 30, a switching layer 40, and a resistance change layer 50. The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

[0151] The lower electrode 10 is an example of a first conductive layer, the upper electrode 20 is an example of a second conductive layer, and the intermediate electrode 30 is an example of a third conductive layer.

[0152] The lower electrode 10, the switching layer 40, and the intermediate electrode 30 constitute a switching element of the memory cell MC. The intermediate electrode 30, the resistance change layer 50, and the upper electrode 20 constitute a resistance change element of the memory cell MC.

[0153] The configuration of the switching layer 40 is the same as that of the storage device of the first embodiment.

[0154] The resistance change layer 50 includes a high resistance layer 50x and a low resistance layer 50y.

[0155] The high-resistance layer 50x is, for example, a metal oxide, such as aluminum oxide, hafnium oxide, zirconium oxide, tantalum oxide, or niobium oxide.

[0156] The low resistance layer 50y is, for example, a metal oxide, such as titanium oxide, niobium oxide, tantalum oxide, or tungsten oxide.

[0157] The resistance change layer 50 has a function of storing data by changing resistance, and has a characteristic that the electrical resistance of the resistance change layer 50 changes when a predetermined voltage is applied, for example.

[0158] Applying a voltage to the resistance change layer 50 causes the resistance change layer 50 to change from a high resistance state to a low resistance state, or from a low resistance state to a high resistance state. Application of a voltage to the resistance change layer 50 causes oxygen ions to move between the high resistance layer 50x and the low resistance layer 50y, changing the amount of oxygen vacancies (oxygen vacancies) in the low resistance layer 50y. The conductivity of the resistance change layer 50 changes depending on the amount of oxygen vacancies in the low resistance layer 50y. The low resistance layer 50y is a so-called vacancy modulated conductive oxide.

[0159] For example, a high resistance state is defined as data “1” and a low resistance state is defined as data “0.” The memory cell MC can store one bit of data, “0” or “1.”

[0160] As described above, according to the memory device of the third embodiment, a switching element having excellent characteristics such as high reliability and low semi-select leakage current can be realized, similar to the first embodiment. Therefore, according to the third embodiment, a memory device having a switching element with excellent characteristics can be realized.

[0161] (Fourth embodiment) A fourth embodiment of the memory device includes a memory cell including a first conductive layer, a second conductive layer, and a memory layer disposed between the first conductive layer and the second conductive layer. The memory layer includes at least one first region and at least one second region having a chemical composition different from that of the first region. The first region includes a first substance including a first element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), and aluminum (Al), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te). The second region includes a second material including the first element, a third element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and having an atomic number greater than that of the second element, a fourth element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a fifth element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), and the first region may or may not include the fourth element, and the atomic concentration of the fourth element in the second region is greater than the atomic concentration of the fourth element in the first region.

[0162] The memory device of the fourth embodiment further includes a plurality of first wirings and a plurality of second wirings intersecting the plurality of first wirings, and the memory cell is provided in a region where one of the plurality of first wirings intersects with one of the plurality of second wirings.

[0163] The memory device of the fourth embodiment differs from the memory device of the first embodiment in that the memory cell does not include a third conductive layer and a resistance change layer, but includes a configuration similar to the switching layer of the first embodiment as a memory layer. Hereinafter, the description of the contents that overlap with the first embodiment will be partially omitted.

[0164] 13 is a schematic cross-sectional view of a memory cell in a memory device according to Embodiment 4. Fig. 13 shows a cross section of one memory cell MC indicated by a dotted circle, for example, in the memory cell array 100 of Fig. 1.

[0165] As shown in FIG. 13, the memory cell MC includes a lower electrode 10, an upper electrode 20, and a memory layer 60.

[0166] The lower electrode 10 is an example of a first conductive layer, and the upper electrode 20 is an example of a second conductive layer.

[0167] The memory element of the memory cell MC is constituted by the lower electrode 10, the memory layer 60, and the upper electrode 20. The memory element of the memory cell MC has a switching function and a function of storing information.

[0168] The memory layer 60 has the same configuration as the switching layer 40 of the first embodiment.

[0169] The memory layer 60 has a nonlinear current-voltage characteristic in which the current rises sharply at a specific threshold voltage. The memory layer 60 also has a characteristic in which the threshold voltage changes with the application of a predetermined voltage. The memory layer 60 also has a characteristic in which the electrical resistance changes with the application of a predetermined voltage. In the fourth embodiment, the high resistance state is a state in which the resistance of the memory layer 60 at a read voltage is relatively high. In the fourth embodiment, the low resistance state is a state in which the resistance of the memory layer 60 at a read voltage is relatively low.

[0170] The memory layer 60 has a function of suppressing an increase in semi-selection leakage current flowing through semi-selected cells. The memory layer 60 also has a function of storing data by resistance change. The memory layer 60 is a single layer that realizes the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment.

[0171] FIG. 14 is an explanatory diagram of the current-voltage characteristics of the memory element of the fourth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In FIG. 14, the horizontal axis represents the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. FIG. 14 shows the current-voltage characteristics of the memory layer 60 of the fourth embodiment. FIG. 14 shows the current-voltage characteristics of the memory cell MC of the fourth embodiment.

[0172] The memory element of the fourth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Fig. 14, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0173] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0174] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0175] The first positive voltage side threshold voltage Vtpp is higher than the second positive voltage side threshold voltage Vtnp, and the first negative voltage side threshold voltage Vtpn is lower than the second negative voltage side threshold voltage Vtnn.

[0176] The memory element of the fourth embodiment can assume a high resistance state and a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, the memory element assumes a high resistance state on both the positive voltage side and the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the memory element assumes a low resistance state on both the positive voltage side and the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC can store one bit of data, "0" or "1".

[0177] 15 is an explanatory diagram of a first operation example of the memory operation of the storage device of the fourth embodiment. Fig. 15 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing the memory operation.

[0178] In the first operation example, the high resistance state and the low resistance state on the negative voltage side are utilized for memory operation. In the first operation example, the negative read voltage Vrn is used as the read voltage.

[0179] When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

[0180] When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

[0181] In the first operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0," current flows even if the positive write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

[0182] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the second positive threshold voltage Vtnp. The voltage Vwn / 2 is higher than the second negative threshold voltage Vtnn.

[0183] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0184] When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0185] In the first operation example, the application of the negative read voltage Vrn does not destroy data, whether the data of the selected cell is data "1" or data "0." In other words, in the first operation example, non-destructive read is possible whether the data of the selected cell is data "1" or data "0."

[0186] 16 is an explanatory diagram of a second example of memory operation of the storage device of the fourth embodiment. Fig. 16 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing memory operation.

[0187] In the second operation example, the high resistance state and the low resistance state on the positive voltage side are utilized for memory operation. In the second operation example, the positive side read voltage Vrp is used as the read voltage.

[0188] When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

[0189] When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

[0190] In the second operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0," current flows even if the positive write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

[0191] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the second positive threshold voltage Vtnp. The voltage Vwn / 2 is higher than the second negative threshold voltage Vtnn.

[0192] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0193] When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0194] In the second operation example, if the data of the selected cell is data "1", applying the positive read voltage Vrp does not destroy the data. In other words, in the second operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

[0195] On the other hand, if the data of the selected cell is data "0," applying a positive read voltage Vrp higher than the second positive threshold voltage Vtnp may cause a current to flow, potentially changing the data of the selected cell to data "1." In other words, in the second operation example, if the data of the selected cell is data "0," a destructive read may occur. Therefore, if the data of the selected cell is data "0," it may be necessary to rewrite data "0" to maintain the data of the selected cell after reading it.

[0196] (First Modification) The storage device of the first modified example of the fourth embodiment differs from the storage device of the fourth embodiment in that the current-voltage characteristics of the memory element are different.

[0197] FIG. 17 is an explanatory diagram of the current-voltage characteristics of a memory element according to the first modified example of the fourth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In FIG. 17, the horizontal axis represents the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. FIG. 17 shows the current-voltage characteristics of the memory layer 60 according to the first modified example of the fourth embodiment. FIG. 17 shows the current-voltage characteristics of a memory cell MC according to the first modified example of the fourth embodiment.

[0198] The memory element of the first modified example of the fourth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Fig. 17, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0199] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0200] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0201] The first positive voltage side threshold voltage Vtpp is lower than the second positive voltage side threshold voltage Vtnp, and the first negative voltage side threshold voltage Vtpn is higher than the second negative voltage side threshold voltage Vtnn.

[0202] The memory element of the first modified example of the fourth embodiment can be in a high resistance state or a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, the memory element is in a low resistance state on both the positive voltage side and the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the memory element is in a high resistance state on both the positive voltage side and the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC can store one bit of data, "0" or "1".

[0203] 18 is an explanatory diagram of a third operation example of the memory operation of the memory device of the first modified example of the fourth embodiment. Fig. 18 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing the memory operation.

[0204] In the third operation example, the high resistance state and the low resistance state on the negative voltage side are utilized for memory operation. In the third operation example, the negative read voltage Vrn is used as the read voltage.

[0205] When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

[0206] When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the second positive threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

[0207] In the third operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0," current flows even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

[0208] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the first positive threshold voltage Vtpp. The voltage Vwn / 2 is higher than the first negative threshold voltage Vtpn.

[0209] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0210] When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0211] In the third operation example, if the data of the selected cell is data "1", applying the negative read voltage Vrn does not destroy the data. In other words, in the third operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

[0212] On the other hand, if the data of the selected cell is data "0," applying a negative read voltage Vrn lower than the first negative threshold voltage Vtpn may cause a current to flow, potentially changing the data of the selected cell to data "1." In other words, in the third operation example, if the data of the selected cell is data "0," a destructive read may occur. Therefore, if the data of the selected cell is data "0," it may be necessary to rewrite data "0" to maintain the data of the selected cell after reading it.

[0213] 19 is an explanatory diagram of a fourth operation example of the memory operation of the memory device of the first modified example of the fourth embodiment. Fig. 19 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing the memory operation.

[0214] In the fourth operation example, the high resistance state and the low resistance state on the positive voltage side are utilized for memory operation. In the fourth operation example, the positive side read voltage Vrp is used as the read voltage.

[0215] When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

[0216] When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

[0217] In the fourth operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0," current flows even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

[0218] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the first positive threshold voltage Vtpp. The voltage Vwn / 2 is higher than the first negative threshold voltage Vtpn.

[0219] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0220] When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0221] In the fourth operation example, the application of the positive read voltage Vrp does not destroy data, whether the data of the selected cell is data "1" or data "0." In other words, in the fourth operation example, non-destructive read is possible whether the data of the selected cell is data "1" or data "0."

[0222] (Second Modification) The storage device of the second modified example of the fourth embodiment differs from the storage device of the fourth embodiment in that the current-voltage characteristics of the memory element are different.

[0223] FIG. 20 is an explanatory diagram of the current-voltage characteristics of a memory element according to the second modified example of the fourth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In FIG. 20, the horizontal axis represents the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. FIG. 20 shows the current-voltage characteristics of the memory layer 60 according to the second modified example of the fourth embodiment. FIG. 20 shows the current-voltage characteristics of a memory cell MC according to the second modified example of the fourth embodiment.

[0224] The memory element of the second modified example of the fourth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Fig. 20, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0225] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0226] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0227] The first positive voltage side threshold voltage Vtpp is lower than the second positive voltage side threshold voltage Vtnp, and the first negative voltage side threshold voltage Vtpn is lower than the second negative voltage side threshold voltage Vtnn.

[0228] The memory element of the second modified example of the fourth embodiment can assume a high resistance state and a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it assumes a low resistance state on the positive voltage side and a high resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it assumes a high resistance state on the positive voltage side and a low resistance state on the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC can store one bit of data, "0" and "1".

[0229] 21 is an explanatory diagram of a fifth operation example of the memory operation of the memory device of the second modified example of the fourth embodiment. Fig. 21 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing the memory operation.

[0230] In the fifth operation example, the high resistance state and the low resistance state on the negative voltage side are utilized for memory operation. In the fifth operation example, the negative read voltage Vrn is used as the read voltage.

[0231] When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

[0232] When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

[0233] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the first positive threshold voltage Vtpp. The voltage Vwn / 2 is higher than the second negative threshold voltage Vtnn.

[0234] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0235] When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0236] In the fifth operation example, the application of the negative read voltage Vrn does not destroy data, whether the data of the selected cell is data "1" or data "0." In other words, in the fifth operation example, non-destructive read is possible whether the data of the selected cell is data "1" or data "0."

[0237] 22 is an explanatory diagram of a sixth operation example of the memory operation of the memory device of the second modified example of the fourth embodiment. Fig. 22 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing the memory operation.

[0238] In the sixth operation example, the high resistance state and the low resistance state on the positive voltage side are utilized for memory operation. In the sixth operation example, the positive side read voltage Vrp is used as the read voltage.

[0239] When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the first negative voltage threshold voltage Vtpn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

[0240] When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the second positive voltage threshold voltage Vtnp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

[0241] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the first positive threshold voltage Vtpp. The voltage Vwn / 2 is higher than the second negative threshold voltage Vtnn.

[0242] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0243] When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0244] In the sixth operation example, the application of the positive read voltage Vrp does not destroy data, whether the data of the selected cell is data "1" or data "0." In other words, in the sixth operation example, non-destructive read is possible whether the data of the selected cell is data "1" or data "0."

[0245] (Third Modification) The storage device of the third modified example of the fourth embodiment differs from the storage device of the fourth embodiment in that the current-voltage characteristics of the memory element are different.

[0246] FIG. 23 is an explanatory diagram of the current-voltage characteristics of a memory element according to the third modified example of the fourth embodiment. The horizontal axis represents the voltage applied to the memory element, and the vertical axis represents the current flowing through the memory element. In FIG. 23, the horizontal axis represents the voltage applied to the upper electrode 20 with respect to the potential of the lower electrode 10. FIG. 23 shows the current-voltage characteristics of the memory layer 60 according to the third modified example of the fourth embodiment. FIG. 23 shows the current-voltage characteristics of a memory cell MC according to the third modified example of the fourth embodiment.

[0247] The memory element of the third modified example of the fourth embodiment exhibits different current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 and when a predetermined negative voltage is applied to the upper electrode 20. In Fig. 23, the current-voltage characteristics when a predetermined positive voltage is applied to the upper electrode 20 are shown by a solid line, and the current-voltage characteristics when a predetermined negative voltage is applied to the upper electrode 20 are shown by a dotted line.

[0248] When a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the first positive voltage side threshold voltage Vtpp. Also, when a predetermined positive voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the first negative voltage side threshold voltage Vtpn.

[0249] On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the positive voltage side at the second positive voltage side threshold voltage Vtnp. Also, when a predetermined negative voltage is applied to the upper electrode 20, the current rises sharply on the negative voltage side at the second negative voltage side threshold voltage Vtnn.

[0250] The first positive voltage side threshold voltage Vtpp is higher than the second positive voltage side threshold voltage Vtnp, and the first negative voltage side threshold voltage Vtpn is higher than the second negative voltage side threshold voltage Vtnn.

[0251] The memory element of the third modified example of the fourth embodiment can assume a high resistance state and a low resistance state on both the positive voltage side and the negative voltage side. When a predetermined positive voltage is applied to the upper electrode 20, it assumes a high resistance state on the positive voltage side and a low resistance state on the negative voltage side. On the other hand, when a predetermined negative voltage is applied to the upper electrode 20, it assumes a low resistance state on the positive voltage side and a high resistance state on the negative voltage side. Hereinafter, the high resistance state is defined as data "1" and the low resistance state is defined as data "0". The memory cell MC can store one bit of data, "0" and "1".

[0252] 24 is an explanatory diagram of a seventh operation example of the memory operation of the memory device of the third modified example of the fourth embodiment. Fig. 24 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the negative read voltage Vrn when performing the memory operation.

[0253] In the seventh operation example, the high resistance state and the low resistance state on the negative voltage side are utilized for memory operation. In the seventh operation example, the negative read voltage Vrn is used as the read voltage.

[0254] When writing data "1" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a high resistance state is realized on the negative voltage side, and data "1" is written to the selected cell.

[0255] When writing data "0" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is higher than the first positive threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a low resistance state is realized on the negative voltage side, and data "0" is written to the selected cell.

[0256] In the seventh operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0," current flows even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

[0257] Furthermore, in the seventh operation example, when writing data "0" to a selected cell, if the data stored in the selected cell is data "1," current flows even if the positive write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "0" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

[0258] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the second positive threshold voltage Vtnp. The voltage Vwn / 2 is higher than the first negative threshold voltage Vtpn.

[0259] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0260] When reading data from a selected cell, a negative read voltage Vrn is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0261] In the seventh operation example, if the data of the selected cell is data "1", applying the negative read voltage Vrn does not destroy the data. In other words, in the seventh operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

[0262] On the other hand, if the data of the selected cell is data "0," applying a negative read voltage Vrn lower than the first negative threshold voltage Vtpn may cause a current to flow, potentially changing the data of the selected cell to data "1." In other words, in the seventh operation example, if the data of the selected cell is data "0," a destructive read may occur. Therefore, if the data of the selected cell is data "0," it may be necessary to rewrite data "0" to maintain the data of the selected cell after reading it.

[0263] 25 is an explanatory diagram of an eighth operation example of the memory operation of the memory device of the third modified example of the fourth embodiment. Fig. 25 shows the positive write voltage Vwp, half the voltage of the positive write voltage Vwp (Vwp / 2), the negative write voltage Vwn, half the voltage of the negative write voltage Vwn (Vwn / 2), and the positive read voltage Vrp when performing the memory operation.

[0264] In the eighth operation example, the high resistance state and the low resistance state on the positive voltage side are utilized for memory operation. In the eighth operation example, the positive side read voltage Vrp is used as the read voltage.

[0265] When writing data "1" to the selected cell, a positive write voltage Vwp is applied to the upper electrode 20. The positive write voltage Vwp is a voltage higher than the first positive voltage threshold voltage Vtpp. By applying the positive write voltage Vwp to the upper electrode 20, a high resistance state is realized on the positive voltage side, and data "1" is written to the selected cell.

[0266] When writing data "0" to the selected cell, a negative write voltage Vwn is applied to the upper electrode 20. The negative write voltage Vwn is a voltage lower than the second negative voltage threshold voltage Vtnn. By applying the negative write voltage Vwn to the upper electrode 20, a low resistance state is realized on the positive voltage side, and data "0" is written to the selected cell.

[0267] In the eighth operation example, when writing data "1" to a selected cell, if the data stored in the selected cell is data "0," current flows even if the positive write voltage Vwp is lower than the first positive voltage side threshold voltage Vtpp, as long as it is higher than the second positive voltage side threshold voltage Vtnp. Therefore, there is a possibility that data "1" can be written. Therefore, for example, by setting the positive write voltage Vwp to a voltage between the second positive voltage side threshold voltage Vtnp and the first positive voltage side threshold voltage Vtpp, it is possible to achieve low power consumption or high reliability of the memory device.

[0268] In the eighth operation example, when writing data "0" to a selected cell, if the data stored in the selected cell is data "1," current flows even if the negative write voltage Vwn is higher than the second negative voltage side threshold voltage Vtnn, as long as it is lower than the first negative voltage side threshold voltage Vtpn. Therefore, there is a possibility that data "0" can be written. Therefore, for example, by setting the negative write voltage Vwn to a voltage between the second negative voltage side threshold voltage Vtnn and the first negative voltage side threshold voltage Vtpn, it is possible to achieve low power consumption or high reliability of the memory device.

[0269] When a positive write voltage Vwp is applied to a selected cell, a voltage Vwp / 2 is applied to the semi-selected cells. When a negative write voltage Vwn is applied to a selected cell, a voltage Vwn / 2 is applied to the semi-selected cells. The voltage Vwp / 2 is lower than the second positive threshold voltage Vtnp. The voltage Vwn / 2 is higher than the first negative threshold voltage Vtpn.

[0270] Therefore, even when the half-selected cells are in a low resistance state, the half-selection leakage current flowing through the half-selected cells can be suppressed, and the memory element therefore also functions as a switching element.

[0271] When reading data from a selected cell, a positive read voltage Vrp is applied to the selected cell. The data in the selected cell can be determined by detecting the change in current or potential caused by the difference in current flow between data "1" and data "0."

[0272] In the eighth operation example, if the data of the selected cell is data "1", applying the positive read voltage Vrp does not destroy the data. In other words, in the eighth operation example, if the data of the selected cell is data "1", non-destructive reading is possible.

[0273] On the other hand, if the data of the selected cell is data "0," applying a positive read voltage Vrp higher than the second positive threshold voltage Vtnp may cause a current to flow, potentially changing the data of the selected cell to data "1." In other words, in the eighth operation example, if the data of the selected cell is data "0," a destructive read may occur. Therefore, if the data of the selected cell is data "0," it may be necessary to rewrite data "0" to maintain the data of the selected cell after reading it.

[0274] In the memory devices of the fourth embodiment and its modifications, the memory elements of the memory cells MC have a switching function and a function of storing information. The memory layer 60 is a single layer and realizes the functions of the switching layer 40 and the resistance change layer 50 of the first embodiment. The memory layer 60 of the fourth embodiment is a single layer and has both a switching function and a memory function, which allows the structure of the memory cells MC to be extremely simple.

[0275] Furthermore, the memory layer 60 of the memory device according to the fourth embodiment and its modifications has a configuration similar to that of the switching layer 40 of the first embodiment. Therefore, according to the fourth embodiment and its modifications, a memory device having switching elements with excellent characteristics can be realized, similar to the first embodiment.

[0276] It should be noted that the multiple current-voltage characteristics of the memory element shown in the fourth embodiment and its modifications can be realized, for example, by employing a memory layer 60 having an appropriate chemical composition.

[0277] Although the first and second embodiments have been described using a magnetoresistive memory as an example of a two-terminal storage device, and the third embodiment has been described using a resistance change memory as an example of a two-terminal storage device, the present invention can be applied to other two-terminal storage devices, such as a phase change memory (PCM) or a ferroelectric random access memory (FeRAM).

[0278] In the fourth embodiment, an example has been described in which the memory layer has a configuration similar to that of the switching layer of the first embodiment, but the memory layer may have a configuration similar to that of, for example, the switching layer of the fourth variant of the first embodiment or the switching layer of the second embodiment.

[0279] Although several embodiments of the present invention have been described above, these embodiments are presented as examples and are not intended to limit the scope of the invention. These novel embodiments may be embodied in various other forms, and various omissions, substitutions, and modifications may be made without departing from the spirit of the invention. For example, components of one embodiment may be replaced or changed with components of another embodiment. These embodiments and their modifications are included within the scope and spirit of the invention, and are also included in the scope of the invention and its equivalents as defined in the claims. [Explanation of symbols]

[0280] 10 Lower electrode (first conductive layer) 20 Upper electrode (second conductive layer) 30 Intermediate electrode (third conductive layer) 40 Switching Layer 41 First Area 42 Second Area 45 Switching Layer 48 Switching Layer 50 Resistive layer 60 Memory Layer 102 word line (first wiring) 103 Bit line (second wiring) MC memory cell

Claims

1. a first conductive layer; and a second conductive layer; and a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; a memory cell including a resistance change layer provided between the third conductive layer and the second conductive layer; the switching layer includes at least one first region and at least one second region having a chemical composition different from a chemical composition of the first region; the first region includes a first material including a first element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), and aluminum (Al), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te); the second region includes a second substance including the first element and a third element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and having an atomic number greater than that of the second element; and a third substance including a fourth element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a fifth element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), The storage device, wherein the first region contains or does not contain the fourth element, and the atomic concentration of the fourth element in the second region is higher than the atomic concentration of the fourth element in the first region.

2. 2. The memory device according to claim 1, wherein said first regions and said second regions are alternately arranged in a first direction from said first conductive layer toward said second conductive layer.

3. 2. The storage device of claim 1, wherein the first element is zirconium (Zr).

4. 2. The storage device according to claim 1, wherein said fourth element is zinc (Zn) and said fifth element is tellurium (Te).

5. 2. The storage device according to claim 1, wherein the first substance is a compound of the first element and the second element, the second substance is a compound of the first element and the third element, and the third substance is a compound of the fourth element and the fifth element.

6. The memory device according to claim 1 , wherein the resistance change layer includes a magnetic tunnel junction.

7. The resistance change layer changes its electrical resistance when a predetermined voltage is applied, 2. The storage device according to claim 1, wherein said switching layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage.

8. a plurality of first wirings; a plurality of second wirings intersecting the plurality of first wirings, 2. The memory device according to claim 1, wherein said memory cell is provided in a region where one of said plurality of first wirings intersects with one of said plurality of second wirings.

9. a first conductive layer; and a second conductive layer; and a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; a memory cell including a resistance change layer provided between the third conductive layer and the second conductive layer; the switching layer includes at least one first region including a first material and at least one second region including a second material and a third material and having a chemical composition different from a chemical composition of the first region; the third substance includes one element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and zinc (Zn); The combination of the first substance and the second substance is a first combination, wherein the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al) and oxygen (O); a second combination, wherein the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of silicon (Si), aluminum (Al), and gallium (Ga), and nitrogen (N); a third combination in which the first material includes silicon (Si) and nitrogen (N), and the second material includes one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al), and oxygen (O); a fourth combination in which the first material includes silicon (Si) and nitrogen (N) and the second material includes aluminum (Al) and nitrogen (N); A fifth combination in which the first material includes aluminum (Al) and nitrogen (N), and the second material includes one element selected from the group consisting of zirconium (Zr) and hafnium (Hf) and oxygen (O); and the first material is a combination selected from the group consisting of zirconium (Zr) and oxygen (O), and the second material is a sixth combination including hafnium (Hf) and oxygen (O); A memory device, wherein the first region may or may not contain zinc (Zn), and the atomic concentration of zinc (Zn) in the second region is higher than the atomic concentration of zinc (Zn) in the first region.

10. 10. The memory device according to claim 9, wherein the first regions and the second regions are alternately arranged in a first direction from the first conductive layer toward the second conductive layer.

11. a first conductive layer; and a second conductive layer; and a third conductive layer provided between the first conductive layer and the second conductive layer; a switching layer provided between the first conductive layer and the third conductive layer; a memory cell including a resistance change layer provided between the third conductive layer and the second conductive layer; the switching layer includes at least one first region and at least one second region having a chemical composition different from a chemical composition of the first region; the first region includes a first material; the second region includes a second material having a band gap smaller than that of the first material, and a third material including a first element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a second element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te); A storage device, wherein the first region may or may not contain the first element, and the atomic concentration of the first element in the second region is higher than the atomic concentration of the first element in the first region.

12. 12. The memory device according to claim 11, wherein the first regions and the second regions are alternately arranged in a first direction from the first conductive layer toward the second conductive layer.

13. the first substance contains oxygen (O) or nitrogen (N); The storage device of claim 11 , wherein the second material includes oxygen (O) or nitrogen (N).

14. 12. The storage device according to claim 11, wherein the amount of charge of the third material when the third material is present in the first material is greater than the amount of charge of the third material when the third material is present in the second material.

15. a first conductive layer; and a second conductive layer; and a memory layer provided between the first conductive layer and the second conductive layer, the memory layer includes at least one first region and at least one second region having a chemical composition different from a chemical composition of the first region; the first region includes a first material including a first element selected from the group consisting of zirconium (Zr), yttrium (Y), tantalum (Ta), lanthanum (La), cerium (Ce), titanium (Ti), hafnium (Hf), magnesium (Mg), and aluminum (Al), and a second element selected from the group consisting of oxygen (O), sulfur (S), selenium (Se), and tellurium (Te); the second region includes a second substance including the first element and a third element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and having an atomic number greater than that of the second element; and a third substance including a fourth element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a fifth element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te), The storage device, wherein the first region contains or does not contain the fourth element, and the atomic concentration of the fourth element in the second region is higher than the atomic concentration of the fourth element in the first region.

16. 16. The storage device according to claim 15, wherein said memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and said threshold voltage changes when a predetermined voltage is applied.

17. a first conductive layer; and a second conductive layer; and a memory layer provided between the first conductive layer and the second conductive layer, the memory layer includes at least one first region including a first material and at least one second region including a second material and a third material and having a chemical composition different from that of the first region; the third substance includes one element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te) and zinc (Zn); The combination of the first substance and the second substance is a first combination, wherein the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al) and oxygen (O); a second combination, wherein the first material includes silicon (Si) and oxygen (O), and the second material includes one element selected from the group consisting of silicon (Si), aluminum (Al), and gallium (Ga), and nitrogen (N); a third combination in which the first material includes silicon (Si) and nitrogen (N), and the second material includes one element selected from the group consisting of zirconium (Zr), hafnium (Hf), titanium (Ti), and aluminum (Al), and oxygen (O); a fourth combination in which the first material includes silicon (Si) and nitrogen (N) and the second material includes aluminum (Al) and nitrogen (N); a fifth combination in which the first material includes aluminum (Al) and nitrogen (N), and the second material includes one element selected from the group consisting of zirconium (Zr) and hafnium (Hf) and oxygen (O); and the first material is a combination selected from the group consisting of zirconium (Zr) and oxygen (O), and the second material is a sixth combination including hafnium (Hf) and oxygen (O); A memory device, wherein the first region may or may not contain zinc (Zn), and the atomic concentration of zinc (Zn) in the second region is higher than the atomic concentration of zinc (Zn) in the first region.

18. 18. The storage device according to claim 17, wherein said memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and said threshold voltage changes when a predetermined voltage is applied.

19. a first conductive layer; and a second conductive layer; and a memory layer provided between the first conductive layer and the second conductive layer, the memory layer includes at least one first region and at least one second region having a chemical composition different from a chemical composition of the first region; the first region includes a first material; the second region includes a second material having a band gap smaller than that of the first material, and a third material including a first element selected from the group consisting of zinc (Zn), tin (Sn), gallium (Ga), indium (In), bismuth (Bi), magnesium (Mg), and calcium (Ca), and a second element selected from the group consisting of sulfur (S), selenium (Se), and tellurium (Te); A storage device, wherein the first region may or may not contain the first element, and the atomic concentration of the first element in the second region is higher than the atomic concentration of the first element in the first region.

20. 20. The storage device according to claim 19, wherein said memory layer has a nonlinear current-voltage characteristic in which a current rises at a specific threshold voltage, and said threshold voltage changes when a predetermined voltage is applied.

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