Semiconductor device

Abstract

To provide a semiconductor device capable of effectively suppressing malfunction of a transistor by ensuring the reliability of NBTI.SOLUTION: A semiconductor device includes: an internal circuit which includes a P-channel MOS transistor inside thereof and which can be switched appropriately between an active state and a standby state; and a voltage supply circuit applying a bias voltage to a back gate of the P-channel MOS transistor. In the voltage supply circuit, the bias voltage is set to a first voltage in the active state, and is set to a second voltage lower than the first voltage in the standby state.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device, and more particularly to a semiconductor device that is effective in suppressing malfunction of a P-channel MOS (Metal Oxide Semiconductor) transistor. [Background technology]

[0002] It is known that P-channel MOS transistors (hereafter referred to as PMOS transistors) included in semiconductor integrated circuits suffer from a characteristic fluctuation called NBTI (Negative Bias Temperature Instability), which has become an even greater problem with the advancement of miniaturization. NBTI is a phenomenon in which the absolute value of the threshold voltage (ΔVth) of a PMOS transistor gradually increases when a negative gate bias is applied to the gate of the transistor. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-79916 Summary of the Invention [Problem to be solved by the invention]

[0004] If NBTI increases the threshold voltage of a transistor, it increases the possibility of malfunction, such as the transistor not turning on or the timing of turning on the transistor being delayed. However, in the past, sufficient measures have not been taken to prevent transistor degradation due to NBTI.

[0005] Specifically, when a circuit switches to an active state and the PMOS transistor operates after being in standby mode for a long period of time, it becomes more difficult to ensure reliability against NBTI, which can cause malfunctions in flip-flop circuits and SRAM memory circuits, potentially damaging the reliability of the semiconductor integrated circuit device.

[0006] The present invention provides a semiconductor device that can ensure reliability against NBTI and effectively suppress malfunction of transistors. [Means for solving the problem]

[0007] A semiconductor device according to the present invention includes an internal circuit that includes a P-channel MOS transistor and is switchable between an active state and a standby state as appropriate, and a voltage supply circuit that applies a bias voltage to a back gate of the P-channel MOS transistor, wherein the voltage supply circuit sets the bias voltage to a first voltage in the active state and sets the bias voltage to a second voltage lower than the first voltage in the standby state. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a semiconductor device that can ensure reliability against NBTI and effectively suppress malfunction of transistors. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a schematic diagram illustrating a semiconductor device 10 according to a first embodiment. [Figure 2] 1 is a circuit diagram showing an example of the detailed configuration of a semiconductor device 10 according to a first embodiment. [Figure 3] FIG. 10 is a circuit diagram showing an example of the detailed configuration of a semiconductor device 10 according to a second embodiment. [Figure 4] FIG. 10 is a circuit diagram showing an example of the detailed configuration of a semiconductor device 10 according to a third embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, functionally identical elements may be designated by the same numerals. Note that the accompanying drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. The descriptions in this specification are merely typical examples and are not intended to limit the scope or application of the present disclosure in any way.

[0011] Although the present embodiment has been described in sufficient detail to enable those skilled in the art to implement the present disclosure, it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0012] [First embodiment] A semiconductor device 10 according to a first embodiment will be described with reference to Figure 1. The semiconductor device 10 is generally composed of a voltage supply circuit 20 and an internal circuit 30. The internal circuit 30 is switched between an active state and a standby state as appropriate. The semiconductor device 10 receives a power supply voltage VI and a ground potential VSS from the outside via voltage terminals T1 and T3, and operates by supplying the power supply voltage VI to the voltage supply circuit 20 and the internal circuit 30.

[0013] The voltage supply circuit 20 receives a power supply voltage VI and generates and supplies a bias voltage Vb to be supplied to the back gate of a PMOS transistor MP included in the internal circuit 30. In addition to the PMOS transistor MP, the internal circuit 30 is configured to include other semiconductor elements (such as an N-channel MOS transistor) and electronic components (resistive elements, capacitive elements, etc.) not shown. The voltage supply circuit 20 can be configured to supply various voltages for the operation of the internal circuit 30 in addition to the bias voltage Vb.

[0014] A switching control signal Cas is supplied to the voltage supply circuit 20 and the internal circuit 30 via the control signal terminal T2 as a signal for switching the voltage supply circuit 20 and the internal circuit 30 between an active state and a standby state. The voltage supply circuit 20 and the internal circuit 30 receive this switching control signal Cas. When the switching control signal Cas goes high, the internal circuit 30 enters an active state, and the voltage supply circuit 20 generates a voltage for operating the internal circuit 30 in the active state and supplies it to the internal circuit 30. Conversely, when the switching control signal Cas goes low, the internal circuit 30 enters a standby state, and the voltage supply circuit 20 generates a voltage corresponding to the standby state and supplies it to the internal circuit 30. In response to the switching of the switching control signal Cas, as will be described later, the voltage supply circuit 20 is configured to be able to change the magnitude of the bias voltage Vb.

[0015] As mentioned above, with the advancement of miniaturization, the problem of PMOS transistor degradation due to NBTI is becoming more serious. It is known that degradation of PMOS transistors due to NBTI can be broadly divided into the following three types. (1) Fixed charge in the gate oxide film that does not recover (ΔVot) (2) Slow-recovery gate oxide / silicon (Si) substrate interface states (3) The time constant is small, about 10 -6 Highly recoverable hole traps in the film (ΔVh) that recover in about s (μs) Here, the hole trap in the film is, for example, 10 -6 In circuits that perform continuous AC operation, the component (ΔVh) that is very easy to recover (see (3) above) recovers during AC operation, so a significant reduction in the amount of degradation can be expected.

[0016] However, when a transistor is in standby mode, i.e., under DC stress, all of the above degradation modes must be taken into consideration, and if the amount of degradation due to NBTI becomes significant, it becomes difficult to ensure high reliability of the transistor. In particular, in the case of P-channel MOS transistors used in flip-flop circuits and SRAM (Static Random Access Memory) memory circuits, which are in standby mode for long periods, it is thought that DC stress will cause significant NBTI degradation.

[0017] The voltage supply circuit 20 switches the bias voltage Vb supplied to the back gate of the PMOS transistor in the internal circuit 30 between, for example, a power supply voltage VI (first voltage) and VI-ΔVa (second voltage: ΔVa is a positive value) in accordance with the switching of the internal circuit 30 between the active state and the standby state by the switching control signal Cas. When the switching control signal Cas is "H" (active state), the bias voltage Vb is set to the power supply voltage VI, and when the switching control signal Cas is "L" (standby state), the bias voltage Vb is set to VI-ΔVa, which is smaller than the power supply voltage VI. As a result, the gate-to-backgate voltage Vgb applied to the gate of the PMOS transistor in the conventional standby state is alleviated by at most |Vthp| (the threshold voltage of the PMOS transistor), thereby improving the reliability of the P-channel MOS transistor against NBTI.

[0018] 2 shows a specific example of the configuration of the voltage supply circuit 20 and the internal circuit 30. As shown in Fig. 2, the voltage supply circuit 20 is configured to include a differential amplifier 21, PMOS transistors M1 and M2, an inverter 24, and resistance elements 25 and 26. The differential amplifier 21, the PMOS transistor M1, and the resistance elements 25 and 26 form a step-down regulator that steps down the power supply voltage VI to a voltage VI-|Vthp| and supplies the voltage.

[0019] The differential amplifier 20 differentially amplifies a reference voltage VREF supplied from a reference voltage generating circuit (not shown) and a voltage VDET at a connection node N1 of resistor elements 25 and 26 connected in series between a voltage terminal T1 and a ground potential node, and outputs an output signal to a PMOS transistor M1. The PMOS transistor M1 is connected between the voltage terminal T1 supplied with a power supply voltage VI and the output terminal of the voltage supply circuit 20, and its conduction is controlled by receiving the output signal of the differential amplifier 20 at its gate.

[0020] The PMOS transistor M2 is connected between the voltage terminal T1 (power supply voltage VI) and the output terminal of the voltage supply circuit 20, and its gate receives an inverted signal of the switching control signal Cas, generated by an inverter 24. The PMOS transistor M2 is turned off (OFF) when the switching control signal Cas is "L" (standby state), but is turned on (ON) when the switching control signal Cas is "H" (active state), and outputs a voltage Vb=VI from the output terminal. That is, the voltage supply circuit 20 outputs an output signal Vb=VI via the PMOS transistor M2 when the switching control signal Cas="H" (active state), and outputs an output signal Vb=VO via the PMOS transistor M1 when the switching control signal Cas="L" (standby state). At its minimum, the voltage VO is VO=VI-|Vthp| (Vthp is the threshold voltage of the PMOS transistor M1).

[0021] 2 shows an SRAM cell as an example of the internal circuit 20. The SRAM cell is configured by cross-connecting a PMOS transistor M3, an NMOS transistor M4, a PMOS transistor M5, and an NMOS transistor M6, and connecting transfer gate transistors M7 and M8 between bit lines BL and NBL and the transistors M3 to M6. The gates of the transfer gate transistors M7 and M8 are connected to a word line WL.

[0022] In such an SRAM cell, when the voltage Vg applied to the gate of the PMOS transistor M5 is 0V and the SRAM cell is activated, the gate-to-backgate voltage Vgb of the PMOS transistor M5 becomes Vgb=VI. In the standby state, the gate-to-backgate voltage Vgb becomes Vgb=VI-|Vthp| at a minimum. As described above, according to the first embodiment, in the standby state, the gate-to-backgate voltage Vgb of the PMOS transistor of the internal circuit 20 can be relaxed by a maximum of |Vthp|, thereby improving the reliability of the PMOS transistor against NBTI.

[0023] [Second embodiment] A semiconductor device 10 according to the second embodiment will be described with reference to Fig. 3. This semiconductor device 10 differs from the first embodiment in the configuration of the voltage supply circuit 20. This voltage supply circuit 20 includes a step-down circuit made up of PMOS transistors M1 and M2 instead of the differential amplifier 21 that constitutes the step-down regulator.

[0024] The PMOS transistors M1 and M2 are connected in series between the voltage terminal T1 and the output terminal of the voltage supply circuit 20. The PMOS transistor M1 is connected between the voltage terminal T1 and the PMOS transistor M2, and a control signal Cas is input to its gate. The PMOS transistor M2 is connected between the PMOS transistor M1 and the output terminal of the voltage supply circuit 20 and is diode-connected, thereby dropping the power supply voltage VI by a threshold voltage |Vthp|.

[0025] Furthermore, a resistor element 25 and an NMOS transistor M10 are connected between the output terminal of the voltage supply circuit 20 and a ground potential node. An inverted signal obtained by inverting the switching control signal Cas using an inverter 24 is input to the gate of the NMOS transistor M10. With this configuration, the voltage supply circuit 20 outputs an output signal Vb=VI via the PMOS transistor M2 when the switching control signal Cas is “H” (active state), and outputs an output signal Vb=VO via the PMOS transistors M1 and M2 when the switching control signal Cas is “L” (standby state). At its minimum, the voltage VO is VO=VI−|Vthp| (Vthp is the threshold voltage of the PMOS transistor M1). In this way, the semiconductor device 10 of the second embodiment can achieve the same effects as the first embodiment.

[0026] [Third embodiment] A semiconductor device 10 according to a third embodiment will be described with reference to Fig. 4. The semiconductor device 10 according to the fourth embodiment shows an example in which a D flip-flop circuit 30B is provided as the internal circuit 30. The voltage supply circuit 20 is the same as in the previous embodiment, and therefore a duplicated description will be omitted.

[0027] The D flip-flop circuit 30B is made up of a D latch circuit DL1 made up of transistors M11 to M18, an inverter IN1 made up of transistors M19 to M20, a D latch circuit DL2 made up of transistors M21 to M28, and an inverter IN2 made up of transistors M29 to M30.

[0028] The transistors M11 to M14 that make up the D latch circuit DL1 are connected in series between the input terminal of the power supply voltage VI and a ground potential node, with the input signal D being input to the gates of the PMOS transistor M11 and the NMOS transistor M14, and clocks CB and C being input to the gates of the PMOS transistor M12 and the NMOS transistor M13, respectively. The transistors M15 to M18 are connected in series between the input terminal of the power supply voltage VI and the ground potential node, with the output signal of the inverter IN1 being supplied to the gates of the PMOS transistor M15 and the NMOS transistor M18, and clocks C and CB being input to the gates of the PMOS transistor M16 and the NMOS transistor M17, respectively. The D latch circuit DL2 has a similar configuration.

[0029] As in the previous embodiments, bias voltage Vb is supplied from voltage supply circuit 20 and supplied to the back gates of PMOS transistors M11, M12, M15, M16, M19, M21, M22, M25, M26, and M29. As in the previous embodiments, bias voltage Vb is set to power supply voltage VI when D flip-flop 20B is in the active state, and is set to a voltage lower than this (at least VI-|Vthp|) when in the standby state. This third embodiment can also achieve the same effects as the previous embodiments.

[0030] [others] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0031] 10...Semiconductor device 20...Voltage supply circuit 21...Differential amplifier 24...Inverter 25, 26...Resistance element M1 to M30: Transistors 30…Internal circuit T1, T3...Voltage terminals T2: Control signal terminal

Claims

1. an internal circuit including a P-channel MOS transistor and capable of being switched between an active state and a standby state as appropriate; a voltage supply circuit that applies a bias voltage to the back gate of the P-channel MOS transistor; Equipped with The voltage supply circuit In the active state, the bias voltage is set to a first voltage; In the standby state, the bias voltage is set to a second voltage lower than the first voltage. A semiconductor device characterized by:

2. the internal circuit and the voltage supply circuit are configured to receive a power supply voltage from an external source and to receive a switching control signal for switching between the active state and the standby state; The voltage supply circuit When the switching control signal designates the active state, the bias voltage is supplied to the internal circuit as the first voltage; When the switching control signal designates a standby state, the bias voltage is lowered to the second voltage and supplied to the internal circuit. The semiconductor device according to claim 1 .

3. 3. The semiconductor device according to claim 2, wherein said voltage supply circuit further comprises a step-down regulator that operates in said standby state to step down said power supply voltage to said second voltage and output the same as said bias voltage.

4. 4. The semiconductor device according to claim 3, wherein said voltage supply circuit further comprises a transistor that is rendered conductive in said active state to supply said power supply voltage as said first voltage to said internal circuitry.

5. 3. The semiconductor device according to claim 2, wherein said voltage supply circuit further comprises: a first transistor that is turned on in said standby state to supply said power supply voltage; and a second transistor that is diode-connected to drop said power supply voltage by a predetermined voltage.

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