Semiconductor device

Abstract

To provide a semiconductor device capable of suppressing the occurrence of dielectric breakdown.SOLUTION: A semiconductor device A10 includes a conductive support including leads 31 and 32 spaced apart from each other in a first direction x, a semiconductor element 11 mounted on the lead 31, a semiconductor element 14 mounted on the lead 32, a wire 41 electrically connecting the semiconductor element 11 and the semiconductor element 14, and a sealing resin 5 covering a portion of the conductive support, the semiconductor element 11, the semiconductor element 14, and the wire 41. The semiconductor element 11 includes a main surface 11a facing one side in a thickness direction z, a pad 112 disposed on the main surface 11a, and a seal ring portion 123 having a different potential from the pad 112. The wire 41 contains copper and is bonded to the pad 112. A distance d2 between the wire 41 and a seal ring portion 113 in the thickness direction z is greater than a predetermined distance d0, and a distance d11 between the pad 112 and the seal ring portion 113 in the first direction x is 100 μm or more and 300 μm or less.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] Semiconductor devices are used in inverter devices used in electric vehicles, hybrid vehicles, home appliances, and the like. The inverter device includes, for example, a semiconductor device and a switching element such as an IGBT (Insulated Gate Bipolar Transistor) or a MOSFET (Metal Oxide Semiconductor Field Effect Transistor). The semiconductor device has a control element and a drive element. In the inverter device, a control signal output from an ECU (Engine Control Unit) is input to the control element of the semiconductor device. The control element converts the control signal into a PWM (Pulse Width Modulation) control signal and transmits it to the drive element. The drive element drives, for example, six switching elements at desired timing based on the PWM control signal. As a result, three-phase AC power for driving a motor is generated from DC power from an on-board battery.

[0003] In the semiconductor device, the power supply voltage supplied to the control element may be low (approximately 5 V), while the power supply voltage supplied to the drive element may be high (approximately 600 V or higher). In this way, an isolation element is used as a means for transmitting signals between multiple elements with different power supply voltages. For example, Patent Document 1 discloses an example of a semiconductor device (intelligent power module) equipped with an isolation element. The intelligent power module described in Patent Document 1 includes a control circuit, an arm circuit (upper arm or lower arm), and an isolation transformer. The control circuit is composed of a CPU or logic IC, or a system LSI equipped with a logic IC and a CPU. The arm circuit is equipped with a gate driver IC. The isolation transformer transmits signals between the control circuit and the arm circuit in an isolated state. The CPU of the control circuit generates gate drive PWM signals that instruct the switching elements to be conductive or non-conductive, and transmits these gate drive PWM signals to the gate driver IC of the arm circuit via the isolation transformer. The gate driver IC then generates gate signals based on the gate drive PWM signals and drives the control terminals of the switching elements, thereby causing the switching elements to perform switching operations. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-49035

[0005] [overview] A plurality of elements with different power supply voltages may be mounted in a single package, resulting in a mixture of relatively high-voltage and low-voltage components within the same package. Such semiconductor devices are susceptible to dielectric breakdown. For example, dielectric breakdown tends to occur more easily as the potential difference between the power supply voltages increases. Dielectric breakdown can cause semiconductor devices to fail and reduce their reliability.

[0006] The present disclosure has been made in view of the above circumstances, and has an object to provide a semiconductor device capable of suppressing the occurrence of dielectric breakdown, a method for designing a semiconductor device capable of suppressing the occurrence of dielectric breakdown, and a method for manufacturing the semiconductor device.

[0007] The semiconductor device provided by the present disclosure comprises a conductive support including a first lead and a second lead arranged apart from each other in a first direction perpendicular to the thickness direction, a first semiconductor element mounted on the first lead, a second semiconductor element mounted on the second lead, a first wire electrically connecting the first semiconductor element and the second semiconductor element, and a sealing resin covering a part of the conductive support, the first semiconductor element, the second semiconductor element, and the first wire, wherein the first semiconductor element includes a main surface facing one side in the thickness direction, a first pad arranged on the main surface, and a seal ring portion having a different potential from the first pad, the first wire including copper and being bonded to the first pad, a first distance in the thickness direction between the first wire and the seal ring portion being greater than the distance d0 determined by equation (1), and a second distance in the first direction between the first pad and the seal ring portion being 100 μm or more and 300 μm or less.

number

[0008] [Figure 1] FIG. 1 is a plan view showing a semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a plan view of FIG. 1, in which the sealing resin is shown by imaginary lines. [Figure 3] FIG. 3 is a front view showing the semiconductor device according to the first embodiment. [Figure 4]FIG. 4 is a left side view showing the semiconductor device according to the first embodiment. [Figure 5] FIG. 5 is a right side view showing the semiconductor device according to the first embodiment. [Figure 6] FIG. 6 is a cross-sectional view taken along line VI-VI in FIG. [Figure 7] FIG. 7 is an enlarged cross-sectional view of a main part of FIG. [Figure 8] FIG. 8 is a cross-sectional view taken along line VIII-VIII in FIG. [Figure 9] FIG. 9 is a cross-sectional view of a main part showing the internal structure of one (insulating element) of the plurality of semiconductor elements of the semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 12] FIG. 12 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 13] FIG. 13 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 14] FIG. 14 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 15] FIG. 15 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 16] FIG. 16 is a cross-sectional view showing one step of the manufacturing method shown in FIG. [Figure 17] FIG. 17 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 18] FIG. 18 is a plan view showing a semiconductor device according to a first modified example of the first embodiment, in which the sealing resin is indicated by imaginary lines. [Figure 19] FIG. 19 is a cross-sectional view taken along line XIX-XIX in FIG. [Figure 20] FIG. 20 is an enlarged cross-sectional view of a main part of FIG. [Figure 21]FIG. 21 is an enlarged cross-sectional view of a main part of a semiconductor device according to a second modification of the first embodiment. [Figure 22] FIG. 22 is a plan view showing a semiconductor device according to the second embodiment. [Figure 23] FIG. 23 is a diagram in which the sealing resin is shown by imaginary lines in the plan view of FIG. [Figure 24] FIG. 24 is a cross-sectional view taken along line XXIV-XXIV in FIG. [Figure 25] FIG. 25 is an enlarged cross-sectional view of a main part of FIG. [Figure 26] FIG. 26 is a cross-sectional view of a main part showing the internal structure of two of the semiconductor elements (two insulating elements) of the semiconductor device according to the second embodiment. [Figure 27] FIG. 27 is a flowchart showing an example of a method for manufacturing a semiconductor device according to the second embodiment. [Figure 28] FIG. 28 is a plan view showing one step of the manufacturing method shown in FIG. [Figure 29] FIG. 29 is a cross-sectional view showing one step of the manufacturing method shown in FIG. [Figure 30] FIG. 30 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modification of the second embodiment. [Figure 31] FIG. 31 is a plan view showing the semiconductor device according to the third embodiment, in which the sealing resin is indicated by imaginary lines. [Figure 32] 32 is an enlarged cross-sectional view of a main part, in which a part of the cross section taken along the line XXXII-XXXII in FIG. 31 is enlarged. [Figure 33] FIG. 33 is an enlarged cross-sectional view of a main part of a semiconductor device according to a modification of the third embodiment. [Figure 34] FIG. 34 is a plan view showing the semiconductor device according to the fourth embodiment, in which the sealing resin is indicated by imaginary lines. [Figure 35] 35 is an enlarged cross-sectional view of a main part, in which a part of the cross section taken along the line XXXV-XXXV in FIG. 34 is enlarged.

[0009] [Detailed explanation] Preferred embodiments of the semiconductor device, semiconductor device design method, and semiconductor device manufacturing method of the present disclosure will be described below with reference to the drawings. In the following, identical or similar components will be assigned the same reference numerals and redundant description will be omitted.

[0010] In this disclosure, unless otherwise specified, "a certain object A is formed on a certain object B" and "a certain object A is formed on (an object) B" include "a certain object A is formed directly on a certain object B" and "a certain object A is formed on a certain object B with another object interposed between the certain object A and the certain object B." Similarly, "a certain object A is disposed on a certain object B" and "a certain object A is disposed on (an object) B" include "a certain object A is disposed directly on a certain object B" and "a certain object A is disposed on a certain object B with another object interposed between the certain object A and the certain object B" unless otherwise specified. Similarly, "a certain object A is located on (an object) B" includes "a certain object A is in contact with a certain object B and is located on (an object) B" and "a certain object A is located on (an object) B with another object interposed between the certain object A and the certain object B." Furthermore, unless otherwise specified, "object A overlaps object B when viewed from a certain direction" includes "object A overlaps the entirety of object B" and "object A overlaps part of object B." Furthermore, "object A (its material) contains material C" includes "object A (its material) is made of material C" and "object A (its material) is primarily made of material C." Furthermore, unless otherwise specified, "a certain surface A faces in direction B (one side or the other)" does not necessarily mean that surface A is at a 90° angle with respect to direction B, but also includes the case where surface A is tilted relative to direction B. Furthermore, unless otherwise specified, "a certain surface A is perpendicular to surface B" does not necessarily mean that surface A is at a 90° angle with respect to surface B, but also includes the case where surface A is tilted relative to surface B.

[0011] 1 to 9 show a semiconductor device A10 according to a first embodiment. As shown in these figures, the semiconductor device A10 includes a plurality of semiconductor elements 11, 13, and 14, a conductive support 3, a plurality of connection members 4, and a sealing resin 5. The conductive support 3 includes a plurality of leads 31 to 34, and the plurality of connection members 4 include a plurality of wires 41, 42, and 44 to 47.

[0012] In this disclosure, the following description will be made with reference to the thickness direction z, the first direction x, and the second direction y, which are perpendicular to each other. The thickness direction z corresponds to the thickness direction of each of the semiconductor elements 11, 12, 13, 14, the conductive support 3, and the sealing resin 5. One side of the thickness direction z may be referred to as the upper side, and the other side as the lower side. Note that terms such as "upper," "lower," "upper," "lower," "top surface," and "bottom surface" indicate the relative positional relationship of each component in the thickness direction z, and do not necessarily define the relationship with the direction of gravity. In the following description, "plan view" refers to a view along the thickness direction z.

[0013] The semiconductor device A10 is surface-mounted on a wiring board of an inverter device of, for example, an electric vehicle or a hybrid vehicle. The semiconductor device A10 controls the switching operation of a switching element such as an IGBT or a MOSFET. As can be seen from FIGS. 1 and 3 to 5, the package format of the semiconductor device A10 is an SOP (Small Outline Package). However, the package format of the semiconductor device A10 is not limited to an SOP.

[0014] The multiple semiconductor elements 11, 13, and 14 are elements that are the functional core of the semiconductor device A10. Each of the multiple semiconductor elements 11, 13, and 14 is composed of individual elements. In the first direction x, the semiconductor element 11 is located between the semiconductor elements 13 and 14. In a plan view, each of the multiple semiconductor elements 11, 13, and 14 has a rectangular shape with the long side extending in the second direction y. Note that the plan view shapes of the multiple semiconductor elements 11, 13, and 14 are not limited to the example shown in the figure.

[0015] The semiconductor element 13 is a controller (control element) of a gate driver that drives switching elements such as IGBTs, MOSFETs, etc. The semiconductor element 13 has a circuit that converts a control signal input from an ECU or the like into a PWM control signal, a transmission circuit that transmits the PWM control signal to the semiconductor element 11, and a reception circuit that receives an electrical signal from the semiconductor element 11.

[0016] 6, the semiconductor element 13 has a main surface 13a and a back surface 13b. The main surface 13a and the back surface 13b are spaced apart in the thickness direction z. The main surface 13a is the top surface of the semiconductor element 13, and the back surface 13b is the bottom surface of the semiconductor element 13. The back surface 13b faces the leads 31.

[0017] 2 and 6, the semiconductor element 13 has a plurality of pads 131. The plurality of pads 131 are provided on the main surface 13a (the surface facing the same direction as the mounting surface 311a of the island portion 311 of the lead 31, which will be described later). Each of the plurality of pads 131 contains, for example, aluminum (Al).

[0018] Semiconductor element 14 is a gate driver (drive element) for driving a switching element. Semiconductor element 14 has a receiving circuit for receiving a PWM control signal, a circuit for driving the switching element based on the PWM control signal, and a transmitting circuit for transmitting an electrical signal to semiconductor element 13. The electrical signal may be, for example, an output signal from a temperature sensor arranged near the motor.

[0019] 6, the semiconductor element 14 has a main surface 14a and a back surface 14b. The main surface 14a and the back surface 14b are spaced apart in the thickness direction z. The main surface 14a is the upper surface of the semiconductor element 14, and the back surface 14b is the lower surface of the semiconductor element 14. The back surface 14b faces the leads 32.

[0020] 2 and 6, the semiconductor element 14 has a plurality of pads 141. The plurality of pads 141 are provided on the main surface 14a (the surface facing the same direction as the mounting surface 321a of the island portion 321 of the lead 32, which will be described later). Each of the plurality of pads 141 contains, for example, aluminum.

[0021] The semiconductor element 11 is an element (insulating element) for transmitting PWM control signals and other electrical signals in an insulated state. The semiconductor element 11 is an inductive type. An example of an inductive type semiconductor element 11 is an insulating transformer. The semiconductor element 11 may be a capacitive type. An example of a capacitive type semiconductor element 11 is a capacitor. Alternatively, the semiconductor element 11 may be a photocoupler.

[0022] 6 to 9, the semiconductor element 11 has a main surface 11a and a back surface 11b. The main surface 11a and the back surface 11b are spaced apart in the thickness direction z. The main surface 11a is the upper surface of the semiconductor element 11, and the back surface 11b is the lower surface of the semiconductor element 11. The back surface 11b faces the leads 31.

[0023] The semiconductor device 11 includes a functional unit 115. The functional unit 115 has multiple sets of upper windings 115a and lower windings 115b inside, with an upper winding 115a and a lower winding 115b as one set. That is, the semiconductor device 11 has multiple upper windings 115a and multiple lower windings 115b. FIGS. 7 and 9 show one set of the multiple sets of upper windings 115a and lower windings 115b. For example, the multiple sets of upper windings 115a and lower windings 115b are arranged along the longitudinal direction (second direction y) of the semiconductor device 11. The set of upper windings 115a and lower windings 115b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, each set of upper windings 115a and lower windings 115b is planarly wound in a spiral shape. The upper winding 115a and the lower winding 115b of each pair are magnetically coupled. The semiconductor element 13 inductively couples the upper winding 115a and the lower winding 115b of each pair, thereby transmitting electrical signals in an insulated state.

[0024] As shown in FIGS. 2, 6, and 7, the semiconductor element 11 has a plurality of pads 111, 112. The plurality of pads 111, 112 are each provided on the main surface 13a. As shown in FIG. 7, each pad 111 is electrically connected to one of the plurality of lower windings 115b, and each pad 112 is electrically connected to one of the plurality of upper windings 115a. Each of the plurality of pads 111, 112 includes, for example, aluminum. As shown in FIGS. 2, 6, and 7, each of the plurality of pads 111 is bonded to one of the plurality of wires 42, and each of the plurality of pads 112 is bonded to one of the plurality of wires 41.

[0025] 2 and 7, the semiconductor element 11 includes a seal ring portion 113. In a plan view, the seal ring portion 113 is formed along each of the four outer peripheries of the semiconductor element 11 and surrounds the outer periphery of the circuit formation region. The seal ring portion 113 is made of, for example, copper (Cu), aluminum (Al), or the like. In this embodiment, as shown in FIGS. 7 and 9, the distance d11 between each pad 112 and the seal ring portion 113 in the first direction x (the direction in which the semiconductor element 14 is positioned relative to the semiconductor element 11) is, for example, not less than 100 μm and not more than 300 μm, but is not limited to this.

[0026] As shown in FIGS. 7 and 9, the semiconductor element 11 includes a semiconductor substrate 110, a protective film 1141, a passivation film 1142, a coil protective film 1143, a laminated structure 117, and a wiring portion 118.

[0027] The semiconductor substrate 110 may be a Si (silicon) substrate, a SiC (silicon carbide) substrate, or the like. The semiconductor element 11 may use an insulating substrate such as a ceramic substrate or a resin substrate instead of the semiconductor substrate 110. The seal ring portion 113 is provided upright on the semiconductor substrate 110 and penetrates the laminated structure 117 in the thickness direction z. In this embodiment, the potential of the seal ring portion 113 is approximately the same as the potential of the semiconductor substrate 110.

[0028] The stacked structure 117 is formed on the semiconductor substrate 110. As shown in FIG. 9, the stacked structure 117 includes a plurality of insulating layers 1171. The insulating layers 1171 are stacked on the upper surface of the semiconductor substrate 110. Except for the lowest insulating layer 1171 in contact with the upper surface of the semiconductor substrate 110, each insulating layer 1171 is formed of a stacked structure including an etching stopper film below and an interlayer insulating film above. The lowest insulating layer 1171 is formed only of an interlayer insulating layer. The etching stopper film may be, for example, a silicon nitride (SiN) film, a silicon carbide (SiC) film, or a silicon carbonitride (SiCN) film. The interlayer insulating film may be, for example, a silicon oxide (SiO) film. The dimension of the insulating layers 1171 in the thickness direction z is not particularly limited, but may be, for example, 2.4 μm. The thicknesses of the insulating layers 1171 may be the same or different.

[0029] The upper winding 115a and the lower winding 115b are formed on different insulating layers 1171 in the laminated structure 117 and face each other with at least one insulating layer 1171 between them. In the illustrated example, the lower winding 115b is formed on the fourth insulating layer 1171 from the semiconductor substrate 110, and the upper winding 115a is formed on the fifteenth insulating layer 1171, with ten insulating layers 1171 between it and the lower winding 115b. The number of insulating layers 1171 is not limited to the illustrated example and can be changed appropriately depending on, for example, the magnitude of the voltage applied to each pad 111 and each pad 112. The greater the number of insulating layers 1171 between the upper winding 115a and the lower winding 115b, the greater the breakdown voltage of the semiconductor element 11, but the greater the thickness of the semiconductor element 11 (the dimension in the thickness direction z). On the other hand, the fewer the number of insulating layers 1171 between the upper winding 115a and the lower winding 115b, the lower the dielectric strength voltage of the semiconductor element 11, but the thinner the semiconductor element 11 (the dimension in the thickness direction z) can be.

[0030] The wiring section 118 electrically connects the pads 111 and 112 to the upper winding 115a and the lower winding 115b. The wiring section 118 includes a plurality of through wires 1181 and lead wires 1182. As shown in FIG. 9, each of the through wires 1181 penetrates one or more insulating layers 1171 in the thickness direction z. In the example shown in FIG. 9, the plurality of through wires 1181 includes one that connects the pad 111 to the lead wire 1182, one that connects the lead wire 1182 to the lower winding 115b, and one that connects the pad 112 to the upper winding 115a. The lead wire 1182 is formed on the lowest insulating layer 1171. The lead wire 1182 forms part of the conduction path between the pad 111 and the lower winding 115b.

[0031] As shown in FIG. 9, the protective film 1141 is laminated on the laminated structure 117. As shown in FIG. 9, the passivation film 1142 is laminated on the protective film 1141. As shown in FIG. 9, the coil protective film 1143 is on the passivation film 1142 and selectively covers the region directly above the upper winding 115a. As can be seen from FIG. 9, pad openings are formed in the protective film 1141, the passivation film 1142, and the coil protective film 1143 to expose each pad 111 and each pad 112. The protective film 1141 includes, for example, SiO2 and has a thickness of approximately 150 nm. The passivation film 1142 includes, for example, SiN and has a thickness of approximately 1000 nm. The coil protective film 1143 includes, for example, polyimide and has a thickness of approximately 4000 nm. The constituent materials and thicknesses of the protective film 1141, the passivation film 1142, and the coil protective film 1143 are not limited to the above examples.

[0032] The structure of the semiconductor element 11 is not limited to the above example. For example, the upper winding 115a and the lower winding 115b are not limited to being planarly wound on a single insulating layer 1171, and may be wound three-dimensionally across multiple insulating layers 1171. However, in order to prevent the thickness of the semiconductor element 11 from increasing, it is preferable that the upper winding 115a and the lower winding 115b are planarly wound on a single insulating layer 1171.

[0033] In the semiconductor device A10, the semiconductor element 14 requires a power supply voltage higher than that required for the semiconductor element 13. This causes a potential difference between the semiconductor elements 13 and 14. Therefore, a first circuit including the semiconductor element 13 as a component and a second circuit including the semiconductor element 14 as a component are insulated from each other by the semiconductor element 11. The components of the first circuit include the semiconductor element 13, a lead 31 and multiple leads 33, multiple wires 42, 44, and 46, and a portion of the semiconductor element 11 (such as each pad 111 and each lower winding 115b). The components of the second circuit include the semiconductor element 14, a lead 32 and multiple leads 34, multiple wires 41, 45, and 47, and a portion of the semiconductor element 11 (such as each pad 112 and each upper winding 115a). The first circuit and the second circuit have relatively different potentials. In the semiconductor device A10, the potential of the second circuit is higher than the potential of the first circuit. Furthermore, semiconductor element 11 relays mutual signals between the first circuit and the second circuit. For example, in an inverter device for an electric vehicle or hybrid vehicle, the voltage applied to the ground of semiconductor element 13 is about 0 V, while the voltage applied to the ground of semiconductor element 14 may transiently reach 600 V or more. Depending on the specifications of the inverter device, the voltage applied to the ground of semiconductor element 14 may reach 3750 V or more.

[0034] The conductive support 3 forms a conductive path between the multiple semiconductor elements 11, 13, and 14 and the wiring board on which the semiconductor device A10 is mounted. As will be described in detail later, the conductive support 3 is obtained, for example, from the same lead frame. The lead frame is made of, for example, copper or a copper alloy, but may be made of other metal materials. As described above, the conductive support 3 has the lead 31, the lead 32, multiple leads 33, and multiple leads 34.

[0035] 1 and 2, the leads 31 and 32 are spaced apart from each other in the first direction x. In the semiconductor device A10, the semiconductor elements 11 and 13 are mounted on the lead 31, and the semiconductor element 14 is mounted on the lead 32.

[0036] As shown in FIG. 2, the lead 31 includes an island portion 311 and two terminal portions 312 .

[0037] As shown in FIGS. 6 and 7, the island portion 311 has a mounting surface 311a facing one side (upward) in the thickness direction z. As shown in FIG. 7, the semiconductor element 11 is bonded to the mounting surface 311a via a conductive bonding material 119, and the semiconductor element 13 is bonded to the mounting surface 311a via a conductive bonding material 139. The semiconductor substrate 110 of the semiconductor element 11 is at approximately the same potential as the island portion 311 via the conductive bonding material 119. Each of the conductive bonding materials 119, 139 is, for example, solder, metal paste, or sintered metal. The island portion 311 is covered with a sealing resin 5. In the illustrated example, the island portion 311 has a rectangular shape in a plan view. The thickness of the island portion 311 is, for example, 100 μm or more and 300 μm or less.

[0038] As shown in FIGS. 2, 6, and 7, a plurality of through holes 313 are formed in the island portion 311. Each of the plurality of through holes 313 penetrates the island portion 311 in the thickness direction z and extends along the second direction y. In a plan view, at least one of the plurality of through holes 313 is located between the semiconductor element 11 and the semiconductor element 13. The plurality of through holes 313 are arranged along the second direction y. Unlike the illustrated example, the island portion 311 does not necessarily have to have a plurality of through holes 313 formed therein.

[0039] As shown in FIG. 2, the two terminal portions 312 extend from both sides of the island portion 311 in the second direction y. The two terminal portions 312 are spaced apart from each other in the second direction y. At least one of the two terminal portions 312 is electrically connected to the ground of the semiconductor element 13 via one of the wires 46. Each of the two terminal portions 312 has a covered portion 312a and an exposed portion 312b. The covered portion 312a is connected to the island portion 311 and is covered with the sealing resin 5. The exposed portion 312b is connected to the covered portion 312a and is exposed from the sealing resin 5. In a plan view, the exposed portion 312b extends along the first direction x. As shown in FIG. 3, the exposed portion 312b is bent in a gull-wing shape when viewed in the second direction y. The surface of the exposed portion 312b may be plated with, for example, tin (Sn).

[0040] As shown in FIG. 2, the lead 32 has an island portion 321 and two terminal portions 322.

[0041] As shown in FIGS. 6 and 7, the island portion 321 has a mounting surface 321a facing one side (upward) in the thickness direction z. As shown in FIG. 7, the semiconductor element 14 is bonded to the mounting surface 321a via a conductive bonding material 149. Each conductive bonding material 129, 149 is, for example, solder, metal paste, or sintered metal. The island portion 321 is covered with a sealing resin 5. In the illustrated example, the island portion 321 has a rectangular shape in a plan view. The thickness of the island portion 321 is, like the island portion 311, for example, not less than 100 μm and not more than 300 μm.

[0042] As shown in FIG. 2, the two terminal portions 322 extend from both sides of the island portion 321 in the second direction y. The two terminal portions 322 are spaced apart from each other in the second direction y. At least one of the two terminal portions 322 is electrically connected to the ground of the semiconductor element 14 via one of the wires 47. Each of the two terminal portions 322 has a covered portion 322a and an exposed portion 322b. The covered portion 322a is connected to the island portion 321 and is covered with the sealing resin 5. The exposed portion 322b is connected to the covered portion 322a and is exposed from the sealing resin 5. In a plan view, the exposed portion 322b extends along the first direction x. As shown in FIG. 3, the exposed portion 322b is bent in a gull-wing shape when viewed in the second direction y. The surface of the exposed portion 322b may be, for example, tin-plated.

[0043] As shown in FIGS. 1 and 2 , the multiple leads 33 are located on the opposite side of the island portion 311 of the lead 31 from the island portion 321 of the lead 32 in the first direction x. The multiple leads 33 are arranged along the second direction y. At least one of the multiple leads 33 is electrically connected to the semiconductor element 13 via one of the multiple wires 44. The multiple leads 33 include multiple (six in the illustrated example) intermediate leads 33A and two side leads 33B. The two side leads 33B are located on either side of the multiple intermediate leads 33A in the second direction y. Each of the two side leads 33B is located between one of the two terminal portions 312 of the lead 31 and the intermediate lead 33A located closest to that terminal portion 312 in the second direction y.

[0044] As shown in FIGS. 2 and 6, each of the leads 33 (the intermediate leads 33A and the two side leads 33B) has a covering portion 331 and an exposed portion 332. The covering portion 331 is covered with the sealing resin 5. In the illustrated example, the dimension of each of the covering portions 331 of the two side leads 33B in the first direction x is larger than the dimension of each of the covering portions 331 of the intermediate leads 33A in the first direction x. As shown in FIGS. 2 and 6, the exposed portion 332 is connected to the covering portion 331 and exposed from the sealing resin 5. In a plan view, the exposed portion 332 extends along the first direction x. As can be seen from FIGS. 2 to 4, the exposed portion 332 is bent in a gull-wing shape when viewed along the second direction y. The shape of the exposed portion 332 is the same as the shape of the exposed portion 312b of each terminal portion 312 of the lead 31. The surface of the exposed portion 332 may be plated with tin, for example.

[0045] The shape, arrangement, and number of the multiple leads 33 are not limited to the example shown in the figure. For example, the number of the multiple leads 33 may be more or less than the example shown (eight). Also, for example, some of the multiple leads 33 may be arranged outward from either of the two terminal portions 312 of the lead 31.

[0046] As shown in FIGS. 1 and 2 , the multiple leads 34 are located on the opposite side of the island portion 311 of the lead 31 from the multiple leads 33 in the first direction x. The multiple leads 34 are arranged along the second direction y. At least one of the multiple leads 34 is electrically connected to the semiconductor element 14 via one of the multiple wires 45. The multiple leads 34 include multiple (six in the illustrated example) intermediate leads 34A and two side leads 34B. The two side leads 34B are located on either side of the multiple intermediate leads 34A in the second direction y. In the second direction y, one of the two terminal portions 322 of the lead 32 is located between one of the two side leads 34B and the intermediate lead 34A located closest to that side lead 34B.

[0047] As shown in FIGS. 2 and 6, each of the leads 34 (the intermediate leads 34A and the two side leads 34B) has a covering portion 341 and an exposed portion 342. The covering portion 341 is covered with the sealing resin 5. In the illustrated example, the dimension of each of the covering portions 341 of the two side leads 34B in the first direction x is larger than the dimension of each of the covering portions 341 of the intermediate leads 34A in the first direction x. As shown in FIGS. 2 and 6, the exposed portion 342 is connected to the covering portion 341 and exposed from the sealing resin 5. In a plan view, the exposed portion 342 extends along the first direction x. As can be seen from FIGS. 2, 3, and 5, the exposed portion 342 is bent in a gull-wing shape when viewed along the second direction y. The shape of the exposed portion 342 is the same as the shape of each of the exposed portions 322b of the two terminal portions 322 of the lead 32. The surface of the exposed portion 342 may be plated with tin, for example.

[0048] The shape, arrangement, and number of the leads 34 are not limited to the example shown in the figure. For example, the number of leads 34 may be more or less than the example shown (eight). Also, for example, each of the two side leads 34B may be located between one of the two terminal portions 322 of the lead 32 and the intermediate lead 34A located closest to that terminal portion 322 in the second direction y.

[0049] Each of the plurality of connection members 4 provides electrical continuity between two portions spaced apart from each other. As described above, the plurality of connection members 4 includes the plurality of wires 41, 42, 44 to 47. The plurality of connection members 4 may be bonding ribbons or plate-shaped metal members instead of the plurality of wires 41, 42, 44 to 47 (bonding wires).

[0050] Each of the wires 41, 42, 44 to 47 includes a metal material, which is copper or a copper alloy (e.g., a palladium-copper alloy). That is, each of the wires 41, 42, 44 to 47 is a copper wire. Each of the wires 41, 42, 44 to 47 may include a core material (e.g., including copper) and a surface layer (e.g., palladium) covering the core material. Note that in this embodiment, the wires 42, 44 to 47 may include gold, aluminum, or silver as the metal material instead of copper or a copper alloy.

[0051] As shown in FIGS. 2 and 7, each of the multiple wires 41 is bonded to one of the multiple pads 112 of the semiconductor element 11 and one of the multiple pads 141 of the semiconductor element 14. Each wire 41 electrically connects the semiconductor element 11 and the semiconductor element 14. The multiple wires 41 are arranged along the second direction y. Each of the multiple wires 41 straddles the island portion 311 of the lead 31 and the island portion 321 of the lead 32 in a plan view.

[0052] As shown in FIG. 7, each of the multiple wires 41 includes two bonding portions 411 and 412 and a loop portion 413. In each wire 41, the bonding portion 411 is bonded to one of the multiple pads 112. The bonding portion 412 is bonded to one of the multiple pads 141. The loop portion 413 connects the two bonding portions 411 and 412. The loop portion 413 rises from the bonding portion 411 in the thickness direction z, curves, and extends toward the bonding portion 412. The loop portion 413 has a rising section 413a. The rising section 413a is a portion of the loop portion 413 that is connected to the bonding portion 411 and rises in the thickness direction z. In the illustrated example (see FIG. 7), the rising section 413a extends along the thickness direction z. Each wire 41 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 112 and second bonded to one of the multiple pads 141. Unlike this example, each wire 41 may be formed by other techniques such as wedge bonding. When each wire 41 is formed by wedge bonding, the shape of the joint 411 will be substantially the same as the shape of the joint 412.

[0053] In the semiconductor device A10, the semiconductor element 11 has a point p1 (see FIG. 7) corresponding to each of the multiple pads 112. Each point p1 is located between the corresponding pad 112 and the seal ring portion 113 in the first direction x. The distance d12 (see FIG. 7) between each point p1 and the pad 112 corresponding to that point p1 is, for example, not less than 50 μm and not more than 150 μm. That is, the semiconductor element 11 has a point p1 on the main surface 11a that is separated by the distance d12 in the first direction x from each pad 112 toward the seal ring portion 113. The distance d13 (see FIG. 7) between each point p1 and the wire 41 (loop portion 413) in the thickness direction z is not less than 85% and not more than 95% of the distance d2. In other words, there is a point p1 on the main surface 11a of the semiconductor element 11 where the distance d13 in the thickness direction z between the wire 41 (loop portion 413) and the main surface 11a is 85% to 95% of the distance d2, and the distance d12 in the first direction x between the point p1 and the pad 112 is 50 μm to 150 μm. Note that the distance d12 and the ratio of the distance d13 to the distance d2 are not limited to these examples.

[0054] As shown in FIGS. 2 and 7, each of the multiple wires 42 is bonded to one of the multiple pads 111 of the semiconductor element 11 and one of the multiple pads 131 of the semiconductor element 13. Each wire 42 electrically connects the semiconductor element 11 and the semiconductor element 13. The multiple wires 42 are arranged along the second direction y. As shown in FIG. 7, in this embodiment, the top of the wire 42 in the thickness direction z is lower than the top of the wire 41 in the thickness direction z (located closer to the main surface 11a of the semiconductor element 11 in the thickness direction z).

[0055] As shown in FIG. 7, each of the multiple wires 42 includes two bonding portions 421, 422 and a loop portion 423. In each wire 42, the bonding portion 421 is bonded to one of the multiple pads 111. The bonding portion 422 is bonded to one of the multiple pads 131. The loop portion 423 connects the two bonding portions 421, 422. The loop portion 423 rises from the bonding portion 421 in the thickness direction z, curves, and extends toward the bonding portion 422. The loop portion 423 has a rising section 423a. The rising section 423a is the portion of the loop portion 423 that is connected to the bonding portion 421 and rises in the thickness direction z. In the illustrated example (see FIG. 7), the rising section 423a extends along the thickness direction z. Each wire 42 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 111 and second bonded to one of the multiple pads 131. Unlike this example, each wire 42 may be formed by other techniques such as wedge bonding. When each wire 42 is formed by wedge bonding, the shape of the joint 421 will be substantially the same as the shape of the joint 422.

[0056] 7, in this embodiment, the topmost portion of the wire 42 in the thickness direction z is lower than the topmost portion of the wire 41 in the thickness direction z. In other words, the topmost portion of the wire 42 in the thickness direction z is located lower in the thickness direction z than the topmost portion of the wire 41 in the thickness direction z (closer to the island portions 311, 321 in the thickness direction z). Unlike this example, the topmost portions of the wires 41, 42 in the thickness direction z may be at the same position in the thickness direction z, or the topmost portion of the wire 42 in the thickness direction z may be located higher in the thickness direction z than the topmost portion of the wire 41 in the thickness direction z.

[0057] 2, each of the plurality of wires 44 is bonded to one of the plurality of pads 131 of the semiconductor element 13 and to the covering portion 331 of one of the plurality of leads 33. Each of the wires 44 electrically connects the semiconductor element 13 to one of the plurality of leads 33.

[0058] 2, each of the plurality of wires 45 is bonded to one of the plurality of pads 141 of the semiconductor element 14 and to the covering portion 341 of one of the plurality of leads 34. Each of the wires 45 electrically connects the semiconductor element 14 to one of the plurality of leads 34.

[0059] 2, each of the plurality of wires 46 is joined to one of the plurality of pads 131 of the semiconductor element 13 and to the covering portion 312a of one of the two terminal portions 312. Each of the plurality of wires 46 electrically connects the semiconductor element 13 and the lead 31. The number of wires 46 is not limited to multiple and may be one.

[0060] 2, each of the plurality of wires 47 is joined to one of the plurality of pads 141 of the semiconductor element 14 and to the covering portion 322a of one of the two terminal portions 322. Each of the plurality of wires 47 electrically connects the semiconductor element 14 and the lead 32. The number of the plurality of wires 47 is not limited to two or more and may be one.

[0061] As shown in FIG. 1, the sealing resin 5 covers the semiconductor elements 11, 13, and 14, a portion of the conductive support 3, and the plurality of connecting members 4. The sealing resin 5 has electrical insulating properties. The sealing resin 5 insulates the components of the first circuit (e.g., lead 31) from the components of the second circuit (e.g., lead 32) from each other. The sealing resin 5 is made of a material containing, for example, a black epoxy resin. In the illustrated example, the sealing resin 5 is rectangular in plan view.

[0062] As shown in FIGS. 2 to 5, the sealing resin 5 has a top surface 51, a bottom surface 52, a pair of side surfaces 53, and a pair of side surfaces .

[0063] 3 to 5, top surface 51 and bottom surface 52 are spaced apart from each other in thickness direction z. Top surface 51 and bottom surface 52 face in opposite directions in thickness direction z. Each of top surface 51 and bottom surface 52 is substantially flat.

[0064] 3 to 5, the pair of side surfaces 53 are connected to the top surface 51 and the bottom surface 52 and are spaced apart from each other in the first direction x. Of the pair of side surfaces 53, the side surface 53 located on one side in the first direction x exposes the exposed portions 312b of the two terminal portions 312 (leads 31) and the exposed portions 332 of the multiple leads 33. Of the pair of side surfaces 53, the side surface 53 located on the other side in the first direction x exposes the exposed portions 322b of the two terminal portions 322 (leads 32) and the exposed portions 342 of the multiple leads 34.

[0065] As shown in FIGS. 3 to 5 , each of the pair of side surfaces 53 includes an upper portion 531, a lower portion 532, and an intermediate portion 533. One side of the upper portion 531 in the thickness direction z is connected to the top surface 51, and the other side in the thickness direction z is connected to the intermediate portion 533. The upper portion 531 is inclined with respect to the top surface 51. One side of the lower portion 532 in the thickness direction z is connected to the bottom surface 52, and the other side in the thickness direction z is connected to the intermediate portion 533. The lower portion 532 is inclined with respect to the bottom surface 52. One side of the intermediate portion 533 in the thickness direction z is connected to the upper portion 531, and the other side in the thickness direction z is connected to the lower portion 532. The in-plane directions of the intermediate portion 533 are the thickness direction z and the second direction y. In a plan view, the intermediate portion 533 is located outward from the top surface 51 and the bottom surface 52. From the middle portion 533 of the pair of side surfaces 53, each exposed portion 312b of the two terminal portions 312 (leads 31), each exposed portion 322b of the two terminal portions 322 (leads 32), each exposed portion 332 of the multiple leads 33, and each exposed portion 342 of the multiple leads 34 are exposed.

[0066] 3 to 5, the pair of side surfaces 54 are connected to the top surface 51 and the bottom surface 52 and are spaced apart from each other in the second direction y. As shown in FIG. 1, the lead 31, the lead 32, the plurality of leads 33, and the plurality of leads 34 are spaced apart from the pair of side surfaces 54.

[0067] As shown in FIGS. 3 to 5 , each of the pair of side surfaces 54 includes an upper portion 541, a lower portion 542, and an intermediate portion 543. One side of the upper portion 541 in the thickness direction z is connected to the top surface 51, and the other side in the thickness direction z is connected to the intermediate portion 543. The upper portion 541 is inclined with respect to the top surface 51. One side of the lower portion 542 in the thickness direction z is connected to the bottom surface 52, and the other side in the thickness direction z is connected to the intermediate portion 543. The lower portion 542 is inclined with respect to the bottom surface 52. One side of the intermediate portion 543 in the thickness direction z is connected to the upper portion 541, and the other side in the thickness direction z is connected to the lower portion 542. The in-plane directions of the intermediate portion 543 are the thickness direction z and the second direction y. In a plan view, the intermediate portion 543 is located outward from the top surface 51 and the bottom surface 52.

[0068] A motor driver circuit in an inverter device typically includes a half-bridge circuit including a low-side (low potential side) switching element and a high-side (high potential side) switching element. The following description focuses on the case where these switching elements are MOSFETs. Here, for the low-side switching element, the reference potentials of the source of the switching element and the gate driver driving the switching element are both ground. For the high-side switching element, the reference potentials of the source of the switching element and the gate driver driving the switching element are both equivalent to the potential at the output node of the half-bridge circuit. The potential at the output node changes depending on the driving of the high-side and low-side switching elements, so the reference potential of the gate driver driving the high-side switching element also changes. When the high-side switching element is on, the reference potential is equivalent to the voltage applied to the drain of the high-side switching element (e.g., 600 V or higher). In the semiconductor device A10, the ground of semiconductor element 13 and the ground of semiconductor element 14 are separated. Therefore, when the semiconductor device A10 is used as a gate driver for driving a high-side switching element, a voltage equivalent to the voltage applied to the drain of the high-side switching element is transiently applied to the ground of the semiconductor element 14.

[0069] In the semiconductor device A10, the components of the first circuit and the components of the second circuit are arranged so that the distance d0 [mm] is greater than the distance d0 [mm] determined by the following formula (2). In formula (2), Y is the insulation life [years] required for the semiconductor device A10, A and B are constants determined by the material of the sealing resin 5, and X is the voltage (for example, effective value) [kVrms] used in the semiconductor device A10. The voltage X is, for example, the voltage difference applied between the two target parts. In the semiconductor device A10, an AC voltage is generated by driving a switching element, and the effective value is used for the voltage X. In an example where the sealing resin 5 is epoxy resin, the constant A is 1000×416 and the constant B is 16. Also, 0.15 is an offset value for calculating the distance d0 [mm]. The offset value is used to match the dimension of the right side of the following equation (2) with the dimension of the left side (distance d0) of the following equation (2), and its unit is, for example, [mm] / (( B As can be seen from equation (2), the distance d0 increases as the voltage increases, as the insulation life increases, and also increases as the insulation life increases, and varies depending on the material of the sealing resin 5. For example, the distance d0 can be calculated by setting the insulation life Y to 20 years, the voltage X to 1 kVrms, and the constant A to 1000 x 4 kVrms of epoxy resin. 16 Then, from equation (2), the calculated value is approximately 0.0294 [mm] (= 29.4 [μm]).

number

[0070] Specifically, the distance d1 (see FIG. 7) between the leads 31 and 32 in the first direction x is greater than the distance d0. When setting the distance d1, the voltage X may be, for example, the difference between the voltage applied to the first circuit (lead 31) and the voltage applied to the second circuit (lead 32). Unlike this example, the voltage X used to set the distance d1 may be greater than the voltage difference between the first circuit and the second circuit. In the example shown in FIG. 7, the distance d1 is the distance between the closest points of the island portion 311 and the island portion 321. The distance d1 is, for example, 10 mm or less. This prevents the semiconductor device A10 from becoming larger. In the semiconductor device A10, the distance d1 is approximately 300 μm, which is greater than the distance d0 (≈29.4 μm) in the example described above.

[0071] Furthermore, the distance d2 (see FIG. 7 ) between each wire 41 and the semiconductor element 11 is greater than the distance d0. In the example shown in FIG. 7 , the distance d2 is the distance in the thickness direction z between the loop portion 413 and the seal ring portion 113 of the semiconductor element 11 at the closest position. In this embodiment, since each wire 41 is a component of the second circuit, the voltage X used to set the distance d2 is, for example, the difference between the voltage applied to the second circuit (each wire 41) and the voltage applied to the first circuit (the seal ring portion 113 of the semiconductor element 11). Unlike this example, the voltage X used to set the distance d2 may be greater than the voltage difference between the first circuit and the second circuit. The distance d2 is, for example, 10 mm or less. This prevents the semiconductor device A10 from becoming larger. In the semiconductor device A10, the distance d2 is approximately 170 μm, which is greater than the distance d0 (= 29.4 μm) in the example above.

[0072] Furthermore, the distance d2' (see FIG. 7) between each wire 41 and the lead 31 is greater than the distance d0. In the example shown in FIG. 7, the distance d2' is the distance in the thickness direction z between the loop portion 413 and the mounting surface 311a of the island portion 311 at the closest position. As with the setting of the distance d2, the voltage X used to set the distance d2' may be, for example, the difference between the voltage applied to the second circuit (each wire 41) and the voltage applied to the first circuit (lead 31). Unlike this example, the voltage X used to set the distance d2' may be greater than the voltage difference between the first circuit and the second circuit. The distance d2' is, for example, 10 mm or less. This prevents the semiconductor device A10 from becoming larger. In the semiconductor device A10, the distance d2' is approximately 470 μm, which is greater than the distance d0 (= 29.4 μm) in the example above.

[0073] Furthermore, the distance d4 (see FIG. 7 ) between each wire 41 and each wire 42 is greater than the distance d0. In the example shown in FIG. 7 , the distance d4 is the distance in a direction perpendicular to the thickness direction z (first direction x in FIG. 7 ) between the portions where the rising section 413a of each loop portion 413 and the rising section 423a of the loop portion 423 are closest to each other. In this embodiment, each wire 41 is a component of the second circuit, and each wire 42 is a component of the first circuit. Therefore, in setting the distance d4, for example, the difference between the voltage applied to the second circuit (each wire 41) and the voltage applied to the first circuit (each wire 42) is used as the voltage X. Unlike this example, the voltage X used in setting the distance d4 may be greater than the voltage difference between the first circuit and the second circuit. In the semiconductor device A10, the distance d4 is approximately 300 μm, which is greater than the distance d0 (=29.4 μm) in the example above.

[0074] Next, an example of a method for manufacturing the semiconductor device A10 will be described with reference to Figures 10 to 17. Figure 10 is a flowchart showing an example of a method for manufacturing the semiconductor device A10. Figures 11 to 15 and Figure 17 are plan views showing one step of the method for manufacturing the semiconductor device A10. Figure 16 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device A10. The cross section of Figure 16 is at the same cross-sectional position as that of Figure 7.

[0075] 10, the manufacturing method of the semiconductor device A10 according to this embodiment includes a lead frame preparation step S11, a lead frame processing step S12, an element mounting step S13, a wire bonding step S14, a sealing step S15, and a singulation step S16. The manufacturing method of the semiconductor device A10 also includes a design method including a design step. The design step includes a lead design process S101, a wire design process S102, and a wire design process S103, which will be described in detail later.

[0076] First, in the lead frame preparation step S11, a lead frame 81 shown in FIG. 11 is prepared. As shown in FIG. 11, the lead frame 81 includes a flat plate portion 810, a plurality of support leads 811b, 812b, a plurality of leads 813, 814, an outer frame 815, and a dam bar 816. The lead frame 81 is formed, for example, by stamping a copper plate having a rectangular shape in a plan view. As shown in FIG. 11, the plurality of support leads 811b, 812b are each connected to the flat plate portion 810. Furthermore, the plurality of support leads 811b, 812b and the plurality of leads 813, 814 are connected by the outer frame 815 and the dam bar 816. Note that, of the lead frame 81, the outer frame 815 and the dam bar 816 do not constitute the semiconductor device A10.

[0077] Next, in the lead frame processing step S12, the flat plate portion 810 of the lead frame 81 is divided into two islands 811a and 812a (see FIG. 13). In the lead frame processing step S12, first, a resist 82 is formed on the lead frame 81 as shown in FIG. 12. In FIG. 12, dots are drawn on the resist 82. Then, the lead frame 81 on which the resist 82 is formed is subjected to an etching process. As a result, the portions of the lead frame 81 exposed from the resist 82 are removed, and as shown in FIG. 13, the flat plate portion 810 is divided into two islands 811a and 812a, and a plurality of through holes 811c are formed in the flat plate portion 810 (island 811a). Thereafter, the resist 82 is removed, thereby forming the lead frame 81 shown in FIG. 13. In the lead frame 81 shown in FIG. 13, a plurality of support leads 811b are each connected to the island 811a, and a lead 811 including the island 811a and the plurality of support leads 811b is formed. In the lead frame 81 shown in FIG. 13, each of the plurality of support leads 812b is connected to the island 812a, forming a lead 812 including the island 812a and the plurality of support leads 812b.

[0078] In this embodiment, as shown in FIG. 10, a lead design process S101 is performed in the lead frame processing step S12.

[0079] In the lead design process S101, when dividing the flat plate portion 810 into two islands 811a and 812a, the distance d1 (see FIGS. 12, 13, and 16) between the island 811a (lead 811) and the island 812a (lead 812) in the first direction x is designed to be greater than the distance d0. The distance d0 is determined by the above formula (2). As will be understood from the configuration described in detail later, the island 811a (lead 811) becomes the island portion 311 (lead 31), and the island 812a (lead 812) becomes the island portion 321 (lead 32). Therefore, in the process of designing the distance d1 in the lead design process S101, the distance d1 between the lead 31 and the lead 32 in the first direction x is designed to be greater than the distance d0. In the lead design process S101, it is preferable to design the distance d1 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the size of the semiconductor device A10 to be manufactured from increasing.

[0080] Next, in the element mounting process S13, three semiconductor elements 11, 13, and 14 are prepared, and as shown in Fig. 14, the three semiconductor elements 11, 13, and 14 are each mounted on the lead frame 81. Specifically, the two semiconductor elements 11 and 13 are each bonded to the island 811a with a conductive bonding material (not shown), and the semiconductor element 14 is bonded to the island 812a with a conductive bonding material (not shown). Here, the semiconductor element 11 to be prepared has a distance d11 (see Fig. 16) along the first direction x between each pad 112 and the seal ring portion 113 of 100 µm or more and 300 µm or less.

[0081] 15 and 16, a plurality of wires 41, a plurality of wires 42, a plurality of wires 44, a plurality of wires 45, a plurality of wires 46, and a plurality of wires 47 are formed. A well-known wire bonder may be used to form the wires 41, 42, 44 to 47. The order in which the wires 41, 42, 44 to 47 are formed is not particularly limited.

[0082] In this embodiment, as shown in FIG. 10, wire design processing S102 and wire design processing S103 are performed in the wire bonding step S14.

[0083] In the wire design process S102, when forming each wire 41, as shown in FIG. 16, the distance d2 between each wire 41 and the semiconductor element 11 in the thickness direction z is designed to be greater than the distance d0. Also, the distance d2' between each wire 41 and the lead 811 in the thickness direction z is designed to be greater than the distance d0. For example, each wire 41 is wire-bonded so that the loop portion 413 of each wire 41 is spaced apart from the seal ring portion 113 of the semiconductor element 11 by a distance greater than d0 and is also spaced apart from the island 811a by a distance greater than d0. Note that, as will be understood from the configuration described in detail later, the lead 811 becomes the lead 31. Therefore, in the process of designing the distance d2' in the wire design process S102, the distance d2' between each wire 41 and the lead 31 in the thickness direction z is designed to be greater than the distance d0. In the wire design process S102, it is preferable to design the distance d2 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A10 from becoming larger in size. Also, in the wire design process S102, it is preferable to design the distance d2' to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A10 from becoming larger in size.

[0084] In the wire design process S103, when forming each wire 41 and each wire 42, the wires 41 and 42 are designed so that the distance d4 between each wire 41 and each wire 42 is greater than the distance d0, as shown in Fig. 16. For example, when each wire 41 is wire-bonded before each wire 42, each wire 42 is wire-bonded so that the rising section 423a of the loop portion 423 of each wire 42 is spaced apart from the rising section 413a of the loop portion 413 of each wire 41 by a distance greater than d0. Conversely, when each wire 42 is wire-bonded before each wire 41, each wire 41 is wire-bonded so that the rising section 413a of the loop portion 413 of each wire 41 is spaced apart from the rising section 423a of the loop portion 423 of each wire 42 by a distance greater than d0. In the wire design process S103, it is preferable to design the distance d4 to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the size of the semiconductor device A10 to be manufactured from increasing.

[0085] Next, in the sealing step S15, sealing resin 5 is formed as shown in Fig. 17. In Fig. 17, sealing resin 5 is shown by an imaginary line (two-dot chain line). The sealing resin 5 is formed by transfer molding. The formed sealing resin 5 is made of, for example, epoxy resin.

[0086] Thereafter, in the singulation step S16, dicing is performed to separate the substrate into individual pieces. As a result, the multiple leads 811, 812, 813, and 814 that were connected to each other by the outer frame 815 and dam bars 816 are appropriately separated. Leads 31 are formed from the separated leads 811. Here, the island 811a becomes the island portion 311, and each support lead 811b becomes each terminal portion 312. Leads 32 are formed from the separated leads 812. Here, the island 812a becomes the island portion 321, and each support lead 812b becomes each terminal portion 322. Furthermore, multiple leads 33 are formed from the separated multiple leads 813, and multiple leads 34 are formed from the separated multiple leads 814. Note that the bending process for the multiple leads 33 (the multiple leads 813) and the multiple leads 34 (the multiple leads 814) may be performed in the singulation step S16 or during the punching process in the lead frame preparation step S11.

[0087] The semiconductor device A10 is manufactured through the steps described above. The manufacturing method of the semiconductor device A10 is not limited to the above example. For example, the two islands 811a, 812a can be formed by punching in the lead frame preparation step S11, thereby eliminating the need for the lead frame processing step S12. In this case, the lead design process S101 is performed in the lead frame preparation step S11. However, the two islands 811a, 812a can be formed more accurately by etching in the lead frame processing step S12 than by punching in the lead frame preparation step S11, and the distance d1 can be made greater than the distance d0. In another manufacturing method, for example, in the lead frame preparation step S11, a copper plate having a rectangular shape in plan view is prepared, and in the lead frame processing step S12, a resist 82 is formed and an etching process is performed to simultaneously form the lead 811 (island 811a and multiple support leads 811b), the lead 812 (island 812a and multiple support leads 812b), multiple leads 813, 814, the outer frame 815, and the dam bar 816 from the prepared copper plate.

[0088] The functions and effects of the semiconductor device A10, the method for designing the semiconductor device A10, and the method for manufacturing the semiconductor device A10 are as follows.

[0089] In the semiconductor device A10, the distance d2 is greater than the distance d0 determined by the above formula (2). The distance d2 is the distance in the thickness direction z between the loop portion 413 of the wire 41 and the seal ring portion 113 of the semiconductor element 11. Because the semiconductor element 11 is joined to the island portion 311 (lead 31), the seal ring portion 113 has the same potential as the island portion 311 and can serve as a component of the first circuit. On the other hand, because the wire 41 is electrically connected to the semiconductor element 14, it has the same potential as the semiconductor element 14 and can serve as a component of the second circuit. In other words, the seal ring portion 113 has a relatively low potential and the wire 41 has a relatively high voltage, resulting in a potential difference between the seal ring portion 113 and the wire 41. Therefore, in the semiconductor device A10, by making the distance d2 greater than the distance d0, it is possible to design a dielectric strength voltage between the seal ring portion 113 and the wire 41 that satisfies actual use conditions. Therefore, the semiconductor device A10 can ensure an appropriate dielectric strength between the seal ring portion 113 and the wire 41, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A10, the wire design process S102 is performed so that the distance d2 is greater than the distance d0. This enables the design and manufacture of a semiconductor device A10 in which the occurrence of dielectric breakdown is suppressed. In this semiconductor device A10, the leads 31 and 32 are examples of the "first lead" and "second lead" recited in the claims, the semiconductor element 11 and the semiconductor element 14 are examples of the "first semiconductor element" and "second semiconductor element" recited in the claims, the wire 41 is an example of the "first wire" recited in the claims, the pad 112 is an example of the "first pad" recited in the claims, the seal ring portion 113 is an example of the "seal ring portion" recited in the claims, and the distance d2 is an example of the "first distance" recited in the claims.

[0090] In the semiconductor device A10, the distance d2 is greater than the distance d0, and the distance d11 in the first direction x between the pad 112 and the seal ring portion 113 is 100 μm or greater. In the semiconductor device A10, the wire 41 contains copper. That is, the wire 41 is a copper wire. The copper wire 41 is less likely to bend than a gold wire (a wire containing gold in its composition). Therefore, if the copper wire 41 is subjected to the same wire bonding process (looping) as a gold wire, cracks may occur in the wire 41 or excessive stress may be applied to the semiconductor element 11 (pad 112), damaging the pad 112. Therefore, if the wire 41 is a copper wire, looping that results in a gradual rise is required. Therefore, in the semiconductor device A10, the distance d11 is 100 μm or greater, so that the distance d2 can be greater than the distance d0 even if the rise of the wire 41 is gradual. That is, when a copper wire is used for the wire 41, the semiconductor device A10 can suppress the occurrence of wire cracks and damage to the semiconductor element 11 while making the distance d2 larger than the distance d0. However, if the distance d11 is too large, the dimension of the semiconductor element 11 in the first direction x increases, resulting in an increase in the size of the semiconductor device A10. Therefore, by setting the distance d11 to be 100 μm or more and 300 μm or less, the occurrence of wire cracks and damage to the semiconductor element 11 can be suppressed while suppressing an increase in the size of the semiconductor device A10. Note that in this semiconductor device A10, the distance d11 is an example of the "second distance" described in the claims.

[0091] In the semiconductor device A10, the distance d11 is greater than the distance d2. With this configuration, even when the rising section 413a of the wire 41 is looped so as to have a gradual rise, the distance d2 is likely to be greater than the distance d0. In other words, it is preferable that the distance d11 is greater than the distance d2 in order to ensure an appropriate dielectric strength and suppress the occurrence of dielectric breakdown.

[0092] In the semiconductor device A10, the distance d12 is 50 μm or more and 150 μm or less. The distance d12 is the separation distance between each pad 112 and a point p1 (see FIG. 7) corresponding to that pad 112. The point p1 is a point on the main surface 11a where the distance d13 in the thickness direction z from the wire 41 is 85% or more and 95% or less of the distance d2. This configuration makes it easy to make the distance d2 larger than the distance d0. That is, a distance d12 of 50 μm or more and 100 μm or less is preferable for ensuring an appropriate dielectric strength and suppressing the occurrence of dielectric breakdown. Note that in the semiconductor device A10, the point p1 is an example of a "point" as defined in the claims, the distance d12 is an example of a "third distance" as defined in the claims, and the distance d13 is an example of a "fourth distance" as defined in the claims.

[0093] In the semiconductor device A10, the distance d1 between the leads 31 and 32 in the first direction x is greater than the distance d0 determined by the above formula (2). As described above, the distance d0 is calculated using the insulation life Y of the semiconductor device A10, the voltage X used in the semiconductor device A10, and a constant A determined by the material of the sealing resin 5. Research by the present inventors has revealed that the above formula (2) makes it possible to design a dielectric strength voltage that satisfies actual usage conditions. Therefore, in the semiconductor device A10, by making the distance d1 greater than the distance d0, it is possible to design a dielectric strength voltage that satisfies actual usage conditions between the two leads 31 and 32. Therefore, the semiconductor device A10 can ensure an appropriate dielectric strength voltage between the two leads 31 and 32, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A10, the lead design process S101 is designed so that the distance d1 is greater than the distance d0. This makes it possible to design a semiconductor device A10 that suppresses the occurrence of dielectric breakdown, and to manufacture the semiconductor device A10.

[0094] In the semiconductor device A10, the distance d2' between each wire 41 and the lead 31 is greater than the distance d0 determined by the above formula (2). In this embodiment, the distance d2' is the distance in the thickness direction z between the loop portion 413 of each wire 41 and the mounting surface 311a of the island portion 311 (lead 31). The wire 41 is electrically connected to the upper winding 115a of the semiconductor element 11 (functional portion 115), and is therefore a component of the second circuit. On the other hand, the lead 31 is a component of the first circuit. In other words, the wire 41 has a relatively high voltage and the lead 31 has a relatively low voltage, resulting in a potential difference between the wire 41 and the lead 31. In the semiconductor device A10, the distance d2' is greater than the distance d0, making it possible to design a dielectric strength voltage between the wire 41 and the lead 31 that satisfies actual use conditions. Therefore, the semiconductor device A10 can ensure an appropriate dielectric strength voltage between the wire 41 and the lead 31, thereby suppressing dielectric breakdown. Furthermore, in the design method for the semiconductor device A10, the wire design process S102 is performed so that the distance d2' is greater than the distance d0, thereby enabling the design and manufacture of the semiconductor device A10 in which the occurrence of dielectric breakdown is suppressed.

[0095] In the semiconductor device A10, the distance d4 between each wire 41 and each wire 42 is greater than the distance d0 determined by the above formula (2). In this embodiment, the distance d4 is the distance between the rising section 413a of the loop portion 413 of each wire 41 and the rising section 423a of the loop portion 423 of each wire 42 in a direction perpendicular to the thickness direction z. The wire 41 is electrically connected to the semiconductor element 14 and is therefore a component of the second circuit. On the other hand, the wire 42 is electrically connected to the semiconductor element 13 and is therefore a component of the first circuit. In other words, the wire 41 has a relatively high voltage and the wire 42 has a relatively low voltage, so a potential difference occurs between the wires 41 and 42. In the semiconductor device A10, the distance d4 is greater than the distance d0, so it is possible to design a dielectric strength voltage between the wires 41 and 42 that satisfies actual use conditions. Therefore, the semiconductor device A10 can ensure an appropriate dielectric strength between the wires 41 and 42, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A10, the wire design process S103 is performed so that the distance d4 is greater than the distance d0. This makes it possible to design the semiconductor device A10 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A10.

[0096] In the semiconductor device A10, the potential of the lower winding 115b of the functional section 115 in the semiconductor element 11 is approximately the same as the potential of the lead 31. In this embodiment, the semiconductor element 11 is joined to the lead 31, so the potential of the semiconductor substrate 110 is approximately the same as the potential of the lead 31. As a result, in the semiconductor device A10, the potential of the semiconductor substrate 110 and the potential of the lower winding 115b are approximately the same. Therefore, in the semiconductor device A10, the number of insulating layers 1171 between the semiconductor substrate 110 and the lower winding 115b can be reduced, and an increase in the thickness of the semiconductor element 11 can be suppressed.

[0097] In the semiconductor device A10, the lower winding 115b is electrically connected to the semiconductor element 13 by connecting a wire 42 to a pad 111 that is conductive to the lower winding 115b. The semiconductor element 13 is also joined to the lead 31. With this configuration, the lower winding 115b and the lead 31 are components of a first circuit that includes the semiconductor element 13. That is, in the semiconductor device A10, the potential of the lower winding 115b can be made substantially the same as the potential of the lead 31.

[0098] Other embodiments and modifications of the semiconductor device of the present disclosure will be described below. The configurations of the components in each embodiment and each modification can be combined with each other as long as no technical contradiction occurs.

[0099] 18 to 20 show a semiconductor device A11 according to a first modified example of the first embodiment. The semiconductor device A11 differs from the semiconductor device A10 in the following respect: in the semiconductor device A11, the semiconductor element 11 is mounted on the lead 32 (island portion 321) rather than on the lead 31 (island portion 311).

[0100] 18 to 20, in the semiconductor device A11, the semiconductor element 11 is bonded to the island portion 321 by a conductive bonding material 119. In this configuration, in the semiconductor element 11, the semiconductor substrate 110 and the seal ring portion 113 have the same potential as the leads 32. In other words, the seal ring portion 113 has the same potential as the second circuit.

[0101] In the semiconductor device A11, as shown in FIGS. 18 to 20, each wire 42 electrically connects the semiconductor element 11 and the semiconductor element 13. A bonding portion 411 of each wire 41 is bonded to one of a plurality of pads 112 of the semiconductor element 11, and a bonding portion 412 of each wire 41 is bonded to one of a plurality of pads 131 of the semiconductor element 13. Also, in the semiconductor device A11, as shown in FIGS. 18 to 20, each wire 42 electrically connects the semiconductor element 11 and the semiconductor element 14. A bonding portion 421 of each wire 42 is bonded to one of a plurality of pads 111 of the semiconductor element 11, and a bonding portion 422 of each wire 42 is bonded to one of a plurality of pads 141 of the semiconductor element 14. As shown in Figures 18 to 20, in semiconductor device A11, in a planar view, the multiple pads 112 are arranged on the side where the semiconductor element 13 is located relative to the multiple pads 111, and the multiple pads 111 are arranged on the side where the semiconductor element 14 is located relative to the multiple pads 112.

[0102] In the semiconductor device A11, the distance d2' is the distance in the thickness direction z between the wire 41 (loop portion 413) and the island portion 321 (mounting surface 321a) of the lead 32 at the portion where they are closest to each other.

[0103] The manufacturing method of the semiconductor device A11 is performed in the same manner as the manufacturing method of the semiconductor device A10 (see FIG. 10). However, in the wire design process S102 in the manufacturing method of the semiconductor device A11, when forming each wire 41, the distance d2 between each wire 41 and the semiconductor element 11 in the thickness direction z is designed to be greater than the distance d0, and the distance d2' between each wire 41 and the lead 812 in the thickness direction z is designed to be greater than the distance d0. The other steps (including specific processing) are the same.

[0104] In the semiconductor device A11, as in the semiconductor device A10, the distance d2 is greater than the distance d0, making it possible to design a dielectric strength voltage between the wire 41 and the seal ring portion 113 that satisfies actual use conditions. Therefore, in the semiconductor device A11, an appropriate dielectric strength voltage can be ensured between the wire 41 and the seal ring portion 113 (semiconductor element 11), thereby suppressing the occurrence of dielectric breakdown. However, unlike the semiconductor device A10, in the semiconductor device A11, the semiconductor element 11 is bonded to the island portion 321 (lead 32), so the seal ring portion 113 has the same potential as the island portion 321 and can serve as a component of the second circuit. Meanwhile, the wire 41 is electrically connected to the semiconductor element 13, so it has the same potential as the semiconductor element 13 and serves as a component of the first circuit. In other words, the seal ring portion 113 has a higher potential and the wire 41 has a lower potential, resulting in a potential difference between the seal ring portion 113 and the wire 41. In this semiconductor device A11, the lead 32 and the lead 31 are examples of the "first lead" and the "second lead" respectively described in the claims, the semiconductor element 11 and the semiconductor element 13 are examples of the "first semiconductor element" and the "second semiconductor element" respectively described in the claims, the wire 41 is an example of the "first wire" described in the claims, the pad 112 is an example of the "first pad" described in the claims, the seal ring portion 113 is an example of the "seal ring portion" described in the claims, and the distance d2 is an example of the "first distance" described in the claims.

[0105] In addition, the semiconductor device A11 has a configuration in common with the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10. For example, in the semiconductor device A11, like the semiconductor device A10, the distance d2 is greater than the distance d0, and the distance d11 in the first direction x between the pad 112 and the seal ring portion 113 is 100 μm or more and 300 μm or less. Therefore, like the semiconductor device A10, the semiconductor device A11 can make the rise of the wire 41 gentler while making the distance d2 greater than the distance d0. Therefore, when a copper wire is used for the wire 41, the occurrence of wire cracks and damage to the semiconductor element 11 can be suppressed while making the distance d2 greater than the distance d0.

[0106] As can be understood from this modified example, in the semiconductor device of the present disclosure, there is no limitation as to whether semiconductor element 11 is mounted (joined) on lead 31 and electrically connected to semiconductor element 14 by wire 41, or whether it is mounted (joined) on lead 32 and electrically connected to semiconductor element 13 by wire 41.

[0107] 21 shows a semiconductor device A12 according to a second modified example of the first embodiment. The semiconductor device A12 differs from the semiconductor device A10 in the following respect: in the semiconductor device A12, the rising section 413a of the loop portion 413 of each wire 41 is inclined with respect to the thickness direction z. Similarly, in the illustrated example, the rising section 423a of the loop portion 423 of each wire 42 is inclined with respect to the thickness direction z, but the rising section 423a of each wire 42 does not have to be inclined with respect to the thickness direction z.

[0108] In the semiconductor device A12, the rising section 413a of the loop portion 413 of each wire 41 is inclined at an inclination angle α with respect to the thickness direction z. The inclination angle α is, for example, greater than 80° and equal to or less than 100°.

[0109] The semiconductor device A12 has a common configuration with the semiconductor device A10 and thus achieves the same effects as the semiconductor device A10. The semiconductor device A12 can have a larger distance d4 than the semiconductor device A10, and therefore can further suppress the occurrence of dielectric breakdown than the semiconductor device A10.

[0110] Second Embodiment 22 to 26 show a semiconductor device A20 according to the second embodiment. The semiconductor device A20 differs from the semiconductor device A10 in the following respect: the semiconductor device A20 further includes a semiconductor element 12.

[0111] Like the semiconductor element 11, the semiconductor element 12 is an element (insulating element) for transmitting PWM control signals and other electrical signals in an insulated state. In a plan view, the semiconductor element 12 has a rectangular shape with its longer sides extending in the second direction y, but the shape of the semiconductor element 12 in a plan view is not limited to a rectangle. The semiconductor element 12 is electrically connected between the semiconductor element 11 and the semiconductor element 14. In the first direction x, the semiconductor element 12 is disposed between the semiconductor element 11 and the semiconductor element 14. In the semiconductor device A20, the first circuit including the semiconductor element 13 and the second circuit including the semiconductor element 14 are insulated from each other by the semiconductor element 11 and the semiconductor element 12.

[0112] The semiconductor element 12 is mounted on the island portion 321 (leads 32) together with the semiconductor element 14. The semiconductor element 12 is bonded to the mounting surface 321a of the island portion 321 via a conductive bonding material 129. Therefore, the semiconductor substrate 120 of the semiconductor element 12 has approximately the same potential as the island portion 321 via the conductive bonding material 129. The conductive bonding material 129 is, for example, any of solder, metal paste, sintered metal, etc.

[0113] 24 to 26, the semiconductor element 12 has a main surface 12a and a back surface 12b. The main surface 12a and the back surface 12b are spaced apart in the thickness direction z. The main surface 12a is the upper surface of the semiconductor element 12, and the back surface 12b is the lower surface of the semiconductor element 12. The back surface 12b faces the leads 32.

[0114] The semiconductor device 12 includes a functional unit 125. The functional unit 125 has multiple sets of upper windings 125a and lower windings 125b inside, with an upper winding 125a and a lower winding 125b as one set. That is, the semiconductor device 12 has multiple upper windings 125a and multiple lower windings 125b. FIG. 25 illustrates one of the multiple sets of upper windings 125a and lower windings 125b. For example, the multiple sets of upper windings 125a and lower windings 125b are arranged along the longitudinal direction (second direction y) of the semiconductor device 12. The set of upper windings 125a and lower windings 125b are spaced apart in the thickness direction z and face each other in the thickness direction z. In this embodiment, each set of upper windings 125a and lower windings 125b is planarly wound in a spiral shape. The upper winding 125a and the lower winding 125b of each pair are magnetically coupled to each other. The semiconductor device 12 inductively couples the upper winding 125a and the lower winding 125b of each pair, thereby transmitting electrical signals in an insulated state.

[0115] As shown in FIGS. 23 to 26, the semiconductor element 12 has a plurality of pads 121, 122. Each of the plurality of pads 121, 122 is provided on the main surface 12a. As shown in FIG. 25, each pad 121 is electrically connected to one of the plurality of lower windings 125b, and each pad 122 is electrically connected to one of the plurality of upper windings 125a. Each of the plurality of pads 121, 122 contains, for example, aluminum. As shown in FIGS. 23 and 25, each of the plurality of pads 121 is bonded to one of the plurality of wires 43, and each of the plurality of pads 122 is bonded to one of the plurality of wires 41.

[0116] 23, 25, and 26, the semiconductor element 12 includes a seal ring portion 123. In a plan view, the seal ring portion 123 is formed along each of the four outer peripheries of the semiconductor element 12 and surrounds the outer periphery of the circuit formation region. The seal ring portion 123 is made of, for example, copper (Cu), aluminum (Al), or the like. In this embodiment, as shown in FIGS. 25 and 26, the distance d21 in the first direction x (the direction in which the semiconductor element 11 is positioned relative to the semiconductor element 12) between each pad 122 and the seal ring portion 123 is, for example, not less than 100 μm and not more than 300 μm, but is not limited to this.

[0117] As shown in FIGS. 25 and 26, the semiconductor element 12 includes a semiconductor substrate 120, a protective film 1241, a passivation film 1242, a coil protective film 1243, a laminated structure 127, and a wiring portion 128.

[0118] The semiconductor substrate 120 may be a Si substrate, a SiC substrate, or the like. The semiconductor element 12 may use an insulating substrate such as a ceramic substrate or a resin substrate instead of the semiconductor substrate 120. The seal ring portion 123 is provided upright on the semiconductor substrate 120 and penetrates the stacked structure 127 in the thickness direction z. In this embodiment, the potential of the seal ring portion 123 is approximately the same as the potential of the semiconductor substrate 120.

[0119] The stacked structure 127 is formed on the semiconductor substrate 120. As shown in FIG. 26 , the stacked structure 127 includes a plurality of insulating layers 1271. The insulating layers 1271 are stacked on the upper surface of the semiconductor substrate 120. Except for the lowest insulating layer 1271 in contact with the upper surface of the semiconductor substrate 120, each insulating layer 1271 is formed of a stacked structure including an etching stopper film below and an interlayer insulating film above. The lowest insulating layer 1271 is formed solely of an interlayer insulating layer. The etching stopper film may be, for example, a SiN film, a SiC film, or a SiCN film, and the interlayer insulating film may be, for example, a SiO2 film. The dimension of the insulating layers 1271 in the thickness direction z is not limited in any way, but may be, for example, 2.4 μm. The thicknesses of the insulating layers 1271 may be the same or different.

[0120] The upper winding 125a and the lower winding 125b are formed on different insulating layers 1271 in the laminated structure 127 and face each other with at least one insulating layer 1271 sandwiched between them. In the illustrated example, the lower winding 125b is formed on the fourth insulating layer 1271 from the semiconductor substrate 120, and the upper winding 125a is formed on the eleventh insulating layer 1271, with six insulating layers 1271 sandwiched between it and the lower winding 125b. The number of insulating layers 1271 is not limited to the illustrated example and can be changed appropriately depending on, for example, the magnitude of the voltage applied to each pad 121 and each pad 122. The greater the number of insulating layers 1271 between the upper winding 125a and the lower winding 125b, the greater the breakdown voltage of the semiconductor element 12, but the greater the thickness (dimension in the thickness direction z) of the semiconductor element 12. On the other hand, the fewer the number of insulating layers 1271 between the upper winding 125a and the lower winding 125b, the smaller the dielectric strength voltage of the semiconductor element 12, but the thinner the semiconductor element 12 (the dimension in the thickness direction z) can be. In this embodiment, considering the relationship between the dielectric strength voltage of the semiconductor element 12 and the thickness of the semiconductor element 12 (suppressing an increase in the thickness of the semiconductor element 12), it is preferable that the number of stacked insulating layers 1271 between the upper winding 125a and the lower winding 125b be four to six. Furthermore, the dimension in the thickness direction z of the multiple insulating layers 1271 between the upper winding 125a and the lower winding 125b (i.e., the separation distance between the upper winding 125a and the lower winding 125b in the thickness direction z) is not particularly limited, but is, for example, 9.6 μm to 14.4 μm. This example dimension (9.6 μm or more and 14.4 μm or less) corresponds to a case where, for example, the dimension in the thickness direction z of each insulating layer 1271 between the upper winding 125a and the lower winding 125b is 2.4 μm and the number of insulating layers 1271 stacked between the upper winding 125a and the lower winding 125b is 4 to 6 layers.

[0121] In this embodiment, the number of laminated insulating layers 1171 in the semiconductor element 11 is equal to the number of laminated insulating layers 1271 in the semiconductor element 12. Specifically, the lower winding 115b is formed on the fourth insulating layer 1171 from the semiconductor substrate 110, and the upper winding 115a is formed on the eleventh insulating layer 1171, with six insulating layers 1171 sandwiched between it and the lower winding 115b. Therefore, the number of insulating layers 1171 between the pair of upper winding 115a and lower winding 115b in the semiconductor device A20 is smaller than the number of insulating layers 1171 between the pair of upper winding 115a and lower winding 115b in the semiconductor device A10. In this embodiment, in consideration of the relationship between the dielectric strength voltage of the semiconductor element 11 and (suppression of increase in) the thickness of the semiconductor element 11, it is preferable that the number of laminated insulating layers 1171 between the upper winding 115a and the lower winding 115b be 4 to 6. Furthermore, the dimension in the thickness direction z of the multiple insulating layers 1171 between the upper winding 115a and the lower winding 115b (i.e., the separation distance between the upper winding 115a and the lower winding 115b in the thickness direction z) is not particularly limited, but is, for example, 9.6 μm to 14.4 μm. This example dimension (9.6 μm or more and 14.4 μm or less) corresponds to a case where, for example, the dimension in the thickness direction z of each insulating layer 1171 between the upper winding 115a and the lower winding 115b is 2.4 μm and the number of insulating layers 1171 stacked between the upper winding 115a and the lower winding 115b is 4 to 6 layers.

[0122] The wiring section 128 electrically connects the pads 121 and 122 to the upper winding 125a and the lower winding 125b. The wiring section 128 includes a plurality of through wires 1281 and lead wires 1282. As shown in FIG. 26, each of the through wires 1281 penetrates one or more insulating layers 1271 in the thickness direction z. In the example shown in FIG. 26, the plurality of through wires 1281 includes one that connects the pad 121 to the lead wire 1282, one that connects the lead wire 1282 to the lower winding 125b, and one that connects the pad 122 to the upper winding 125a. The lead wire 1282 is formed on the lowest insulating layer 1271. The lead wire 1282 forms part of the conduction path between the pad 121 and the lower winding 125b.

[0123] As shown in FIG. 26, the protective film 1241 is laminated on the laminated structure 127. As shown in FIG. 26, the passivation film 1242 is laminated on the protective film 1241. As shown in FIG. 26, the coil protective film 1243 is on the passivation film 1242 and selectively covers the region directly above the upper winding 125a. As can be seen from FIG. 26, pad openings are formed in the protective film 1241, the passivation film 1242, and the coil protective film 1243 to expose each pad 121 and each pad 122. The protective film 1241 includes, for example, SiO2 and has a thickness of approximately 150 nm. The passivation film 1242 includes, for example, SiN and has a thickness of approximately 1000 nm. The coil protective film 1243 includes, for example, polyimide and has a thickness of approximately 4000 nm. The constituent materials and thicknesses of the protective film 1241, the passivation film 1242, and the coil protective film 1243 are not limited to the above examples.

[0124] The structure of the semiconductor element 12 is not limited to the above example. For example, the upper winding 125a and the lower winding 125b are not limited to being planarly wound on a single insulating layer 1271, and may be wound three-dimensionally across multiple insulating layers 1271. However, in order to prevent the thickness of the semiconductor element 12 from increasing, it is preferable that the upper winding 125a and the lower winding 125b are planarly wound on a single insulating layer 1271.

[0125] 23 to 25 , in the semiconductor device A20, each of the multiple wires 41 is bonded to one of the multiple pads 112 of the semiconductor element 11 and one of the multiple pads 122 of the semiconductor element 12. In this embodiment, the multiple wires 41 electrically connect the semiconductor element 11 and the semiconductor element 12. A bonded portion 411 of each wire 41 is bonded to one of the multiple pads 112 of the semiconductor element 11, and a bonded portion 412 of each wire 41 is bonded to one of the multiple pads 122 of the semiconductor element 12.

[0126] In the semiconductor device A20, the multiple connection members 4 include multiple wires 43. As shown in FIGS. 23 to 25, each of the multiple wires 43 is bonded to one of the multiple pads 121 of the semiconductor element 12 and one of the multiple pads 141 of the semiconductor element 14. Each wire 43 electrically connects the semiconductor element 12 and the semiconductor element 14. The multiple wires 43 are arranged along the second direction y.

[0127] As shown in FIG. 25 , each of the multiple wires 43 includes two bonding portions 431 and 432 and a loop portion 433. In each wire 43, the bonding portion 431 is bonded to one of the multiple pads 121. The bonding portion 432 is bonded to one of the multiple pads 141. The loop portion 433 connects the two bonding portions 431 and 432. The loop portion 433 rises from the bonding portion 431 in the thickness direction z, curves, and extends toward the bonding portion 432. The loop portion 433 has a rising section 433a. The rising section 433a is the portion of the loop portion 433 that is connected to the bonding portion 431 and rises in the thickness direction z. Each wire 43 is formed, for example, by ball bonding, and is first bonded to one of the multiple pads 121 and second bonded to one of the multiple pads 141. Unlike this example, each wire 43 may be formed by other methods, such as wedge bonding. When each wire 43 is formed by wedge bonding, the shape of the joint 431 is substantially the same as the shape of the joint 432 .

[0128] The conductive support 3 of the semiconductor device A20 differs from the conductive support 3 of the semiconductor device A10 in the following respects. First, the number of the leads 33 and the number of the leads 34 are each six. Second, all of the leads 34 are sandwiched between two terminal portions 322 of the leads 32 in the second direction y. Note that the shape, size, and arrangement, etc., of the conductive support 3 of the semiconductor device A20 are not limited to the example shown in the figure. For example, the island portion 321 may have a through-hole penetrating in the thickness direction z, similar to the island portion 311 of the semiconductor device A10. The through-hole may be formed, for example, between the semiconductor element 12 and the semiconductor element 14.

[0129] In the semiconductor device A20, the first circuit and the second circuit are electrically insulated by two semiconductor elements 11 and 12 (two insulating elements), thereby providing a third circuit whose potential is intermediate between the potentials of the first circuit and the second circuit. In other words, the semiconductor device A20 includes not only the first circuit and the second circuit but also the third circuit. In this embodiment, the third circuit includes a portion of the semiconductor element 11 (such as the upper windings 115a and the pads 112), a portion of the semiconductor element 12 (such as the upper windings 125a and the pads 122), and multiple wires 41. In a configuration in which the potential of the second circuit is higher than the potential of the first circuit, the potential of the third circuit is higher than the potential of the first circuit and lower than the potential of the second circuit. In this embodiment, the semiconductor elements 11 and 12 are configured identically, and the voltage difference between the first circuit and the second circuit is equally shared to provide insulation. Therefore, the potential of the third circuit is half the potential difference between the first circuit and the second circuit. Unlike this example, the potential of the third circuit may be biased toward either the potential of the first circuit or the potential of the second circuit with respect to half the potential difference between the first circuit and the second circuit.

[0130] In the semiconductor device A20, any two of the components of the first circuit, the components of the second circuit, and the components of the third circuit are arranged so that the distance between them is greater than the distance d0 [mm] determined by the above formula (2).

[0131] Specifically, the distance d1 (see FIG. 25) between the leads 31 and 32 in the first direction x is greater than the distance d0. In setting the distance d1, the voltage X is, for example, the difference between the voltage applied to the first circuit (lead 31) and the voltage applied to the second circuit (lead 32). In the example shown in FIG. 25, the distance d1 is the distance between the two island portions 311 and 321 at their closest points. The distance d1 is, for example, 10 mm or less. This prevents the semiconductor device A20 from becoming larger. In the semiconductor device A20, the distance d1 is approximately 300 μm, which is greater than the distance d0 (≈29.4 μm) in the example above.

[0132] Furthermore, the distance d2 (see FIG. 25 ) between each wire 41 and the semiconductor element 11 is greater than the distance d0. In the example shown in FIG. 25 , the distance d2 is the distance in the thickness direction z between each loop portion 413 and the seal ring portion 113 of the semiconductor element 11 at the closest position. In this embodiment, each wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d2, the voltage X is, for example, the difference between the voltage applied to the third circuit (each wire 41) and the voltage applied to the first circuit (the seal ring portion 113 of the semiconductor element 11). That is, the voltage X used to set the distance d2 may be smaller than the voltage X used to set the distance d1. Unlike this example, the voltage X used to set the distance d2 may be greater than the voltage difference between the third circuit and the first circuit. For example, the voltage X may be the same as the voltage X used to set the distance d1. The distance d2 is, for example, 10 mm or less. This prevents the semiconductor device A20 from becoming larger. In the semiconductor device A20, the distance d2 is about 170 μm, which is greater than the distance d0 (=29.4 μm) in the example given above.

[0133] Furthermore, the distance d2' (see FIG. 25) between each wire 41 and the lead 31 is greater than the distance d0. In the example shown in FIG. 25, the distance d2' is the distance in the thickness direction z between the loop portion 413 and the mounting surface 311a of the island portion 311 at the closest position. As with the setting of the distance d2, the voltage X used to set the distance d2' may be, for example, the difference between the voltage applied to the third circuit (each wire 41) and the voltage applied to the first circuit (lead 31). Unlike this example, the voltage X used to set the distance d2' may be greater than the voltage difference between the third circuit and the first circuit. For example, it may be the same as the voltage X used to set the distance d1. The distance d2' is, for example, 10 mm or less. This prevents the semiconductor device A20 from becoming larger. In the semiconductor device A20, the distance d2' is approximately 470 μm, which is greater than the distance d0 (= 29.4 μm) in the example above.

[0134] Furthermore, the distance d3 (see FIG. 25 ) between each wire 41 and the semiconductor element 12 is greater than the distance d0. In the example shown in FIG. 25 , the distance d3 is the distance in the thickness direction z between the loop portion 413 and the seal ring portion 123 of the semiconductor element 12 at the closest position. In this embodiment, each wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d3, the voltage X is, for example, the difference between the voltage applied to the third circuit (each wire 41) and the voltage applied to the second circuit (the seal ring portion 123 of the semiconductor element 12). That is, the voltage X used to set the distance d3 may be smaller than the voltage X used to set the distance d1. Unlike this example, the voltage X used to set the distance d3 may be greater than the voltage difference between the third circuit and the second circuit. For example, the voltage X may be the same as the voltage X used to set the distance d1. The distance d3 is, for example, 10 mm or less. This prevents the semiconductor device A20 from becoming larger. In the semiconductor device A20, the distance d3 is about 170 μm, which is greater than the distance d0 (=29.4 μm) in the example above.

[0135] Furthermore, the distance d3' (see FIG. 25) between each wire 41 and the lead 32 is greater than the distance d0. In the example shown in FIG. 25, the distance d3' is the distance in the thickness direction z between each loop portion 413 and the mounting surface 321a of the island portion 321 at the closest position. As with the setting of the distance d3, the voltage X used to set the distance d3' may be, for example, the difference between the voltage applied to the third circuit (each wire 41) and the voltage applied to the second circuit (lead 32). Unlike this example, the voltage X used to set the distance d3' may be greater than the voltage difference between the third circuit and the second circuit. For example, it may be the same as the voltage X used to set the distance d1. The distance d3' is, for example, 10 mm or less. This prevents the semiconductor device A20 from becoming larger. In the semiconductor device A20, the distance d3' is approximately 470 μm, which is greater than the distance d0 (= 29.4 μm) in the example above.

[0136] Furthermore, a distance d4 (see FIG. 25 ) between each wire 41 and each wire 42 is greater than the distance d0. In the example shown in FIG. 25 , the distance d4 is the distance in a direction perpendicular to the thickness direction z (the first direction x in FIG. 7 ) between the portions where the rising section 413a of the loop portion 413 of each wire 41 and the rising section 423a of the loop portion 423 of each wire 42 are closest to each other. In this embodiment, each wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d4, the voltage X is, for example, the difference between the voltage applied to the third circuit (each wire 41) and the voltage applied to the first circuit (each wire 42). In other words, the voltage X used to set the distance d4 may be smaller than the voltage X used to set the distance d1. Unlike this example, the voltage X used to set the distance d4 may be greater than the voltage difference between the third circuit and the first circuit. For example, the voltage X may be the same as the voltage X used to set the distance d1. In the semiconductor device A20, the distance d4 is about 300 μm, which is greater than the distance d0 (=29.4 μm) in the example given above.

[0137] Furthermore, a distance d5 (see FIG. 25 ) between each wire 41 and each wire 43 is greater than the distance d0. In the example shown in FIG. 25 , the distance d5 is the distance in a direction perpendicular to the thickness direction z (the first direction x in FIG. 7 ) between the joint 412 of each wire 41 and the rising section 433a of the loop portion 433 of each wire 43, where the joint 412 and the rising section 433a are closest to each other. In this embodiment, each wire 41 is a component of a third circuit that has an intermediate potential between the first circuit and the second circuit. Therefore, in setting the distance d5, the voltage X is, for example, the difference between the voltage applied to the third circuit (each wire 41) and the voltage applied to the second circuit (each wire 43). That is, the voltage X used to set the distance d5 may be smaller than the voltage X used to set the distance d1. Unlike this example, the voltage X used to set the distance d5 may be greater than the voltage difference between the third circuit and the second circuit. For example, the voltage X may be the same as the voltage X used to set the distance d1. In the semiconductor device A20, the distance d5 is about 300 μm, which is greater than the distance d0 (=29.4 μm) in the example above.

[0138] Next, an example of a method for manufacturing the semiconductor device A20 will be described with reference to Figures 27 to 29. Figure 27 is a flowchart showing an example of a method for manufacturing the semiconductor device A20. Figure 28 is a plan view showing one step of the method for manufacturing the semiconductor device A20. Figure 29 is a cross-sectional view showing one step of the method for manufacturing the semiconductor device A20. The cross section of Figure 29 corresponds to the cross section of Figure 25.

[0139] As shown in FIG. 27, the manufacturing method for the semiconductor device A20 according to this embodiment includes a lead frame preparation step S11, a lead frame processing step S12, an element mounting step S13, a wire bonding step S14, a sealing step S15, and a singulation step S16, similar to the manufacturing method for the semiconductor device A10 (see FIG. 10). However, the manufacturing method for the semiconductor device A20 differs from the manufacturing method for the semiconductor device A10 in the following respects. First, in the element mounting step S13, a semiconductor element 12 is further mounted. Second, in the wire bonding step S14, in addition to the wire design steps S102 and S103, wire design steps S104 and S105 are further performed. Therefore, the design method in the manufacturing method for the semiconductor device A20 further includes wire design steps S104 and S105. The manufacturing method for the semiconductor device A20 is the same as the manufacturing method for the semiconductor device A10 (see FIG. 10) except for the above two points.

[0140] In the element mounting process S13, a semiconductor element 12 is prepared together with three semiconductor elements 11, 13, and 14, and two semiconductor elements 11 and 13 are each bonded to an island 811a, and two semiconductor elements 12 and 14 are each bonded to an island 812a, as shown in Figures 28 and 29. Here, the semiconductor element 12 to be prepared has a distance d21 (see Figure 29) along the first direction x between each pad 122 and the seal ring portion 123 of 100 µm or more and 300 µm or less.

[0141] In the wire design process S104, when forming each wire 41, as shown in FIG. 29 , the distance d3 between each wire 41 and the semiconductor element 12 in the thickness direction z is designed to be greater than the distance d0. The distance d3′ between each wire 41 and the lead 812 in the thickness direction z is also designed to be greater than the distance d0. For example, each wire 41 is wire-bonded so that the loop portion 413 of each wire 41 is spaced apart from the seal ring portion 123 of the semiconductor element 12 by more than the distance d0 and from the island 812a by more than the distance d0. Because the lead 812 becomes the lead 32, the process of designing the distance d3′ in the wire design process S104 designs the distance d3′ between each wire 41 and the lead 32 in the thickness direction z to be greater than the distance d0. In the wire design process S104, it is preferable to design the distance d2 to be greater than the distance d0 and, for example, 10 mm or less, in order to prevent the semiconductor device A20 from becoming larger in size. Furthermore, in the wire design process S104, it is preferable to design the distance d3' to be greater than the distance d0 and to be, for example, 10 mm or less, in order to prevent the semiconductor device A20 to be manufactured from becoming larger.

[0142] In the wire design process S105, when forming each wire 41 and each wire 43, the distance d5 between each wire 41 and each wire 43 is designed to be greater than the distance d0, as shown in FIG. 29 . For example, when each wire 41 is wire-bonded before each wire 43, each wire 43 is wire-bonded such that the rising section 433a of the loop portion 433 of each wire 43 is spaced apart from the joint 412 of each wire 41 by a distance greater than d0. Conversely, when each wire 43 is wire-bonded before each wire 41, each wire 41 is wire-bonded such that the joint 412 of each wire 41 is spaced apart from the rising section 433a of the loop portion 433 of each wire 43 by a distance greater than d0. In the wire design process S105, it is preferable to design the distance d5 to be greater than the distance d0 and, for example, 10 mm or less, in order to prevent the semiconductor device A20 to be manufactured from becoming larger in size.

[0143] The functions and effects of the semiconductor device A20, the method for designing the semiconductor device A20, and the method for manufacturing the semiconductor device A20 are as follows.

[0144] In the semiconductor device A20, the distance d2 is greater than the distance d0 determined by the above formula (2). The distance d2 is the distance in the thickness direction z between the loop portion 413 of the wire 41 and the seal ring portion 113 of the semiconductor element 11. The seal ring portion 113 is at the potential of the first circuit, and the wire 41 is at the potential of the third circuit, which is the intermediate potential between the first and second circuits. In other words, the seal ring portion 113 is at a relatively low potential and the wire 41 is at a relatively high voltage, resulting in a potential difference between the seal ring portion 113 and the wire 41. Therefore, in the semiconductor device A20, by making the distance d2 greater than the distance d0, it is possible to design a dielectric strength voltage between the seal ring portion 113 and the wire 41 that satisfies actual use conditions. Therefore, like the semiconductor device A10, the semiconductor device A20 can ensure an appropriate dielectric strength voltage between the seal ring portion 113 and the wire 41, thereby suppressing the occurrence of dielectric breakdown. In the design method for the semiconductor device A20, the wire design process S102 is performed to design the distance d2 to be greater than the distance d0. This makes it possible to design the semiconductor device A20 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A20. In the semiconductor device A20, the leads 31 and 32 are examples of the "first lead" and "second lead" recited in the claims, the semiconductor elements 11 and 12 are examples of the "first semiconductor element" and "second semiconductor element" recited in the claims, the wire 41 is an example of the "first wire" recited in the claims, the pad 112 is an example of the "first pad" recited in the claims, the seal ring portion 113 is an example of the "seal ring portion" recited in the claims, and the distance d2 is an example of the "first distance" recited in the claims.

[0145] In the semiconductor device A20, similar to the semiconductor device A10, the distance d2 is greater than the distance d0, and the distance d11 in the first direction x between the pad 112 and the seal ring portion 113 is 100 μm or more and 300 μm or less. Therefore, similar to the semiconductor device A10, the semiconductor device A20 can make the rise of the wire 41 gentler while making the distance d2 greater than the distance d0. Therefore, when a copper wire is used for the wire 41, the occurrence of wire cracks and damage to the semiconductor element 11 can be suppressed while making the distance d2 greater than the distance d0. In this semiconductor device A20, the distance d11 is an example of a "second distance" as defined in the claims.

[0146] In the semiconductor device A20, the distance d21 in the first direction x between the pad 122 and the seal ring portion 123 is 100 μm or more and 300 μm or less. The larger the distance d21, the more likely it is that the distance d3 will be greater than the distance d0, ensuring an appropriate dielectric strength voltage between the wire 41 and the seal ring portion 123. On the other hand, if the distance d21 is too large, the dimension of the semiconductor element 12 in the first direction x will increase, resulting in an increase in the size of the semiconductor device A20. In other words, having the distance d21 be 100 μm or more and 300 μm or less can prevent dielectric breakdown from occurring while also preventing the semiconductor device A20 from becoming larger.

[0147] In the semiconductor device A20, the semiconductor elements 13 and 14 are electrically insulated by the semiconductor elements 11 and 12. In a configuration in which the semiconductor elements 13 and 14 are electrically insulated by a single semiconductor element 11 (insulating element), as in the semiconductor device A10, the voltage difference between the first circuit and the second circuit occurs within the single insulating element (semiconductor element 11). In contrast, in the semiconductor device A20, the voltage difference between the first circuit and the second circuit is shared by two insulating elements (semiconductor element 11 and semiconductor element 12). This reduces the voltage difference between the semiconductor elements 11 and 12. Therefore, compared to the semiconductor device A10, the semiconductor device A20 can more effectively improve the dielectric strength voltage between the lead 31 (island portion 311) and the semiconductor element 11. Furthermore, the semiconductor device A20 can more effectively improve the dielectric strength voltage between the lead 32 (island portion 321) and the semiconductor element 12.

[0148] Furthermore, since the voltage difference generated in the semiconductor element 11 can be reduced, the number of insulating layers 1171 between the upper winding 115a and the lower winding 115b can be reduced. This allows the thickness (dimension in the thickness direction z) of the semiconductor element 11 to be reduced, thereby enabling a thinner semiconductor device A20. Similarly, since the voltage difference generated in the semiconductor element 12 can be reduced, the number of insulating layers 1271 between the upper winding 125a and the lower winding 125b can be reduced. This allows the thickness (dimension in the thickness direction z) of the semiconductor element 12 to be reduced, thereby enabling a thinner semiconductor device A20. In other words, the semiconductor device A20 can be made thinner compared to the semiconductor device A10 while maintaining the same dielectric strength. Furthermore, when the thickness of the semiconductor device A20 is limited due to product specifications or the like, the semiconductor device A20 can improve the dielectric strength within the thickness limit of the semiconductor device A20 compared to the semiconductor device A10. This is because the first circuit and the second circuit can be insulated from each other by the multiple insulating layers 1171 between the upper winding 115a and the lower winding 115b of the semiconductor element 11 and the multiple insulating layers 1271 between the upper winding 125a and the lower winding 125b of the semiconductor element 12. In other words, when the first circuit and the second circuit are insulated from each other by the semiconductor element 11 and the semiconductor element 12, the number of insulating layers between the first circuit and the second circuit can be made larger than when isolation is provided by a single insulating element (semiconductor element 11).

[0149] In the semiconductor device A20, the distance d3 between each wire 41 and the semiconductor element 12 is greater than the distance d0 determined by the above formula (2). In this embodiment, the distance d3 is the distance in the thickness direction z between the loop portion 413 of each wire 41 and the seal ring portion 123 of the semiconductor element 12. As described above, each wire 41 has an intermediate potential between the first circuit and the second circuit. On the other hand, since the semiconductor element 12 is joined to the island portion 321 (lead 32), the seal ring portion 123 can have the same potential as the island portion 321. In other words, each wire 41 has a relatively low voltage and the seal ring portion 123 has a relatively high voltage, so a potential difference occurs between each wire 41 and the seal ring portion 123. In the semiconductor device A20, the distance d3 is greater than the distance d0, so it is possible to design a dielectric strength voltage between each wire 41 and the seal ring portion 123 that satisfies actual use conditions. Therefore, the semiconductor device A10 can ensure an appropriate dielectric strength between each wire 41 and the semiconductor element 12, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A20, the wire design process S104 is performed so that the distance d3 is greater than the distance d0. This makes it possible to design the semiconductor device A20 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A20.

[0150] In the semiconductor device A20, the distance d3' between each wire 41 and the lead 32 is greater than the distance d0 determined by the above formula (2). In this embodiment, the distance d3' is the distance in the thickness direction z between the loop portion 413 of each wire 41 and the mounting surface 321a of the island portion 321 (lead 32). The wire 41 is electrically connected to the upper winding 125a of the semiconductor element 12 (functional portion 125), and is therefore a component of the third circuit. On the other hand, the lead 32 is a component of the second circuit. In other words, the wire 41 has a relatively low voltage and the lead 32 has a relatively high voltage, resulting in a potential difference between the wire 41 and the lead 32. In the semiconductor device A20, the distance d3' is greater than the distance d0, making it possible to design a dielectric strength voltage between the wire 41 and the lead 32 that satisfies actual use conditions. Therefore, the semiconductor device A20 can ensure an appropriate dielectric strength voltage between the wire 41 and the lead 32, thereby suppressing dielectric breakdown. Furthermore, in the design method for the semiconductor device A20, the wire design process S104 is performed so that the distance d3' is greater than the distance d0, thereby enabling the design and manufacture of the semiconductor device A20 in which the occurrence of dielectric breakdown is suppressed.

[0151] In the semiconductor device A20, the distance d5 between each wire 41 and each wire 43 is greater than the distance d0 determined by the above formula (2). In this embodiment, the distance d5 is the distance between the joint 412 of each wire 41 and the rising section 433a of the loop portion 433 of each wire 43 in a direction perpendicular to the thickness direction z. The wire 41 is electrically connected to the upper winding 125a of the semiconductor element 12 (functional unit 125), and is therefore a component of the third circuit. On the other hand, the wire 43 is electrically connected to the lower winding 125b of the semiconductor element 12 (functional unit 125), and is therefore a component of the second circuit. In other words, the wire 41 has a relatively low potential and the wire 43 has a relatively high potential, and therefore a potential difference occurs between the wires 41 and 43. In the semiconductor device A20, the distance d5 is greater than the distance d0, and therefore it is possible to design a dielectric strength voltage between the wires 41 and 43 that satisfies actual use conditions. Therefore, the semiconductor device A20 can ensure an appropriate dielectric strength between the wires 41 and 43, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A20, the wire design process S105 is performed so that the distance d5 is greater than the distance d0. This makes it possible to design the semiconductor device A20 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A20.

[0152] In the semiconductor device A20, the potential of the lower winding 125b of the functional unit 125 in the semiconductor element 12 is approximately the same as the potential of the lead 32. In this embodiment, the semiconductor element 12 is joined to the lead 32, so the potential of the semiconductor substrate 120 is approximately the same as the potential of the lead 32. As a result, in the semiconductor device A20, the potential of the semiconductor substrate 120 and the potential of the lower winding 125b are approximately the same. Therefore, in the semiconductor device A20, the number of insulating layers 1271 between the semiconductor substrate 120 and the lower winding 125b can be reduced, and an increase in the thickness of the semiconductor element 12 can be suppressed.

[0153] In the semiconductor device A20, the lower winding 125b is electrically connected to the semiconductor element 14 by connecting a wire 43 to a pad 121 that is conductive to the lower winding 125b. The semiconductor element 14 is also joined to the lead 32. With this configuration, the lower winding 125b and the lead 32 become components of a second circuit that includes the semiconductor element 14. That is, in the semiconductor device A20, the potential of the lower winding 125b can be made substantially the same as the potential of the lead 32.

[0154] Additionally, the semiconductor device A20 has a configuration in common with the semiconductor device A10, and thus achieves the same effects as the semiconductor device A10. As can be seen from the semiconductor device A20, the semiconductor device of the present disclosure is not limited to a configuration in which the first circuit and the second circuit are isolated by one isolation element (semiconductor element 11), but also includes a configuration in which the first circuit and the second circuit are isolated by two isolation elements (semiconductor elements 11 and 12).

[0155] 30 shows a semiconductor device A21 according to a modification of the second embodiment. The semiconductor device A21 differs from the semiconductor device A20 in the following respect: the wire 41 is first bonded to the pad 122 of the semiconductor element 12, and second bonded to the pad 112 of the semiconductor element 11.

[0156] 30 , in the semiconductor device A21, the bonded portion 411 of each wire 41 is bonded to a pad 122 of the semiconductor element 12. Therefore, in the semiconductor device A21, the distance d5 is the distance between the rising section 413a of the loop portion 413 of each wire 41 and the rising section 433a of the loop portion 433 of each wire 43 in a direction perpendicular to the thickness direction z. Furthermore, the bonded portion 412 of each wire 41 is bonded to a pad 112 of the semiconductor element 11. Therefore, in the semiconductor device A21, the distance d4 is the distance between the bonded portion 412 of each wire 41 and the rising section 423a of the loop portion 423 of each wire 42 in a direction perpendicular to the thickness direction z.

[0157] In the semiconductor device A21, the semiconductor element 12 has a point p2 (see FIG. 30) corresponding to each of the multiple pads 122. Each point p2 is located between the corresponding pad 122 and the seal ring portion 123 in the first direction x. The distance d22 (see FIG. 30) between each point p2 and the pad 122 corresponding to that point p2 is, for example, not less than 50 μm and not more than 150 μm. That is, the semiconductor element 12 has a point p2 on the main surface 12a that is separated by the distance d22 in the first direction x from each pad 122 toward the seal ring portion 123. The distance d23 (see FIG. 30) between each point p2 and the wire 41 (loop portion 413) in the thickness direction z is not less than 85% and not more than 95% of the distance d3. In other words, there is a point p2 on the main surface 12a of the semiconductor element 12 where the distance d23 in the thickness direction z between the wire 41 (loop portion 413) and the main surface 12a is 85% to 95% of the distance d3, and the distance d22 in the first direction x between the point p2 and the pad 122 is 50 μm to 150 μm. Note that the distance d22 and the ratio of the distance d23 to the distance d3 are not limited to these examples.

[0158] In the semiconductor device A21, the distance d3 between the wire 41 and the semiconductor element 12 is greater than the distance d3 determined by the above formula (2). As described above, the wire 41 has an intermediate potential between the first circuit and the second circuit. Meanwhile, since the semiconductor element 12 is bonded to the island portion 321 (lead 32), the seal ring portion 123 can have the same potential as the island portion 321. In other words, the wire 41 has a relatively low voltage and the seal ring portion 123 has a relatively high voltage, resulting in a potential difference between the wire 41 and the seal ring portion 123. Since the distance d3 is greater than the distance d0 in the semiconductor device A21, it is possible to design a dielectric strength voltage between the wire 41 and the seal ring portion 123 that satisfies actual use conditions. Therefore, the semiconductor device A21 can ensure an appropriate dielectric strength voltage between the wire 41 and the semiconductor element 12, thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A21, the wire design process S104 is performed so that the distance d3 is greater than the distance d0. This makes it possible to design the semiconductor device A21 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A21. Note that in this semiconductor device A21, the lead 32 and the lead 31 are examples of the "first lead" and the "second lead" respectively set forth in the claims, the semiconductor element 12 and the semiconductor element 11 are examples of the "first semiconductor element" and the "second semiconductor element" respectively set forth in the claims, the wire 41 is an example of the "first wire" set forth in the claims, the pad 122 is an example of the "first pad" set forth in the claims, the seal ring portion 123 is an example of the "seal ring portion" set forth in the claims, and the distance d3 is an example of the "first distance" set forth in the claims.

[0159] In the semiconductor device A21, the distance d3 is greater than the distance d0, and the distance d21 in the first direction x between the pad 122 and the seal ring portion 123 is 100 μm or more and 300 μm or less. The wire 41 is a copper wire (containing copper). This configuration allows the wire 41 to rise gently while making the distance d3 greater than the distance d0. Therefore, in the semiconductor device A21, when a copper wire is used for the wire 41, the occurrence of wire cracks and damage to the semiconductor element 12 can be suppressed while making the distance d2 greater than the distance d0. In the semiconductor device A21, the distance d21 is an example of the "second distance" described in the claims.

[0160] In the semiconductor device A21, the distance d11 in the first direction x between the pad 112 and the seal ring portion 113 is 100 μm or more and 300 μm or less. The larger the distance d11, the more likely it is that the distance d2 will be greater than the distance d0, ensuring an appropriate dielectric strength voltage between the wire 41 and the seal ring portion 113. On the other hand, if the distance d11 is too large, the dimension of the semiconductor element 11 in the first direction x will increase, resulting in an increase in the size of the semiconductor device A21. In other words, having the distance d11 be 100 μm or more and 300 μm or less can prevent dielectric breakdown from occurring while also preventing the semiconductor device A21 from becoming larger.

[0161] In the semiconductor device A21, the distance d22 is 50 μm or more and 150 μm or less. The distance d22 is the separation distance between each pad 122 and a point p2 (see FIG. 30) corresponding to that pad 122. The point p2 is a point on the main surface 12a where the distance d23 in the thickness direction z from the wire 41 is 85% or more and 95% or less of the distance d3. This configuration makes it easy to make the distance d3 larger than the distance d0. That is, a distance d22 of 50 μm or more and 150 μm or less is preferable for ensuring an appropriate dielectric strength and suppressing the occurrence of dielectric breakdown. Note that in the semiconductor device A21, the point p2 is an example of a "point" as defined in the claims, the distance d22 is an example of a "third distance" as defined in the claims, and the distance d23 is an example of a "fourth distance" as defined in the claims.

[0162] In addition, the semiconductor device A21 has a configuration in common with the semiconductor device A20, and thus achieves the same effects as the semiconductor device A20. As can be understood from the semiconductor device A21, in the semiconductor device of the present disclosure, the bonding targets of the first bonding and second bonding of each wire 41 are not limited in any way.

[0163] 30, the first bonding and second bonding may be reversed for each wire 42 and each wire 43, as with each wire 41. In other words, in the semiconductor device of the present disclosure, there are no limitations on the bonding targets of each wire 42 and each wire 43 for the first bonding and the second bonding.

[0164] In the above second embodiment (including the modified example), an example was shown in which the two semiconductor elements 13 and 14 were insulated from each other by two insulating elements (two semiconductor elements 11 and 12), but this is not limited to this and the two semiconductor elements may be insulated from each other by three or more insulating elements.

[0165] Third Embodiment 31 and 32 show a semiconductor device A30 according to the third embodiment. The semiconductor device A30 differs from the semiconductor device A20 in the following respects: the semiconductor device A30 does not include the semiconductor element 13 and the semiconductor element 14. Note that the connections of the multiple wires 42 and the multiple wires 43 are merely examples and are not limited to the example shown in FIG. 31 , and can be changed as appropriate depending on the configurations of the semiconductor elements 11 and 12.

[0166] In the semiconductor device A30, the plurality of wires 42 are joined to any of the plurality of pads 111 and any of the two terminal portions 312 (coated portions 312a) of the lead 31 or any of the plurality of leads 33, thereby establishing electrical continuity between them. In other words, the plurality of wires 42 establish electrical continuity between the semiconductor element 11 and either the lead 31 or the plurality of leads 33.

[0167] In the semiconductor device A30, the plurality of wires 43 are joined to any of the plurality of pads 121 and any of the two terminal portions 322 (coated portions 322a) of the lead 32 or any of the plurality of leads 34, thereby establishing electrical continuity between them. In other words, the plurality of wires 43 establish electrical continuity between the semiconductor element 12 and the lead 32 or any of the plurality of leads 34.

[0168] In the semiconductor device A30, for example, a semiconductor element 13 is disposed on a wiring board on which the semiconductor device A30 is mounted, and the semiconductor element 13 can be electrically connected to the semiconductor element 11 via the wiring board and a plurality of leads 33. Furthermore, the lead 31 can be electrically connected to the ground of a first circuit including the semiconductor element 13 via the wiring board. Similarly, a semiconductor element 14 is disposed on the wiring board on which the semiconductor device A30 is mounted, and the semiconductor element 14 can be electrically connected to the semiconductor element 12 via the wiring board and a plurality of leads 34. Furthermore, the lead 32 can be electrically connected to the ground of a second circuit including the semiconductor element 14 via the wiring board. In this configuration, the semiconductor device A30 (semiconductor elements 11 and 12) can be used to insulate the first circuit (the circuit including the semiconductor element 13) from the second circuit (the circuit including the semiconductor element 14).

[0169] The manufacturing method of the semiconductor device A30 configured as above is the same as the manufacturing method of the semiconductor device A20 (see FIG. 27) except for the following steps: First, in the element mounting step S13, there is no step of mounting the semiconductor elements 13 and 14. Second, in the wire bonding step S14, there is no step of forming the plurality of wires 44 to 47.

[0170] The functions and effects of the semiconductor device A30, the method for designing the semiconductor device A30, and the method for manufacturing the semiconductor device A30 are as follows.

[0171] In the semiconductor device A30, as in each semiconductor device A20, the distance d2 is greater than the distance d0, making it possible to design a dielectric strength voltage that satisfies actual use conditions between the wire 41 and the seal ring portion 113. Therefore, in the semiconductor device A30, an appropriate dielectric strength voltage can be ensured between the wire 41 and the seal ring portion 113 (semiconductor element 11), thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A30, as in the design method for the semiconductor device A20, the wire design process S102 is performed to design the distance d2 to be greater than the distance d0. This makes it possible to design a semiconductor device A30 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A30. In this semiconductor device A30, the leads 31 and 32 are examples of the "first lead" and "second lead" respectively described in the claims, the semiconductor elements 11 and 12 are examples of the "first semiconductor element" and "second semiconductor element" respectively described in the claims, the wire 41 is an example of the "first wire" described in the claims, the pad 112 is an example of the "first pad" described in the claims, the seal ring portion 113 is an example of the "seal ring portion" described in the claims, and the distance d2 is an example of the "first distance" described in the claims.

[0172] In the semiconductor device A30, similar to the semiconductor devices A10 and A20, the distance d2 is greater than the distance d0, and the distance d11 in the first direction x between the pad 112 and the seal ring portion 113 is 100 μm or more and 300 μm or less. Therefore, similar to the semiconductor devices A10 and A20, the semiconductor device A30 can make the rise of the wire 41 gentler while making the distance d2 greater than the distance d0, and therefore, when a copper wire is used for the wire 41, it is possible to suppress the occurrence of wire cracks and damage to the semiconductor element 11 while making the distance d2 greater than the distance d0.

[0173] In the semiconductor device A30, similarly to the semiconductor device A20, the distance d21 is set to 100 μm or more and 300 μm or less, which makes it possible to suppress the occurrence of dielectric breakdown and to suppress an increase in the size of the semiconductor device A30.

[0174] In addition, the semiconductor device A30 (its design method and manufacturing method) has a configuration in common with the other semiconductor devices A10 and A20 (their design methods and manufacturing methods), and therefore achieves the same effects as the semiconductor devices A10 and A20 (their design methods and manufacturing methods). As can be seen from the semiconductor device A30, the semiconductor device of the present disclosure is not limited to a configuration including two semiconductor elements 13 and 14, and includes a configuration that does not include two semiconductor elements 13 and 14.

[0175] In the third embodiment, the semiconductor device A30 does not include both the semiconductor element 13 and the semiconductor element 14, but may include either one of them. In other words, the semiconductor device of the present disclosure does not need to include either or both of the semiconductor element 13 and the semiconductor element 14.

[0176] Fig. 33 shows a semiconductor device A31 according to a modification of the third embodiment. Fig. 33 is an enlarged cross-sectional view of a main part of the semiconductor device A31, which corresponds to the cross section of Fig. 32. The semiconductor device A31 differs from the semiconductor device A30 in the following respect: the wire 41 is first bonded to the pad 122 of the semiconductor element 12, and second bonded to the pad 112 of the semiconductor element 11.

[0177] 33, in the semiconductor device A31, the rising section 413a of the loop portion 413 of each wire 41 is bonded to the pad 122 of the semiconductor element 12. In the semiconductor device A31, the distance d5 is the distance between the rising section 413a of the loop portion 413 of each wire 41 and the rising section 433a of the loop portion 433 of each wire 43 in a direction perpendicular to the thickness direction z. In addition, the joint portion 412 of each wire 41 is bonded to the pad 112 of the semiconductor element 11. In the semiconductor device A31, the distance d4 is the distance between the joint portion 412 of each wire 41 and the rising section 423a of the loop portion 423 of each wire 42 in a direction perpendicular to the thickness direction z.

[0178] In the semiconductor device A31, the distance d3 between the wire 41 and the semiconductor element 12 is greater than the distance d3 determined by the above formula (2). As described above, the wire 41 has an intermediate potential between the first circuit and the second circuit. Meanwhile, since the semiconductor element 12 is bonded to the island portion 321 (lead 32), the seal ring portion 123 can have the same potential as the island portion 321. In other words, the wire 41 has a relatively low voltage and the seal ring portion 123 has a relatively high voltage, resulting in a potential difference between the wire 41 and the seal ring portion 123. Since the distance d3 is greater than the distance d0, the semiconductor device A31 can be designed to have a dielectric strength between the wire 41 and the seal ring portion 123 that satisfies actual use conditions. Therefore, the semiconductor device A31 can ensure an appropriate dielectric strength between the wire 41 and the semiconductor element 12, thereby suppressing dielectric breakdown. In the design method for the semiconductor device A31, the wire design process S104 is performed to design the distance d3 to be greater than the distance d0. This makes it possible to design the semiconductor device A31 in which the occurrence of dielectric breakdown is suppressed, and to manufacture the semiconductor device A31. In this semiconductor device A31, the lead 32 and the lead 31 are examples of the "first lead" and the "second lead," respectively, the semiconductor element 12 and the semiconductor element 11 are examples of the "first semiconductor element" and the "second semiconductor element," respectively, the wire 41 is an example of the "first wire," the pad 122 is an example of the "first pad," the seal ring portion 123 is an example of the "seal ring portion," and the distance d3 is an example of the "first distance."

[0179] In the semiconductor device A31, the distance d3 is greater than the distance d0, and the distance d21 is 100 μm or more and 300 μm or less. The wire 41 is a copper wire (containing copper). With this configuration, the wire 41 can rise gently while the distance d3 is greater than the distance d0. Therefore, when a copper wire is used for the wire 41, the semiconductor device A31 can suppress the occurrence of wire cracks and damage to the semiconductor element 11 while making the distance d3 greater than the distance d0. In the semiconductor device A31, the distance d21 is an example of the "second distance" described in the claims.

[0180] In the semiconductor device A31, similar to the semiconductor device A21, the distance d22 is 50 μm or more and 150 μm or less. Therefore, similar to the semiconductor device A21, in the semiconductor device A31, it is easy to make the distance d3 greater than the distance d0. That is, in the semiconductor device A31, it is preferable that the distance d22 is 50 μm or more and 150 μm or less in order to ensure an appropriate dielectric strength voltage and suppress the occurrence of dielectric breakdown. Note that in this semiconductor device A31, the point p2 is an example of a "point" recited in the claims, the distance d22 is an example of a "third distance" recited in the claims, and the distance d23 is an example of a "fourth distance" recited in the claims.

[0181] In addition, the semiconductor device A31 has a configuration in common with the semiconductor device A30, and thus exhibits the same effects as the semiconductor device A30. As can be understood from the semiconductor device A31, in the semiconductor device of the present disclosure, the bonding targets of the first bonding and second bonding of each wire 41 are not limited in any way.

[0182] 33, the first bonding and second bonding may be reversed for each wire 42 and each wire 43, as with each wire 41. In other words, in the semiconductor device of the present disclosure, there are no limitations on the bonding targets of each wire 42 and each wire 43 for the first bonding and the second bonding.

[0183] <Fourth embodiment> 34 and 35 show a semiconductor device A40 according to the fourth embodiment. The semiconductor device A40 differs from the semiconductor device A30 in the following respects. First, the semiconductor element 11 of the semiconductor device A40 includes a functional unit 116 in addition to the functional unit 115. Second, the semiconductor element 12 of the semiconductor device A40 includes a functional unit 126 in addition to the functional unit 125. Note that the connections of the multiple wires 42 and the multiple wires 43 are merely examples and are not limited to the example shown in FIG. 34 and can be changed as appropriate depending on the configurations of the semiconductor elements 11 and 12.

[0184] The functional unit 116 functions as the semiconductor element 13 (i.e., the control element). The functional unit 116 can be formed on, for example, the semiconductor substrate 110. The functional unit 116 is electrically connected to the functional unit 115 inside the semiconductor element 11. In the example shown in FIG. 35, the functional unit 116 is electrically connected to the lower winding 115b. In this example, the multiple pads 111 are electrically connected to the functional unit 116, and the multiple pads 112 are electrically connected to the functional unit 115 (upper winding 115a). The semiconductor element 11 of the semiconductor device A40 has a configuration in which the control element and the insulating element are integrated into a single chip.

[0185] The functional unit 126 functions as the semiconductor element 14 (i.e., the driving element). The functional unit 126 can be formed on, for example, the semiconductor substrate 120. The functional unit 126 is electrically connected to the functional unit 125 inside the semiconductor element 12. In the example shown in FIG. 35, the functional unit 126 is electrically connected to the lower winding 125b. In this example, the multiple pads 121 are electrically connected to the functional unit 126, and the multiple pads 122 are electrically connected to the functional unit 125 (upper winding 125a). The semiconductor element 12 of the semiconductor device A40 has a configuration in which the driving element and the insulating element are integrated into a single chip.

[0186] In the semiconductor device A40 configured in this manner, a first circuit including the functional unit 116 of the semiconductor element 11 and a second circuit including the functional unit 126 of the semiconductor element 12 are insulated by the functional unit 115 of the semiconductor element 11 and the functional unit 125 of the semiconductor element 12.

[0187] The manufacturing method of the semiconductor device A40 is the same as the manufacturing method of the semiconductor device A30. That is, the manufacturing method of the semiconductor device A40 is the same as the manufacturing method of the semiconductor device A30 (see FIG. 10) except for the following processes: First, in the element mounting process S13, there is no process of mounting the semiconductor elements 13 and 14. Second, in the wire bonding process S14, there is no process of forming the multiple wires 44 to 47.

[0188] The functions and effects of the semiconductor device A40, the method for designing the semiconductor device A40, and the method for manufacturing the semiconductor device A40 are as follows.

[0189] In the semiconductor device A40, as in the semiconductor device A30, the distance d2 is greater than the distance d0, making it possible to design a dielectric strength voltage that satisfies actual use conditions between the wire 41 and the seal ring portion 113. Therefore, in the semiconductor device A40, an appropriate dielectric strength voltage can be ensured between the wire 41 and the seal ring portion 113 (semiconductor element 11), thereby suppressing the occurrence of dielectric breakdown. Furthermore, in the design method for the semiconductor device A40, as in the design method for the semiconductor device A30, the wire design process S102 is performed to design the distance d2 to be greater than the distance d0. This makes it possible to design a semiconductor device A40 in which the occurrence of dielectric breakdown is suppressed, and the semiconductor device A40 can be manufactured. In this semiconductor device A40, the leads 31 and 32 are examples of the "first lead" and "second lead" respectively described in the claims, the semiconductor elements 11 and 12 are examples of the "first semiconductor element" and "second semiconductor element" respectively described in the claims, the wire 41 is an example of the "first wire" described in the claims, the pad 112 is an example of the "first pad" described in the claims, the seal ring portion 113 is an example of the "seal ring portion" described in the claims, and the distance d2 is an example of the "first distance" described in the claims.

[0190] In the semiconductor device A40, similar to the semiconductor devices A10, A20, and A30, the distance d2 is greater than the distance d0, and the distance d11 (see FIG. 35) in the first direction x between the pad 112 and the seal ring portion 113 is 100 μm or more and 300 μm or less. As a result, similar to the semiconductor devices A10, A20, and A30, the semiconductor device A40 can make the rise of the wire 41 gentler while making the distance d2 greater than the distance d0. Therefore, when a copper wire is used for the wire 41, it is possible to suppress the occurrence of wire cracks and damage to the semiconductor element 11 while making the distance d2 greater than the distance d0. In this semiconductor device A40, the distance d11 corresponds to the "second distance" recited in the claims.

[0191] In the semiconductor device A40, similar to the semiconductor devices A20 and A30, the distance d21 (see FIG. 35) in the first direction x between the pad 122 and the seal ring portion 123 is 100 μm or more and 300 μm or less. This makes it possible to prevent the semiconductor device A40 from becoming too large while suppressing the occurrence of dielectric breakdown, similar to the semiconductor devices A20 and A30.

[0192] Additionally, semiconductor device A40 (its design method and manufacturing method) has a common configuration with other semiconductor devices A10, A20, and A30 (their design methods and manufacturing methods), and thus achieves the same effects as semiconductor devices A10, A20, and A30 (their design methods and manufacturing methods). As can be seen from semiconductor device A40, in the semiconductor device of the present disclosure, semiconductor element 11 (isolation element) and semiconductor element 13 (control element) may be configured on a single chip or on separate chips. Similarly, in the semiconductor device of the present disclosure, semiconductor element 12 (isolation element) and semiconductor element 14 (drive element) may be configured on a single chip or on separate chips.

[0193] In the semiconductor device A40 of the above-described fourth embodiment, an example was shown in which the semiconductor element 11 includes the functional portion 115 and the functional portion 116, and the semiconductor element 12 includes the functional portion 125 and the functional portion 126, but it is also possible that the semiconductor element 11 does not include the functional portion 116, or that the semiconductor element 12 does not include the functional portion 126.

[0194] In the second to fourth embodiments (including the respective modifications), the semiconductor element 11 and the semiconductor element 12 are described as insulating each other by equally sharing the voltage difference between the first circuit and the second circuit. That is, the semiconductor element 11 and the semiconductor element 12 have the same insulation ratio with respect to the voltage difference between the first circuit and the second circuit. Unlike this configuration, the semiconductor element 11 and the semiconductor element 12 may have different insulation ratios with respect to the voltage difference between the first circuit and the second circuit. In this case, the number of insulating layers 1171 between the upper winding 115a and the lower winding 115b and the number of insulating layers 1271 between the upper winding 125a and the lower winding 125b differ depending on the insulation ratio between the semiconductor element 11 and the semiconductor element 12. For example, if the insulation ratio of the semiconductor element 11 is greater than that of the semiconductor element 12, the number of insulating layers 1171 will be greater than the number of insulating layers 1271. As described above, in the semiconductor device of the present disclosure, the insulation ratio between semiconductor element 11 and semiconductor element 12 is not limited in any way.

[0195] The semiconductor device, semiconductor device design method, and semiconductor device manufacturing method according to the present disclosure are not limited to the above-described embodiments. The specific configuration of each part of the semiconductor device according to the present disclosure, and the specific processing of each step of the semiconductor device design method and semiconductor device manufacturing method according to the present disclosure, can be freely designed and modified in various ways. For example, the semiconductor device, semiconductor device design method, and semiconductor device manufacturing method according to the present disclosure include embodiments related to the following supplementary notes. Note that, although examples of each component and each step (each processing) in the following supplementary notes are shown in parentheses using the symbols in the above-described embodiments (including modified examples), the present disclosure is not limited to these. Appendix 1. a conductive support (3) including first leads (31)(31) and second leads (32) arranged apart from each other in a first direction (x) perpendicular to a thickness direction (z); a first semiconductor element (11) mounted on the first lead (31); a second semiconductor element (12, 14) mounted on the second lead (32); a first wire (41) that electrically connects the first semiconductor element (11) and the second semiconductor element (12, 14); a sealing resin (5) that covers a portion of the conductive support (3), the first semiconductor element (11), the second semiconductor element (12, 14), and the first wire (41); Equipped with The first semiconductor element (11) includes a main surface (11a) facing one side in the thickness direction (z), a first pad (112) arranged on the main surface (11a), and a seal ring portion (113) having a different potential from the first pad (112), the first wire (41) includes copper and is bonded to the first pad (112); a first distance (d2) in the thickness direction (z) between the first wire (41) and the seal ring portion (113) is greater than a distance d0 determined by equation (3), In the semiconductor device (A10, A20, A30, A40), a second distance (d11) in the first direction (x) between the first pad (112) and the seal ring portion (113) is 100 μm or more and 300 μm or less.

number

number

[0196] A10, A11, A12, A20, A21, A30, A31, A40: Semiconductor device 11, 12: Semiconductor elements 11a, 12a: Main surface 11b,12b: Back side 110, 120: Semiconductor substrate 111,121: Pad 112,122: Pad 113, 123: Seal ring part 1141,1241:Protective film 1142, 1242: Passivation film 1143, 1243: Coil protective film 115,125: Functional section 115a, 125a: Upper winding 115b, 125b: Lower winding 116,126: Functional section 117,127:Laminated structure 1171, 1271: Insulating layer 118,128:Wiring section 1181, 1281: Through wiring 1182,1282: Output wiring 119,129: Conductive bonding material 13, 14: Semiconductor elements 13a, 14a: Main surface 13b,14b: Back side 131,141: Pad 139,149: Conductive bonding material 3: Conductive support 31: Lead 311: Island section 311a: Mounting surface 312:Terminal section 312a: Covering part 312b: Exposed part 313: Through hole 32: Lead 321: Island section 321a: Mounting surface 322:Terminal section 322a: Covering part 322b:Exposed part 33: Lead 33A: Intermediate lead 33B: Side lead 331: Covering part 332 :Exposed part 34: Lead 34A: Intermediate lead 34B: Side lead 341: Covering part 342 :Exposed part 4: Connection parts 41~47: Wire 411,421,431:Joint 412,422,432:Joint 413, 423, 433: Loop section 413a, 423a, 433a: Rising section 5: Sealing resin 51:Top surface 52: Bottom 53: Side 531: Upper 532: Lower 533: Middle section 54: Side 541: Upper 542: Lower 543: Middle section 81: Lead frame 810: Flat plate part 811, 812, 813, 814: Lead 811a, 812a: Island 811b, 812b: Supporting Lead 811c: Through hole 815: Outer frame 816: Dambar 82: Resist S11: Lead frame preparation process S12: Lead frame processing process S101: Lead design processing S13: Element mounting process S14: Wire bonding process S102, S103, S104, S105: Wire design processing S15: Sealing process S16:Singulation process p1,p2:point

Claims

1. a conductive support including a first lead and a second lead spaced apart from each other in a first direction perpendicular to the thickness direction; a first semiconductor element mounted on the first lead; a second semiconductor element mounted on the second lead; a first wire electrically connecting the first semiconductor element and the second semiconductor element; a sealing resin that covers a portion of the conductive support, the first semiconductor element, the second semiconductor element, and the first wire; Equipped with the first semiconductor element includes a main surface facing one side in the thickness direction, a first pad disposed on the main surface, and a seal ring portion having a different potential from the first pad; the first wire comprises copper and is bonded to the first pad; a first distance in the thickness direction between the first wire and the seal ring portion is greater than a distance d0 determined by Equation (1); a second distance in the first direction between the first pad and the seal ring portion being equal to or greater than 100 μm and equal to or less than 300 μm; [Equation 1] Here, Y is the insulation life [years] required for the semiconductor device, A and B are constants determined by the material of the sealing resin, 0.15 is an offset value for calculating the distance d0 [mm], and X is the voltage [kVrms].

2. the first semiconductor element has, on the main surface, a point that is a third distance away in the first direction from the first pad toward the seal ring portion; the third distance is equal to or greater than 50 μm and equal to or less than 150 μm, The semiconductor device according to claim 1 , wherein a fourth distance in the thickness direction between the first wire and the point is 85% to 95% of the first distance.

3. The semiconductor device according to claim 1 , wherein the second distance is greater than the first distance.

4. the first semiconductor element includes a second pad disposed on the main surface; 2. The semiconductor device according to claim 1, wherein the potential of said second pad is different from the potential of said first pad.

5. the first semiconductor element includes an upper winding and a lower winding spaced apart in the thickness direction, the upper winding is electrically connected to the first pad; The semiconductor device according to claim 4 , wherein the lower winding is electrically connected to the second pad.

6. the first semiconductor element includes a semiconductor substrate at the same potential as the first lead; 6. The semiconductor device according to claim 5, wherein the upper winding and the lower winding are located on an opposite side of the semiconductor substrate from the first lead in the thickness direction.

7. 7. The semiconductor device according to claim 6, wherein the lower winding is at the same potential as the semiconductor substrate.

8. 7. The semiconductor device according to claim 6, wherein the seal ring portion is located on the same side as the upper winding and the lower winding with respect to the thickness direction, with the semiconductor substrate as a reference, and is provided upright on the semiconductor substrate.

9. The semiconductor device according to claim 4 , further comprising a second wire bonded to said second pad.

10. The semiconductor device according to claim 9 , wherein a top of said second wire in said thickness direction is lower than a top of said first wire in said thickness direction.

11. a third semiconductor element supported by the conductive support and electrically connected to the first semiconductor element via the second wire; 11. The semiconductor device according to claim 9, wherein the first semiconductor element is an insulating element for transmitting an electrical signal between the second semiconductor element and the third semiconductor element in an insulated state.

12. The semiconductor device according to claim 11 , wherein the third semiconductor element is mounted on the first lead.

13. 11. The semiconductor device according to claim 1, wherein each of the first semiconductor element and the second semiconductor element is an insulating element for transmitting an electric signal in an insulated state.

14. 11. The semiconductor device according to claim 1, wherein the seal ring portion has an annular shape along a side surface of the first semiconductor element when viewed in the thickness direction.

15. 11. The semiconductor device according to claim 1, wherein the sealing resin comprises an epoxy resin.

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