Semiconductor integrated circuit device. motor drive device, and motor system

Abstract

To reduce the number of terminals of a semiconductor integrated circuit device.SOLUTION: A semiconductor integrated circuit device (1B) controls an inverter (INV1) which drives a three-phase motor (5). The semiconductor integrated circuit device comprises: U, V and W phase lower gate drivers (15, 17 and 19) which output U, V and W phase lower gate signals for driving U, V and W phase lower switching elements (2L, 3L and 4L) of the inverter; U, V and W phase detection circuits (OP1-OP3 and R4-R11) which detect voltages corresponding to U, V and W phase currents of the three-phase motor; a first terminal (URNF) connected to a negative-side power supply terminal of the U phase lower gate driver and an input end of the U phase detection circuit; a second terminal (VRNF) connected to a negative-side power supply terminal of the V phase lower gate driver and an input end of the V phase detection circuit; and a third terminal (WRNF) connected to a negative-side power supply terminal of the W phase lower gate driver and an input end of the W phase detection circuit.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a semiconductor integrated circuit device, a motor drive device, and a motor system. [Background technology]

[0002] Conventionally, a current detection method called a three-shunt method has been known (see, for example, Patent Document 1). The three-shunt method makes it possible to detect currents of the U phase, V phase, and W phase.

[0003] A U-phase detection circuit that detects a potential difference across a first shunt resistor through which a U-phase current flows, a V-phase detection circuit that detects a potential difference across a second shunt resistor through which a V-phase current flows, and a W-phase detection circuit that detects a potential difference across a third shunt resistor through which a W-phase current flows are provided inside or outside a semiconductor integrated circuit device that controls the three-phase inverter. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 2022-134631

[0005] [overview] When the U-phase detection circuit, V-phase detection circuit, and W-phase detection circuit are provided inside a semiconductor integrated circuit device, it is necessary to provide a terminal connected to the input terminal of the U-phase detection circuit, a terminal connected to the input terminal of the V-phase detection circuit, and a terminal connected to the input terminal of the W-phase detection circuit in the semiconductor integrated circuit device.

[0006] A semiconductor integrated circuit device according to the present disclosure is a semiconductor integrated circuit device configured to control an inverter configured to drive a three-phase motor. The semiconductor integrated circuit device includes a U-phase low-side gate driver configured to output U-phase low-side gate signals for driving U-phase low-side switching elements of the inverter, a U-phase detection circuit configured to detect a voltage corresponding to a U-phase current of the three-phase motor, and a first terminal connected to a negative power supply terminal of the U-phase low-side gate driver and an input terminal of the U-phase detection circuit. The semiconductor integrated circuit device also includes a V-phase low-side gate driver configured to output V-phase low-side gate signals for driving V-phase low-side switching elements of the inverter, a V-phase detection circuit configured to detect a voltage corresponding to a V-phase current of the three-phase motor, and a second terminal connected to a negative power supply terminal of the V-phase low-side gate driver and an input terminal of the V-phase detection circuit. The semiconductor integrated circuit device includes a W-phase low-side gate driver configured to output a W-phase low-side gate signal for driving a W-phase low-side switching element of the inverter, a W-phase detection circuit configured to detect a voltage corresponding to a W-phase current of the three-phase motor, and a third terminal connected to a negative power supply terminal of the W-phase low-side gate driver and an input terminal of the W-phase detection circuit.

[0007] A motor drive device according to the present disclosure includes the semiconductor integrated circuit device having the above configuration and the inverter.

[0008] A motor system according to the present disclosure includes the motor drive device configured as described above and the motor. [Brief explanation of the drawings]

[0009] [Figure 1] FIG. 1 is a diagram showing a comparative example of a motor system. [Figure 2] FIG. 2 is a perspective view of the appearance of the semiconductor integrated circuit device. [Figure 3] FIG. 3 is a diagram showing a first embodiment of a motor system. [Figure 4] FIG. 4 is a diagram showing a second embodiment of the motor system. [Figure 5] FIG. 5 is a diagram showing a third embodiment of the motor system. [Figure 6] FIG. 6 is a diagram showing a fourth embodiment of the motor system. [Figure 7] FIG. 7 is a schematic diagram of a double wire.

[0010] [Detailed explanation] <Motor system (comparison example)> 1 is a diagram showing a comparative example of a motor system (= a general configuration to be compared with the embodiments described later). The motor system SYS1A of this comparative example includes a semiconductor integrated circuit device 1A, high-side switches 2H-4H, low-side switches 2L-4L, shunt resistors R1-R3, a three-phase motor 5, and a host device 6.

[0011] In FIG. 1, the high-side switches 2H to 4H and the low-side switches 2L to 4L are each an N-channel MOS (Metal Oxide Semiconductor) field-effect transistor. The high-side switches 2H to 4H and the low-side switches 2L to 4L may each be configured with a switch element other than an N-channel MOS field-effect transistor. The high-side switches 2H to 4H and the low-side switches 2L to 4L form an inverter INV1. The semiconductor integrated circuit device 1A and the inverter INV form a motor drive device. The three-phase motor 5 is a three-phase brushless DC motor. The host device 6 is, for example, an MCU (Micro Controller Unit).

[0012] The semiconductor integrated circuit device 1A drives a three-phase motor 5 via an inverter INV1 based on a control signal output from a host device 6.

[0013] The connection node between high-side switch 2H and low-side switch 2L is connected to the U-phase of three-phase motor 5. The connection node between high-side switch 3H and low-side switch 3L is connected to the V-phase of three-phase motor 5. The connection node between high-side switch 4H and low-side switch 4L is connected to the W-phase of three-phase motor 5.

[0014] A shunt resistor R1 is provided between the low-side switch 2L and the ground potential. A shunt resistor R2 is provided between the low-side switch 3L and the ground potential. A shunt resistor R3 is provided between the low-side switch 4L and the ground potential.

[0015] FIG. 2 is an external perspective view of the semiconductor integrated circuit device 1A. The semiconductor integrated circuit device 1A is an electronic component including a semiconductor chip having a semiconductor integrated circuit formed on a semiconductor substrate, a housing (package) that houses the semiconductor chip, and a plurality of external terminals that are exposed to the outside of the semiconductor integrated circuit device 1A from the housing. The semiconductor integrated circuit device 1A is formed by encapsulating the semiconductor chip in a housing (package) made of resin. Note that the number of external terminals of the semiconductor integrated circuit device 1A and the type of housing of the semiconductor integrated circuit device 1A shown in FIG. 2 are merely examples, and can be designed as desired. The external appearances of semiconductor integrated circuit devices 1B to 1E, which will be described later, are similar to that of the semiconductor integrated circuit device 1A.

[0016] As shown in FIG. 1, the semiconductor integrated circuit device 1A includes a communication circuit 10, a control circuit 11, a high-side gate driver power supply circuit 12, a low-side gate driver power supply circuit 13, pre-drivers 14 to 19 which are gate drivers, detection circuits D1 to D3, and an ADC (analog to digital converter) 20.

[0017] The semiconductor integrated circuit device 1A also includes terminals C, UH, UO, UL, URNF, VH, VO, VL, VRNF, WH, WO, WL, WRNF, INP1, INN1, INP2, INN2, INP3, INN3, OUT1, OUT2, and OUT3 as external terminals for establishing electrical connection with the outside. Although not shown in FIG. 1, the semiconductor integrated circuit device 1A also includes external terminals such as a power supply terminal and a ground terminal. Semiconductor integrated circuit devices 1B to 1E, which will be described later, also include external terminals such as a power supply terminal and a ground terminal. Although only one terminal C is shown in FIG. 1, the semiconductor integrated circuit device 1A may include one or more terminals C. Semiconductor integrated circuit devices 1B to 1E, which will be described later, also include one or more terminals C.

[0018] The communication circuit 10 communicates with the host device 6 .

[0019] The control circuit 11 controls the pre-drivers 14 to 19 based on the control signal output from the host device 6 and the output of the ADC 20, thereby controlling the energization of the three-phase motor 5. The control method of the control circuit 11 is, for example, vector control.

[0020] The pre-drivers 14, 16, and 18 drive the high-side switches 2H to 4H, respectively. The pre-drivers 15, 17, and 19 drive the low-side switches 2L to 4L, respectively.

[0021] The output voltage of the high-side gate driver power supply circuit 12 is supplied to the positive power supply terminals of the pre-drivers 14, 16, and 18, respectively.

[0022] The output voltage of the low-side gate driver power supply circuit 13 is supplied to the positive power supply terminals of the pre-drivers 15, 17, and 19, respectively.

[0023] The detection circuit D1 detects the potential difference across the shunt resistor R1 (a voltage corresponding to the U-phase current of the three-phase motor 5). The detection circuit D1 includes resistors R4 to R6 and an operational amplifier OP1. A reference voltage REF is applied to the inverting input terminal of the operational amplifier OP1.

[0024] The detection circuit D2 detects the potential difference across the shunt resistor R2 (a voltage corresponding to the V-phase current of the three-phase motor 5). The detection circuit D2 includes resistors R7 to R9 and an operational amplifier OP2. A reference voltage REF is applied to the inverting input terminal of the operational amplifier OP2.

[0025] The detection circuit D3 detects the potential difference across the shunt resistor R3 (a voltage corresponding to the W-phase current of the three-phase motor 5). The detection circuit D3 includes resistors R10 to R12 and an operational amplifier OP3. A reference voltage REF is applied to the inverting input terminal of the operational amplifier OP3.

[0026] The outputs of the detection circuits D1 to D3 are converted into digital voltages by the ADC 10 and supplied to the control circuit 11.

[0027] The terminal C is connected to a communication circuit 10 inside the semiconductor integrated circuit device 1A, and is connected to a host device 6 outside the semiconductor integrated circuit device 1A.

[0028] The terminal UH is connected to the output terminal of the pre-driver 14 inside the semiconductor integrated circuit device 1A, and is connected to the gate of the high-side switch 2H outside the semiconductor integrated circuit device 1A. The terminal UO is connected to the negative power supply terminal of the pre-driver 14 inside the semiconductor integrated circuit device 1A, and is connected to the connection node between the high-side switch 2H and the low-side switch 2L outside the semiconductor integrated circuit device 1A.

[0029] The terminal UL is connected to the output terminal of the pre-driver 15 inside the semiconductor integrated circuit device 1A, and is connected to the gate of the low-side switch 2L outside the semiconductor integrated circuit device 1A. The terminal URNF is connected to the negative power supply terminal of the pre-driver 15 inside the semiconductor integrated circuit device 1A, and is connected to the source of the low-side switch 2L outside the semiconductor integrated circuit device 1A.

[0030] The terminal VH is connected to the output terminal of the pre-driver 16 inside the semiconductor integrated circuit device 1A, and is connected to the gate of the high-side switch 3H outside the semiconductor integrated circuit device 1A. The terminal VO is connected to the negative power supply terminal of the pre-driver 16 inside the semiconductor integrated circuit device 1A, and is connected to the connection node between the high-side switch 3H and the low-side switch 3L outside the semiconductor integrated circuit device 1A.

[0031] The terminal VL is connected to the output terminal of the pre-driver 17 inside the semiconductor integrated circuit device 1A, and is connected to the gate of the low-side switch 3L outside the semiconductor integrated circuit device 1A. The terminal VRNF is connected to the negative power supply terminal of the pre-driver 17 inside the semiconductor integrated circuit device 1A, and is connected to the source of the low-side switch 3L outside the semiconductor integrated circuit device 1A.

[0032] The terminal WH is connected to the output terminal of the pre-driver 18 inside the semiconductor integrated circuit device 1A, and is connected to the gate of the high-side switch 4H outside the semiconductor integrated circuit device 1A. The terminal WO is connected to the negative power supply terminal of the pre-driver 18 inside the semiconductor integrated circuit device 1A, and is connected to the connection node between the high-side switch 4H and the low-side switch 4L outside the semiconductor integrated circuit device 1A.

[0033] The terminal WL is connected to the output terminal of the pre-driver 19 inside the semiconductor integrated circuit device 1A, and is connected to the gate of the low-side switch 4L outside the semiconductor integrated circuit device 1A. The terminal WRNF is connected to the negative power supply terminal of the pre-driver 19 inside the semiconductor integrated circuit device 1A, and is connected to the source of the low-side switch 4L outside the semiconductor integrated circuit device 1A.

[0034] The terminal INP1 is connected to a positive input terminal of the detection circuit D1 inside the semiconductor integrated circuit device 1A, and is connected to a first end of the shunt resistor R1 via a low-pass filter circuit F1 outside the semiconductor integrated circuit device 1A. The terminal INN1 is connected to a negative input terminal of the detection circuit D1 inside the semiconductor integrated circuit device 1A, and is connected to a second end of the shunt resistor R1 outside the semiconductor integrated circuit device 1A.

[0035] The terminal INP2 is connected to a positive input terminal of the detection circuit D2 inside the semiconductor integrated circuit device 1A, and is connected to a first end of the shunt resistor R2 via a low-pass filter circuit F2 outside the semiconductor integrated circuit device 1A. The terminal INN2 is connected to a negative input terminal of the detection circuit D2 inside the semiconductor integrated circuit device 1A, and is connected to a second end of the shunt resistor R2 outside the semiconductor integrated circuit device 1A.

[0036] The terminal INP3 is connected to a positive input terminal of the detection circuit D3 inside the semiconductor integrated circuit device 1A, and is connected to a first end of the shunt resistor R3 via a low-pass filter circuit F3 outside the semiconductor integrated circuit device 1A. The terminal INN3 is connected to a negative input terminal of the detection circuit D3 inside the semiconductor integrated circuit device 1A, and is connected to a second end of the shunt resistor R3 outside the semiconductor integrated circuit device 1A.

[0037] Terminal OUT1 is connected to the output terminal of detection circuit D2 and a first input terminal of ADC 20 inside semiconductor integrated circuit device 1A. Terminal OUT2 is connected to the output terminal of detection circuit D2 and a second input terminal of ADC 20 inside semiconductor integrated circuit device 1A. Terminal OUT3 is connected to the output terminal of detection circuit D2 and a third input terminal of ADC 20 inside semiconductor integrated circuit device 1A.

[0038] If there is no need to prevent switching noise of the inverter INV1 from flowing into the detection circuits D1-D3, the low-pass filter circuits F1-F3 may be omitted. Also, if there is no need to debug the outputs of the detection circuits D1-D3, the output terminals OUT1-OUT3 may not be provided in the semiconductor integrated circuit device 1A.

[0039] Compared to a configuration in which the detection circuits D1 to D3 are provided externally to the semiconductor integrated circuit device, the semiconductor integrated circuit device 1A has six additional terminals. This increases the package size of the semiconductor integrated circuit device 1A. Alternatively, if the terminals not associated with the detection circuits D1 to D3 are reduced in order to prevent the package size from increasing, this would result in a decrease in the functionality of the semiconductor integrated circuit device 1A. The following embodiments can solve this problem.

[0040] <Motor system (first embodiment)> Fig. 3 is a diagram showing a first embodiment of the motor system. In Fig. 3 and other figures described later, the same parts as in Fig. 1 are given the same reference numerals, and descriptions of the same parts as in Fig. 1 will be omitted as appropriate.

[0041] The motor system SYS1B of this embodiment includes a semiconductor integrated circuit device 1B, high-side switches 2H to 4H, low-side switches 2L to 4L, shunt resistors R1 to R3, a three-phase motor 5, and a host device 6.

[0042] The semiconductor integrated circuit device 1B does not include terminals INP1-INP3 and terminals OUT1-OUT3. Therefore, compared to the semiconductor integrated circuit device 1A, the semiconductor integrated circuit device 1B can reduce the number of external terminals for establishing electrical connection with the outside, thereby enabling a smaller package size. Note that, since the semiconductor integrated circuit device 1B does not include terminals OUT1-OUT3, it is not possible to debug the outputs of the detection circuits D1-D3, but other functions can be made equivalent to those of the semiconductor integrated circuit device 1A.

[0043] The terminal URNF is connected not only to the negative power supply terminal of the pre-driver 15 inside the semiconductor integrated circuit device 1B but also to the positive input terminal of the detection circuit D1. With this configuration, even if the semiconductor integrated circuit device 1B is not provided with the terminal INP1, the detection circuit D1 can detect the potential difference across the shunt resistor R1 (the voltage corresponding to the U-phase current of the three-phase motor 5).

[0044] The terminal VRNF is connected not only to the negative power supply terminal of the pre-driver 17 inside the semiconductor integrated circuit device 1B but also to the positive input terminal of the detection circuit D2. With this configuration, even if the semiconductor integrated circuit device 1B is not provided with the terminal INP2, the detection circuit D2 can detect the potential difference across the shunt resistor R2 (a voltage corresponding to the V-phase current of the three-phase motor 5).

[0045] The terminal WRNF is connected not only to the negative power supply terminal of the pre-driver 19 inside the semiconductor integrated circuit device 1B but also to the positive input terminal of the detection circuit D3. With this configuration, even if the semiconductor integrated circuit device 1B is not provided with the terminal INP13, the detection circuit D3 can detect the potential difference across the shunt resistor R3 (a voltage corresponding to the W-phase current of the three-phase motor 5).

[0046] <Motor system (second embodiment)> 4 is a diagram showing a motor system according to a second embodiment of the present invention. The motor system SYS1C according to this embodiment includes a semiconductor integrated circuit device 1C, high-side switches 2H to 4H, low-side switches 2L to 4L, shunt resistors R1 to R3, a three-phase motor 5, and a host device 6.

[0047] The semiconductor integrated circuit device 1C has a configuration in which terminals OUT1 to OUT3 are added to the semiconductor integrated circuit device 1B. Therefore, the semiconductor integrated circuit device 1C can debug the outputs of the detection circuits D1 to D3.

[0048] <Motor system (third embodiment)> 5 is a diagram showing a motor system according to a third embodiment of the present invention. The motor system SYS1D according to this embodiment includes a semiconductor integrated circuit device 1D, high-side switches 2H to 4H, low-side switches 2L to 4L, shunt resistors R1 to R3, a three-phase motor 5, and a host device 6.

[0049] The semiconductor integrated circuit device 1D has a configuration in which resistors R13 to R15 are added to the semiconductor integrated circuit device 1C.

[0050] The resistor R13 is provided between the detection circuit D1 and the terminal OUT1. The terminal OUT1 is connected to the output terminal of the detection circuit D1 and the first input terminal of the ADC 20 via the resistor R13 inside the semiconductor integrated circuit device 1D.

[0051] The resistor R14 is provided between the detection circuit D2 and the terminal OUT2. The terminal OUT2 is connected to the output terminal of the detection circuit D2 and the second input terminal of the ADC 20 via the resistor R14 inside the semiconductor integrated circuit device 1D.

[0052] The resistor R15 is provided between the detection circuit D3 and the terminal OUT3. The terminal OUT3 is connected to the output terminal of the detection circuit D3 and the third input terminal of the ADC 20 via the resistor R15 inside the semiconductor integrated circuit device 1D.

[0053] 5, when a first end of a capacitor C1 is connected to a terminal OUT1 outside the semiconductor integrated circuit device 1D and a second end of the capacitor C1 is connected to ground potential, a low-pass filter circuit is formed by the resistor R13 and the capacitor C1. The low-pass filter circuit including the resistor R13 and the capacitor C1 can suppress switching noise of the inverter INV1 from flowing from the detection circuit D1 to the ADC 20.

[0054] 5, when a first end of a capacitor C2 is connected to a terminal OUT2 outside the semiconductor integrated circuit device 1D and a second end of the capacitor C2 is connected to the ground potential, a low-pass filter circuit is formed by the resistor R14 and the capacitor C2. The low-pass filter circuit including the resistor R14 and the capacitor C2 can suppress switching noise of the inverter INV1 from flowing from the detection circuit D2 to the ADC 20.

[0055] 5, when a first end of a capacitor C3 is connected to a terminal OUT3 outside the semiconductor integrated circuit device 1D and a second end of the capacitor C3 is connected to the ground potential, a low-pass filter circuit is formed by the resistor R15 and the capacitor C3. The low-pass filter circuit including the resistor R15 and the capacitor C3 can suppress switching noise of the inverter INV1 from flowing from the detection circuit D3 to the ADC 20.

[0056] Note that by observing the voltages of the terminals OUT1 to OUT3 outside the semiconductor integrated circuit device 1D, it is also possible to debug the outputs of the detection circuits D1 to D3.

[0057] <Motor system (fourth embodiment)> 6 is a diagram showing a fourth embodiment of the motor system SYS1E. The motor system SYS1E of this embodiment includes a semiconductor integrated circuit device 1E, high-side switches 2H to 4H, low-side switches 2L to 4L, shunt resistors R1 to R3, a three-phase motor 5, and a host device 6.

[0058] The semiconductor integrated circuit device 1E has a configuration in which switches SW1 to SW3 are added to the semiconductor integrated circuit device 1D.

[0059] The switch SW1 is connected in parallel with the resistor R13. The switch SW2 is connected in parallel with the resistor R14. The switch SW3 is connected in parallel with the resistor R15.

[0060] 6, each of the switches SW1 to SW3 is an N-channel MOS field effect transistor. However, each of the switches SW1 to SW3 may be configured with a switch element other than an N-channel MOS field effect transistor.

[0061] For example, the control circuit 11 includes a register that stores the on / off settings of the switches SW1 to SW3, and controls the switches SW1 to SW3 based on the settings stored in the register. The on / off settings of the switches SW1 to SW3 may be changed by the host device 6, for example.

[0062] As shown in FIG. 6, when a first end of a capacitor C1 is connected to a terminal OUT1 outside the semiconductor integrated circuit device 1E and the first end of the capacitor C1 is connected to the ground potential, the control circuit 11 turns the switch SW1 off.

[0063] As shown in FIG. 6, when a first end of a capacitor C2 is connected to a terminal OUT2 outside the semiconductor integrated circuit device 1E and the first end of the capacitor C2 is connected to the ground potential, the control circuit 11 turns off the switch SW2.

[0064] As shown in FIG. 6, when a first end of a capacitor C3 is connected to a terminal OUT3 outside the semiconductor integrated circuit device 1E and the first end of the capacitor C3 is connected to the ground potential, the control circuit 11 turns off the switch SW3.

[0065] On the other hand, when capacitor C1 is not connected to terminal OUT1, capacitor C2 is not connected to terminal OUT2, and capacitor C3 is not connected to terminal OUT3 outside the semiconductor integrated circuit device 1E, switches SW1 to SW3 are turned on by control circuit 11. By turning on switches SW1 to SW3, the impedance of the analog voltage transmission path between detection circuits D1 to D3 and ADC 20 can be reduced, and the propagation delay time of the analog voltage transmission path between detection circuits D1 to D3 and ADC 20 can be reduced.

[0066] <Double wire> 7 is a schematic diagram of a double wire applicable to each of the first to fourth embodiments. The semiconductor integrated circuit device includes a semiconductor chip CH1, terminals URNF, VRNF, and WRNF, and wires W1 to W6. The semiconductor chip CH1 includes pads P1 to P6.

[0067] The pad P1 is connected to a negative power supply terminal of a pre-driver 15 (not shown in FIG. 7) inside the semiconductor chip CH1, and the pad P2 is connected to a positive input terminal of a detection circuit D1 (not shown in FIG. 7) inside the semiconductor chip CH1.

[0068] The pad P3 is connected to a negative power supply terminal of a pre-driver 17 (not shown in FIG. 7) inside the semiconductor chip CH1, and the pad P4 is connected to a positive input terminal of a detection circuit D2 (not shown in FIG. 7) inside the semiconductor chip CH1.

[0069] The pad P5 is connected to a negative power supply terminal of a pre-driver 19 (not shown in FIG. 7) inside the semiconductor chip CH1, and the pad P6 is connected to a positive input terminal of a detection circuit D3 (not shown in FIG. 7) inside the semiconductor chip CH1.

[0070] The wire W1 connects the terminal URNF and the pad P1. The wire W2 connects the terminal URNF and the pad P2. The double-wire configuration of the wires W1 and W2 can reduce the influence of impedance on the detection of the detection circuit D1.

[0071] The wire W3 connects the terminal VRNF and the pad P3. The wire W4 connects the terminal VRNF and the pad P4. The double-wire configuration of the wires W3 and W4 can reduce the influence of impedance on the detection of the detection circuit D2.

[0072] A wire W5 connects the terminal WRNF and the pad P5. A wire W6 connects the terminal WRNF and the pad P6. The double-wire configuration of the wires W5 and W6 can reduce the influence of impedance on the detection of the detection circuit D3.

[0073] <Additional Notes> A supplementary note will be provided for the present disclosure, the specific configuration examples of which have been shown in the above-described embodiments.

[0074] A semiconductor integrated circuit device (1B, 1C, 1D, 1E) of the present disclosure is a semiconductor integrated circuit device configured to control an inverter (INV1) configured to drive a three-phase motor (5), and includes a U-phase low-side gate driver (15) configured to output a U-phase low-side gate signal for driving a U-phase low-side switching element (2L) of the inverter, a U-phase detection circuit (D1) configured to detect a voltage corresponding to a U-phase current of the three-phase motor, a first terminal (URNF) connected to a negative power supply terminal of the U-phase low-side gate driver and an input terminal of the U-phase detection circuit, and a V-phase low-side gate driver (15) configured to output a V-phase low-side gate signal for driving a V-phase low-side switching element (3L) of the inverter. a V-phase detection circuit (D2) configured to detect a voltage corresponding to a V-phase current of the three-phase motor; a second terminal (VRNF) connected to a negative power supply terminal of the V-phase low-side gate driver and an input terminal of the V-phase detection circuit; a W-phase low-side gate driver (19) configured to output a W-phase low-side gate signal for driving a W-phase low-side switching element (4L) of the inverter; a W-phase detection circuit (D3) configured to detect a voltage corresponding to a W-phase current of the three-phase motor; and a third terminal (WRNF) connected to a negative power supply terminal of the W-phase low-side gate driver and an input terminal of the W-phase detection circuit.

[0075] In the semiconductor integrated circuit device of the first configuration, the negative power supply terminal of the U-phase lower gate driver and the input terminal of the U-phase detection circuit are connected to the same terminal (first terminal), the negative power supply terminal of the V-phase lower gate driver and the input terminal of the V-phase detection circuit are connected to the same terminal (second terminal), and the negative power supply terminal of the W-phase lower gate driver and the input terminal of the W-phase detection circuit are connected to the same terminal (third terminal), making it possible to reduce the number of terminals of the semiconductor integrated circuit device.

[0076] In the semiconductor integrated circuit device of the first configuration, a first pad (P1) connected to a negative power supply terminal of the U-phase low-side gate driver, a second pad (P2) connected to an input end of the U-phase detection circuit, a first wire (W1) connecting the first terminal and the first pad, a second wire (W2) connecting the first terminal and the second pad, a third pad (P3) connected to a negative power supply terminal of the V-phase low-side gate driver, and a fourth pad (P4) connected to an input end of the V-phase detection circuit. a third wire (W3) connecting the second terminal and the third pad, a fourth wire (W4) connecting the second terminal and the fourth pad, a fifth pad (P5) connected to the negative power supply terminal of the W-phase low-side gate driver, a sixth pad (P6) connected to the input end of the W-phase detection circuit, a fifth wire (W5) connecting the third terminal and the fifth pad, and a sixth wire (W6) connecting the third terminal and the sixth pad (P6).

[0077] The semiconductor integrated circuit device of the first or second configuration may be configured (third configuration) to include a fourth terminal (OUT1) connected to the output terminal of the U-phase detection circuit, a fifth terminal (OUT2) connected to the output terminal of the V-phase detection circuit, and a sixth terminal (OUT3) connected to the output terminal of the W-phase detection circuit.

[0078] The semiconductor integrated circuit device of the third configuration may be configured (fourth configuration) to include a first resistor (R13), a second resistor (R14), and a third resistor (R15), wherein the fourth terminal is connected to the output terminal of the U-phase detection circuit via the first resistor, the fifth terminal is connected to the output terminal of the V-phase detection circuit via the second resistor, and the sixth terminal is connected to the output terminal of the V-phase detection circuit via the third resistor.

[0079] The semiconductor integrated circuit device of the fourth configuration may be configured (fifth configuration) to include a first switch (SW1) connected in parallel to the first resistor, a second switch (SW2) connected in parallel to the second resistor, and a third switch (SW3) connected in parallel to the third resistor.

[0080] The motor drive device of the present disclosure has a configuration (sixth configuration) including the semiconductor integrated circuit device of any one of the first to fifth configurations and the inverter.

[0081] The motor systems (SYS1B, SYS1C, SYS1D, SYS1E) of the present disclosure have a configuration (seventh configuration) that includes the motor drive device of the sixth configuration and the motor. [Explanation of symbols]

[0082] 1A~1E Semiconductor integrated circuit device 2H~4H High Side Switch 2L~4L low side switch 5 Three-phase motor 6 Host Device 10 Communication Circuits 11 Control circuit 12 High-side gate driver power supply circuit 13 Low-side gate driver power supply circuit 14~19 Pre-driver 20 ADC C, UH, UO, UL, URNF, VH, VO, VL, VRNF, WH, WO, WL, WRNF, INP1, INN1, INP2, INN2, INP3, INN3, OUT1, OUT2, OUT3 terminal CH1 semiconductor chip D1~D3 detection circuit F1~F3 filter circuit OP1~OP3 operational amplifiers P1~P6 pads R1~R3 ​​shunt resistors R4~R15 shunt resistors SW1~SW3 switches SYS1A~SYS1E Motor Systems W1~W6 wires

Claims

1. 1. A semiconductor integrated circuit device configured to control an inverter configured to drive a three-phase motor, comprising: a U-phase low-side gate driver configured to output a U-phase low-side gate signal for driving a U-phase low-side switching element of the inverter; a U-phase detection circuit configured to detect a voltage corresponding to a U-phase current of the three-phase motor; a first terminal connected to a negative power supply terminal of the U-phase low-side gate driver and an input terminal of the U-phase detection circuit; a V-phase low-side gate driver configured to output a V-phase low-side gate signal for driving a V-phase low-side switching element of the inverter; a V-phase detection circuit configured to detect a voltage corresponding to a V-phase current of the three-phase motor; a second terminal connected to a negative power supply terminal of the V-phase low-side gate driver and an input terminal of the V-phase detection circuit; a W-phase low-side gate driver configured to output a W-phase low-side gate signal for driving a W-phase low-side switching element of the inverter; a W-phase detection circuit configured to detect a voltage corresponding to a W-phase current of the three-phase motor; a third terminal connected to a negative power supply terminal of the W-phase low-side gate driver and an input terminal of the W-phase detection circuit; A semiconductor integrated circuit device comprising:

2. a first pad connected to a negative power supply terminal of the U-phase low-side gate driver; a second pad connected to an input terminal of the U-phase detection circuit; a first wire connecting the first terminal and the first pad; a second wire connecting the first terminal and the second pad; a third pad connected to a negative power supply terminal of the V-phase low-side gate driver; a fourth pad connected to an input terminal of the V-phase detection circuit; a third wire connecting the second terminal and the third pad; a fourth wire connecting the second terminal and the fourth pad; a fifth pad connected to a negative power supply terminal of the W-phase low-side gate driver; a sixth pad connected to an input end of the W-phase detection circuit; a fifth wire connecting the third terminal and the fifth pad; a sixth wire connecting the third terminal and the sixth pad; 2. The semiconductor integrated circuit device according to claim 1, comprising:

3. a fourth terminal connected to the output terminal of the U-phase detection circuit; a fifth terminal connected to the output end of the V-phase detection circuit; a sixth terminal connected to the output end of the W-phase detection circuit; 2. The semiconductor integrated circuit device according to claim 1, comprising:

4. A first resistor; A second resistor; and A third resistor; Equipped with the fourth terminal is connected to an output terminal of the U-phase detection circuit via the first resistor; the fifth terminal is connected to an output terminal of the V-phase detection circuit via the second resistor; 4. The semiconductor integrated circuit device according to claim 3, wherein said sixth terminal is connected to an output end of said V-phase detection circuit via said third resistor.

5. a first switch connected in parallel with the first resistor; a second switch connected in parallel to the second resistor; a third switch connected in parallel to the third resistor; 5. The semiconductor integrated circuit device according to claim 4, comprising:

6. A motor drive device comprising: the semiconductor integrated circuit device according to any one of claims 1 to 5; and the inverter.

7. A motor system comprising: the motor drive device according to claim 6; and the motor.

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