Method for manufacturing silicon carbide semiconductor device

Abstract

To provide a method for manufacturing silicon carbide semiconductor devices that can reduce the variation in Von without Von ranking after manufacturing.SOLUTION: A method for manufacturing a silicon carbide semiconductor device includes a first step of forming, on a front surface of a first conductivity type silicon carbide semiconductor substrate, an epitaxial film of a first conductivity type having a lower impurity concentration than the silicon carbide semiconductor substrate, a second step of evaluating the film thickness or carrier concentration of the epitaxial film, a third step of estimating an on-voltage from the film thickness or carrier concentration, a fourth step of ranking and selecting the silicon carbide semiconductor substrates based on the estimated on-voltage, and a fifth step of forming an element structure on the selected silicon carbide semiconductor substrate.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This disclosure relates to methods for manufacturing silicon carbide semiconductor devices. [Background technology]

[0002] Conventionally, a technique has been known in which the JFET resistance in a chip region is adjusted to set the on-voltage of SiC-MOSFETs to be approximately the same in all chip regions within the surface of a semiconductor wafer (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2023-31337 Summary of the Invention [Problem to be solved by the invention]

[0004] In conventional methods for manufacturing silicon carbide semiconductor devices, it is not possible to stabilize variations in Von (on-state voltage) simply by controlling the manufacturing process, and therefore there is a problem in that the silicon carbide semiconductor devices must be ranked by Von after they are manufactured. An object of this disclosure is to provide a method for manufacturing a silicon carbide semiconductor device that can reduce variations in Von without ranking Von after manufacturing. [Means for solving the problem]

[0005] In order to solve the above-mentioned problems and achieve the object of the present disclosure, a method for manufacturing a silicon carbide semiconductor device according to this disclosure has the following features: A first step is performed in which an epitaxial film of a first conductivity type is formed on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, the epitaxial film having a lower impurity concentration than the silicon carbide semiconductor substrate. Next, a second step is performed in which a film thickness or carrier concentration of the epitaxial film is evaluated. Next, a third step is performed in which an on-voltage is estimated from the film thickness or the carrier concentration. Next, a fourth step is performed in which the silicon carbide semiconductor substrates are ranked and selected based on the estimated on-voltage. Next, a fifth step is performed in which an element structure is formed on the selected silicon carbide semiconductor substrate.

[0006] According to the above disclosure, the Von value is estimated from the thickness and carrier concentration of the epitaxial film. This makes it possible to stabilize the variation in Von by controlling the manufacturing process, and eliminates the need to rank silicon carbide semiconductor devices by Von after manufacturing. [Effects of the Invention]

[0007] The method for manufacturing a silicon carbide semiconductor device according to the present disclosure advantageously reduces variations in Von without requiring Von ranking after manufacturing. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a flowchart showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. [Figure 2] 1 is a cross-sectional view showing a structure of a silicon carbide semiconductor device according to an embodiment; [Figure 3] 1 is a graph showing the relationship between the film thickness of an epitaxial film and Von in a silicon carbide semiconductor device (part 1). [Figure 4] 1 is a graph showing the relationship between carrier concentration and Von in an epitaxial film in a silicon carbide semiconductor device (part 1). [Figure 5] 10 is a graph showing the relationship between the film thickness of an epitaxial film and Von in a silicon carbide semiconductor device (part 2). [Figure 6] 10 is a graph showing the relationship between carrier concentration and Von in an epitaxial film in a silicon carbide semiconductor device (part 2). [Figure 7] 10 is a graph showing the distribution of Von ranks according to the carrier concentration of an epitaxial film in a manufacturing method of a silicon carbide semiconductor device according to an embodiment. [Figure 8] 10 is a graph showing the distribution of Von ranks according to the film thickness of an epitaxial film in a manufacturing method of a silicon carbide semiconductor device according to an embodiment. [Figure 9] 1 is a flowchart showing a conventional method for manufacturing a silicon carbide semiconductor device. [Figure 10] 10 is a graph showing the distribution of Von ranks according to Von measurement values ​​in a conventional method for manufacturing a silicon carbide semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Summary of Embodiments of the Present Disclosure> In order to solve the above-mentioned problems and achieve the object of the present disclosure, a method for manufacturing a silicon carbide semiconductor device according to this disclosure has the following features: A first step is performed in which an epitaxial film of a first conductivity type is formed on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, the epitaxial film having a lower impurity concentration than the silicon carbide semiconductor substrate. Next, a second step is performed in which a film thickness or carrier concentration of the epitaxial film is evaluated. Next, a third step is performed in which an on-voltage is estimated from the film thickness or the carrier concentration. Next, a fourth step is performed in which the silicon carbide semiconductor substrates are ranked and selected based on the estimated on-voltage. Next, a fifth step is performed in which an element structure is formed on the selected silicon carbide semiconductor substrate.

[0010] According to the above disclosure, the Von value is estimated from the thickness and carrier concentration of the epitaxial film. This makes it possible to stabilize the variation in Von by controlling the manufacturing process, and eliminates the need to rank silicon carbide semiconductor devices by Von after manufacturing.

[0011] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, in the second step, both the film thickness and the carrier concentration are evaluated, and in the third step, an on-state voltage is estimated from the film thickness and the carrier concentration.

[0012] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the above disclosure, in the fourth step, the selected silicon carbide semiconductor substrates are ranked into a plurality of ranks based on the film thickness or the carrier concentration.

[0013] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the on-voltage of the silicon carbide semiconductor device is not inspected after the fifth step.

[0014] According to the above disclosure, the number of steps required for Von inspection can be reduced.

[0015] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the above disclosure, includes a sixth step, after the fourth step and before the fifth step, of bringing the on-voltage of the silicon carbide semiconductor substrates that have not been sorted into a standard range.

[0016] According to the above disclosure, silicon carbide semiconductor devices that are deemed out of standard and cannot be shipped using existing manufacturing methods can be made to meet the standards and can be shipped.

[0017] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, the sixth step is a step of implanting an impurity into the epitaxial film.

[0018] Furthermore, in the method for manufacturing a silicon carbide semiconductor device according to the present disclosure, in the above disclosure, the sixth step is a step of changing the width of any one or more of the portions of the JFET section in the fifth step.

[0019] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the fifth step includes a step of forming a current diffusion layer of a first conductivity type on the epitaxial film, and the sixth step is a step of changing an impurity concentration of the current diffusion layer.

[0020] Furthermore, the method for manufacturing a silicon carbide semiconductor device according to the present disclosure is characterized in that, in the above disclosure, the fifth step includes a step of forming a base layer of a second conductivity type on the epitaxial film, and the sixth step is a step of changing an impurity concentration of the base layer.

[0021] <Findings underlying this disclosure> First, the problems with the conventional method for manufacturing a silicon carbide semiconductor device will be described. Fig. 9 is a flowchart showing a conventional method for manufacturing a silicon carbide semiconductor device. In the conventional silicon carbide semiconductor device, first, n + An epitaxial film made of silicon carbide is formed on a first main surface (front surface) of a silicon carbide substrate while doping it with n-type impurities, for example, nitrogen (N) atoms (step S101). + A substrate having an epitaxial film formed on a silicon carbide substrate may be purchased.

[0022] Next, an element structure of a silicon carbide semiconductor device is formed on the epitaxial film by a conventional manufacturing method (step S102). For example, in a MOSFET (Metal Oxide Semiconductor Field Effect Transistor), a p-type base region, an n-type gate electrode, and a n-type gate electrode are formed on the epitaxial film that serves as the drift layer. + Type source region, p + Forming the mold contact region, gate insulating film, gate electrode, source electrode, backside electrode, etc. Next, after manufacturing, chip testing (step S103) is performed to select only products that have the specified electrical characteristics. The chip testing can be performed either in wafer state or in chip state.

[0023] In silicon carbide semiconductor devices, Von varies due to variations in the carrier concentration and film thickness of the epitaxial film. For this reason, in existing manufacturing methods, Von is measured after chip testing and a Von rank is assigned according to the Von measurement value (step S104). FIG. 10 is a graph showing the Von rank assignment according to the Von measurement value in a conventional manufacturing method for silicon carbide semiconductor devices. In FIG. 10, the horizontal axis represents Von and the vertical axis represents frequency. As shown in FIG. 10, the Von distribution exhibits a normal distribution shape centered around a target Von value.

[0024] Conventionally, silicon carbide semiconductor devices are ranked into (1) to (4) according to the measured Von value. For example, a device with a Von greater than or equal to Vmin and less than or equal to Vmax is considered within the specifications. (1) indicates a Von measurement greater than or equal to Vmin and less than V1, (4) indicates a Von measurement greater than or equal to V3 and less than or equal to Vmax, and the same applies to (2) and (3). Furthermore, devices with a Von measurement lower than Vmin or higher than Vmax are considered out of specifications and are not shipped.

[0025] After the Von rank is assigned according to the Von measurement value, the product is shipped (step S105). As described above, with the existing manufacturing method, it is not possible to stabilize the variation in Von by controlling the manufacturing process alone, and therefore there is a problem in that after the silicon carbide semiconductor device is manufactured, it is necessary to rank the silicon carbide semiconductor device by Von.

[0026] (Embodiment) Preferred embodiments of a method for manufacturing a silicon carbide semiconductor device according to the present disclosure, which solves the problems of the conventional methods for manufacturing a silicon carbide semiconductor device described above, will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are designated by the same reference numerals, and redundant explanations will be omitted. Furthermore, the terms "same" or "equivalent" should preferably be interpreted as including variations within 10% in consideration of variations in manufacturing.

[0027] Fig. 1 is a flowchart showing a method for manufacturing a silicon carbide semiconductor device according to an embodiment. First, a structure of the silicon carbide semiconductor device according to the embodiment will be described. In the embodiment, a trench MOSFET 70 will be described as an example of the silicon carbide semiconductor device. Fig. 2 is a cross-sectional view showing the structure of the silicon carbide semiconductor device according to the embodiment.

[0028] 2, the trench MOSFET 70 has a MOS gate with a trench gate structure on the front surface (the surface on the side of the p-type base layer 6 described later) of the semiconductor substrate. + A first n-type silicon carbide substrate (a silicon carbide semiconductor substrate of a first conductivity type) 1 is formed on the - The silicon carbide epitaxial layer (first conductivity type epitaxial film) 2 is epitaxially grown. - The silicon carbide epitaxial layer 4 is formed as a 1n - It may be epitaxially grown on the silicon carbide epitaxial layer 2. + a silicon carbide substrate 1, a p-type base layer 6, and a first n-type - a silicon carbide epitaxial layer 2 and a 2n-th silicon carbide epitaxial layer - The silicon carbide epitaxial layer 4 and the silicon carbide epitaxial layer 5 form a silicon carbide semiconductor substrate (a semiconductor substrate made of silicon carbide).

[0029] The MOS gate of the trench gate structure includes a p-type base layer 6, an n-type source region 7, and an n + Type source region 8, p ++ The p-type base layer 6 is composed of a contact region 9, a trench 10, a gate insulating film 11, and a gate electrode 12. The p-type base layer 6 has a thickness of 0.4 μm or more and 0.6 μm or less, and an impurity concentration of 5.0×10 16 / cm 3 Over 2.0 x 10 18 / cm 3 Preferably, the p-type base layer 6 has a conductivity of 1×10 17 / cm 3 5x10 or more 17 / cm 3 The impurity concentrations are as follows:

[0030] Specifically, the trench 10 penetrates the p-type base layer 6 in the depth direction y from the front surface of the semiconductor substrate, and extends to a depth of 2n. - The silicon carbide epitaxial layer 4 (second n - When the silicon carbide epitaxial layer 4 is not provided, the first n - The trenches 10 reach the silicon carbide epitaxial layer 2 (hereinafter referred to as (2)). The depth direction y is the direction from the front surface to the back surface of the semiconductor substrate. The trenches 10 are arranged, for example, in a stripe pattern.

[0031] Inside the trench 10, a gate insulating film 11 is provided along the inner wall of the trench 10, and a gate electrode 12 is provided on the gate insulating film 11 so as to be embedded inside the trench 10. One unit cell of the main semiconductor element is composed of the gate electrode 12 in one trench 10 and adjacent mesa regions (regions between adjacent trenches 10) sandwiching the gate electrode 12. Although only one trench MOS structure is shown in FIG. 2, more trench-structured MOS gate (insulated gate made of metal-oxide film-semiconductor) structures may be arranged in parallel.

[0032] 1st n - An n-type region (hereinafter referred to as a second n-type region) is formed in the surface layer of the source side (the source electrode 16 side described later) of the silicon carbide epitaxial layer 2 so as to contact the p-type base layer 6.- A second silicon carbide epitaxial layer (hereinafter referred to as a 2n-th silicon carbide epitaxial layer) 4 may be provided. - The 2n-th silicon carbide epitaxial layer 4 is a so-called current spreading layer (CSL) that reduces the spreading resistance of carriers. - The silicon carbide epitaxial layer 4 is formed uniformly in a direction parallel to the front surface of the substrate (front surface of the semiconductor substrate) so as to cover the inner wall of the trench 10, for example. - The 2n-th silicon carbide epitaxial layer 4 is provided from the interface with the p-type base layer 6 to a position on the drain side (the drain electrode 15 side described later) of the bottom surface of the trench 10. - The impurity concentration of the silicon carbide epitaxial layer 4 is - The impurity concentration may be higher than that of the silicon carbide epitaxial layer 2 .

[0033] 1st n - The surface layer of the silicon carbide epitaxial layer 2 is formed with a first p + The mold region 3 may be selectively provided. + The mold region 3 is disposed between adjacent trenches 10. - The second p type silicon carbide epitaxial layer 4 contains + The mold region 5 may be selectively provided. + The mold region 5 is the first p + The 2nth - The silicon carbide epitaxial layer 4 is penetrated, and the bottom surface is the first p + The second p-type region 3 is in contact with the p-type base layer 6. + The p-type base layer 6 and the first p-type region 5 are + The mold region 3 is electrically connected to the mold region 3 .

[0034] 2nd n - The silicon carbide epitaxial layer 4 and the second p +A p-type base region 6 is provided on the surface of the n-type region 5. The p-type base region 6 is a p-type epitaxial layer that has not been ion-implanted. The p-type base region 6 may be configured by ion-implanting p-type impurities into an n-type epitaxial layer. An n-type source region 7 is provided on the surface of the p-type base layer 6. An n-type source region 7 is provided inside the n-type source region 7. + type source region 8 and p ++ A contact region 9 is optionally provided. + The n-type source region 8 is the n-type source region 7. + The n-type source region 7 and the n-type silicon carbide substrate 1 are provided on the surface layer opposite to the n-type source region 7. + The n-type source region 8 is in contact with the gate insulating film 11 on the sidewall of the trench 10, and faces the gate electrode 10 via the gate insulating film 11 on the sidewall of the trench 10. Inside the n-type source region 7, there is a p-type insulating film that penetrates the n-type source region 7 and reaches the p-type base region 6. ++ A contact region 9 is provided. ++ The n-type contact region 9 is connected to the n-type source region 7 and the n-type + The source region 8 is in contact with the p ++ The impurity concentration of the p-type contact region 9 is higher than the impurity concentration of the p-type base region 6.

[0035] The n-type source region 7 is + The n-type source region 7 and the n-type source region 8 are provided on the drain side. + The n-type source regions 7 and 8 are in contact with each other. + The width of the source region 8 is approximately the same. + In a portion of the n-type source region 8, + The thickness of the n-type source region 8 is + The thickness of the n-type source region 7 is thinner than the thickness of the n-type source region 7 sandwiched between the n-type source region 8 and the p-type base region 6.

[0036] Interlayer insulating film 13 is provided on the entire front surface of the semiconductor substrate so as to cover gate electrode 12. Contact holes are opened in interlayer insulating film 13, penetrating interlayer insulating film 13 in depth direction y and reaching the front surface of the substrate.

[0037] The source electrode 16 is formed on the semiconductor substrate (n + The source electrode 16 is in ohmic contact with the n-type source region 8 and is electrically insulated from the gate electrode 12 by an interlayer insulating film 13. + type source region 8 and p ++ The source electrode 16 is in ohmic contact with the contact region 9. A barrier metal (not shown) for preventing diffusion of metal atoms from the source electrode 16 toward the gate electrode 12 may be provided between the source electrode 16 and the interlayer insulating film 13. A source electrode pad 14 is provided on the source electrode 16. A drain electrode 15 serving as a drain electrode is provided on the back surface of the semiconductor substrate. A drain electrode pad (not shown) is provided on the drain electrode 15. A barrier metal (not shown) may also be provided between the source electrode 16 and the interlayer insulating film 13 and the source electrode pad 14.

[0038] (Method for manufacturing silicon carbide semiconductor device according to embodiment) Next, a method for manufacturing a silicon carbide semiconductor device according to an embodiment will be described. The method for manufacturing a silicon carbide semiconductor device is the same as an existing manufacturing method, and therefore illustrations thereof will be omitted.

[0039] First, n-type silicon carbide + A silicon carbide substrate 1 is prepared. + On the first main surface (front surface) of the silicon carbide substrate 1, a first n-type impurity, for example, a silicon carbide layer is formed by doping with n-type impurities, such as nitrogen (N) atoms. - In this way, the n-type silicon carbide epitaxial layer 2 is formed. + A first n-th type silicon carbide substrate is formed on a first main surface of the silicon carbide substrate. - An epitaxial film made of a silicon carbide epitaxial layer 2 is formed (step S1: first step).

[0040] Next, the thickness and carrier concentration of the epitaxial film are evaluated (step S2: second process). For example, the carrier concentration of the epitaxial film can be evaluated by CV (Cyclic Voltammetry) measurement or Raman spectroscopy. The thickness of the epitaxial film can also be evaluated by Fourier Transform Infrared Spectroscopy (FTIR). The thickness and carrier concentration of the epitaxial film are evaluated for each semiconductor wafer.

[0041] Next, the Von (on-state voltage) of the silicon carbide semiconductor device (semiconductor element) is estimated (step S3: third process). Here, there is a correlation between the carrier concentration of the epitaxial film and Von, and similarly, there is a correlation between the thickness of the epitaxial film and Von. For this reason, the above correlation data is acquired in advance, and based on this, the Von value for the epitaxial film thickness t and the carrier concentration N of the epitaxial film is calculated. Two examples of the calculation formula are shown below. This makes it possible to rank Von without measuring it. Calculation formula (1) Von(t,N)=At / N+B (A and B are constants) Calculation formula (2) Von(t,N)=Ct+DN+E (C, D, E are constants)

[0042] Figures 3 and 5 are graphs showing the relationship between the thickness of the epitaxial film and Von in a silicon carbide semiconductor device. In Figures 3 and 5, the horizontal axis represents the thickness (epi thickness) t of the epitaxial film, and the vertical axis represents Von. Figure 3 shows the results of the above calculation formula (1), and Figure 5 shows the results of the above calculation formula (2).

[0043] 4 and 6 are graphs showing the relationship between the carrier concentration N of the epitaxial film and Von in a silicon carbide semiconductor device. In Fig. 4 and Fig. 6, the horizontal axis represents the carrier concentration N of the epitaxial film, and the vertical axis represents Von. Fig. 4 shows the results of the above calculation formula (1), and Fig. 6 shows the results of the above calculation formula (2).

[0044] Next, the silicon carbide semiconductor devices are ranked according to their on-state voltage, and silicon carbide semiconductor devices whose on-state voltages are within the standard are selected (step S4: fourth process). Furthermore, silicon carbide semiconductor devices whose estimated on-state voltages are within the standard are ranked according to their on-state voltages (step S5). FIG. 7 is a graph showing the Von rank distribution according to the carrier concentration of the epitaxial film in the method for manufacturing a silicon carbide semiconductor device according to the embodiment. In FIG. 7, the horizontal axis represents the carrier concentration N, and the vertical axis represents the frequency. As shown in FIG. 7, the distribution of the carrier concentration of the epitaxial film exhibits a normal distribution shape centered on the carrier concentration targeted by epitaxial growth.

[0045] If an on-state voltage (Von) between Vmin and Vmax is within the specification, the carrier concentrations corresponding to Vmin and Vmax can be determined from FIGS. 4 and 6. The carrier concentration corresponding to Vmin is the lower limit Nmin, and the carrier concentration corresponding to Vmax is the upper limit Nmax. In this embodiment, for example, the range from the lower limit to the upper limit is divided into four 25% divisions, and the results are ranked into (1) to (4). In this case, N1 = Nmin + (Nmax - Nmin) × 0.25. The same applies to N2 and N3. (1) is a carrier concentration between Nmin and N1, (4) is a carrier concentration between N3 and Nmax, and the same applies to (2) and (3). An epitaxial film with a carrier concentration between Nmin and Nmax is classified as within the specification (Step S4: Yes). An epitaxial film with a carrier concentration lower than Nmin or higher than Nmax is classified as out of the specification (Step S4: No).

[0046] 8 is a graph showing the Von rank distribution according to the thickness of the epitaxial film in the manufacturing method of a silicon carbide semiconductor device according to the embodiment. In Fig. 8, the horizontal axis represents the thickness (epi-thickness) t of the epitaxial film, and the vertical axis represents the frequency. As shown in Fig. 8, the distribution of the carrier concentration of the epitaxial film exhibits a normal distribution shape centered on the film thickness targeted by the epitaxial growth.

[0047] If an on-state voltage (Von) between Vmin and Vmax is within the standard, the film thicknesses corresponding to Vmin and Vmax can be determined from FIGS. 3 and 5. The film thickness corresponding to Vmin is the lower limit tmin, and the film thickness corresponding to Vmax is the upper limit tmax. In this embodiment, for example, the range from the lower limit to the upper limit is divided into four 25% intervals, and the results are ranked into (1)' to (4)'. In this case, t1 = tmin + (tmax - tmin) × 0.25. The same applies to t2 and t3. For example, (1)' is a film thickness between tmin and t1, (4)' is a film thickness between t3 and tmax, and the same applies to (2)' and (3)'. Epitaxial film thicknesses between tmin and tmax are classified as within the standard (Step S4: Yes). Epitaxial film thicknesses lower than tmin and higher than tmax are classified as out of the standard (Step S4: No).

[0048] 7 and 8, the on-state voltage is estimated from the carrier concentration and the thickness of the epitaxial film and is divided into four ranks. However, the present invention is not limited to this and the on-state voltage may be divided into multiple ranks. Furthermore, the process of dividing the on-state voltage into ranks is not essential and the process of dividing the on-state voltage into ranks is not necessary.

[0049] Next, a step of bringing the on-voltage within the standard may be carried out on silicon carbide semiconductor devices that have been screened out as having an out-of-standard on-voltage (step S9: sixth step). The semiconductor wafers on which this step is carried out are the circled areas in FIGS. 7 and 8. This allows silicon carbide semiconductor devices that would be out-of-standard and therefore unshippable using existing manufacturing methods to be brought within the standard and thus be able to be shipped. At this time, a step of bringing the on-voltage within the standard may be carried out on (1) and (4) in FIG. 7 and (1)' and (4)' in FIG. 8, which are close to the upper and lower limits of the standard.

[0050] To bring the on-state voltage within the specification, for example, if the carrier concentration of the epitaxial film is low, impurities of the same conductivity type are implanted to lower the on-state voltage, thereby bringing the on-state voltage within the specification. If the carrier concentration of the epitaxial film is high, impurities of a different conductivity type are implanted to increase the on-state voltage, thereby bringing the on-state voltage within the specification. Furthermore, if the epitaxial film is thin, lifetime killers such as electron beams, H (hydrogen) ions, or He (helium) ions can be implanted into the epitaxial film to increase the on-state voltage and bring the on-state voltage within the specification. Furthermore, if the epitaxial film is thin, the thickness of the epitaxial film can be increased by epitaxial growth again, thereby increasing the on-state voltage and bringing the on-state voltage within the specification.

[0051] Furthermore, the process of bringing the on-state voltage within the standard range can also be achieved by adjusting parameters when manufacturing the following device structure. For example, the width of one or more of the JFET sections can be appropriately changed to adjust the JFET resistance and bring the on-state voltage within the standard range. The JFET section can be formed, for example, by forming a current spreading layer (2nth - The first p-type silicon carbide epitaxial layer 4) and the trench + The p-type region 3 is located between the trench bottom and the p-type region 4. + When a type region is provided, the p + p between the type region and the trench + The impurity concentration of the current spreading layer can be appropriately changed to keep the on-state voltage within the standard range. Furthermore, the impurity concentration of the p-type base layer 6 in which the channel is formed can be appropriately changed to keep the on-state voltage within the standard range.

[0052] Next, the element structure of the silicon carbide semiconductor device is formed (step S6: fifth step). The element structure of the silicon carbide semiconductor device is formed as follows. First, the 1nth -An ion implantation mask (not shown) having predetermined openings is formed on the surface of the silicon carbide epitaxial layer 2 by photolithography, for example, an oxide film. Then, using this oxide film as a mask, p-type impurities, for example, aluminum (Al) atoms, are implanted by ion implantation to form a first n-type impurity. - The first p-type epitaxial layer 2 has a depth of 0.3 μm or more and 1.0 μm or less in the surface layer. + For example, mold area 3 is 2.0 × 10 17 / cm 3 Over 2.0 x 10 18 / cm 3 The impurity concentration is as follows:

[0053] Next, the 1nth - A second n-type silicon carbide epitaxial layer having a thickness of 0.3 μm to 1.0 μm and doped with n-type impurities such as nitrogen is formed on the surface of the silicon carbide epitaxial layer 2. - The silicon carbide epitaxial layer 4 is formed by, for example, 1.0×10 16 / cm 3 Over 5.0 x 10 17 / cm 3 The impurity concentration is as follows:

[0054] Next, the 2nth - An ion implantation mask (not shown) having predetermined openings is formed on the surface of the silicon carbide epitaxial layer 4 by photolithography, for example, an oxide film. Then, using this oxide film as a mask, p-type impurities, for example, aluminum atoms, are implanted by ion implantation to form a 2n-type silicon carbide epitaxial layer. - The surface layer of the silicon carbide epitaxial layer 4 is formed with a 2n-th order. - The second p-type silicon carbide epitaxial layer 4 is formed at a depth of + The mold area 5 is, for example, 2.0 × 10 17 / cm 3 Over 2.0 x 10 18 / cm 3 The impurity concentration is as follows:

[0055] Next, the 2nth - On the surface of the silicon carbide epitaxial layer 4, a p-type base layer 6 is formed, for example, at a thickness of 5.0×1016 / cm 3 Over 2.0 x 10 18 / cm 3 The p-type base layer 6 is formed by epitaxial growth at the following impurity concentration. After the p-type base layer 6 is formed by epitaxial growth, p-type impurities such as aluminum may be further ion-implanted into the channel region of the p-type base layer 6. The p-type base layer 6 is also formed by epitaxial growth at the following impurity concentration. - Alternatively, the p-type silicon carbide epitaxial layer 4 may be epitaxially grown and then ion-implanted with p-type impurities such as aluminum.

[0056] Next, an n-type source region 7 with a thickness of about 0.5 μm is formed on the surface of the p-type base layer 6 by, for example, 1.0×10 17 / cm 3 After the n-type source region 7 is formed by epitaxial growth, n-type impurities such as phosphorus (P) or nitrogen are ion-implanted into the surface of the n-type source region 7, thereby forming n-type impurities in the surface layer of the n-type source region 7. + The source region 8 is, for example, 3.0 × 10 19 / cm 3 At this time, n + The thickness of the n-type source region 8 is + The thickness of the n-type source region 7 is thinner than the thickness of the portion sandwiched between the n-type source region 8 and the p-type base region 6. This prevents damage caused by ion implantation from remaining in the p-type base layer 6. + The n-type source region 8 can also be selectively formed by forming an ion implantation mask having a predetermined opening on the n-type source region 7 using, for example, an oxide film as a mask by ion implantation.

[0057] Next, an ion implantation mask (not shown) having predetermined openings is formed of, for example, an oxide film. Then, using this oxide film as a mask, p-type impurities, for example, aluminum atoms, are implanted by ion implantation to form n-type source regions 7 and n-type impurity regions 8. + A part of the source region 8 is p ++ The contact area 9 is, for example, 1.0×1020 / cm 3 The impurity concentration is formed as follows: p ++ The impurity concentration of the p-type contact region 9 is higher than the impurity concentration of the p-type base region 6, and is 1.0×10 19 / cm 3 Over 5.0 x 10 20 / cm 3 It is preferable to form it so that: ++ The contact region 9 is formed so that the bottom surface thereof reaches the p-type base layer 6 .

[0058] Next, n + A trench forming mask having a predetermined opening is formed by photolithography on the surface of the source region 8, using, for example, an oxide film. Next, an n + The second n-type source region 8, the n-type source region 7, and the p-type base layer 6 are penetrated. - Trenches 10 are formed so as to reach the silicon carbide epitaxial layer 4. Next, the trench forming mask is removed.

[0059] Next, heat treatment (annealing) is carried out in an inert gas atmosphere at about 1750°C to form the first p + Type area 3, 2nd p + type area 5, n + type source region 8 and p ++ An activation process is performed on the mold contact region 9. As described above, the ion implantation regions may be activated all at once by a single heat treatment, or activation may be performed by performing a heat treatment after each ion implantation.

[0060] Next, n + type source region 8 and p ++ A gate insulating film 11 is formed along the surface of the contact region 9 and the bottom and sidewalls of the trench 10. This gate insulating film 11 may be formed by thermal oxidation at a temperature of about 1300°C in an oxygen atmosphere. Alternatively, this gate insulating film 11 may be formed by a deposition method using a chemical reaction such as high temperature oxidation (HTO).

[0061] Next, a polycrystalline silicon film doped with, for example, phosphorus atoms is provided on the gate insulating film 11. This polycrystalline silicon film may be formed so as to fill the trench 10. This polycrystalline silicon film is patterned by photolithography and left inside the trench 10 to form the gate electrode 12. A p-type polycrystalline silicon film may be used for the gate electrode 12.

[0062] Next, for example, phosphorus glass is deposited to a thickness of about 1 μm so as to cover the gate insulating film 11 and the gate electrode 12, thereby forming the interlayer insulating film 13. The interlayer insulating film 13 and the gate insulating film 11 are patterned by photolithography. + type source region 8 and p ++ A contact hole is formed to expose the mold contact region 9 .

[0063] Next, a conductive film that will become the source electrode 16 is formed in the contact hole provided in the interlayer insulating film 13 and on the interlayer insulating film 13. The conductive film is, for example, a nickel (Ni) film. After that, a heat treatment is performed at a temperature of, for example, about 700°C to selectively react the conductive film with silicon carbide, and then the unreacted portion of the conductive film is selectively removed to leave the source electrode 16 only in the contact hole, and n + type source region 8 and p ++ The mold contact region 9 is brought into contact with the source electrode 16 .

[0064] Next, a metal layer that will become the source electrode pad 14 is formed on the source electrode 16 on the front surface of the silicon carbide semiconductor substrate and on the interlayer insulating film 13, for example, by sputtering. At this time, a barrier metal (not shown) made of titanium or titanium nitride may be formed first. The thickness of the metal layer on the interlayer insulating film 13 may be, for example, 5.5 μm. The metal layer may be made of, for example, aluminum containing 1% silicon (Al-Si). Next, the metal film is selectively removed to form the source electrode pad 14.

[0065] Next, n +On the second main surface (rear surface) of the silicon carbide substrate 1, a conductive film, for example, a molybdenum film and a nickel film, which will become the drain electrode 15, are successively formed by, for example, sputtering. Then, a heat treatment such as laser annealing is performed to form the n + The drain electrode 15 is formed by reacting the silicon carbide substrate 1 with a conductive film to form an ohmic junction.

[0066] Next, a film of titanium, nickel, and gold is formed in this order as a drain electrode pad (not shown) on the surface of the drain electrode 15. In this way, the trench MOSFET 70 shown in FIG.

[0067] Next, after manufacturing, a chip test (step S7) is performed to select only products that have the specified electrical characteristics. The chip test may be performed in either a wafer state or a chip state. After Von ranking according to the Von value estimated in step S3, the products are shipped (step S8). For example, silicon carbide semiconductor devices whose Von value falls within the range (1) in step S3 are shipped with a Von of not less than Vmin and not more than V1. The same applies to other ranges. In the embodiment, since Von ranking has already been performed, there is no need to perform Von inspection for Von ranking after manufacturing. This reduces the number of steps required for Von inspection.

[0068] As described above, according to the embodiment, the Von value is estimated from the film thickness and carrier concentration of the epitaxial film. This makes it possible to stabilize the variation in Von by controlling the manufacturing process, and eliminates the need to rank silicon carbide semiconductor devices by Von after manufacturing the silicon carbide semiconductor devices.

[0069] In the above, the present disclosure has been described using an example in which a MOS gate structure is configured on the first main surface of a silicon carbide substrate, but the present disclosure is not limited to this and various changes are possible for the type of semiconductor (e.g., silicon (Si), gallium nitride (GaN), etc.), the surface orientation of the substrate main surface, etc. Furthermore, while the embodiments of the present disclosure have been described using a trench MOSFET as an example, the present disclosure is not limited to this and can be applied to semiconductor devices with various configurations, such as MOS type semiconductor devices such as trench IGBTs. Furthermore, in each embodiment of the present disclosure, the first conductivity type is n-type and the second conductivity type is p-type, but the present disclosure is equally valid even if the first conductivity type is p-type and the second conductivity type is n-type. [Industrial Applicability]

[0070] INDUSTRIAL APPLICABILITY As described above, a method for manufacturing a silicon carbide semiconductor device according to the present disclosure is useful for high-voltage semiconductor devices used in power conversion devices and power supply devices for various industrial machines and the like. [Explanation of symbols]

[0071] 1n + Silicon carbide substrate 2 1stn - Silicon carbide epitaxial layer 3 1st p. + type area 4 2nd n - Silicon carbide epitaxial layer 5 2nd p. + type area 6 p-type base layer 7 n-type source region 8n + Type Source Area 9 p ++ Mold contact area 10 Trench 11 Gate insulating film 12 gate electrode 13 Interlayer insulating film 14 Source electrode pad 15 Drain electrode 16 Source electrode 70 Trench MOSFET

Claims

1. a first step of forming an epitaxial film of a first conductivity type on a front surface of a silicon carbide semiconductor substrate of the first conductivity type, the epitaxial film having an impurity concentration lower than that of the silicon carbide semiconductor substrate; a second step of evaluating the thickness or carrier concentration of the epitaxial film; a third step of estimating an on-state voltage from the film thickness or the carrier concentration; a fourth step of ranking and selecting the silicon carbide semiconductor substrates based on the estimated on-state voltage; a fifth step of forming a device structure on the selected silicon carbide semiconductor substrate; 2. A method for manufacturing a silicon carbide semiconductor device, comprising:

2. In the second step, both the film thickness and the carrier concentration are evaluated, 2 . The method for manufacturing a silicon carbide semiconductor device according to claim 1 , wherein in the third step, an on-state voltage is estimated from the film thickness and the carrier concentration.

3. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein in the fourth step, the selected silicon carbide semiconductor substrates are ranked into a plurality of ranks according to the film thickness or the carrier concentration.

4. 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein after the fifth step, an inspection of an on-voltage of the silicon carbide semiconductor device is not performed.

5. After the fourth step and before the fifth step, 3. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further comprising a sixth step of bringing the on-voltage of the silicon carbide semiconductor substrates that have not been selected into a standard range.

6. 6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the sixth step is a step of implanting an impurity into the epitaxial film.

7. 6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the sixth step is a step of changing the width of at least one of the portions of the JFET portion in the fifth step.

8. the fifth step includes a step of forming a current diffusion layer of a first conductivity type on the epitaxial film, 6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the sixth step is a step of changing an impurity concentration of the current diffusion layer.

9. the fifth step includes a step of forming a base layer of a second conductivity type on the epitaxial film, 6. The method for manufacturing a silicon carbide semiconductor device according to claim 5, wherein the sixth step is a step of changing an impurity concentration of the base layer.

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