Decision circuit and semiconductor device

Abstract

To provide a decision circuit in which processing performed by a software of a microcomputer is divided into processing for branch decision and processing after decision and which includes a hardware performing at least a part of the processing for branch decision.SOLUTION: A decision circuit 13 includes: an input circuit 17 having an input receiving an analog signal SANA and an output; a processing circuit 19 including an analog-to-digital conversion circuit 23 generating a converted value SDIG from an input signal as the output of the input circuit 17, an arithmetic circuit 25 performing digital calculations on the converted value SDIG to generate a calculation result, and an output configured to provide at least one of the calculation result and the converted value to a central processing unit; and a comparison circuit 21 comparing the calculation result with a threshold to generate a comparison result and generating an interrupt signal SINT in response to the comparison result showing that interrupt conditions are satisfied. The analog-to-digital conversion circuit 23 includes at least one analog-to-digital converter.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a determination circuit and a semiconductor device. [Background technology]

[0002] Patent Document 1 discloses a method for avoiding erroneous determination due to the influence of noise in an input analog signal. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-148630 Summary of the Invention [Problem to be solved by the invention]

[0004] In semiconductor devices incorporating a microcomputer, the microcomputer not only controls the internal circuits mounted on the semiconductor device, but also controls external devices connected to the semiconductor device. Specifically, the semiconductor device is required to perform several branching processes in response to changes in signals from the external devices. Therefore, the processing by the microcomputer software includes branching judgment processing and post-judgment processing. In particular, the branching judgment processing is repeatedly performed regardless of whether post-judgment processing is performed.

[0005] The microcomputer that performs the post-determination processing can use the arithmetic unit of the microcomputer, and therefore it is not a good idea to newly provide the post-determination processing as hardware in the semiconductor device.

[0006] On the other hand, if the hardware executes the repeated execution of the branch decision process, the burden of software processing on the microcomputer is reduced.

[0007] What is required is the division of processing in microcomputer software.

[0008] Furthermore, signals from external devices are often time-series analog signals. Therefore, these analog signals are converted into digital signals by an A / D converter built into the semiconductor device and stored in a register until they are processed by the microcomputer software. This waiting time depends on the level of busyness in the software processing. The microcomputer can utilize the potentially existing waiting time to execute branch judgment processing using hardware. This hardware notifies the microcomputer that the branch judgment processing result requires post-judgment processing.

[0009] The present disclosure aims to provide a judgment circuit and a semiconductor device that divide the processing executed by a microcomputer into branch judgment processing and post-judgment processing, and that are equipped with hardware that executes at least a part of the branch judgment processing. [Means for solving the problem]

[0010] A determination circuit according to a first aspect of the present disclosure comprises: an input circuit having an input and an output configured to receive one or more analog signals; an analog-to-digital conversion circuit configured to receive one or more input signals from the output of the input circuit and generate respective conversion values ​​from the received input signals; a processing circuit including an arithmetic circuit including an operator configured to perform a digital operation on the conversion values ​​to generate an operation result; and an output configured to provide at least one of the operation result and the conversion value to a central processing unit; and a comparison circuit configured to compare the operation result with a threshold to generate a comparison result, and to generate an interrupt signal in response to the comparison result indicating that an interrupt condition is satisfied, wherein the analog-to-digital conversion circuit includes at least one analog-to-digital converter.

[0011] A semiconductor device according to a second aspect of the present disclosure includes the determination circuit according to the first aspect, and a processor configured to receive the interrupt signal from the determination circuit. [Effects of the Invention]

[0012] According to the above aspect, it is possible to provide a judgment circuit and a semiconductor device that are provided with hardware that executes at least a part of the branch judgment process by dividing the processing executed by the microcomputer into branch judgment processing and post-judgment processing. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram schematically showing a semiconductor device according to this embodiment. [Figure 2] FIG. 2 is a diagram schematically illustrating a semiconductor device including an averaging circuit as an exemplary arithmetic circuit according to this embodiment. [Figure 3] FIG. 3 is a diagram schematically illustrating a semiconductor device including a subtraction circuit as an exemplary arithmetic circuit according to this embodiment. [Figure 4] FIG. 4 is a diagram showing an exemplary averaging circuit of the arithmetic circuit according to this embodiment. [Figure 5] FIG. 5 is a diagram showing the operation of the analog-to-digital conversion circuit and the arithmetic circuit in the decision circuit according to this embodiment. [Figure 6] FIG. 6 is a diagram showing the operation of the analog-to-digital conversion circuit and the arithmetic circuit in the decision circuit according to this embodiment. [Figure 7] FIG. 7 is a diagram showing the operation of the analog-to-digital conversion circuit and the arithmetic circuit in the decision circuit according to this embodiment. [Figure 8] FIG. 8 is a flow chart including exemplary steps in a method for generating an interrupt signal according to an embodiment. [Figure 9] FIG. 9 is a flow chart including exemplary steps in a method for generating an interrupt signal according to the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, embodiments of the present invention will be described with reference to the drawings. Identical parts are designated by the same reference numerals and redundant description will be omitted.

[0015] Fig. 1 is a diagram schematically illustrating a semiconductor device according to an embodiment of the present invention. Fig. 2 is a diagram schematically illustrating a semiconductor device including an averaging circuit as an exemplary arithmetic circuit according to an embodiment of the present invention. Fig. 3 is a diagram schematically illustrating a semiconductor device including a subtraction circuit as an exemplary arithmetic circuit according to an embodiment of the present invention.

[0016] The semiconductor device 11 includes a decision circuit 13 and a processing device 15 such as a central processing unit (CPU). The decision circuit 13 and the processing device 15 are integrated on a single semiconductor chip. The decision circuit 13 includes an input circuit 17, a processing circuit 19, and a comparison circuit 21. The processing circuit 19 includes an analog-to-digital conversion circuit 23 and an arithmetic circuit 25. In the decision circuit 13 of FIG. 1, a control circuit 31 controls the circuits within the decision circuit 13.

[0017] The input circuit 17 has one or more inputs 17b and an output 17c. The input circuit 17 is configured to receive one or more analog signals SANA at one or more inputs 17b.

[0018] The analog-to-digital conversion circuit 23 is configured to receive one or more input signals SIN from the output 17c of the input circuit 17 and to generate respective conversion values ​​SDIG from the received input signals SIN. The analog-to-digital conversion circuit 23 may include at least one analog-to-digital converter.

[0019] The calculation circuit 25 includes one or more calculators (26, 26b, 26c), each configured to perform a digital calculation on the converted value to generate a calculation result. Exemplary digital calculations may include, but are not limited to, generating an average value and subtraction.

[0020] Processing circuit 19 has an output 19b and one or more inputs 19c. Processing circuit 19 is configured to provide at least one of the calculation result of calculation circuit 25 and the conversion value SDIG at output 19b to processing device 15, specifically to output circuit 29 of processing circuit 19. Processing circuit 19 provides signal SDATA from output circuit 29 at output 19b.

[0021] The comparator circuit 21 compares the calculation result with a threshold value to generate a comparison result, and generates an interrupt signal SINT in response to the comparison result indicating that the interrupt condition is satisfied.

[0022] Specifically, the calculation result of the calculation circuit 25, for example, the generated average value and subtraction, is compared with a threshold value. If the comparison result does not satisfy the set interrupt condition, the interrupt signal SINT is not generated. On the other hand, if the comparison result satisfies the set interrupt condition, the interrupt signal SINT is generated.

[0023] By setting interrupt conditions for the calculation results accordingly, the amount of software processing can be reduced. The branch decision in software processing is replaced by the hardware arithmetic circuit 25 and the comparator circuit 21. When the analog-to-digital converter circuit 23 generates a series of converted values ​​required for digital calculation, the arithmetic circuit 25 immediately generates the calculation result of the digital calculation.

[0024] After the decision circuit 13 receives the analog signals required for the decision and performs AD conversion, the decision of the decision circuit 13 becomes executable regardless of whether the remaining analog signals have been received. When an interrupt signal SINT is generated as a result of the decision of the decision circuit 13, the processing unit 15 can start a specific process according to the priority of the interrupt. A series of converted values ​​and calculation results from the analog-to-digital conversion circuit 23 are stored in the processing circuit 19. These stored values ​​are provided to the processing unit 15. The storage values ​​can be provided to the processing unit 15 when the processing unit 15 starts a specific process. The processing unit 15 may be able to access a storage area in the processing circuit 19.

[0025] Specifically, when the calculation result is provided by the averaging circuit 26b, the comparison circuit 21 can be configured to generate the interrupt signal SINT when the calculation result is greater than a threshold value. Alternatively, the comparison circuit 21 can be configured to generate the interrupt signal SINT when the calculation result is less than a threshold value. The calculation specification register 26m receives a fifth selection signal SSEL5 to specify the conversion value SDIG to be averaged. The fifth selection signal SSEL5 can be provided to the analog-to-digital conversion circuit 23.

[0026] Furthermore, when the calculation result is provided by the subtraction circuit 26c, the comparison circuit 21 can be configured to generate an interrupt signal SINT when the calculation result is greater than a threshold value. Alternatively, the comparison circuit 21 can be configured to generate an interrupt signal SINT when the calculation result is less than a threshold value. The calculation specification register 26n receives a sixth selection signal SSEL6 to specify the conversion value SDIG to be subtracted. The sixth selection signal SSEL6 can be provided to the processing circuit 19.

[0027] The exemplary comparison circuit 21 includes a comparator 22b and a threshold register 22c. The comparison circuit 21 receives the calculated value from the averaging circuit 26b and / or the calculated value from the subtraction circuit 26c. In the exemplary comparison circuit 21, one or both of these values ​​are selectively or sequentially provided to the comparator 22b by a selector 22d of the comparison circuit 21. The comparator 22b compares the received calculated value with the threshold value of the threshold register 22c to generate a comparison result. The selector 22d operates to select the calculated value from the averaging circuit 26b and the calculated value from the subtraction circuit 26c in response to a selection signal SOPE.

[0028] The interrupt signal SINT may not be generated when the calculated value from the averaging circuit 26b does not satisfy the threshold condition, when the calculated value from the subtraction circuit 26c does not satisfy the threshold condition, or when both of these do not satisfy the threshold condition.

[0029] The processing device 15 may include a processor 16b and a memory 16c. The processor 16b is configured to receive an interrupt signal SINT from the determination circuit 13. The memory 16c is communicatively connected to the processor 16b. The memory 16c is configured to store specific program code. The processor 16b is configured to execute the specific program code in response to the interrupt signal SINT.

[0030] Specifically, the memory 16c is configured to store a first program code and a specific program code. Upon receiving the interrupt signal SINT from the determination circuit 13, the processor 16b executes the first program code.

[0031] The processor 16b is configured to save register values ​​in the first program code being executed in the processor 16b in response to receiving the interrupt signal SINT from the decision circuit 13. The specific program code is loaded in response to the completion of the saving. The specific program code is configured to cause the processor 16b to process the signal from the decision circuit 13. The specific program code is configured to carry out the remaining processing that was interrupted.

[0032] In the decision circuit 13, the input 17b of the input circuit 17 is configured to further receive a first selection signal SSEL1 that specifies the analog signal SANA to be accepted.

[0033] The input circuit 17 includes a selector circuit 28 configured to provide a signal of interest selected from the analog signal SANA in response to a first selection signal SSEL1 as an input signal SIN to the output 17c. The input circuit 17 captures the analog signal SANA at one or more times and provides the signal captured at that time as the input signal SIN.

[0034] The analog-to-digital conversion circuit 23 is configured to generate a conversion value SDIG of the input signal SIN received at the input 23c and to provide the conversion value SDIG at the output 23b. To this end, the input circuit 17 may include respective sample-and-hold circuits 28b connected to the inputs of the analog-to-digital converters (24a, 24b, 24c, 24f, 24g) of the analog-to-digital conversion circuit 23.

[0035] The exemplary arithmetic circuit 25 may include at least one of an averaging circuit 26b and a subtraction circuit 26c as a computing unit, but the arithmetic circuit 25 is not limited thereto.

[0036] The processing circuit 19 may include a data register circuit 27. The data register circuit 27 is connected between the analog-to-digital conversion circuit 23 and the output circuit 29. An exemplary averaging circuit 26b is connected between the analog-to-digital conversion circuit 23 and the data register circuit 27. An exemplary subtraction circuit 26c is connected between the data register circuit 27 and the output circuit 29 (or processing unit 15).

[0037] 1 and 2, the arithmetic circuit 25 is provided with an averaging circuit 26b as the calculator 26. In the decision circuit 13 of Fig. 2, a control circuit 31 controls the circuits in the decision circuit 13. The data register circuit 27 includes, for example, five registers 28d.

[0038] The averaging circuit 26b performs digital arithmetic on a predetermined number of conversion values ​​(at past capture times) including the most recent conversion value in the calculator 26. The exemplary averaging circuit 26b averages the most recent conversion value among the conversion values ​​SDIG and conversion values ​​at a predetermined number of past times.

[0039] In the exemplary calculation circuit 25, the averaging circuit 26b has one or more first inputs 25b, a first output 25c, and multiple second outputs 25d. The first input 25b is configured to receive the converted value SDIG from the analog-to-digital conversion circuit 23. The first output 25c is configured to provide an averaged signal SAVE indicative of the calculation result. The second output 25d is configured to provide the converted value SDIG from the analog-to-digital conversion circuit 23 without applying digital calculation.

[0040] An exemplary operation performed by the averaging circuit 26b is to generate an arithmetic mean value of a predetermined number of past and current converted values ​​among the converted values, a total of n converted values.

[0041] 4 is a diagram showing an exemplary averaging circuit of the arithmetic circuit according to this embodiment. Referring to part (a) of FIG. 4, five conversion values ​​SDIG are stored in five registers (RG0 to RG4) from the present time to the past (horizontal axis). The conversion period TAD indicates the period given for one analog-to-digital conversion.

[0042] As shown in part (a) of Figure 4, the signal LN from the external device contains noise and is assumed to vary, on average, as shown by the straight line AVRG. Five AD conversions generate five conversion values ​​SDIG (D0, D1, D2, D3, D4). These are stored in five registers (RG0, RG1, RG2, RG3, RG4) in order.

[0043] The exemplary averaging circuit 26b generates an arithmetic average of a predetermined number of past and most recent conversion values ​​SDIG (e.g., n conversion values ​​SDIG). As shown in part (b) of FIG. 4, the averaging circuit 26b may include a shift register 26h, an adder 26j, and a divider 26k. The shift register 26h stores the conversion values ​​SDIG for the averaging operation. The adders 26j are connected to the outputs of the shift registers 26h. The divider 26k is connected to the output of the adder 26j.

[0044] The connection between the averaging circuit 26b and the data register circuit 27 will be described with reference to FIGS.

[0045] The arithmetic circuit 25 sequentially receives a predetermined number of converted values ​​SDIG from the output 23b of the analog-to-digital conversion circuit 23 at the input 25b of the averaging circuit 26b, and generates an average value of the received predetermined number of converted values ​​SDIG. After receiving the predetermined number of converted values ​​SDIG, the generation of the average value can be performed each time a new converted value SDIG is received, or can be performed each time a new predetermined number of converted values ​​SDIG is received.

[0046] The data register circuit 27 has a plurality of inputs 27b, an output 27c, and an input 27f. Specifically, the data register circuit 27 receives a signal from the output 25d of the averaging circuit 26b at the input 27b, and can also receive the calculation result of the averaging circuit 26b. The data register circuit 27 can sequentially receive the converted value SDIG, which has not been subjected to digital calculation, from the output 23b of the analog-to-digital conversion circuit 23, at the input 27f, without passing through the averaging circuit 26b.

[0047] The input 27d receives the second selection signal SSEL2. The data register circuit 27 is configured to store the converted values ​​SDIG from the output 25f of the averaging circuit 26b in association with the input order in response to the second selection signal SSEL2.

[0048] The data register circuit 27 includes a first selector 28f and a plurality of registers 28d, and the first selector 28f stores the conversion value SDIG in the register 28d in response to a second selection signal SSEL2.

[0049] The data register circuit 27 is configured to provide at least one of the stored conversion values ​​SDIG to an output 27c in response to a fourth select signal SSEL4.

[0050] 1 and 3, the arithmetic circuit 25 is provided with a subtraction circuit 26c as the calculator 26. In the decision circuit 13 of Fig. 3, a control circuit 31 controls the circuits in the decision circuit 13. The data register circuit 27 includes five exemplary registers.

[0051] The subtraction circuit 26c is configured to provide a subtraction signal SSUB indicating the result of the operation in the operator 26. The subtraction circuit 26c has an input 25h, a first output 25f, and a plurality of second outputs 25g. The first output 25f provides the subtraction signal SSUB indicating the result of the operation. The second output 25g can provide a converted value SDIG from the analog-to-digital conversion circuit 23 to which no digital operation has been applied.

[0052] Exemplary operations in the subtraction circuit 26c include generating difference values ​​between different (same-time) signals from different external devices, generating difference values ​​between different (different-time) signals from different external devices, or generating difference values ​​between signals from the same external device at different times. Exemplary operations in the subtraction circuit 26c also include generating a difference value between a converted value at the current time and a converted value at a time point in the past from the current time. The past time point can be the time point immediately preceding the current time point, and the sign of the difference value indicates whether the trend of change at the current time point is either increasing or decreasing, and the absolute value of the difference value indicates the rate of change.

[0053] The connection between the subtraction circuit 26c and the data register circuit 27 will be described with reference to FIGS.

[0054] The data register circuit 27 has one or more inputs 27f, 27g, and an output 27h. Specifically, the data register circuit 27 receives the converted value SDIG from the analog-to-digital conversion circuit 23 at the input 27f. The data register circuit 27 has an output 27h connected to an input 25h of the arithmetic circuit 25. The subtraction circuit 26c receives a sixth select signal SSEL6 at an input 25j.

[0055] The arithmetic circuit 25 receives a predetermined number of converted values ​​SDIG from the output 23b of the analog-to-digital conversion circuit 23 at an input 25h of a subtraction circuit 26c, and generates a difference value of the received converted values ​​SDIG. The exemplary subtraction circuit 26c receives two converted values ​​SDIG at an input 25h via a data register circuit 27.

[0056] The data register circuit 27 includes a second selector 28g in addition to a first selector 28f and a plurality of registers 28d, and the second selector 28g stores the conversion value SDIG in the register 28d in response to a third select signal SSEL3 received at an input 27g.

[0057] The data register circuit 27 is configured to provide at least one of the stored conversion values ​​SDIG to an output 27c in response to a fourth select signal SSEL4.

[0058] The subtraction circuit 26c calculates the difference between two converted values ​​SDIG provided consecutively or in parallel from the data register circuit 27. These converted values ​​SDIG are stored in a storage 26f of the subtraction circuit 26c and calculated in a subtractor 26g connected to the storage 26f. The calculation result is provided to an output 25f and provided to the comparison circuit 21 via the output 25f. The subtraction circuit 26c provides converted values ​​SDIG to the output 25g. These converted values ​​SDIG can be provided to the output circuit 29. The calculation specification register 26n specifies two analog signals to be subtracted based on a sixth selection signal SSEL6. The sixth selection signal SSEL6 can be provided to the data register circuit 27.

[0059] The processing circuitry 19 may include a control circuitry 31. The control circuitry 31 may determine values ​​of the first select signal SSEL1, the second select signal SSEL2, the third select signal SSEL3, the fourth select signal SSEL4, and the fifth select signal SSEL5 in response to signals from the processor 16b.

[0060] 2 and 3, the input circuit 17 of the semiconductor device 11 receives signals from five external devices (AIN0, AIN1, AIN2, AIN3, and AIN4). The external devices (AIN0, AIN1, AIN2, AIN3, and AIN4) may include, for example, sensor elements and sensor circuits.

[0061] 5, 6, and 7 are diagrams showing the operation of the analog-to-digital conversion circuit and the arithmetic circuit in the decision circuit according to this embodiment.

[0062] Referring to FIG. 5, the input circuit 17 receives signals from two external devices (AIN0, AIN1).

[0063] The input circuit 17 alternately receives analog signals (A00, A10, A01, A11, A02, A12, A30, A13, A04, A14, A05) from two external devices (AIN0, AIN1). These analog signals are provided to the AD converter 24b of the analog-to-digital conversion circuit 23 in the order received by the input circuit 17, and the AD converter 24b generates conversion values ​​SDIG (A00, A10, A01, A11, A02, A12, A03, A13, A04, A14, A05) in sequence within a conversion period TAD. For example, the analog signals (A00, A10) are converted into conversion values ​​SDIG (A00, A10) in sequence by the single AD converter 24b of the analog-to-digital conversion circuit 23 in the order received by the input circuit 17 and stored in the respective register circuits. The values ​​stored in these register circuits are provided to the subtraction circuit 26c, which generates a difference value (A00-A10).

[0064] The two values ​​that generate the difference value are not taken at exactly the same time, but have a difference of a conversion period TAD (conversion cycle).

[0065] Referring to FIG. 6, the input circuit 17 receives signals from two external devices (AIN0, AIN1). The input circuit 17 receives analog signals (A00, A10) from the two external devices (AIN0, AIN1) at the same time. Specifically, the input circuit 17 receives the analog signals from the external devices (AIN0, AIN1) through respective sample-and-hold circuits 28b. The sample-and-hold circuits 28b are configured to simultaneously sample and hold the two analog signals. The two held analog signals (A00, A10) are sequentially provided by a selector 17d to a single AD converter 24c of the analog-to-digital conversion circuit 23. The AD converter 24c sequentially generates conversion values ​​SDIG (A00, A10), which are stored in a register circuit 24d including respective registers.

[0066] The two values ​​that generate the difference value are sampled at the same time, while the AD conversion is performed serially. For this purpose, a selector 17d is connected to the input side of an AD converter 24c, and a register circuit 24d is connected to the output side of the AD converter 24c. The conversion time is the conversion period TAD (conversion cycle).

[0067] Referring to FIG. 7, the input circuit 17 receives signals from two external devices (AIN0, AIN1). The input circuit 17 receives analog signals (A00, A10) from the two external devices (AIN0, AIN1) at the same time. Specifically, the input circuit 17 receives two analog signals from the external devices (AIN0, AIN1) and provides them to the AD converters 24f and 24g, respectively. The AD converters 24f and 24g generate conversion values ​​SDIG (A00, A10) in parallel and store them in their respective register circuits. These conversion values ​​SDIG (A00, A10) or the values ​​stored in the register circuits are provided to the subtraction circuit 26c, which generates a difference value (A00-A10).

[0068] The two values ​​that generate the difference value are input at the same time, and AD conversion is performed in parallel. For this purpose, the analog-to-digital conversion circuit 23 includes two AD converters, 24f and 24g. The conversion time is the conversion period TAD (conversion cycle).

[0069] FIG. 8 is a flow chart including exemplary steps in a method for generating an interrupt signal according to an embodiment.

[0070] Referring to Figure 8, there is shown a method 100. In the following description, where possible, reference numerals already used will be used to avoid redundant description.

[0071] The method 100 includes an exemplary step S01, in which the processing unit is set to wait for an interrupt and the analog-to-digital conversion circuit 23 is set to be operational.

[0072] The method 100 includes an exemplary step S02, in which the number of registers to be averaged and a threshold for determining the average value are set, and a register indicator is initialized.

[0073] The method 100 includes an exemplary step S03, in which the analog signal SANA is subjected to AD conversion.

[0074] Method 100 includes exemplary step S04, in which the contents of the register designated by the register designator are received by an averaging circuit.

[0075] The method 100 includes an exemplary step S05, in which a register designator is updated.

[0076] The method 100 includes an exemplary step S06, in which it is determined whether the register indicator exceeds the number of registers to be averaged. If the register specifier does not exceed the number of registers to be averaged, step S03 is carried out. If the register specifier exceeds the number of registers to be averaged, step S07 is carried out.

[0077] The method 100 includes an exemplary step S07, in which an average value of the values ​​stored in the averaging circuit 26b is calculated and the calculated value is output.

[0078] The method 100 includes an exemplary step S08, in which the calculated value from the averaging circuit 26b is compared with a decision threshold to determine whether the comparison result satisfies a condition for generating an interrupt signal SINT. If the comparison result does not satisfy the conditions for generating the interrupt signal SINT, step S02 is carried out. If the comparison result satisfies the condition for generating the interrupt signal SINT, step S09 is carried out.

[0079] The method 100 includes an exemplary step S09, in which an interrupt signal SINT is generated.

[0080] In the method 100, the processor 16b receives the interrupt signal SINT and performs a specific process.

[0081] FIG. 9 is a flow chart including exemplary steps in a method for generating an interrupt signal according to the present invention.

[0082] Referring to Figure 9, there is shown a method 110. In the following description, where possible, reference numerals already used will be used to omit redundant description.

[0083] The method 110 includes an exemplary step S11, in which the processing unit is set to wait for an interrupt and the analog-to-digital conversion circuit 23 is set to be operational.

[0084] The method 110 includes an exemplary step S12, in which an input analog port to be subjected to subtraction is designated.

[0085] The method 110 includes an exemplary step S13, in which a threshold for determining the difference in the subtraction is set.

[0086] The method 110 includes an exemplary step S14, in which the setting for the analog signal to be subtracted is performed in the decision circuit 13.

[0087] The method 110 includes an exemplary step S15, in which an analog signal from an input analog port to be subtracted is received, and an AD conversion is performed to receive a conversion value SDIG from the analog signal.

[0088] The method 110 includes an exemplary step S16, in which the conversion values ​​SDIG to be subtracted are received and their subtraction values ​​are calculated.

[0089] The method 110 includes an exemplary step S17, in which the subtracted value is compared with a difference determination threshold to determine whether the comparison result satisfies the condition for generating the interrupt signal SINT. If the comparison result does not satisfy the conditions for generating the interrupt signal SINT, step S15 is carried out. If the comparison result satisfies the condition for generating the interrupt signal SINT, step S18 is carried out.

[0090] The method 110 includes an exemplary step S18, in which an interrupt signal SINT is generated.

[0091] The method 110 includes an exemplary step S19, in which the processor 16b, upon receiving the interrupt signal SINT, starts interrupt processing.

[0092] The method 110 includes an exemplary step S20, in which the processor 16b performs a specific process using the conversion value SDIG.

[0093] According to this embodiment, the processing executed by the microcomputer is divided into branch judgment processing and post-judgment processing, and a judgment circuit and a semiconductor device can be provided that include hardware that executes at least a part of the branch judgment processing.

[0094] As described above, this embodiment has various aspects as follows.

[0095] A first aspect of the determination circuit of this embodiment comprises: an input circuit having an input and an output configured to receive one or more analog signals; an analog-to-digital conversion circuit configured to receive one or more input signals from the output of the input circuit and generate respective conversion values ​​from the received input signals; an arithmetic circuit including an operator configured to perform a digital operation on the conversion values ​​to generate an operation result; and an output configured to provide at least one of the operation result and the conversion value to a central processing unit; and a comparison circuit configured to compare the operation result with a threshold to generate a comparison result, and to generate an interrupt signal in response to the comparison result indicating that an interrupt condition is satisfied, wherein the analog-to-digital conversion circuit includes at least one analog-to-digital converter.

[0096] In a determination circuit of a second aspect according to the first aspect of this embodiment, the input of the input circuit is further configured to receive a selection signal, the input circuit includes a selector circuit configured to provide a target signal selected from the analog signal in response to the selection signal to the output of the input circuit, the input circuit captures the analog signal at one or more times and provides the input signal, and the analog-to-digital converter can be configured to generate the conversion value of the input signal captured at the times.

[0097] In the determination circuit of the third aspect according to the second aspect of the present embodiment, the arithmetic circuit can include at least one of an averaging circuit and a subtraction circuit as the arithmetic unit.

[0098] In the judgment circuit of the fourth aspect according to the third aspect of this embodiment, the averaging circuit is provided as the calculator in the calculation circuit, and the averaging circuit can perform the digital calculation of averaging the most recent converted value among the converted values ​​and the converted values ​​at a predetermined number of past times in the calculator.

[0099] In a determination circuit of a fifth aspect according to the third or fourth aspect of this embodiment, the averaging circuit of the arithmetic circuit has one or more first inputs configured to receive the converted values ​​from the analog-to-digital converter, a first output configured to provide an averaged signal indicative of the operation result, and a plurality of second outputs configured to provide the converted values ​​from the analog-to-digital converter without applying the digital operation, and the processing circuit includes a data register circuit, the data register circuit having a plurality of inputs configured to receive a plurality of signals from the second outputs of the averaging circuit and a second selection signal, and a plurality of outputs, the data register circuit including a plurality of registers that store the converted values ​​from the second outputs of the averaging circuit, and the data register circuit configured to output at least one of the converted values ​​from the second outputs of the averaging circuit in response to the second selection signal.

[0100] In a determination circuit of a sixth aspect according to any one of the third to fifth aspects of this embodiment, the averaging circuit generates an arithmetic mean value of a predetermined number of past and most recent converted values ​​among the converted values, and the averaging circuit may include shift registers that store the converted values ​​for averaging calculation, adders connected to the outputs of the shift registers, and a divider that is connected to the output of the adders and performs division by the number of converted values ​​related to the arithmetic mean.

[0101] In the determination circuit of the seventh aspect according to the third aspect of this embodiment, the subtraction circuit is provided as the operator in the arithmetic circuit, and the subtraction circuit can have, in the operator, a first output configured to provide a subtraction signal indicative of the operation result, and a plurality of second outputs configured to provide the converted value from the analog-to-digital converter without applying the digital operation.

[0102] In the judgment circuit of the eighth aspect according to any one of the third to seventh aspects of this embodiment, the processing circuit includes a plurality of data register circuits, each having a plurality of inputs configured to receive a signal from the output of the analog-to-digital converter and a third selection signal, and a plurality of outputs, the data register circuits being configured to store the signal from the output of the analog-to-digital converter as a stored value, and the data register circuits being configured to provide at least two of the stored values ​​to the subtraction circuit in response to the third selection signal.

[0103] In the determination circuit of the ninth aspect according to any one of the third to eighth aspects of this embodiment, the analog-to-digital converter can be configured to perform analog-to-digital conversion of a first target signal among the input signals from the input circuit in a first conversion cycle, and to perform analog-to-digital conversion of a second target signal different from the first target signal among the input signals from the input circuit in a second conversion cycle different from the first conversion cycle, and the subtraction circuit can be configured to perform the digital operation of subtracting a first conversion value from the first target signal from a second conversion value from the second target signal to generate a subtraction signal.

[0104] In a determination circuit of a tenth aspect according to any one of the third to eighth aspects of this embodiment, the input circuit includes a sample-and-hold circuit configured to hold the analog signal from the input, and the sample-and-hold circuit, at a certain time, samples and holds a first target signal from the signals from the input of the input circuit, and also samples and holds a second target signal different from the first target signal from the signals from the input of the input circuit, the selector circuit sequentially provides a first sample-and-hold value of the first target signal and a second sample-and-hold value of the second target signal to the analog-to-digital converter, the analog-to-digital converter performs analog-to-digital conversion of the first sample-and-hold value in a first conversion cycle to generate a first converted value, and performs analog-to-digital conversion of the second sample-and-hold value in a second conversion cycle different from the first conversion cycle to generate a second converted value, and the subtraction circuit can perform subtraction of the first converted value and the second converted value as the digital operation.

[0105] In a determination circuit of an eleventh aspect according to any one of the third to ninth aspects of this embodiment, the analog-to-digital conversion circuit includes a first analog-to-digital converter and a second analog-to-digital converter, the input circuit includes a sample-and-hold circuit configured to hold the analog signal from the input, the sample-and-hold circuit samples and holds a first target signal among the input signals from the input circuit at a certain time, and samples and holds a second target signal different from the first target signal among the input signals from the input circuit, the selector circuit provides a first sampled-and-held value of the first target signal and a second sampled-and-held value of the second target signal in parallel to the first analog-to-digital converter and the second analog-to-digital converter of the processing circuit during at least a part of a period, the first analog-to-digital converter performs analog-to-digital conversion of the first sampled-and-held value to generate a first converted value, and the second analog-to-digital converter performs analog-to-digital conversion of the second sampled-and-held value to generate a second converted value, and the subtraction circuit can perform subtraction of the first converted value and the second converted value as the digital operation.

[0106] A semiconductor device according to a twelfth aspect of this embodiment includes a determination circuit according to any one of the first to eleventh aspects, and a processor configured to receive the interrupt signal from the determination circuit.

[0107] The present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit and scope of the present invention, all of which are included in the technical concept of the present invention. [Explanation of symbols]

[0108] 11. Semiconductor device, 13...judgment circuit, 15. Processing equipment, 16b processor, 16c... memory, 17···Input circuit, 17b···input, 17c···output, 17d···Selector, 19... Processing circuit, 21...comparison circuit, 22b...Comparator, 22c Threshold register, 22d···Selector, 23 Analog-to-digital conversion circuit, 24b, 24c, 24f, 24g...AD converter, 24d... resistor circuit, 25... Arithmetic circuit, 25... Data register circuit, 26...Arithmetic unit, 26b...Averaging circuit, 26c... Subtraction circuit, 26th floor hangar, 26g... subtractor, 26h...shift register, 26j···adder, 26k··· divider, 26m, 26n... Operation specification register, 27... Data register circuit, 28...Selector circuit, 28b... Sample and hold circuit, 28d... register, 28f···Selector, 28g···Selector, 29... Output circuit, 31... control circuit, AVRG...straight line, LN··· signal, SANA...analog signal, SAVE...Average signal, SDATA signal, SDIG conversion value, SIN: Input signal, SINT...interrupt signal, SOPE...selection signal, SSEL1, SSEL2, SSEL3, SSEL4, SSEL5, SSEL6...selection signals, SSUB: Subtraction signal, TAD: Conversion period.

Claims

1. an input circuit having an input and an output configured to receive one or more analog signals; a processing circuit including: an analog-to-digital conversion circuit configured to receive one or more input signals from the output of the input circuit and generate respective conversion values ​​from the received input signals; an arithmetic circuit including an operator configured to perform digital operations on the conversion values ​​to generate operation results; and an output configured to provide at least one of the operation results and the conversion values ​​to a central processing unit; a comparison circuit configured to compare the operation result with a threshold to generate a comparison result, and to generate an interrupt signal in response to the comparison result indicating that an interrupt condition is satisfied; Equipped with the analog-to-digital conversion circuit includes at least one analog-to-digital converter; Judgment circuit.

2. the input of the input circuit is further configured to receive a select signal; the input circuit includes a selector circuit configured to provide a signal of interest selected from the analog signal in response to the selection signal to the output of the input circuit; the input circuitry captures the analog signal at one or more times and provides the input signal; the analog-to-digital converter is configured to generate the converted value of the input signal captured at the time; 2. The determination circuit according to claim 1.

3. the arithmetic circuit includes at least one of an averaging circuit and a subtraction circuit as the arithmetic unit; 3. The determination circuit according to claim 2.

4. the arithmetic circuit is provided with the averaging circuit as the arithmetic unit, the averaging circuit performs, in the computing unit, the averaging of the most recent converted value and the converted values ​​at a predetermined number of past times as the digital computation; 4. The determination circuit according to claim 3.

5. the averaging circuit of the arithmetic circuit has one or more first inputs configured to receive the converted values ​​from the analog-to-digital converter, a first output configured to provide an averaged signal indicative of the result of the arithmetic operation, and a plurality of second outputs configured to provide the converted values ​​from the analog-to-digital converter without applying the digital operation; the processing circuitry includes a data register circuit; the data register circuit has a plurality of inputs configured to receive a plurality of signals from the second output of the averaging circuit and a second selection signal, and a plurality of outputs; the data register circuit includes a plurality of registers for storing the converted values ​​from the second output of the averaging circuit; the data register circuit is configured to output at least one of the converted values ​​from the second output of the averaging circuit in response to the second selection signal.

4. The determination circuit according to claim 3.

6. the averaging circuit generates an arithmetic mean of a predetermined number of past and most recent converted values ​​among the converted values; the averaging circuit comprises a shift register for storing the converted values ​​for averaging; an adder connected to each output of said shift register; a divider connected to the output of the adder and performing division by the number of the converted values ​​related to the arithmetic mean; Including, 4. The determination circuit according to claim 3.

7. the arithmetic circuit is provided with the subtraction circuit as the arithmetic unit, the subtraction circuit has a first output configured to provide a subtraction signal indicative of the operation result at the operator, and a plurality of second outputs configured to provide the converted value from the analog-to-digital converter without application of the digital operation; 4. The determination circuit according to claim 3.

8. the processing circuitry includes a plurality of data register circuits; the data register circuit has a plurality of inputs configured to receive a signal from the output of the analog-to-digital converter and a third select signal, and a plurality of outputs; the data register circuit is configured to store the signal from the output of the analog-to-digital converter as a stored value; the data register circuit is configured to provide at least two of the stored values ​​to the subtraction circuit in response to the third selection signal; 4. The determination circuit according to claim 3.

9. the analog-to-digital converter performs analog-to-digital conversion of a first target signal among the input signals from the input circuit in a first conversion cycle, and performs analog-to-digital conversion of a second target signal different from the first target signal among the input signals from the input circuit in a second conversion cycle different from the first conversion cycle; the subtraction circuit is configured to perform, as the digital operation, a subtraction of a first conversion value from the first target signal and a second conversion value from the second target signal to generate a subtraction signal; 4. The determination circuit according to claim 3.

10. the input circuit includes a sample and hold circuit configured to hold the analog signal from the input; the sample-and-hold circuit samples and holds, at a certain time, a first target signal among the signals from the input of the input circuit, and also samples and holds a second target signal different from the first target signal among the signals from the input of the input circuit; the selector circuit sequentially provides the analog-to-digital converter with a first sample-and-hold value of the first target signal and a second sample-and-hold value of the second target signal; the analog-to-digital converter performs analog-to-digital conversion of the first sample-and-hold value in a first conversion cycle to generate a first conversion value, and performs analog-to-digital conversion of the second sample-and-hold value in a second conversion cycle different from the first conversion cycle to generate a second conversion value; the subtraction circuit performs the subtraction of the first converted value and the second converted value as the digital operation.

4. The determination circuit according to claim 3.

11. the analog-to-digital conversion circuit includes a first analog-to-digital converter and a second analog-to-digital converter; the input circuit includes a sample and hold circuit configured to hold the analog signal from the input; the sample-and-hold circuit samples and holds, at a certain time, a first target signal among the input signals from the input circuit, and also samples and holds a second target signal different from the first target signal among the input signals from the input circuit; the selector circuit provides the first sample-and-hold value of the first target signal and the second sample-and-hold value of the second target signal in parallel to the first analog-to-digital converter and the second analog-to-digital converter of the processing circuit during at least a portion of a period; the first analog-to-digital converter performs analog-to-digital conversion of the first sample-and-hold value to generate a first converted value, and the second analog-to-digital converter performs analog-to-digital conversion of the second sample-and-hold value to generate a second converted value; the subtraction circuit performs the subtraction of the first converted value and the second converted value as the digital operation.

4. The determination circuit according to claim 3.

12. A determination circuit according to any one of claims 1 to 11; a processor configured to receive the interrupt signal from the determination circuit; Equipped with Semiconductor device.

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