Semiconductor device

Abstract

To provide a semiconductor device that suppresses the degradation of processing performance in the semiconductor device containing two or more semiconductor chips with different communication speeds.SOLUTION: The semiconductor device includes a first peripheral circuit provided on a first semiconductor chip equipped with a first bus and arranged around a specific circuit on the first semiconductor chip, a register provided in the first peripheral circuit, a second peripheral circuit provided on a second semiconductor chip equipped with a second bus having a communication speed equal to or greater than the communication speed of the first bus and arranged around a specific circuit on the second semiconductor chip, and one or more signal lines that transmit signals corresponding to data held in the register to the second peripheral circuit. The data held in the register is transmitted to the second peripheral circuit via the one or more signal lines without passing through the first bus.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present disclosure relates to semiconductor devices. [Background technology]

[0002] In a multi-die package (chip), which is an example of a semiconductor device disclosed in Patent Document 1, a plurality of dies (semiconductor chips) are connected by inter-chip signal lines for data communication. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Special Publication No. 2018-510512 Summary of the Invention [Problem to be solved by the invention]

[0004] For example, when a commonly used die of an advanced process is combined with one or more dies of a legacy process, the communication speed (transfer rate) of the communication bus provided on the die of the advanced process is generally faster than the communication speed (transfer rate) of the communication bus provided on the die of the legacy process. Therefore, the difference in these communication speeds, i.e., the communication speed of the die of the legacy process, may cause a decrease in the processing performance of the entire chip. Therefore, the conventional technology has room for improvement in suppressing a decrease in the processing performance of a semiconductor device including two or more semiconductor chips with different communication speeds.

[0005] In view of the above circumstances, the present disclosure has an object to provide a semiconductor device that suppresses a decrease in the processing performance of a semiconductor device that includes two or more semiconductor chips with different communication speeds. [Means for solving the problem]

[0006] In order to solve the above problem, the semiconductor device according to the present disclosure comprises: a first peripheral circuit provided on a first semiconductor chip having a first bus and arranged around a specific circuit on the first semiconductor chip; a register provided in the first peripheral circuit; a second peripheral circuit provided on a second semiconductor chip having a second bus whose communication speed is equal to or higher than the communication speed of the first bus and arranged around the specific circuit on the second semiconductor chip; and one or more signal lines for transmitting a signal corresponding to data held in the register to the second peripheral circuit, wherein the data held in the register is transmitted to the second peripheral circuit via the one or more signal lines without passing through the first bus. [Brief explanation of the drawings]

[0007] [Figure 1A] FIG. 1A is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 1B] FIG. 1B is a hardware configuration diagram of a semiconductor device 100 according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a diagram showing a specific example of a circuit included in the semiconductor device 100 according to the embodiment of the present disclosure. [Figure 3A] FIG. 3A is a diagram showing an example of the configuration of the bus I / F of the first peripheral circuit 11. As shown in FIG. [Figure 3B] FIG. 3B is a diagram showing an example of the configuration of the second peripheral circuit 21. As shown in FIG. [Figure 4A] 3A to 3C are diagrams for explaining the operation of the semiconductor device 100 of the present disclosure. [Figure 4B] 3A to 3C are diagrams for explaining the operation of the semiconductor device 100 of the present disclosure. [Figure 5] FIG. 5 is a diagram showing an example of the configuration of a semiconductor device 100A according to a comparative example. [Figure 6] FIG. 6 is a diagram showing an example of the configuration of a first peripheral circuit 11A of a semiconductor device 100A according to a comparative example. [Figure 7] FIG. 7 is a diagram for explaining the operation of the semiconductor device 100A according to the comparative example. [Figure 8]FIG. 8 is a diagram showing an example of the configuration of a semiconductor device 100-1 according to a modified example. [Figure 9A] FIG. 9A is a diagram showing the connection relationship between a first semiconductor chip 101-1 and a first transfer circuit 14 included in a semiconductor device 100-1 according to a modified example. [Figure 9B] FIG. 9B is a diagram showing the connection relationship between the second semiconductor chip 102-1 and the second transfer circuit 26 included in the semiconductor device 100-1 according to the modified example. [Figure 10A] FIG. 10A is a diagram for explaining the operation of the semiconductor device 100-1 according to the modified example. [Figure 10B] FIG. 10B is a diagram for explaining the operation of the semiconductor device 100-1 according to the modified example. [Figure 11A] FIG. 11A is a diagram showing an example of the configuration of the first transfer circuit 14. As shown in FIG. [Figure 11B] FIG. 11B is a diagram showing an example of the configuration of the second transfer circuit 26. As shown in FIG. [Figure 11C] FIG. 11C is a diagram showing the configuration of the transmission priority control unit 1. [Figure 12A] FIG. 12A is a diagram for explaining the transmission priority order of a group. [Figure 12B] FIG. 12B is a diagram for explaining a specific example of the value of a signal indicating a group including a changed signal. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, embodiments will be described with reference to the drawings. Note that the same or similar reference numerals are used to designate the same functions or configurations, and descriptions thereof will be omitted as appropriate.

[0009] (Embodiment) FIG. 1A is an external view of a semiconductor device 100 according to an embodiment of the present disclosure. FIG. 1B is a schematic diagram of a hardware configuration of the semiconductor device 100 according to an embodiment of the present disclosure. FIG. 2 is a diagram showing a specific example of a circuit included in the semiconductor device 100 according to an embodiment of the present disclosure. The semiconductor device 100 may include a first semiconductor chip 101 and a second semiconductor chip 102. The second semiconductor chip 102 is connected to the first semiconductor chip 101 via multiple signal lines SW and multiple buses (BUS). The first semiconductor chip 101 may be interpreted as a custom die, and the second semiconductor chip 102 as a core (RORE) die, for example.

[0010] (First semiconductor chip 101) As shown in FIG. 2, the first semiconductor chip 101 may include a first peripheral circuit 11, a first bus 12, and a level shifter 13.

[0011] (First peripheral circuit 11) The first peripheral circuit 11 may be interpreted as a circuit provided around a specific circuit on the first semiconductor chip 101. The first peripheral circuit 11 may include a register .

[0012] (First bus 12) The first bus 12 may be interpreted as a bus having a specific communication speed, and may transmit a signal transmitted from the first peripheral circuit 11 to the level shifter 13. The first bus 12 may also transmit a signal transmitted from the second semiconductor chip 102 via the level shifter 13 to the first peripheral circuit 11.

[0013] (Level Shifter 13) The level shifter 13 may change the voltage level of a signal transmitted between dies, that is, between the first semiconductor chip 101 and the second semiconductor chip 102. Specifically, the level shifter 13 receives a signal corresponding to the data held in the register 10, converts the voltage level of the signal to a voltage level that can be handled by the second semiconductor chip 102, and transmits the converted signal to the second semiconductor chip 102 via one or more signal lines SW. The level shifter 13 may convert the voltage level of a signal transmitted from the second semiconductor chip 102 to a voltage level that can be handled by the first semiconductor chip 101, and transmits the converted signal to the first semiconductor chip 101 via one or more signal lines SW. In this embodiment, as an example, four signal lines SW for transmitting 12-bit data are used.

[0014] (Second semiconductor chip 102) 2, the second semiconductor chip 102 may include a plurality of peripheral circuits, a synchronization unit 22, a second bus 24, a level shifter 20, and a bus master 25. The second semiconductor chip 102 may include a second peripheral circuit 21 and a peripheral circuit 23 as the plurality of peripheral circuits. The bus master 25 may be interpreted as a CPU. The bus master 25 may be provided in the second semiconductor chip 102 and may read data held in the second peripheral circuit 21 via the second bus 24. The synchronization unit 22 adjusts the difference between the communication speed of the first bus 12 and the communication speed of the second bus 24.

[0015] (Second peripheral circuit 21) The second peripheral circuit 21 may be provided around a specific circuit on the second semiconductor chip 102. The specific circuit may be interpreted as a bus master 25.

[0016] (2nd bus 24) The second bus 24 may be interpreted as a bus whose communication speed is equal to or greater than that of the first bus 12. Specifically, the communication speed of the first bus 12 may be 37.5 MHz, and the communication speed of the second bus 24 may be 150 MHz. The second bus 24 may transmit a signal transmitted from the second peripheral circuit 21 to the level shifter 20, and may transmit a signal transmitted from the first semiconductor chip 101 and transmitted via the level shifter 20 to the second peripheral circuit 21.

[0017] (Level Shifter 20) The level shifter 20 may change the voltage level of a signal transmitted between dies, that is, between the first semiconductor chip 101 and the second semiconductor chip 102, similarly to the level shifter 13.

[0018] 3A is a diagram showing an example of the configuration of the bus I / F of the first peripheral circuit 11. The bus I / F of the first peripheral circuit 11 may include an address decoder 11a and a register 11b that reads and writes the address decoded by the address decoder 11a. The bus I / F of the first peripheral circuit 11 may also include a read data selector 11c that performs a read process of read data prdata and transmits the read data prdata to the second semiconductor chip 102 every time the address read enable is enabled, and a register 10.

[0019] The register 10 may hold data, such as data that has been analog-to-digital converted (hereinafter referred to as ADC or AD converted), to be handled by a circuit on the first semiconductor chip 101. A signal corresponding to the data held in the register 10 may be transmitted to the second peripheral circuit 21 on the second semiconductor chip 102 via one or more signal lines SW, without passing through the first bus 12.

[0020] 3B is a diagram showing an example of the configuration of the second peripheral circuit 21. The second peripheral circuit 21 may include an address decoder 21a and a read data selection unit 21b. Each time an address read enable decoded by the address decoder 21a is enabled, the read data selection unit 21b performs a read process of the read data prdata, data from the register 10, etc., and transmits the read data to the bus master 25 via the second bus 24.

[0021] 4A and 4B are diagrams illustrating the operation of the semiconductor device 100 of the present disclosure. The semiconductor device 100 of the present disclosure can transmit data held in the register 10 provided in the first semiconductor chip 101 directly to the second peripheral circuit 21. That is, the semiconductor device 100 can transmit the data held in the register 10 to the second peripheral circuit 21 without passing through the first bus 12. The bus master 25 can read the value of the register 10 from the second peripheral circuit 21 at the communication speed of the second bus 24, regardless of the communication speed of the first bus 12. This reduces the number of read access cycles to the first peripheral circuit 11 on the custom die side. Data transmission path A shown in FIG. 4A is a data transmission path from the first peripheral circuit 11 to the level shifter 13, and data transmission path B is a data transmission path from the level shifter 20 to the second peripheral circuit 21 (and the bus master 25). Data transmission path A is a simple wire connection that does not involve logic gates, and therefore the delay is extremely small compared to the operation cycle of the bus master 25 (CPU). For example, the data transmission path A completes the data transmission by the time the bus master 25 (CPU) receives a read data preparation completion interrupt from the first peripheral circuit 11 and detects it.

[0022] FIG. 4B shows timing charts of the processes of a semiconductor device according to a comparative example (described later) and the semiconductor device 100 according to the present disclosure. In the semiconductor device according to the comparative example, the bus master 25 (CPU) receives a read data preparation completion interrupt, detects it, and then reads multiple pieces of data after AD conversion. In contrast, in the semiconductor device 100 according to the present disclosure, data propagation along the data transmission path A is completed by the time the bus master 25 (CPU) detects the read data preparation completion interrupt. Therefore, the bus master 25 (CPU) can read the value of the register 10 from the second peripheral circuit 21 at the communication speed of the second bus 24, without relying on the communication speed of the slow first bus 12. This reduces the processing time of the bus master 25 (CPU) for reading the value of the register 10, and also suppresses an increase in the processing load of the bus master 25 (CPU). The reduced processing time of the bus master 25 (CPU) allows the bus master 25 (CPU) to perform other processes.

[0023] 5 is a diagram showing a configuration example of a semiconductor device 100A according to a comparative example. FIG. 6 is a diagram showing a configuration example of a first peripheral circuit 11A of the semiconductor device 100A according to the comparative example. The semiconductor device 100A includes a first peripheral circuit 11A instead of the first peripheral circuit 11 shown in FIG. 2. The first peripheral circuit 11A does not include the register 10 shown in FIG. 2. Furthermore, the semiconductor device 100A does not include a second peripheral circuit 21.

[0024] 7 is a diagram illustrating the operation of the semiconductor device 100A according to the comparative example. The bus master 25 (CPU) accesses the first peripheral circuit 11A via the synchronization unit 22, the level shifter 20, the level shifter 13, and the first bus 12. In the semiconductor device 100A, the bus master 25 (CPU) receives a read data preparation completion interrupt, and after detecting it, reads multiple pieces of data after AD conversion. Because data reading depends on the communication speed of the slow first bus 12, the processing load on the bus master 25 (CPU) increases accordingly.

[0025] In the semiconductor device 100 of the present disclosure, even if two or more buses with different communication speeds are included, the value of the register 10 can be read from the second peripheral circuit 21 at the communication speed of the second bus 24, regardless of the communication speed of the slower bus. This makes it possible to reduce the number of read access cycles to the first peripheral circuit 11 on the custom die side, and also to suppress a decrease in the processing performance of the entire semiconductor device 100.

[0026] (Variation) Fig. 8 is a diagram showing a configuration example of a semiconductor device 100-1 according to a modified example. Fig. 9A is a diagram showing the connection relationship between a first semiconductor chip 101-1 and a first transfer circuit 14 included in the semiconductor device 100-1 according to the modified example. Fig. 9B is a diagram showing the connection relationship between a second semiconductor chip 102-1 and a second transfer circuit 26 included in the semiconductor device 100-1 according to the modified example.

[0027] The semiconductor device 100-1 may include a first semiconductor chip 101-1 and a second semiconductor chip 102-1 instead of the first semiconductor chip 101 and the second semiconductor chip 102.

[0028] The first semiconductor chip 101-1 may include a first transfer circuit 14 in addition to the components of the first semiconductor chip 101 described above. The first transfer circuit 14 is provided in the first semiconductor chip 101-1 and time-divides data held in the register 10 and transfers the time-divided data to the second peripheral circuit 21 via one or more signal lines SW. Specifically, the first transfer circuit 14 time-divides data transmitted from the register 10 into four cycles via, for example, four signal lines SW transmitting 12-bit data, and transfers the time-divided data to the second peripheral circuit 21 via, for example, one signal line SW transmitting 12-bit data. This allows the number of inter-die ports to be reduced to one-fourth. Specific examples of the first transfer circuit 14 will be described later. For convenience of explanation, an example is described here using four signal lines SW transmitting 12-bit data and one signal line SW transmitting 12-bit data.

[0029] The second semiconductor chip 102-1 may include a second transfer circuit 26 in addition to the configuration of the second semiconductor chip 102 described above. The second transfer circuit 26 may restore the data held in the register 10 from the data transferred from the first transfer circuit 14, and transfer the restored data to the second peripheral circuit 21.

[0030] 10A and 10B are diagrams for explaining the operation of a semiconductor device 100-1 according to a modified example. In the semiconductor device 100-1 according to the modified example, data held in a register 10 provided in a first semiconductor chip 101-1 is transferred to a second peripheral circuit 21 via a data transmission path C shown in Fig. 10A. That is, the data held in the register 10 is time-shared by a first transfer circuit 14, and the time-shared data is transferred to the second peripheral circuit 21 via a single signal line SW.

[0031] The second transfer circuit 26 restores the data held in the register 10 from the data transferred from the first transfer circuit 14, and transfers the restored data to the second peripheral circuit 21 via the signal line SW that transmits 12-bit data. The bus master 25 can read the value of the register 10 from the second peripheral circuit 21 via the data transfer path B at the communication speed of the second bus 24, regardless of the communication speed of the first bus 12. This allows the number of read access cycles to the first peripheral circuit 11 on the custom die side to be reduced, similar to the semiconductor device 100.

[0032] FIG. 10B shows timing charts of the processes of the semiconductor device 100A according to the comparative example and the semiconductor device 100-1 according to the modified example. In the semiconductor device 100A according to the comparative example, the bus master 25 (CPU) receives a read data preparation completion interrupt, and after detecting the interrupt, the bus master 25 (CPU) reads multiple pieces of data after AD conversion. In contrast, in the semiconductor device 100-1 according to the modified example, multiple AD conversion results (1 to 3) generated in chronological order are autonomously transferred upon completion of AD conversion. In other words, even if the bus master 25 (CPU) does not read the AD conversion results from the first semiconductor chip 101-1, the AD conversion results are transferred to the second semiconductor chip 102-1 in chronological order. Therefore, data propagation through the data transmission path A is completed by the time the bus master 25 (CPU) detects the read data preparation completion interrupt. Therefore, the bus master 25 (CPU) can read the value of the register 10 from the second peripheral circuit 21 at the communication speed of the second bus 24, without depending on the communication speed of the slow first bus 12.

[0033] FIG. 11A is a diagram illustrating a configuration example of the first transfer circuit 14. The first transfer circuit 14 may transmit a plurality of signals (e.g., snd_sig[11:0], snd_sig[23:12], snd_sig[24:35]) held in the register 10 of the first peripheral circuit 11 to the second transfer circuit 26 via, for example, 12 signal lines SW. Each of the plurality of signals may be interpreted as a 12-bit signal. These signals are input to the first transfer circuit 14 via, for example, 36 signal lines SW (12 bits per line × 3 groups). Note that the number of these signals and the number of signal lines SW are merely an example in the present disclosure, and the embodiment of the present disclosure is not limited thereto.

[0034] The first transfer circuit 14 may have a function for controlling transmission of all signals in a group including signals whose values ​​have changed among the plurality of signals, and non-transmission of all signals in a group including signals whose values ​​have not changed. The first transfer circuit 14 may include a signal change detection unit 2, a plurality of selectors S_0 to S_2, a selector S_n, a plurality of registers R_0 to R_2, a register R_a, a register R_b, and a transmission priority control unit 1.

[0035] (Signal change detection unit 2) The signal change detection section 2 may detect whether or not the value of any of the signals included in any of a plurality of groups, each of which includes one or more signals, has changed.

[0036] Specifically, if the values ​​of all signals held in each of the multiple registers R_0 to R_2 match the values ​​of the signals included in a group that can be newly transmitted, the signal change detection unit 2 may determine that the values ​​of the signals included in the group have not changed.If the values ​​of all signals held in each of the multiple registers R_0 to R_2 do not match the values ​​of the signals included in the group that can be newly transmitted (i.e., there is a mismatch), the signal change detection unit 2 may determine that the value of one of the signals included in the group has changed.

[0037] (Group 0) More specifically, the signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[11:0]) included in group 0 has changed by comparing the value of the signal (snd_sig[11:0]) included in group 0 with the value of the signal held in register R_0. The signals (snd_sig[11:0]) included in group 0 may be interpreted as the lowest 4 bits of the 36-bit signal.

[0038] (Group 1) The signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[23:12]) included in group 1 has changed by comparing the value of the signal (snd_sig[23:12]) included in group 1 with the value of the signal held in register R_1. The signals (snd_sig[23:12]) included in group 1 may be interpreted as the upper 4 bits of the signals in group 0 out of the 36-bit signal.

[0039] (Group 2) The signal change detection unit 2 may detect whether the value of any of the signals (snd_sig[35:24]) included in group 2 has changed by comparing the value of the signals (snd_sig[35:24]) included in group 2 with the value of the signals held in register R_2. The signals (snd_sig[35:24]) included in group 2 may be interpreted as the upper 4 bits of the signals in group 1 out of the 36-bit signal.

[0040] When the value of any of the signals changes, the signal change detection unit 2 inputs to the transmission priority control unit 1 a signal (snd_chg[2:0]) indicating the group containing the signal whose value has changed among the multiple groups.

[0041] For example, if the value of any of the signals included in group 0 changes, the signal change detection unit 2 inputs a signal (snd_chg[0]) indicating group 0 to the transmission priority control unit 1, and if the value of any of the signals included in group 1 changes, the signal change detection unit 2 inputs a signal (snd_chg[1]) indicating group 1 to the transmission priority control unit 1. Furthermore, if the value of any of the signals included in group 2 changes, the signal change detection unit 2 inputs a signal (snd_chg[2]) indicating group 2 to the transmission priority control unit 1.

[0042] When the signal change detector 2 detects that the value of any of the signals included in any of the groups has changed, it inputs a signal (snd_update) indicating that there is a group including the signal whose value has changed to the register R_b. As a result, the signal held in the register R_b is transmitted to the second transfer circuit 26 via the level shifter 13.

[0043] (Transmission priority control unit 1) When there are multiple groups in which signals have changed, the transmission priority control unit 1 determines the priority order in order to transmit the signals included in each of the multiple groups in accordance with a specific priority order.

[0044] Specifically, the transmission priority control unit 1 determines the transmission priority of signals in the group including the signal whose value has changed, based on the signal (snd_chg[2:0]) from the signal change detection unit 2, and inputs a signal (snd_num[1:0]) indicating the group number to be transmitted to the register R_a. The signal held in the register R_a is input to the selector S_n and further transmitted to the second transfer circuit 26 via the level shifter 13. By providing the transmission priority control unit 1, it is possible to avoid a situation where, when signals in group 0 continue to change, all signals in group 0 continue to be transmitted, and signals in other groups are not transmitted even if the signals in other groups change. The configuration of the transmission priority control unit 1 will be described in detail later.

[0045] (Selector S_n) The selector S_n selects all signals in the group to be transmitted from the registers R_0 to R_2 based on the signal, and the selected signals are transmitted to the second transfer circuit 26 via the level shifter 13.

[0046] (Registers R_0 to R_2) The registers R_0 to R_2 hold the signals selected by the selectors S_0 to S_2, respectively. Specifically, the register R_0 holds the signal (snd_sig[11:0]) included in group 0 from the selector S_0. The register R_1 holds the signal (snd_sig[23:12]) included in group 1 from the selector S_1. The register R_2 holds the signal (snd_sig[35:24]) included in group 2 from the selector S_2.

[0047] (Selectors S_0 to S_2) The selector S_0 may input a selection signal (snd_sel[0]) to output a signal (snd_sig[11:0]) included in group 0. When the selector S_0 does not input a selection signal (snd_sel[0]), the selector S_0 may output a signal held in the register R_0.

[0048] The selector S_1 may input a selection signal (snd_sel[1]) to output a signal (snd_sig[23:12]) included in group 1. When the selector S_1 does not input a selection signal (snd_sel[1]), the selector S_1 may output a signal held in the register R_1.

[0049] The selector S_2 may input a selection signal (snd_sel[2]) to output a signal (snd_sig[35:24]) included in group 2. When the selector S_2 does not input a selection signal (snd_sel[2]), the selector S_2 may output a signal held in the register R_2.

[0050] These selection signals may be input in a specific order, for example, snd_sel[0], snd_sel[1], snd_sel[2], snd_sel[0], snd_sel[1], and so on, each time the value of a specific counter is incremented.

[0051] The first transfer circuit 14 configured in this way may not transmit the signal to the second transfer circuit 26 if the value of any of the signals in the group does not change.

[0052] Furthermore, if there are two or more groups among the multiple groups in which the values ​​of any of the signals included in a specific group have changed simultaneously, the first transfer circuit 14 may select a specific group from these groups and transmit all of the signals included in the selected group to the second transfer circuit 26.

[0053] For example, if the value of any of the signals included in group 0 and the value of any of the signals included in group 1 have changed, but none of the signals included in group 2 have changed, the first transfer circuit 14 may transmit the signals included in group 0 and the signals included in group 1 to the second transfer circuit 26, and may not transmit the signals included in group 2 to the second transfer circuit 26. Furthermore, the first transfer circuit 14 may store these transmitted signals in register R_0 and register R_1.

[0054] In this way, the first transfer circuit 14 detects whether or not a signal in a group has changed, and transmits all signals in the group only if a change has occurred. Also, if signals in multiple groups change simultaneously, the transmission priority control unit 1 selects one group to transmit, and the first transfer circuit 14 transmits all signals in the selected group, and simultaneously holds the values ​​of the transmitted signals.

[0055] (Second transfer circuit 26) 11B is a diagram showing an example of the configuration of the second transfer circuit 26. The second transfer circuit 26 is configured similarly to the first transfer circuit 14. For example, when signals (snd_num[1:0], snd_update) from the first transfer circuit 14 are input as received signals (rcv_num[1:0], rcv_update), the second transfer circuit 26 generates selection signals (rcv_sel[11:0], rcv_sel[23:12], rcv_sel[35:24]) that select one of the signals (rcv_data[1:0]) received by the multiple selectors S_0 to S_2. The signal selected by the selection signal is held in registers R_0 to R_2 and output as a received signal. In this way, the values ​​of snd_sig, snd_reg, and rcv_sig are all the same.

[0056] 11C is a configuration diagram of the transmission priority control unit 1. The transmission priority control unit 1 rotates the transmission priorities of multiple groups 0 to 2 by incrementing snd_cnt[1:0] with the counter 3. That is, in order to transmit only signals in the group that includes a signal whose value has changed, a signal (snd_num[1:0]) indicating the group number to be transmitted is output at the timing when the group number is incremented by the counter 3. By rotating the transmission priorities of the groups, signals included in each group are transmitted equally. That is, multiple groups are transmitted evenly over a fixed period of time.

[0057] FIG. 12A is a diagram illustrating the transmission priority order of groups. FIG. 12B is a diagram illustrating a specific example of the value of a signal indicating a group including a changed signal. As shown in FIG. 12A, for example, when snd_cnt[1:0] is 00 (binary: 0), the order of transmission priority of groups is group 0, group 1, and group 2. That is, group 0 has the highest priority. When snd_cnt[1:0] is 01 (binary: 1), the order of priority is group 3, group 2, and group 1. That is, group 0 has the highest priority. Also, as shown in FIG. 12A, if groups 0 and 2 have changed but group 1 has not changed, group 2 is transmitted. That is, group 1 has the highest priority, but because the signal within group 1 has not changed, group 2, which has the next highest priority, is transmitted.

[0058] If there is only one group in which signals have changed, the value of the signal indicating that group containing the signal whose value has changed will be 0001 (binary: 1) if only the signals in group 0 have changed, as shown in FIG. 12B. Similarly, if only the signals in group 1 have changed, the signal value will be 0010 (binary: 2). If only the signals in group 2 have changed, the signal value will be 0100 (binary: 4).

[0059] If there are multiple groups whose signals changed at the same time, the value of the signal indicating the group containing the signal whose value changed will be 0101 (binary: 5) if the signals of group 0 and group 2 change, as shown in Figure 12B. In this case, snd_cnt[1:0] may be 10 (binary: 2) indicating that group 2 has a higher priority, and snd_num[1:0] may be 10 (binary: 2).

[0060] In the present disclosure, a configuration example in which a signal transmitted from the first transfer circuit 14 is received by the second transfer circuit 26 has been described, but the configuration of the present disclosure is not limited to this. The first transfer circuit 14 may be provided with the function of the second transfer circuit 26, and the second transfer circuit 26 may be provided with the function of the first transfer circuit 14. In this case, the signal transmitted from the second transfer circuit 26 is received by the first transfer circuit 14. In other words, the signal may be transmitted in either direction.

[0061] Thus, according to the semiconductor device 100-1 of the modified example, in addition to the effects of the semiconductor device 100 described above, the effect of being able to reduce the number of signal lines SW (signal lines SW for transmitting AD conversion data) between dies can be obtained, for example, from 36 to 12.

[0062] In addition, the following supplementary notes are provided in relation to the above description.

[0063] (Appendix 1) a first peripheral circuit provided on a first semiconductor chip having a first bus and provided around a specific circuit on the first semiconductor chip; a register provided in the first peripheral circuit; a second peripheral circuit provided on a second semiconductor chip including a second bus whose communication speed is equal to or faster than the communication speed of the first bus, the second peripheral circuit being provided around a specific circuit on the second semiconductor chip; one or more signal lines for transmitting signals corresponding to the data held in the register to the second peripheral circuit; Equipped with The data held in the register is transmitted to the second peripheral circuit via one or more of the signal lines, without passing through the first bus. (Appendix 2) 2. The semiconductor device according to claim 1, further comprising a circuit provided in the second semiconductor chip, the circuit reading out data held in the second peripheral circuit via the second bus. (Appendix 3) a first transfer circuit provided in the first semiconductor chip, which time-divides data held in the register and transfers the time-divided data to the second peripheral circuit via one or more of the signal lines; a second transfer circuit that restores data held in the register from the data transferred from the first transfer circuit and transfers the restored data to the second peripheral circuit. (Appendix 4) the first semiconductor chip is a first semiconductor chip, 4. The semiconductor device according to claim 1, wherein the second semiconductor chip is a second semiconductor chip connected to the first semiconductor chip via one or more of the signal lines. [Explanation of symbols]

[0064] 1 Transmission priority control section 2. Signal change detection section 3 Counter 10 Registers 11 First peripheral circuit 11A First peripheral circuit 11a Address Decoder Register 11b 11c Read data selection section 12 First Bus 13 Level Shifter 14 First transfer circuit 20 Level Shifter 21 Second peripheral circuit 21a Address decoder 21b Read data selection section 22 Synchronization section 23 Peripheral Circuits 24 Second Bus 25 Bus Master 26 Second transfer circuit 100 Semiconductor device 100-1 Semiconductor device 100A Semiconductor Device 101 First Semiconductor Chip 101-1 First semiconductor chip 101A First semiconductor chip 102 Semiconductor Chip 102-1 Semiconductor chip 102A Semiconductor Chip

Claims

1. a first peripheral circuit provided on a first semiconductor chip having a first bus and provided around a specific circuit on the first semiconductor chip; a register provided in the first peripheral circuit; a second peripheral circuit provided on a second semiconductor chip including a second bus whose communication speed is equal to or faster than the communication speed of the first bus, the second peripheral circuit being provided around a specific circuit on the second semiconductor chip; one or more signal lines for transmitting signals corresponding to the data held in the register to the second peripheral circuit; Equipped with The data held in the register is transmitted to the second peripheral circuit via one or more of the signal lines, not via the first bus.

2. 2. The semiconductor device according to claim 1, further comprising a circuit provided in said second semiconductor chip, which reads out data held in said second peripheral circuit via said second bus.

3. a first transfer circuit provided in the first semiconductor chip, which time-divides data held in the register and transfers the time-divided data to the second peripheral circuit via one or more of the signal lines; 2. The semiconductor device according to claim 1, further comprising: a second transfer circuit that restores data held in said register from data transferred from said first transfer circuit and transfers the restored data to said second peripheral circuit.

4. the first semiconductor chip is a first semiconductor chip, 2. The semiconductor device according to claim 1, wherein the second semiconductor chip is a second semiconductor chip connected to the first semiconductor chip via one or more of the signal lines.

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