Technology for bridge die for optical interconnection

Abstract

To provide a device in which a long trace length is suppressed to improve power distribution.SOLUTION: In an integrated circuit package 100, build-up layers 104 are adjacent to a substrate 102, and a bridge die 110 and a photonic integrated circuit (PIC) die 114 are each mounted on the substrate. A first electronic integrated circuit (EIC) die 108 is mounted on the build-up layers and the bridge die, and a second EIC die 112 is mounted on the bridge die and the PIC die. The bridge die transfers electronic signals between the EIC dies and provides power signals from the substrate through one or more through-silicon vias 304 defined in the bridge die. The power signals are provided to the PIC die, which allows for a shorter path for a power signal compared to passing the power signal through the build-up layers, and such a shorter path improves power distribution integrity and reduces parasitic power distribution drop.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This case relates to technology for bridge dies for optical interconnects. [Background technology]

[0002] Photonic integrated circuit (PIC) dies can be used for a number of applications, such as communications. PIC dies can provide high-speed, compact communications. However, PIC dies may be fabricated on a separate die from electronic integrated circuit (EIC) dies on the same package. As a result, the total trace length for power signals can be relatively long due to passing through build-up layers and extending through one or more EIC dies before reaching the PIC die. Such long trace lengths can result in poorer power distribution integrity and parasitic power distribution degradation. [Brief explanation of the drawings]

[0003] [Figure 1] FIG. 1 is a perspective view of a system including an integrated circuit package having a substrate, an electrical integrated circuit (EIC) die, a bridge die, and a photonic integrated circuit (PIC) die. [Figure 2] FIG. 2 is a plan view of the system of FIG. [Figure 3]

[0004] FIG. 3 is a cross-sectional view of one embodiment of the system of FIG. [Figure 4]

[0005] Figure 4 is a cross-sectional view of one embodiment of a system including an EIC die, a bridge die, and a PIC die. [Figure 5]

[0006] Figure 5 is a cross-sectional view of one embodiment of a system including an EIC die, a bridge die, and a PIC die. [Figure 6]

[0007] Figure 6 is a cross-sectional view of one embodiment of a system including an EIC die, a bridge die, and a PIC die. [Figure 7]

[0008] Figure 7 is a cross-sectional view of one embodiment of a system including an EIC die, a bridge die, and a PIC die. [Figure 8]

[0009] Figure 8 is a plan view of one embodiment of a system including an EIC die, a bridge die, and a PIC die. [Figure 9]

[0010] FIG. 9 is a cross-sectional view of one embodiment of the system of FIG. [Figure 10]

[0011] Figure 10 is a plan view of one embodiment of a system including an EIC die, a bridge die, and a PIC die. [Figure 11]

[0012] Figure 11 is a plan view of one embodiment of a system including several EIC dies and a bridge die. [Figure 12]

[0013] FIG. 12 is a cross-sectional view of one embodiment of the system of FIG. [Figure 13]

[0014] FIG. 13 is a cross-sectional view of one embodiment of a system including an EIC die, a bridge die, and a micro LED die. [Figure 14]

[0015] FIG. 14 is a plan view of a wafer and die that may be included in a microelectronic assembly according to any embodiment disclosed herein. [Figure 15]

[0016] FIG. 15 is a cross-sectional side view of an integrated circuit device that may be included in a microelectronic assembly according to any embodiment disclosed herein. [Figure 16A]

[0017] 16A-16D are perspective views of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 16B]16A-16D are perspective views of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 16C] 16A-16D are perspective views of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 16D] 16A-16D are perspective views of exemplary planar, gate-all-around, and stacked gate-all-around transistors. [Figure 17]

[0018] FIG. 17 is a cross-sectional side view of an integrated circuit device assembly that may include a microelectronic assembly according to any embodiment disclosed herein. [Figure 18]

[0019] FIG. 18 is a block diagram of an exemplary electrical device that may include a microelectronic assembly according to any embodiment disclosed herein. DETAILED DESCRIPTION OF THE INVENTION

[0004]

[0020] In various embodiments disclosed herein, a system includes an electronic integrated circuit (EIC) die, a bridge die, and a photonic integrated circuit (PIC), such as a PIC die. In an exemplary embodiment, the bridge die includes through-silicon vias that deliver power signals to the photonic integrated circuit. The bridge die can provide a more direct path for the power signal compared to, for example, through build-up layers and the EIC die. This results in improved power delivery integrity and reduced parasitic power delivery.

[0005]

[0021] As used herein, the phrase "communicatively coupled" refers to the ability of one component to send or receive signals to another component. The signal can be any type of signal, such as an input signal, an output signal, or a power signal. A component can send or receive signals to another component to which it is communicatively coupled via a wired or wireless communication medium (e.g., conductive traces, conductive contacts, air). Examples of communicatively coupled components include integrated circuit dies located within the same package that communicate via embedded bridges in the package substrate, and integrated circuit components mounted on a printed circuit board that send or receive signals to or from other integrated circuit components or electronic devices mounted on the printed circuit board.

[0006]

[0022] Although specific details are set forth in the following description, embodiments of the technology described herein may be practiced without these specific details. Well-known circuits, structures, and techniques are not shown in detail so as not to obscure an understanding of the description. Phrases such as "embodiments," "various embodiments," and "some embodiments" may include a feature, structure, or characteristic, but not all embodiments necessarily include that particular feature, structure, or characteristic.

[0007]

[0023] Some embodiments may have all, some, or none of the features described with respect to other embodiments. "First," "second," "third," and the like describe a common subject and indicate different instances of the same referenced subject. Such adjectives do not imply that the subjects so described must be present in a given order, temporally or spatially, ranking, or in any other manner. "Connected" may indicate that elements are in direct physical or electrical contact, and "coupled" may indicate that elements cooperate or interact, but that they may or may not be in direct physical or electrical contact. Furthermore, when used in connection with embodiments of the present disclosure, terms such as "comprising," "including," and "having" are synonymous. Terms modified by the word "substantially" include placement, orientation, spacing, or position that differs slightly from the meaning of the unmodified term. For example, the central axis of a magnetic plug substantially coaxially aligned with a through-hole may be offset from the central axis of the through-hole by a few degrees. In another example, a feature of a substrate assembly, such as a feedthrough width, that is described as having substantially recited dimensions may vary within a few percent of the recited dimensions.

[0008]

[0024] It will be understood that in the examples further described and shown below, the drawings may not be drawn to scale and may not include all possible layers and / or circuit components. Additionally, while certain drawings show transistor designs with source / drain regions and electrodes having orthogonal boundaries (within + / - 5 or 10 degrees of the perpendicular), it will be understood that embodiments of the present invention may achieve such boundaries in a substantially orthogonal manner (e.g., within + / - 5 or 10 degrees of the perpendicular) due to the fabrication methods used to create such devices or for other reasons.

[0009]

[0025] Reference is now made to the drawings, which are not necessarily drawn to scale, and in which the same or similar numbers may be used to indicate the same or similar parts in different drawings. The use of the same or similar numbers in different drawings does not necessarily mean that all drawings containing the same or similar numbers constitute a single or the same embodiment. Like numbers with different suffixes may represent different instances of like components. The drawings illustrate generally, by way of example, but not by way of limitation, various embodiments discussed in the present specification.

[0010]

[0026] In the following description, for purposes of explanation, numerous specific details are set forth to provide a thorough understanding thereof. However, it will be apparent that novel embodiments may be practiced without these specific details. In other instances, well-known structures and devices are shown in block diagram form to facilitate explanation. It is intended to cover all modifications, equivalents, and alternatives within the scope of the claims.

[0011]

[0027] As used in this case, The phrase "located on," in the context of a "first layer or component" that is located on a "second layer or component," means that the "first layer or component" is either directly physically attached to the "second layer or component" (with no layers or components between the "first layer or component" and the "second layer or component") or is physically attached to the "second layer or component" with one or more intervening layers or components.

[0012]

[0028] As used herein, the term "adjacent" refers to layers or components that are in physical contact with one another. That is, there are no layers or components between the referenced adjacent layers or components. For example, layer X adjacent to layer Y refers to the layer that is in physical contact with layer Y.

[0013]

[0029] 1-3, in one embodiment, integrated circuit package 100 includes a substrate 102, one or more build-up layers 104, an EIC die 108 attached to build-up layer 104, a PIC die 114 attached to substrate 102, an EIC die 112 attached to PIC die 114, and a bridge die 110 attached to a shelf 106 defined in build-up layer 104. Bridge die 110 can be connected to substrate 102, EIC die 108, and EIC die 112. FIG. 1 illustrates a perspective view of integrated circuit package 100, FIG. 2 illustrates a top view of integrated circuit package 100, and FIG. 3 illustrates a cross-sectional view of one embodiment of integrated circuit package 100.

[0014]

[0030] In the exemplary embodiment, traces 314 are defined in substrate 102. Traces 314 carry power signals for PIC die 114 and, in some embodiments, also carry power signals for EIC die 112 and / or EIC die 108. In the exemplary embodiment, cavities 310 are defined in build-up layer 104 to form shelves 106 on which bridge die 110 is mounted. Trace and via stacks 308 defined in build-up layer 104 connect traces 314 to pads 306 in build-up layer 104. Pads 306 in build-up layer 104 are connected to pads 306 on bridge die 110. Pads 306 on build-up layer 104 and bridge die 110 may be connected by, for example, solder bumps 312, hybrid bonds, and / or the like. Pads 306 on the bottom of the bridge die 110 are connected to pads 306 on the top of the bridge die 110 by through-silicon vias 304. Pads 306 on the top of the bridge die 110 are connected to pads 306 on the bottom of the EIC die 112 by solder bumps 312, hybrid bonds, etc. Traces on the EIC die 112 connect pads 306 on the bridge die 110 to pads 306 on the PIC die 114. Pads 306 of the EIC die 112 on the PIC die 114 are connected to pads 306 on the PIC die 114 via solder bumps 312, hybrid bonds, etc.

[0015]

[0031] In this manner, power can be delivered from the substrate 102, through the build-up layers 104, through the bridge die 110, through the EIC die 112, and to the PIC die 114. It should be understood that alternate paths for power delivery may require longer trace lengths, for example, in the EIC die 108. In some embodiments, the edges 302 of the build-up layers 104 may be slightly angled, and / or the power vias and / or traces may be limited by being within a lateral distance of, for example, 100-500 micrometers from the PIC die 112. In contrast, the through-silicon vias 304 in the bridge die 110 may be within a lateral distance of, for example, 10-80 micrometers from the edge of the PIC die 114, resulting in a shorter path length for the power signal, better power transfer integrity, and less parasitic losses.

[0016]

[0032] An exemplary substrate 102 is glass, such as silicon dioxide glass. In other embodiments, the substrate 102 may be made of any suitable material, which may be crystalline, non-crystalline, amorphous, etc., such as fused silicon, borosilicate, sapphire, or yttrium aluminum garnet. The glass substrate 102 may be, for example, aluminosilicate glass, borosilicate glass, aluminoborosilicate glass, silica, or fused silica. The glass substrate 102 may include one or more additives, such as Al2O3, BO3, MgO, CaO, SrO, BaO, SnO2, Na2O, KO, SrO, PO3, ZrO2, Li2O, Ti, and Zn. The glass substrate 102 may include silicon and oxygen, as well as any one or more of aluminum, boron, magnesium, calcium, barium, tin, sodium, potassium, strontium, phosphorus, zirconium, lithium, titanium, and zinc. The glass substrate 102 may include at least 20-40 weight percent silicon, at least 20-40 weight percent oxygen, and at least 5 weight percent aluminum. For example, some embodiments of the glass substrate 102 may include, for example, at least 20-23 weight percent silicon and at least 20-26 weight percent oxygen.

[0017]

[0033] In other embodiments, the substrate 102 may be any suitable material, such as a ceramic substrate or an organic substrate. In some embodiments, the substrate 102 may be embodied as a printed circuit board made from ceramic, organic materials including fiberglass and resins, such as FR-4, and / or ceramic. The substrate 102 may have any suitable length or width, such as 10-500 millimeters. The substrate 102 may have any suitable thickness, such as 0.2-5 millimeters. The substrate 102 may support additional components, such as additional photonic or electronic integrated circuit components, processor units, memory devices, accelerator devices, etc., in addition to the build-up layers 104, EIC dies 108, 112, bridge die 110, and PIC die 114.

[0018]

[0034] The cavity 310 and the shelf 106 may be formed in any suitable manner. In an exemplary embodiment, the cavity 310 is formed by removing material from the build-up layer 104, for example, by using a mechanical drill, a laser drill, wet etching, dry etching, or the like. The height of the build-up layer 104 may be any suitable value, such as 5-500 micrometers. The height of the shelf 106 may be any suitable value, such as 3-300 micrometers. It should be understood that the smaller height of the shelf 106 relative to the rest of the build-up layer 104 may allow the trace and via stack 308 to be closer to the edge of the PIC die 114 than elsewhere in the build-up layer 104. The shelf 106 allows the bridge die 110 to be positioned at a different height and / or for different thicknesses of the bridge die 110 to be used.

[0019]

[0035] The PIC die 114 may be made of any suitable material, such as silicon. In an exemplary embodiment, a waveguide is defined within the PIC die 114. The waveguide may be a silicon waveguide embedded in a silicon oxide cladding. The PIC die 114 may include any suitable number of waveguides, such as 1-1,024. In an exemplary embodiment, the waveguide within the PIC die 114 is an edge-coupled waveguide. In other embodiments, the waveguide may be vertically coupled from the PIC die 114. In some embodiments, the PIC die 114 may be embodied as or include, for example, indium phosphide, gallium arsenide, lithium niobate, silicon nitride, chalcogenides, and / or the like.

[0020]

[0036] The PIC die 114 is configured to generate, detect, and / or manipulate light. The PIC die 114 may include active or passive optical elements such as splitters, couplers, filters, optical amplifiers, lasers, photodetectors, modulators, routers, etc. The PIC die 114 may operate at any suitable wavelength, such as 400-2,000 nanometers. In an exemplary embodiment, the PIC die 114 operates, for example, around 1,200-1,400 nanometers.

[0021]

[0037] The EIC die 108 and / or 112 may include any suitable electronic integrated circuit components, such as resistors, capacitors, inductors, transistors, etc. The EIC die 108 and / or 112 may include any suitable analog and / or digital circuitry, such as a processor, memory, an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), etc. In an exemplary embodiment, the EIC die 108 may be embodied as an xPU, such as a central processing unit or a graphics processing unit, and the EIC die 112 may be embodied as or otherwise include circuitry that drives components on the PIC die 114, such as lasers and modulators, and / or circuitry that receives signals from components on the PIC die 114, such as photodetectors. The EIC die 112 may use the PIC die 114 to communicate using optical signals with other dies within the same package 100, other integrated circuit packages, other computing devices, etc. In some embodiments, the integrated circuit package 100 may be embodied as a router, a switch, a network interface controller, and / or the like. In such an embodiment, EIC die 108 and / or 112 may include network interface controller circuitry for processing, parsing, routing, etc., network packets sent and received by integrated circuit package 100.

[0022]

[0038] The EIC die 108 is attached to the build-up layers 104. The EIC die 108 is connected to the build-up layers 104 and the substrate 102 via pads 306 and / or solder bumps 312. The pads 306 and / or solder bumps 312 may be used to transmit and receive signals between the EIC die 108 and the substrate 102, to provide power to the EIC die 108, etc. The substrate 102 may provide various electrical connections. For example, the substrate 102 may include a redistribution layer on the bottom of the substrate 102 and / or a redistribution layer on top of the substrate 102, which may be embodied as the build-up layers 104.

[0023]

[0039] The bridge die 110 provides interconnect circuitry for connection between the EIC dies 108, 112 and / or the substrate 102. The bridge die 110 may be embodied, for example, as an embedded multi-die interconnect bridge (EMIB) or an omnidirectional interconnect (ODI). The bridge die 110 may carry power and / or data signals to, from, or between any suitable combination of the EIC dies 108, 112 and the substrate 102. For example, power may be provided from the substrate 102 through the bridge die 110 and the EIC die 112 to the PIC die 114, and data signals may be sent between the EIC die 108 and the PIC die 114 through the bridge die 110 and the EIC die 112. Bridge die 110 may include any suitable number of power and / or data signal pads 306 connected to EIC die 108, EIC die 112, build-up layer 104, or other components, e.g., 1-1,024 pads 306 each.

[0024]

[0040] In some embodiments, bridge die 110 may include thermal plugs or thermal vias to aid in heat removal. In some embodiments, some or all of through-silicon vias 304 may act as thermal vias as well as conductive power path vias.

[0025]

[0041] 4 , in one embodiment, integrated circuit package 400 includes substrate 102, one or more build-up layers 104, an EIC die 108 attached to build-up layer 104, a PIC die 114 attached to substrate 102, an EIC die 112 attached to PIC die 114, and a bridge die 110 attached to substrate 102. The various components of integrated circuit package 400 may be the same or similar to those of integrated circuit package 100 or other integrated circuit packages described herein, and detailed descriptions thereof will not be repeated for clarity. In integrated circuit package 400, bridge die 110 is directly attached to substrate 102. Attaching bridge die 110 directly to substrate 102 can, in some embodiments, provide certain advantages, such as shorter overall trace lengths for power signals to PIC die 114.

[0026]

[0042] 4, the PIC die 114 may include through-silicon vias 304 (or through-die vias 304 if the PIC die 114 is not a silicon substrate). The through-silicon vias 304 may provide power or data signals from the substrate 102, through the PIC die 114, and to the top surface of the PIC die 114, where components such as lasers, modulators, and amplifiers may be located. The connections provided by the vias 304 may be present instead of or in addition to the vias 304 in the bridge die 110.

[0027]

[0043] Referring now to FIG. 5 , in one embodiment, an integrated circuit package 500 includes a substrate 102, one or more build-up layers 104, an EIC die 108 attached to the build-up layer 104, a PIC die 114 attached to the substrate 102, an input / output (I / O) die 502 attached to the PIC die 114 along with a PIC driver block 504, and a bridge die 110 attached to the substrate 102. The various components of the integrated circuit package 500 may be the same or similar to those of the integrated circuit package 100 or other integrated circuit packages described herein, and detailed descriptions thereof will not be repeated for clarity. The I / O die 502 may include circuitry for performing I / O, such as network interface controller (NIC) circuitry. The I / O die 502 includes a PIC driver block 504 to interface with the PIC die 114.

[0028]

[0044] 6, in one embodiment, integrated circuit package 600 includes substrate 102, PIC die 114 attached to substrate 102, one or more build-up layers 104, a bridge die 110 attached to substrate 102, and an EIC die 108 attached to build-up layer 104, bridge die 110, and PIC die 114. The various components of integrated circuit package 600 may be the same as or similar to integrated circuit package 100 or other integrated circuit packages described herein, and detailed descriptions thereof will not be repeated for clarity. EIC die 108, which may be an xPU, includes PIC driver circuitry 504 to interface with PIC die 114.

[0029]

[0045] Referring now to FIG. 7 , in one embodiment, an integrated circuit package 700 includes a substrate 102, one or more build-up layers 104, an EIC die 108 attached to the build-up layer 104, a bridge die 110 attached to the substrate 102, and a PIC die 114 attached to the bridge die 110. The various components of the integrated circuit package 700 may be the same or similar as those of the integrated circuit package 100 or other integrated circuit packages described herein, and detailed descriptions thereof will not be repeated for clarity. The PIC die 114 may be directly attached to the bridge die 110, as shown. The bridge die 110 may include the PIC driver circuit 504. Additionally or alternatively, the EIC die 108 may include the PIC driver circuit 504. Attaching the PIC die 114 directly to the bridge die 110 may reduce the number of dies within the integrated circuit package 700. Interfaces on the PIC die 114, such as V-grooves, edge-emitting waveguides, and vertical-emitting waveguides, may be on the bottom or top of the PIC die 114, increasing the flexibility of possible placements. In some embodiments, through-die vias may be used to carry signals from the bridge die 110 to the top of the PIC die 114.

[0030]

[0046] 8 and 9, in one embodiment, a transceiver module 800 includes a substrate 102 and one or more build-up layers 104 on the substrate 102. FIG. 8 illustrates a plan view of the transceiver module, and FIG. 9 illustrates a cross-sectional view of the transceiver module 800. An edge connector including one or more pads 802 is attached to the substrate 102. In some embodiments, the edge connector including one or more pads 802 may be attached to one or more build-up layers. An EIC die 804 is attached to the build-up layer 104. The build-up layer 104 defines a cavity 816. A bridge die 110 is attached to the build-up layer 104 within the cavity 816. A PIC die 114 is also attached to the build-up layer 104 within the cavity 816. A receiver EIC die 806 and a transmitter EIC die 808 are attached to the bridge die 110 and the PIC die 114, respectively. A receive fiber attachment unit 810 and a transmit fiber attachment unit 812 are each attached to the PIC die 114, with one or more fibers 814 extending from each of the fiber attachment units 810, 812.

[0031]

[0047] In use, the transceiver module 800 may be plugged or otherwise connected to a communications port of a computing device. The transceiver module 800 may receive electronic data signals and convert them to optical signals transmitted over a fiber 814 connected to a transmit fiber attachment unit 812, and may also receive optical signals over a fiber 814 connected to a receive fiber attachment unit 810. The received optical signals may be amplified by a transimpedance amplifier in the receive EIC die 806. The EIC die 804 may be embodied as a digital signal processor 804 for processing incoming and outgoing signals. The bridge die 110 may be used to provide power and / or data signals to the EIC die 804, the receive EIC die 806, the transimpedance amplifier of the receive EIC die 806, the transmit EIC die 808, etc. The use of the bridge die 110 may reduce the electrical paths between various components, compared to using wire bonding, allowing for the use of smaller form factors. In some embodiments, substrate 102 may include thermal vias, a slug, etc. to aid in heat dissipation. Transceiver module 800 may have any suitable form factor, such as a QSFP-DD having dimensions of 70.86 mm by 16.42 mm, or an OSFP having dimensions of 78.59 mm by 20.65 mm. Transceiver module 800 may include other components not shown, such as a cover, a housing, other electrical or optical components, etc.

[0032]

[0048] Referring now to FIG. 10, in one embodiment, the transceiver module 800 may include separate receive PIC die 1002 and transmit PIC die 1004 rather than a single PIC die 114 for both transmit and receive.

[0033]

[0049] 11 and 12, in one embodiment, an integrated circuit package 1100 includes a substrate 102 and one or more build-up layers 104 on the substrate 102. FIG. 11 illustrates a plan view of the integrated circuit package 1100, and FIG. 12 illustrates a cross-sectional view of the integrated circuit package 1100. A bridge die 110 is attached to the substrate 102, and several EIC dies 108 are attached to the bridge die 1100. The bridge die 1102 includes a photonics layer 1102, such as a silicon photonics layer 1102. The photonics layer 1102 may have similar components and perform similar functions as the PIC die 114 described above. In use, the bridge die 110 may use the photonics layer 1102 to provide optical communication between the various EIC dies 108. In an exemplary embodiment, wavelength division multiplexing may be used to use the same waveguide for communication between the various EIC dies 108. For example, a micro-ring resonator can be used to detect and modulate light at a specific frequency, allowing one EIC die 108 to modulate light that will only be detected by another EIC die 108. The light source for optical communication can be, for example, a hybrid or off-chip laser. The EIC dies 108 can be arranged, for example, in a ring network.

[0034]

[0050] 13, in one embodiment, an integrated circuit package 1300 includes a substrate 102, one or more build-up layers 104, a bridge die 110 mounted on the substrate 102, an EIC die 108 mounted on the build-up layers 104, and an array of micro LED dies 1302 mounted on the bridge die 110. The EIC die 108 may include circuitry to drive the micro LEDs and / or photodetectors on the micro LED dies 1302.

[0035]

[0051] The micro LED die 1302 may be any suitable micro LED, such as a gallium nitride micro LED 1302, a quantum dot LED, a single nanowire LED, or the like. As used herein, a micro LED refers to a light emitting diode having a length and width of its light emitting surface less than 100 micrometers. In some embodiments, the length and / or width of the light emitting surface of the micro LED 1302 may be smaller, e.g., less than 10-50 micrometers. In an exemplary embodiment, the micro LED die 1302 is fabricated on a separate substrate and transferred to the base die, bridge die 110, or other die. In some embodiments, other components, such as a vertical cavity surface emitting laser (VCSEL) or a photodetector, may be used in place of all or part of the micro LED die 1302. In some embodiments, the micro LED die 1302 can be attached to the bridge die 110 and tested as a unit, allowing the bridge die 110 and micro LED die to be integrated into a known good module.

[0036]

[0052] It should be understood that the various features of the various embodiments may be combined together in any suitable combination, for example, any PIC die 114 may include through silicon vias 304, a shelf 106 may be integrated into any embodiment, features of any embodiment may be integrated into a transceiver module 700, etc.

[0037]

[0053] FIG. 14 is a plan view of a wafer 1400 and dies 1402 that may be included (e.g., as any suitable one of dies 108, 110, 112, etc.) in any integrated circuit package 100, 400, 500, etc. disclosed herein. The wafer 1400 may be composed of a semiconductor material and may include one or more dies 1402 having integrated circuit structures formed on the surface of the wafer 1400. The individual dies 1402 may be repeating units of an integrated circuit product including any suitable integrated circuit. After fabrication of the semiconductor product is complete, the wafer 1400 is subjected to a singulation process in which the dies 1402 are separated from one another to yield individual "chips" of the integrated circuit product. The dies 1402 may be any of the dies 108, 110, 112, etc. disclosed herein. Die 1402 may include one or more transistors (e.g., some of transistors 1540 of FIG. 15 , described below), support circuitry for routing electrical signals to the transistors, passive components (e.g., signal traces, resistors, capacitors, or inductors), and / or any other integrated circuit components. In some embodiments, wafer 1400 or die 1402 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM) devices, conductive bridging RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1402. For example, a memory array formed by multiple memory devices may be formed on the same die 1402 as a processor unit (e.g., processor unit 1802 of FIG. 18 ) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.Various of the integrated circuit packages 100, 400, 500, etc. disclosed herein may be manufactured using die-to-wafer assembly techniques, in which any die 108, 110, 112, etc. is attached to a wafer 1400 containing other die 108, 110, 112, etc., and then the wafer 1400 is singulated.

[0038]

[0054] FIG. 15 is a cross-sectional side view of an integrated circuit device 1500 that may be included in any integrated circuit package 100, 400, 500, etc. disclosed herein (e.g., in any die 108, 110, 112, etc.). One or more integrated circuit devices 1500 may be included in one or more dies 1402 (FIG. 14). The integrated circuit device 1500 may be formed on a die substrate 1502 (e.g., wafer 1400 of FIG. 14) or included in a die (e.g., die 1402 of FIG. 14). The die substrate 1502 may be a semiconductor substrate composed of a semiconductor material system, including, for example, an n-type or p-type material system (or a combination of both). The die substrate 1502 may include, for example, a crystalline substrate formed using bulk silicon or a silicon-on-insulator (SOI) substructure. In some embodiments, the die substrate 1502 may be formed using alternative materials, which may or may not be combined with silicon, including, but not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Additional materials classified as II-VI, III-V, or IV may also be used to form the die substrate 1502. While some examples of materials that may form the die substrate 1502 are described herein, any material capable of serving as the basis for the integrated circuit device 1500 may be used. The die substrate 1502 may be part of a singulated die (e.g., die 1402 in FIG. 14 ) or wafer (e.g., wafer 1400 in FIG. 14 ).

[0039]

[0055] The integrated circuit device 1500 may include one or more device layers 1504 disposed on a die substrate 1502. The device layer 1504 may include features of one or more transistors 1540 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed in the die substrate 1502. The transistor 1540 may include, for example, one or more source and / or drain (S / D) regions 1520, a gate 1522 for controlling current flow between the S / D regions 1520, and one or more S / D contacts 1524 for routing electrical signals to / from the S / D regions 1520. The transistor 1540 may include additional features not shown for clarity, such as device isolation regions, gate contacts, etc. The transistor 1540 is not limited to the types and configurations shown in FIG. 15 and may include a wide variety of other types and configurations, such as planar transistors, non-planar transistors, or a combination of both. Non-planar transistors may include FinFET transistors, such as double-gate or tri-gate transistors, and wrap-around or all-around gate transistors, such as nanoribbon, nanosheet, or nanowire transistors.

[0040]

[0056] 16A-16D are simplified perspective views of exemplary planar, FinFET, gate-all-around, and stacked-gate-all-around transistors. The transistors shown in FIGS. 16A-16D are formed in a substrate 1616 having a surface 1608. Isolation regions 1614 separate the source and drain regions of the transistor from other transistors and from a bulk region 1618 of the substrate 1616.

[0041]

[0057] 16A is a perspective view of an exemplary planar transistor 1600 having a gate 1602 that controls the flow of current between a source region 1604 and a drain region 1606. The transistor 1600 is planar in that the source region 1604 and the drain region 1606 are flat with respect to a substrate surface 1608.

[0042]

[0058] Figure 16B is a perspective view of an exemplary FinFET transistor 1620 having a gate 1622 that controls the flow of current between a source region 1624 and a drain region 1626. The transistor 1620 is non-planar in that the source region 1624 and the drain region 1626 include "fins" that extend upward from a substrate surface 1628. Because the gate 1622 encompasses three sides of the semiconductor fin that extends from the source region 1624 to the drain region 1626, the transistor 1620 can be considered a tri-gate transistor. Although Figure 16B shows one source / drain fin extending through the gate 1622, multiple source / drain fins can extend through the gate of a FinFET transistor.

[0043]

[0059] 16C is a perspective view of a gate-all-around (GAA) transistor 1640 having a gate 1642 that controls the flow of current between a source region 1644 and a drain region 1646. Transistor 1640 is non-planar in that source region 1644 and drain region 1646 are elevated from substrate surface 1628.

[0044]

[0060] FIG. 16D is a perspective view of a gate-attached (GAA) transistor 1660 having a gate 1662 that controls current flow between multiple elevated source regions 1664 and multiple elevated drain regions 1666. Transistor 1660 is a stacked gate-attached (GAA) transistor because the gate controls current flow between multiple elevated source / drain regions stacked on top of each other. Transistors 1640 and 1660 are considered gate-all-around transistors because the gate encompasses all sides of the semiconductor portion extending from the source region to the drain region. Transistors 1640 and 1660 may alternatively be referred to as nanowire, nanosheet, or nanoribbon transistors, depending on the width of the semiconductor portion extending through the gate (e.g., widths 1648 and 1668 of transistors 1640 and 1660, respectively).

[0045]

[0061] 15, transistor 1540 may include a gate 1522 formed from at least two layers, a gate dielectric and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or a high-k dielectric material.

[0046]

[0062] High-k dielectric materials may contain elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used in gate dielectrics include, but are not limited to, hafnium oxide, hafnium-silicon oxide, lanthanum oxide, lanthanum-aluminum oxide, zirconium oxide, zirconium-silicon oxide, tantalum oxide, titanium oxide, barium-strontium-titanium oxide, barium-titanium oxide, strontium-titanium oxide, yttrium oxide, aluminum oxide, lead-scandium-tantalum oxide, and lead-zinc niobate. In some embodiments, an annealing process may be performed on the gate dielectric to improve its quality when a high-k material is used.

[0047]

[0063] A gate electrode may be formed on the gate dielectric and may include at least one p-type work function metal or n-type work function metal, depending on whether transistor 1540 is a p-type metal oxide semiconductor (PMOS) transistor or an n-type metal oxide semiconductor (NMOS) transistor. In some implementations, the gate electrode may be composed of a stack of two or more metal layers, where one or more metal layers are work function metal layers and at least one metal layer is a fill metal layer. Additional metal layers, such as barrier layers, may be included for other purposes.

[0048]

[0064] For PMOS transistors, metals that may be used for the gate electrode include, but are not limited to, ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any of the metals described below for NMOS transistors (e.g., for work function tuning). For NMOS transistors, metals that may be used for the gate electrode include, but are not limited to, hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals described above for PMOS transistors (e.g., for work function tuning).

[0049]

[0065] In some embodiments, when viewed as a cross-section of the transistor 1540 along the source-channel-drain direction, the gate electrode may comprise a U-shaped structure with a bottom substantially parallel to the surface of the die substrate 1502 and two sidewalls substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the die substrate 1502 and without sidewalls substantially perpendicular to the top surface of the die substrate 1502. In other embodiments, the gate electrode may comprise a combination of U-shaped and planar / non-U-shaped structures. For example, the gate electrode may comprise one or more U-shaped metal layers formed on one or more flat, non-U-shaped layers.

[0050]

[0066] In some embodiments, a pair of sidewall spacers may be formed on opposite sides of the gate stack, sandwiching the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. Processes for forming sidewall spacers are well known in the art and generally include deposition and etching process steps. In some embodiments, multiple spacer pairs may be used: for example, two, three, or four pairs of sidewall spacers may be formed on opposite sides of the gate stack.

[0051]

[0067] The S / D regions 1520 may be formed in the die substrate 1502 adjacent to the gates 1522 of the individual transistors 1540. The S / D regions 1520 may be formed using, for example, an implantation / diffusion process or an etching / deposition process. In the former process, dopants such as boron, aluminum, antimony, phosphorus, or arsenic may be ion-implanted into the die substrate 1502 to form the S / D regions 1520. An annealing process may follow the ion-implantation process to activate the dopants and further diffuse them into the die substrate 1502. In the latter process, the die substrate 1502 may first be etched to form recesses at the locations of the S / D regions 1520. An epitaxial deposition process may then be performed to fill the recesses with the material used to fabricate the S / D regions 1520. In some implementations, the S / D regions 1520 may be fabricated using silicon alloys such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be in-situ doped with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D regions 1520 may be formed using one or more alternative semiconductor materials, such as germanium or a III-V material or alloy. In further embodiments, one or more layers of metal and / or metal alloy may be used to form the S / D regions 1520.

[0052]

[0068] Electrical signals, such as power and / or input / output (I / O) signals, can be routed to and / or from devices (e.g., transistor 1540) in device layer 1504 through one or more interconnect layers (shown in FIG. 15 as interconnect layers 1506-1510) disposed on device layer 1504. For example, conductive features (e.g., gate 1522 and S / D contacts 1524) in device layer 1504 can be electrically coupled with interconnect structures 1528 in interconnect layers 1506-1510. One or more interconnect layers 1506-1510 can form a metallization stack (also referred to as an "ILD stack") 1519 of integrated circuit device 1500.

[0053]

[0069] Interconnect structures 1528 may be arranged within interconnect layers 1506-1510 to route electrical signals according to a wide variety of designs; in particular, the arrangement is not limited to the particular configuration of interconnect structures 1528 shown in Figure 15. Although a particular number of interconnect layers 1506-1510 are depicted in Figure 15, embodiments of the present disclosure may include integrated circuit devices having more or fewer interconnect layers than depicted.

[0054]

[0070] In some embodiments, the interconnect structures 1528 may include lines 1528a and / or vias 1528b filled with a conductive material, such as metal. The lines 1528a may be arranged to route electrical signals in a plane substantially parallel to the surface of the die substrate 1502 on which the device layer 1504 is formed. For example, the lines 1528a may route electrical signals into and out of the plane of the paper and / or across the plane of the paper. The vias 1528b may be arranged to route electrical signals in a plane substantially perpendicular to the surface of the die substrate 1502 on which the device layer 1504 is formed. In some embodiments, the vias 1528b may electrically couple together the lines 1528a of different interconnect layers 1506-1510.

[0055]

[0071] The interconnect layers 1506-1510 may include a dielectric material 1526 disposed between interconnect structures 1528, as shown in FIG. 15. In some embodiments, the dielectric material 1526 disposed between the interconnect structures 1528 in different ones of the interconnect layers 1506-1510 may have different compositions; in other embodiments, the composition of the dielectric material 1526 between different interconnect layers 1506-1510 may be the same. The device layer 1504 may also include a dielectric material 1526 disposed between the transistor 1540 and the bottom layer of the metallization stack. The dielectric material 1526 included in the device layer 1504 may have a different composition than the dielectric material 1526 included in the interconnect layers 1506-1510; in other embodiments, the composition of the dielectric material 1526 in the device layer 1504 may be the same as the dielectric material 1526 included in any one of the interconnect layers 1506-1510.

[0056]

[0072] A first interconnect layer 1506 (referred to as metal 1 or "M1") may be formed directly on the device layer 1504. In some embodiments, the first interconnect layer 1506 may include lines 1528a and / or vias 1528b, as shown. The lines 1528a of the first interconnect layer 1528 may be coupled to contacts (e.g., S / D contacts 1524) of the device layer 1504. The vias 1506b of the first interconnect layer 1528 can be coupled to lines 1508a of the second interconnect layer 1528.

[0057]

[0073] A second interconnect layer 1508 (referred to as metal 2 or "M2") may be formed directly on the first interconnect layer 1506. In some embodiments, the second interconnect layer 1508 may include vias 1528b to couple lines 1528 of the second interconnect layer 1508 with lines 1528a of the third interconnect layer 1510. Although the lines 1528a and vias 1528b are depicted structurally with lines within individual interconnect layers for clarity, the lines 1528a and vias 1528b may be structurally and / or materially continuous in some embodiments (e.g., filled simultaneously during a dual damascene process).

[0058]

[0074] A third interconnect layer 1510 (referred to as metal 3 or "M3") (and additional interconnect layers, if desired) may be formed contiguous with the second interconnect layer 1508 according to techniques and configurations similar to those described with respect to the second interconnect layer 1508 or the first interconnect layer 1506. In some embodiments, interconnect layers "higher" in the metallization stack 1519 within the integrated circuit device 1500 (i.e., further from the device layer 1504) may be thicker than interconnect layers lower in the metallization stack 1519, with lines 1528a and vias 1528b in the higher interconnect layers being thicker than those in the lower interconnect layers.

[0059]

[0075] The integrated circuit device 1500 may include a solder resist material 1534 (e.g., polyimide or a similar material) and one or more conductive contacts 1536 formed on the interconnect layers 1506-1510. In FIG. 15, the conductive contacts 1536 are shown in the form of bond pads. The conductive contacts 1536 may be electrically coupled to the interconnect structure 1528 and configured to route electrical signals from the transistor 1540 to an external device. For example, solder bonds may be formed on one or more of the conductive contacts 1536 to mechanically and / or electrically couple an integrated circuit die including the integrated circuit device 1500 to another component (e.g., a printed circuit board). The integrated circuit device 1500 may include additional or alternative structures for routing electrical signals from the interconnect layers 1506-1510; for example, the conductive contacts 1536 may include other similar features (e.g., posts) that route electrical signals to an external component. The conductive contacts 1536 may function as conductive contacts 306 or 802, as desired.

[0060]

[0076] In some embodiments in which integrated circuit device 1500 is a double-sided die, integrated circuit device 1500 may include another metallization stack (not shown) on the opposite side of device layer 1504. This metallization stack may include multiple interconnect layers as described above with reference to interconnect layers 1506-1510 to provide conductive paths (e.g., including conductive lines and vias) between device layer 1504 and additional conductive contacts (not shown) on the opposite side of integrated circuit device 1500 from conductive contact 1536. These additional conductive contacts may function as conductive contacts 306 or 802, as desired.

[0061]

[0077] In other embodiments in which integrated circuit device 1500 is a double-sided die, integrated circuit device 1500 may include one or more through silicon vias (TSVs) that extend through die substrate 1502; these TSVs may contact device layer 1504 and may provide a conductive path between device layer 1504 and additional conductive contacts (not shown) on the opposite side of integrated circuit device 1500 from conductive contact 1536. These additional conductive contacts may function as conductive contacts 306 or 802, as needed. In some embodiments, TSVs extending through the substrate may be used to route power and ground signals from the conductive contacts on the opposite side of integrated circuit device 1500, from conductive contact 1536 to transistor 1540 and any other components integrated on die 1500, and metallization stack 1519 may be used to route I / O signals from conductive contact 1536 to transistor 1540 and any other components integrated on die 1500.

[0062]

[0078] Multiple integrated circuit devices 1500 can be stacked with one or more TSVs in each stacked device providing a connection between one device and any other device in the stack. For example, one or more high-bandwidth memory (HBM) integrated circuit dies can be stacked on top of a base integrated circuit die, with the TSVs in the HBM die providing a connection between each HBM and the base integrated circuit die. Conductive contacts can provide additional connections between adjacent integrated circuit dies in the stack. In some embodiments, the conductive contacts can be fine-pitch solder bumps (microbumps).

[0063]

[0079] FIG. 17 is a cross-sectional side view of an integrated circuit device assembly 1700, which may include any of the integrated circuit packages 100, 400, 500, etc. disclosed herein. In some embodiments, the integrated circuit device assembly 1700 may be the integrated circuit package 100, 400, 500, etc. The integrated circuit device assembly 1700 includes multiple components disposed on a circuit board 1702 (which may be a motherboard, system board, mainboard, etc.). The integrated circuit device assembly 1700 includes components disposed on a first side 1740 of the circuit board 1702 and an opposing second side 1742 of the circuit board 1702; generally, components may be disposed on one or both sides 1740 and 1742. Any of the integrated circuit components described below with reference to the integrated circuit device assembly 1700 may take the form of any suitable embodiment of the integrated circuit package 100, 400, 500, etc. disclosed herein.

[0064]

[0080] In some embodiments, the circuit board 1702 may be a printed circuit board (PCB) including multiple metal (or interconnect) layers separated from each other by layers of dielectric material and interconnected by conductive vias. Each metal layer includes conductive traces. Any one or more metal layers may be formed with a desired circuit pattern to route electrical signals (optionally with other metal layers) between components coupled to the circuit board 1702. In other embodiments, the circuit board 1702 may be a non-PCB substrate. In some embodiments, the circuit board 1702 may be embodied as or otherwise include, for example, the substrate 102. The integrated circuit device assembly 1700 shown in FIG. 17 includes a package-on-interposer structure 1736 coupled to a first surface 1740 of the circuit board 1702 by a coupling component 1716. The coupling components 1716 may electrically and mechanically couple the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (as shown in FIG. 17), pins (e.g., as part of a pin grid array (PGA)), contacts (e.g., as part of a land grid array (LGA)), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure. The coupling components 1716 may function as the coupling components shown or described for any of the substrate assemblies or substrate assembly components described herein, as appropriate.

[0065]

[0081] Package-on-interposer structure 1736 may include an integrated circuit component 1720 coupled to interposer 1704 by a coupling component 1718. Coupling component 1718 may take any form suitable for the application, such as those described above with reference to coupling component 1716. While a single integrated circuit component 1720 is shown in FIG. 17, multiple integrated circuit components may be coupled to interposer 1704; in fact, additional interposers may be coupled to interposer 1704. Interposer 1704 may provide an intervening substrate used to bridge circuit board 1702 and integrated circuit component 1720.

[0066]

[0082] Integrated circuit component 1720 may be a packaged or unpackaged integrated circuit product including one or more integrated circuit dies (e.g., die 1402 of FIG. 14 , integrated circuit device 1500 of FIG. 15 ) and / or one or more other suitable components. A packaged integrated circuit component comprises one or more integrated circuit dies attached to a package substrate, and the integrated circuit dies and package substrate are encapsulated in a casing material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit component 1720, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. The solder bumps allow the die to be directly attached to interposer 1704. Integrated circuit component 1720 may include one or more computing system components, such as one or more processor units (e.g., a system-on-chip (SoC), processor core, graphics processor unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, integrated circuit component 1720 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0067]

[0083] In embodiments in which integrated circuit component 1720 includes multiple integrated circuit dies, the dies may be of the same type (a homogeneous multi-die integrated circuit component) or two or more different types (a heterogeneous multi-die integrated circuit component). A multi-die integrated circuit component may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0068]

[0084] In addition to including one or more processor units, integrated circuit component 1720 may include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controllers, or memory controllers. Any of these additional components may be located on the same integrated circuit die as the processor unit or on one or more integrated circuit dies separate from the integrated circuit die that includes the processor unit. These separate integrated circuit dies may be referred to as "chiplets." In embodiments where the integrated circuit component includes multiple integrated circuit dies, interconnection between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (e.g., Intel® Embedded Multi-Die Interconnect Bridges (EMIBs)), or a combination thereof.

[0069]

[0085] In general, interposer 1704 may spread connections to a wider pitch or reroute connections to different connections. For example, interposer 1704 may couple integrated circuit component 1720 to a set of ball grid array (BGA) conductive contacts of coupling component 1716 for coupling to circuit board 1702. In the embodiment shown in FIG. 17 , integrated circuit component 1720 and circuit board 1702 are attached to the front and back sides of interposer 1704; in other embodiments, integrated circuit component 1720 and circuit board 1702 may be attached to the same side of interposer 1704. In some embodiments, more than two components may be interconnected by interposer 1704.

[0070]

[0086] In some embodiments, interposer 1704 may be formed as a PCB, including multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, interposer 1704 may be formed from a polymeric material such as epoxy, glass-reinforced epoxy, epoxy with inorganic fillers, ceramic material, or polyimide. In some embodiments, interposer 1704 may be formed from alternative rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other III-V and IV materials. The interposer 1704 may include metal interconnects 1708 and vias 1710, including, but not limited to, through-hole vias 1710-1 (extending from the first surface 1750 of the interposer 1704 to the second surface 1754 of the interposer 1704), blind vias 1710-2 (extending from the first surface 1750 or the second surface 1754 of the interposer 1704 to an internal metal layer), and buried vias 1710-3 (connecting internal metal layers).

[0071]

[0087] In some embodiments, the interposer 1704 may include a silicon interposer. Through-silicon vias (TSVs) extending through the silicon interposer may connect connections on a first side of the silicon interposer to an opposite second side of the silicon interposer. In some embodiments, the interposer 1704 including a silicon interposer may further include one or more routing layers for routing connections on the first side of the interposer 1704 to the opposite second side of the interposer 1704.

[0072]

[0088] The interposer 1704 may further include embedded devices 1714, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on the interposer 1704. The package-on-interposer structure 1736 may take the form of any package-on-interposer structure known in the art.

[0073]

[0089] Integrated circuit device assembly 1700 can include an integrated circuit component 1724 coupled to a first surface 1740 of circuit board 1702 by a coupling component 1722. Coupling component 1722 can take the form of any of the embodiments described above with reference to coupling component 1716, and integrated circuit component 1724 can take the form of any of the embodiments described above with reference to integrated circuit component 1720.

[0074]

[0090] 17 includes a package-on-package structure 1734 coupled to a second surface 1742 of a circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include an integrated circuit component 1726 and an integrated circuit component 1732 coupled to one another by a coupling component 1730, such that the integrated circuit component 1726 is disposed between the circuit board 1702 and the integrated circuit component 1732. The coupling components 1728 and 1730 may take the form of any embodiment of the coupling component 1716 described above, and the integrated circuit components 1726 and 1732 may take the form of any embodiment of the integrated circuit component 1720 described above. The package-on-package structure 1734 may be configured according to any package-on-package structure known in the art.

[0075]

[0091] FIG. 18 is a block diagram of an exemplary electrical device 1800 that may include one or more integrated circuit packages 100, 400, 500, etc., as disclosed herein. For example, any suitable components of the electrical device 1800 may include one or more of the integrated circuit device assemblies 1700, integrated circuit components 1720, integrated circuit devices 1500, or integrated circuit dies 1402 disclosed herein and may be disposed in any of the integrated circuit packages 100, 400, 500, etc., as disclosed herein. While FIG. 18 illustrates numerous components as being included in the electrical device 1800, any one or more of these components may be omitted or added depending on the application. In some embodiments, all or some of the components included in the electrical device 1800 may be mounted on one or more motherboards, mainboards, or system boards. In some embodiments, one or more of these components are fabricated in a single system-on-chip (SoC) die.

[0076]

[0092] 18 , but the electrical device 1800 may include interface circuitry for coupling to one or more components. For example, the electrical device 1800 may not include a display device 1806, but may include display device interface circuitry (e.g., connectors and driver circuitry) to which the display device 1806 may be coupled. In another set of examples, the electrical device 1800 may not include an audio input device 1824 or an audio output device 1808, but may include audio input or output device interface circuitry (e.g., connectors and support circuitry) to which the audio input device 1824 or the audio output device 1808 may be coupled.

[0077]

[0093] The electrical device 1800 may include one or more processor units 1802 (e.g., one or more processor units). As used herein, the terms “processor unit,” “processing unit,” or “processor” may refer to any device or portion of a device that processes electronic data from registers and / or memory and converts the electronic data into other electronic data that can be stored in registers and / or memory. The processor unit 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processor units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controller cryptoprocessors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processor unit. Therefore, the processor unit may be called an xPU (or xPU).

[0078]

[0094] The electrical device 1800 may include memory 1804, which itself may include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogenide-based phase-change non-voltage memory), solid-state memory, and / or a hard drive. In some embodiments, the memory 1804 may include memory located on the same integrated circuit die as the processor unit 1802. This memory may be used as cache memory (e.g., level 1 (L1), level 2 (L2), level 3 (L3), level 4 (L4), last level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetization random access memory (STT-MRAM).

[0079]

[0095] In some embodiments, electrical device 1800 may include one or more processor units 1802 that are heterogeneous or asymmetric with respect to other processor units 1802 within electrical device 1800. There may be various differences between processing units 1802 within a system with respect to a spectrum of performance metrics, including architectural characteristics, microarchitectural characteristics, thermal characteristics, power consumption characteristics, etc. These differences may manifest effectively as asymmetries or heterogeneities between processor units 1802 within electrical device 1800.

[0080]

[0096] In some embodiments, electrical device 1800 may include a communications component 1812 (e.g., one or more communications components). For example, communications component 1812 may manage wireless communications for the transfer of data to and from electrical device 1800. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communications channels, etc., that are capable of communicating data through the use of modulated electromagnetic radiation over a non-solid medium. The term "wireless" does not necessarily imply that the associated device does not include any wires, although in some embodiments it may not.

[0081]

[0097] Communications component 1812 may implement any of a number of wireless standards or protocols, including, but not limited to, Institute of Electrical and Electronics Engineers (IEEE) standards including Wi-Fi (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), the Long Term Evolution (LTE) project and any amendments, updates, and / or revisions (e.g., Advanced LTE project, Ultra Mobile Broadband (UMB) project (also known as "3GPP2"), etc.). IEEE 802.16-compatible broadband wireless access (BWA) networks are commonly referred to as WiMAX networks, an acronym that stands for "Worldwide Interoperability for Microwave Access," which is a certification mark for products that have passed compliance and interoperability testing to the IEEE 802.16 standard. The communications component 1812 may operate according to a Global System for Mobile Communications (GSM), General Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE network. The communications component 1812 may operate according to a GSM Evolution High Speed ​​Data Exchange (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communications component 1812 may operate according to code division multiple access (CDMA), time division multiple access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO), and their derivatives, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communications component 1812 may operate according to other wireless protocols. Electrical device 1800 may include an antenna 1822 for facilitating wireless communications and / or receiving other wireless communications (such as AM or FM radio transmissions).

[0082]

[0098] In some embodiments, the communications component 1812 may manage wired communications, such as electrical, optical, or any other suitable communications protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, the communications component 1812 may include multiple communications components. For example, a first communications component 1812 may be dedicated to short-range wireless communications, such as Wi-Fi or Bluetooth, and a second communications component 1812 may be dedicated to long-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or others. In some embodiments, the first communications component 1812 may be dedicated to wireless communications, and the second communications component 1812 may be dedicated to wired communications.

[0083]

[0099] Electrical device 1800 may include battery / power circuitry 1814. Battery / power circuitry 1814 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1800 to an energy source separate from electrical device 1800 (e.g., AC line power).

[0084]

[0100] Electrical device 1800 may include a display device 1806 (or corresponding interface circuitry as described above), which may include one or more embedded or wired or wirelessly connected external visual indicators, such as a heads-up display, a computer monitor, a projector, a touchscreen display, a liquid crystal display (LCD), a light-emitting diode display, or a flat panel display.

[0085]

[0101] Electrical device 1800 may include audio output device 1808 (or corresponding interface circuitry as described above), which may include any embedded or wired or wirelessly connected external device that generates an audible indicator, such as a speaker, headset, or earphones.

[0086]

[0102] The electrical device 1800 may include an audio input device 1824 (or corresponding interface circuitry, as described above). The audio input device 1824 may include any embedded, wired, or wirelessly connected device that generates signals representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a Musical Instrument Digital Interface (MIDI) output). The electrical device 1800 may include a global navigation satellite system (GNSS) device 1818 (or corresponding interface circuitry, as described above), such as a global positioning system (GPS) device. The GNSS device 1818 may communicate with a satellite-based system and may determine the geolocation of the electrical device 1800 based on information received from one or more GNSS satellites, as known in the art.

[0087]

[0103] The electrical device 1800 may include other output devices 1810 (or corresponding interface circuitry as described above). Examples of other output devices 1810 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0088]

[0104] The electrical device 1800 may include other input devices 1820 (or corresponding interface circuitry as described above). Examples of other input devices 1820 may include an accelerometer, a gyroscope, a compass, an image capture device (e.g., a monocular or binocular camera), a trackball, a trackpad, a touchpad, a keyboard, a cursor control device (such as a mouse), a stylus, a touchscreen, a proximity sensor, a microphone, a bar code reader, a quick response (QR) code reader, an electrocardiogram (ECG) sensor, a photoplethysmogram (PPG) sensor, a galvanic skin response sensor, any other sensor, or a radio frequency identification (RFID) reader.

[0089]

[0105] Electrical device 1800 may have any desired form factor and may be, for example, a handheld or mobile electrical device (e.g., a cellular phone, a smart phone, a mobile Internet device, a music player, a tablet computer, a laptop computer, a 2-in-1 enabled computer, a portable all-in-one computer, a netbook computer, an ultrabook computer, a personal digital assistant (PDA), an ultra-mobile personal computer, a portable gaming console, etc.), a desktop electrical device, a server, a rack-level computing solution (e.g., a blade, tray, or sled computing system), a workstation or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a stationary gaming console, a smart television, a vehicle control unit, a digital camera, a digital video recorder, a wearable electrical device, or an embedded computing system (e.g., a computing system that is part of a vehicle, a smart appliance, a consumer electronic product or device, or manufacturing equipment). In some embodiments, electrical device 1800 may be any other electronic device that processes data. In some embodiments, electrical device 1800 may have multiple separate physical components. Given the range of devices that electrical device 1800 may be manifested as in various embodiments, in some embodiments electrical device 1800 may be referred to as a computing device or computing system.

[0090]

[0106] Example Illustrative examples of the presently disclosed technology are provided below. Embodiments of the technology may include any one or more, and any combination, of the examples described below.

[0091]

[0107] Example 1 includes an apparatus, the apparatus comprising: substrate and; one or more build-up layers adjacent to the substrate; a first electronic integrated circuit (EIC) die attached to one or more build-up layers; a photonic integrated circuit (PIC) die attached to a substrate; a second EIC die attached to the PIC die; a bridge die electrically coupled to the substrate, the first EIC die, and the second EIC die; the bridge die having through-silicon vias defined therein, the through-silicon vias electrically coupling pads defined on the substrate to pads defined on the second EIC die, the pads defined on the second EIC die being electrically coupled to the PIC die.

[0092]

[0108] Example 2 includes the subject matter of example 1, wherein the through silicon vias include conductive power paths.

[0093]

[0109] Example 3 includes the subject matter of any of examples 1 and 2, wherein a lateral distance between the PIC die and the bridge die is less than 50 micrometers.

[0094]

[0110] Example 4 includes the subject matter of any of Examples 1-3, wherein the one or more build-up layers have a first surface, a first EIC die attached to the first surface, a cavity defined in the one or more build-up layers, a second surface defined in the one or more build-up layers at an end of the cavity, and a bridge die attached to the second surface.

[0095]

[0111] Example 5 includes the subject matter of any of Examples 1-4, wherein the bridge die is attached to the substrate.

[0096]

[0112] Example 6 includes the subject matter of any of Examples 1-5, wherein the device is a transceiver module, the first EIC die includes a digital signal processor die, and one or more optical fibers are coupled to the PIC die.

[0097]

[0113] Example 7 includes the subject matter of any of Examples 1-6, wherein the substrate has a solid glass layer that is rectangular in plan view.

[0098]

[0114] Example 8 includes the subject matter of any of Examples 1-7, wherein the PIC die includes a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

[0099]

[0115] Example 9 includes the subject matter of any of Examples 1-8, wherein the second EIC is an input / output EIC die, and the input / output EIC die includes a PIC driver circuit.

[0100]

[0116] Example 10 includes the subject matter of any of examples 1-9, wherein the bridge die is for carrying data signals between the first EIC die and the second EIC die.

[0101]

[0117] Example 11 includes an apparatus, the apparatus comprising: substrate and; one or more build-up layers adjacent to the substrate; a photonic integrated circuit (PIC) die attached to a substrate; an electronic integrated circuit (EIC) die attached to one or more build-up layers and a PIC die; a bridge die electrically coupled to the substrate and the EIC die; the bridge die having a through-silicon via defined therein, the through-silicon via electrically coupling a pad defined on the substrate to a pad defined on the EIC die, the pad defined on the EIC die being electrically coupled to the PIC die.

[0102]

[0118] Example 12 includes the subject matter of example 11, wherein the bridge die is configured to provide power to the PIC die from the substrate through a through silicon via.

[0103]

[0119] Example 13 includes the subject matter of any of examples 11 and 12, wherein the lateral distance between the PIC die and the bridge die is less than 50 micrometers.

[0104]

[0120] Example 14 includes the subject matter of any of Examples 11-13, wherein the bridge die is attached to the substrate.

[0105]

[0121] Example 15 includes the subject matter of any of Examples 11-14, wherein the device is a transceiver module, the EIC die includes a digital signal processor die, and the PIC die is coupled to one or more optical fibers.

[0106]

[0122] Example 16 includes the subject matter of any of Examples 11-15, wherein the substrate has a solid layer of glass that is rectangular in plan view.

[0107]

[0123] Example 17 includes the subject matter of any of Examples 11-16, wherein the PIC die includes a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

[0108]

[0124] Example 18 includes an apparatus, the apparatus comprising: substrate and; one or more build-up layers adjacent to the substrate; an electronic integrated circuit (EIC) die attached to one or more build-up layers; a bridge die electrically coupled to the substrate and the EIC die; a photonic integrated circuit (PIC) die attached to the bridge die; the bridge die having a through silicon via defined therein, the through silicon via electrically coupling a pad defined on the substrate to a pad defined on the PIC die.

[0109]

[0125] Example 19 includes the subject matter of example 18, wherein the PIC die has a through silicon via defined therein, the through silicon via of the PIC die being connected to a pad defined on the PIC die.

[0110]

[0126] Example 20 includes the subject matter of any of examples 18 and 19, wherein the bridge die includes a PIC driver circuit that drives one or more components of the PIC die.

[0111]

[0127] Example 21 includes the subject matter of any of examples 18-20, wherein the bridge die is configured to provide power to the PIC die from the substrate through the through silicon via.

[0112]

[0128] Example 22 includes the subject matter of any of Examples 18-21, wherein the bridge die is attached to the substrate.

[0113]

[0129] Example 23 includes the subject matter of any of Examples 18-22, wherein the device is a transceiver module, the EIC die includes a digital signal processor die, and one or more optical fibers are coupled to the PIC die.

[0114]

[0130] Example 24 includes the subject matter of any of Examples 18-23, wherein the substrate has a solid glass layer that is rectangular in plan view.

[0115]

[0131] Example 25 includes the subject matter of any of Examples 18-24, wherein the PIC die includes a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

[0116]

[0132] Example 26 includes an apparatus, the apparatus comprising: substrate and; one or more build-up layers adjacent to the substrate; a bridge die electrically coupled to the substrate, the bridge die including a silicon photonics layer; a first electronic integrated circuit (EIC) die attached to one or more build-up layers and a bridge die; and a second EIC die attached to one or more build-up layers and a bridge die.

[0117]

[0133] Example 27 includes the subject matter of example 26, wherein the first EIC die has a PIC driver circuit that generates an optical signal for the PIC die that is sent to the second EIC die, and the second EIC die has a PIC driver circuit that receives the optical signal.

[0118]

[0134] Example 28 includes the subject matter of any of Examples 26 and 27, wherein a waveguide is defined in the silicon photonics layer, and the silicon photonics layer has a plurality of microring resonators coupled to the waveguide, each microring resonator of the plurality of microring resonators resonating at a different wavelength channel.

[0119]

[0135] Example 29 includes the subject matter of any of Examples 26-28, wherein the bridge die is configured to provide power from the substrate to the silicon photonics layer through through-silicon vias defined in the bridge die.

[0120]

[0136] Example 30 includes the subject matter of any of Examples 26-29, wherein the bridge die is attached to the substrate.

[0121]

[0137] Example 31 includes the subject matter of any of Examples 26-30, wherein the substrate has a solid glass layer that is rectangular in plan view.

[0122]

[0138] Example 32 includes the subject matter of any of Examples 26-31, wherein the silicon photonics layer includes a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

[0123]

[0139] Example 33 includes an apparatus, the apparatus comprising: substrate and; one or more build-up layers adjacent to the substrate; an electronic integrated circuit (EIC) die attached to one or more build-up layers; a bridge die electrically coupled to the substrate and the EIC die; Multiple micro LED dies attached to a bridge die; the bridge die having a through-silicon via defined therein, the through-silicon via electrically coupling a pad defined on the substrate to a pad defined on one of the plurality of micro LED dies.

[0124]

[0140] Example 34 includes the subject matter of example 33, wherein the bridge die is configured to provide power to the plurality of micro LED dies from the substrate through through silicon vias.

[0125]

[0141] Example 35 includes the subject matter of any of Examples 33 and 34, wherein the bridge die is attached to the substrate.

[0126]

[0142] Example 36 includes the subject matter of any of Examples 33-35, wherein the substrate has a solid glass layer that is rectangular in plan view.

[0127]

[0143] Example 37 includes an apparatus, the apparatus comprising: substrate and; one or more build-up layers adjacent to the substrate; an electronic integrated circuit (EIC) die mounted on one or more build-up layers; Photonic Integrated Circuit (PIC) die and; a bridge die, the bridge die having a through-silicon via defined therein; and means for supplying power to the PIC die from the substrate through a through silicon via.

[0128]

[0144] Example 38 includes the subject matter of example 37, wherein the bridge die is configured to provide power from the substrate to the PIC die through a through silicon via.

[0129]

[0145] Example 39 includes the subject matter of any of Examples 37 and 38, wherein the lateral distance between the PIC die and the bridge die is less than 50 micrometers.

[0130]

[0146] Example 40 includes the subject matter of any of Examples 37-39, wherein the bridge die is attached to the substrate.

[0131]

[0147] Example 41 includes the subject matter of any of Examples 37-40, wherein the device is a transceiver module, the EIC die includes a digital signal processor die, and one or more optical fibers are coupled to the PIC die.

[0132]

[0148] Example 42 includes the subject matter of any of Examples 37-41, wherein the substrate has a solid glass layer that is rectangular in plan view.

[0133]

[0149] Example 43 includes the subject matter of any of Examples 37-42, wherein the PIC die includes a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

Claims

1. a substrate; one or more build-up layers adjacent to the substrate; a first electronic integrated circuit (EIC) die attached to the one or more build-up layers; a photonic integrated circuit (PIC) die attached to the substrate; a second EIC die attached to the PIC die; a bridge die electrically coupled to the substrate, the first EIC die, and the second EIC die; the bridge die having through-silicon vias defined therein, the through-silicon vias electrically coupling pads defined on the substrate to pads defined on the second EIC die, the pads defined on the second EIC die being electrically coupled to the PIC die.

2. 10. The device of claim 1, wherein the through silicon via comprises a conductive power path.

3. 10. The apparatus of claim 1, wherein the lateral distance between the PIC die and the bridge die is less than 50 micrometers.

4. 10. The apparatus of claim 1, wherein the one or more build-up layers have a first surface, the first EIC die is attached to the first surface, a cavity is defined in the one or more build-up layers, a second surface of the one or more build-up layers is defined at an end of the cavity, and the bridge die is attached to the second surface.

5. 10. The apparatus of claim 1, wherein the bridge die is attached to the substrate.

6. 10. The apparatus of claim 1, wherein the apparatus is a transceiver module, the first EIC die includes a digital signal processor die, and the one or more optical fibers are coupled to the PIC die.

7. 10. The device according to claim 1, wherein the substrate comprises a solid layer of glass having a rectangular shape in plan view.

8. 10. The apparatus of claim 1, wherein the PIC die comprises a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

9. 10. The apparatus of claim 1, wherein the second EIC is an input / output EIC die, the input / output EIC die including a PIC driver circuit.

10. 10. The apparatus of claim 1, wherein the bridge die is for carrying data signals between the first EIC die and the second EIC die.

11. a substrate; one or more build-up layers adjacent to the substrate; a photonic integrated circuit (PIC) die attached to the substrate; an electronic integrated circuit (EIC) die attached to the one or more build-up layers and the PIC die; a bridge die electrically coupled to the substrate and the EIC die; the bridge die having through-silicon vias defined therein, the through-silicon vias electrically coupling pads defined on the substrate to pads defined on the EIC die, the pads defined on the EIC die being electrically coupled to the PIC die.

12. 12. The apparatus of claim 11, wherein the bridge die is configured to provide power from the substrate through the through silicon via to the PIC die.

13. 12. The apparatus of claim 11, wherein the lateral distance between the PIC die and the bridge die is less than 50 micrometers.

14. 12. The apparatus of claim 11, wherein the bridge die is attached to the substrate.

15. 12. The apparatus of claim 11, wherein the apparatus is a transceiver module, the EIC die includes a digital signal processor die, and the one or more optical fibers are coupled to the PIC die.

16. 12. The device according to claim 11, wherein the substrate comprises a solid layer of glass that is rectangular in shape in plan view.

17. 12. The apparatus of claim 11, wherein the PIC die comprises a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

18. a substrate; one or more build-up layers adjacent to the substrate; an electronic integrated circuit (EIC) die attached to said one or more build-up layers; a photonic integrated circuit (PIC) die; a bridge die, the bridge die having a through-silicon via defined therein; means for supplying power from the substrate to the PIC die through the through silicon vias; An apparatus comprising:

19. 20. The apparatus of claim 18, wherein the bridge die is configured to provide power from the substrate through the through silicon via to the PIC die.

20. 20. The apparatus of claim 18, wherein the lateral distance between the PIC die and the bridge die is less than 50 micrometers.

21. 20. The apparatus of claim 18, wherein the bridge die is attached to the substrate.

22. 20. The apparatus of claim 18, wherein the apparatus is a transceiver module, the EIC die includes a digital signal processor die, and the one or more optical fibers are coupled to the PIC die.

23. 20. The device of claim 18, wherein the substrate comprises a solid layer of glass that is rectangular in plan view.

24. 24. The apparatus of any one of claims 18-23, wherein the PIC die comprises a first waveguide, a modulator coupled to the first waveguide, a second waveguide, and a photodetector coupled to the second waveguide.

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