Multilayer encapsulation and manufacturing method for moisture robustness and high accelerated life testing

Abstract

To provide a semiconductor die comprising a semiconductor body and a multilayer environmental barrier on the semiconductor body.SOLUTION: A multilayer environmental barrier comprises a first sublayer and a second sublayer of first and second oxide materials, respectively, and the first oxide material has a higher density and greater thickness than the second oxide material.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This application claims priority to U.S. Patent Application No. 17 / 591,704, filed February 3, 2022, which is a continuation-in-part of and claims priority to U.S. Patent Application No. 17 / 335,796, filed June 1, 2021, the disclosure of which is incorporated herein by reference in its entirety.

[0002] The present invention relates to semiconductor devices, and more particularly to environmental protection of semiconductor devices and related manufacturing methods. [Background technology]

[0003] Materials such as silicon (Si) and gallium arsenide (GaAs) have found wide application in semiconductor devices for low power, and in the case of Si, low frequency, applications. However, these materials may be less suitable for high power and / or high frequency applications due, for example, to their relatively small band gaps (1.12 eV for Si and 1.42 eV for GaAs at room temperature) and relatively small breakdown voltages.

[0004] For high-power, high-temperature, and / or high-frequency applications and devices, wide-bandgap semiconductor materials such as silicon carbide (SiC) (e.g., 4H—SiC has a bandgap of about 3.2 eV at room temperature) and Group III nitrides (e.g., gallium nitride (GaN) has a bandgap of about 3.36 eV at room temperature) may be used. As used herein, the term “Group III nitrides” refers to semiconductor compounds formed between nitrogen (N) and elements from Group III of the periodic table, usually aluminum (Al), gallium (Ga), and / or indium (In). This term refers to binary, ternary, and quaternary compounds such as GaN, AlGaN, and AlInGaN. These compounds have empirical formulas in which one mole of nitrogen is combined with one mole of a total of Group III elements. These materials may have higher electric field breakdown strengths and higher electron saturation velocities compared to GaAs and Si.

[0005] Semiconductor devices fabricated from SiC and / or III-nitrides may include power transistor devices such as field-effect transistor (FET) devices, including MOSFETs (metal-oxide-semiconductor field-effect transistors), DMOS (double-diffused metal-oxide-semiconductor) transistors, HEMTs (high-electron-mobility transistors), MESFETs (metal-semiconductor field-effect transistors), LDMOS (latently diffused metal-oxide-semiconductor) transistors, etc. These devices are typically passivated with an oxide layer, such as silicon dioxide (SiO), to protect exposed surfaces of the device and / or for other reasons. However, the interface between the semiconductor body and the oxide layer may be insufficient to achieve high surface mobility of electrons. For example, the interface between SiC and SiO traditionally exhibits a high density of interface states, which may reduce surface electron mobility and introduce carrier traps, which in turn may reduce the desired performance characteristics of the device. Therefore, semiconductor devices, including those containing oxide layers, may incorporate one or more layers of silicon nitride (e.g., amorphous silicon nitride, SiNx) to improve the resulting electronic properties, as described, for example, in U.S. Pat. No. 6,449,394.

[0006] Semiconductor devices may be required to operate in high temperature and / or high humidity environments, and poorly designed or processed chips may exhibit failure mechanisms that may reduce or compromise the expected device operating life. For example, if moisture is allowed to reach the semiconductor device, corrosion may occur, which may degrade the performance of the semiconductor device. Moisture protection in semiconductor components is typically implemented using a final passivation film, such as SiN, which has a single layer deposited by CVD.

[0007] As an environmental barrier, SiN may form a better seal on a device compared to SiO2, reducing or preventing contaminants such as water from reaching the epitaxial layers of the device and causing degradation. For example, as described in U.S. Patent No. 6,275,999, plasma-enhanced chemical vapor deposition (PECVD) may be used to form SiN as an environmental barrier for semiconductor devices. However, PECVD SiN layers may be prone to defects such as pinholes and columnar structures, which can allow moisture to penetrate the SiN layer and reach the device. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] U.S. Patent No. 6,246,076 [Patent Document 2] U.S. Patent No. 7,525,122 Summary of the Invention

[0009] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier including first and second sub-layers of first and second oxide materials, respectively, the first oxide material being different from the second oxide material.

[0010] In some embodiments, the first and second sub-layers may be atomic layer deposition (ALD) layers.

[0011] In some embodiments, at least one of the first or second oxide materials may have a density greater than silicon nitride.

[0012] In some embodiments, at least one of the first or second oxide materials may be an insulating metal oxide.

[0013] In some embodiments, the first and second sub-layers may be included in a repeating layer structure, and the first and second oxide materials include an insulating metal oxide and a non-metal oxide, respectively.

[0014] In some embodiments, the insulating metal oxide may be at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0015] In some embodiments, the insulating metal oxide may be aluminum oxide and the non-metal oxide includes silicon oxide.

[0016] In some embodiments, the ratio of the thickness of the first sublayer to the thickness of the second sublayer can be about 2:1 or greater, about 5:1 or greater, or about 8:1 or greater.

[0017] In some embodiments, a passivation layer may be provided between the semiconductor body and the multi-layer environmental barrier. For example, the passivation layer may include silicon nitride.

[0018] In some embodiments, the surface of the multi-layer environmental barrier opposite the passivation layer may include a layer of silicon oxide or silicon nitride.

[0019] In some embodiments, the first oxide material may have a different diffusion coefficient with respect to water than the second oxide material.

[0020] In some embodiments, a gate, a source contact, and a drain contact may be provided on the semiconductor body, and the passivation layer may extend over the gate, the source contact, and the drain contact, and the first and second sublayers may conformally extend over the passivation layer with respective thicknesses that are substantially uniform along the gate, the source contact, and the drain contact.

[0021] In some embodiments, the first and second sub-layers may be included in a repeating layer structure. The multi-layer environmental barrier may include at least two repeating layer structures, at least 10 repeating layer structures, or at least 20 repeating layer structures.

[0022] In some embodiments, the total thickness of the multi-layer environmental barrier can be from about 500 Angstroms to about 3000 Angstroms.

[0023] In some embodiments, the repeating layer structure may be a two-layer structure in which a first and second sublayer are stacked, a three-layer structure in which a first sublayer, a second sublayer, and a third sublayer are stacked, and / or a four-layer structure in which a first sublayer, a second sublayer, a third sublayer, and a fourth sublayer are stacked.

[0024] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier including a repeating layer structure having two or more sub-layers of respective insulating materials, at least one of the respective insulating materials having a density greater than silicon nitride.

[0025] In some embodiments, two or more of the sublayers may be atomic layer deposition (ALD) layers.

[0026] In some embodiments, the density of at least one of the respective insulating materials may be greater than the density of at least one other of the respective insulating materials.

[0027] In some embodiments, at least one of the respective insulating materials may be a metal oxide and at least one other of the respective insulating materials may be a non-metal oxide.

[0028] In some embodiments, the metal oxide may be aluminum oxide, zirconium oxide, or hafnium oxide.

[0029] In some embodiments, the non-metal oxide may be silicon oxide.

[0030] In some embodiments, a passivation layer may be provided between the semiconductor body and the multi-layer environmental barrier.

[0031] In some embodiments, the ratio of the thickness of each of the first and second sublayers of the two or more sublayers can be about 2:1 or greater, about 5:1 or greater, or about 8:1 or greater.

[0032] In some embodiments, a gate, a source contact, and a drain contact may be provided on the semiconductor body, and the passivation layer may extend over the gate, the source contact, and the drain contact. Two or more sublayers may conformally extend over the passivation layer with respective thicknesses that are substantially uniform along the gate, the source contact, and the drain contact.

[0033] In some embodiments, at least two of the respective insulating materials may have different diffusion coefficients with respect to water.

[0034] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier including a repeating layer structure having a first insulating sub-layer and a second insulating sub-layer, wherein a ratio of a first thickness of the first insulating sub-layer to a second thickness of the second insulating sub-layer is about 2:1 or greater.

[0035] In some embodiments, the first and second insulating sublayers may be first and second materials, respectively, and the density of the first material may be greater than the density of the second material.

[0036] In some embodiments, at least one of the first material or the second material may have a density greater than silicon nitride.

[0037] In some embodiments, the first and second insulating sub-layers may be atomic layer deposition (ALD) layers.

[0038] In some embodiments, the first material may be a metal and the second material may be a non-metal.

[0039] In some embodiments, the first material may be aluminum oxide, zirconium oxide, hafnium oxide, or silicon nitride.

[0040] In some embodiments, the second material may be silicon oxide.

[0041] In some embodiments, the first material may have a different diffusion coefficient with respect to water than the second material.

[0042] According to some embodiments of the present invention, a method of manufacturing a semiconductor die includes providing a semiconductor body and forming a multi-layer environmental barrier over the semiconductor body, the multi-layer environmental barrier including first and second sub-layers of first and second oxide materials, respectively, the first oxide material being different from the second oxide material.

[0043] In some embodiments, forming the multi-layer environmental barrier on the passivation layer may include forming the first and second sub-layers by atomic layer deposition (ALD).

[0044] In some examples, forming the multi-layer environmental barrier may include alternating between performing a first ALD process to form a first sub-layer and a second ALD process to form a second sub-layer on the first sub-layer to define a repeating layer structure.

[0045] In some embodiments, at least one of the first or second oxide materials may have a density greater than silicon nitride.

[0046] In some embodiments, at least one of the first or second oxide materials may be an insulating metal oxide.

[0047] In some embodiments, another of the first and second oxide materials may be a non-metal oxide.

[0048] In some embodiments, the insulating metal oxide may be at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0049] In some embodiments, the insulating metal oxide may be aluminum oxide and the non-metal oxide may be silicon oxide.

[0050] In some embodiments, a passivation layer may be formed on the semiconductor body prior to forming the multi-layer environmental barrier.

[0051] In some embodiments, a gate, a source contact, and a drain contact may be formed on the semiconductor body. A passivation layer may be formed on the gate, the source contact, and the drain contact. The first and second sublayers may conformally extend on the passivation layer with respective thicknesses that are substantially uniform along the gate, the source contact, and the drain contact.

[0052] In some embodiments, the surface of the multi-layer environmental barrier opposite the semiconductor body may include a layer of silicon oxide or silicon nitride.

[0053] In some embodiments, the first oxide material may have a different diffusion coefficient with respect to water than the second oxide material.

[0054] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier including multiple sublayers stacked on the semiconductor body, each sublayer having a respective stress in one or more directions, and the respective stresses of at least two of the sublayers being different.

[0055] In some embodiments, at least two of the sublayers may include a first stressor sublayer including a first stress and a second stressor sublayer including a second stress that at least partially compensates for the first stress in one or more directions.

[0056] In some embodiments, the first stress may be tensile and the second stress may be compressive.

[0057] In some embodiments, the first and second stressor sublayers may comprise first and second oxide materials, respectively, and the first oxide material may be different from the second oxide material.

[0058] In some embodiments, at least one of the first or second stressor sublayers may include a metal-insulating material.

[0059] In some embodiments, another of the first or second stressor sublayers may include a metal.

[0060] In some embodiments, the metal insulating material may include at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0061] In some embodiments, another of the first or second stressor sublayers may include a non-metallic insulating material.

[0062] In some embodiments, the metallic insulating material may include aluminum oxide and the non-metallic insulating material may include silicon oxide.

[0063] In some embodiments, the sublayer comprises a repeating layer structure including first and second stressor sublayers.

[0064] In some embodiments, the repeating layer structure may include a two-layer structure in which a first and a second stressor sublayer are stacked, a three-layer structure in which a first stressor sublayer, a second stressor sublayer, and a third stressor sublayer are stacked, and / or a four-layer structure in which a first stressor sublayer, a second stressor sublayer, a third stressor sublayer, and a fourth stressor sublayer are stacked.

[0065] In some embodiments, the multi-layer environmental barrier may include at least two repeating layer structures, at least ten repeating layer structures, or at least twenty repeating layer structures.

[0066] In some embodiments, the first stressor sublayer may be between the second stressor sublayer and the semiconductor body, and the first stressor sublayer may include a first material having a higher density than a second material of the second stressor sublayer.

[0067] In some embodiments, at least one of the first material of the first stressor sublayer or the second material of the second stressor sublayer may have a density greater than silicon nitride.

[0068] In some embodiments, the ratio of the thickness of the first stressor sublayer to the thickness of the second stressor sublayer can be about 2:1 or greater, about 5:1 or greater, or about 8:1 or greater.

[0069] In some embodiments, the semiconductor die may further include a gate, a source contact, and a drain contact on the semiconductor body, and the first and second stressor sublayers may extend conformally directly over the gate, the source contact, and the drain contact with substantially uniform respective thicknesses.

[0070] In some embodiments, the first and second stressor sublayers may include atomic layer deposition (ALD) layers.

[0071] In some embodiments, the multi-layer environmental barrier may include one or more diffusion barrier properties, and the collective stress of the sub-layers of the multi-layer environmental barrier may be less than that of the one or more silicon nitride layers that include at least one of the diffusion barrier properties.

[0072] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier including two or more sub-layers stacked on the semiconductor body in a repeating layer structure, the multi-layer environmental barrier including two or more diffusion barrier properties, and a collective stress of the multi-layer environmental barrier less than that of one or more silicon nitride layers including at least one of the diffusion barrier properties.

[0073] In some embodiments, each sublayer may include a respective stress in one or more directions, and the respective stresses of at least two of the sublayers may be different.

[0074] In some embodiments, at least one of the diffusion barrier properties may include moisture protection, and the total thickness of the multi-layer environmental barrier may be from about 500 Angstroms to about 3500 Angstroms.

[0075] In some embodiments, the collective stress of the multi-layer environmental barrier may be less than that of one or more silicon nitride layers over the operating temperature range of the packaged device that includes the semiconductor die.

[0076] According to some embodiments of the present invention, a method of manufacturing a semiconductor die includes providing a semiconductor body and forming a multi-layer environmental barrier including a plurality of sublayers stacked on the semiconductor body, wherein forming the multi-layer environmental barrier includes forming a first stressor sublayer including a first stress and forming a second stressor sublayer on the first stressor sublayer including a second stress, the second stress at least partially compensating for the first stress in one or more directions.

[0077] In some embodiments, the first stress may be tensile and the second stress may be compressive.

[0078] In some embodiments, forming the multi-layer environmental barrier may include forming the first and second stressor sublayers using atomic layer deposition (ALD).

[0079] In some embodiments, forming the multi-layer environmental barrier may include alternating between performing a first ALD process to form a first stressor sublayer and a second ALD process to form a second stressor sublayer in a repeating layer structure.

[0080] In some embodiments, the first and second stressor sublayers may comprise first and second oxide materials, respectively, where the first oxide material is different from the second oxide material.

[0081] In some embodiments, at least one of the first or second stressor sublayers may include a metal insulating material, which may include at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

[0082] In some embodiments, another of the first or second stressor sublayers may include a metal.

[0083] In some embodiments, another of the first or second stressor sublayers may include a non-metallic insulating material.

[0084] In some embodiments, the metallic insulating material may include aluminum oxide and the non-metallic insulating material may include silicon oxide.

[0085] In some embodiments, the first stressor sublayer may include a first material having a greater density than a second material of the second stressor sublayer.

[0086] In some embodiments, the multi-layer environmental barrier may include one or more diffusion barrier properties, and the collective stress of the sub-layers of the multi-layer environmental barrier may be less than that of the one or more silicon nitride layers that include at least one of the diffusion barrier properties.

[0087] In some embodiments, the total thickness of the multi-layer environmental barrier can be from about 500 Angstroms to about 3500 Angstroms.

[0088] According to some embodiments of the present invention, a semiconductor die includes a semiconductor body and a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier including a first sub-layer of a metallic insulating material and a second sub-layer of a non-metallic insulating material stacked together.

[0089] In some embodiments, the metallic insulating material may be a metal oxide or a metal nitride, and the non-metallic insulating material may be a non-metal oxide or a non-metal nitride.

[0090] In some embodiments, the metallic insulating material may include at least one of aluminum (Al), zirconium (Zr), or hafnium (Hf), and the non-metallic insulating material may include at least one of bismuth (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), or tellurium (Te).

[0091] In some embodiments, the first sublayer may be between the second sublayer and the semiconductor body.

[0092] In some embodiments, the first sublayer may include a first stress and the second sublayer may include a second stress that at least partially compensates for the first stress in one or more directions.

[0093] In some embodiments, the first and second sublayers may be stacked alternately in a repeating layer structure, for example, the multi-layer environmental barrier includes at least two repeating layer structures, at least 10 repeating layer structures, or at least 20 repeating layer structures.

[0094] In some embodiments, the semiconductor die may include a high electron mobility transistor.

[0095] In some embodiments, the semiconductor die may include a metal oxide semiconductor field effect transistor.

[0096] Other devices, apparatus, and / or methods according to some embodiments will become apparent to one of ordinary skill in the art upon examination of the following figures and detailed description. All such additional embodiments, as well as any and all combinations of the above embodiments, are intended to be included within this description, be within the scope of the invention, and be protected by the accompanying claims. [Brief explanation of the drawings]

[0097] [Figure 1] 1 is a schematic cross-sectional view of a semiconductor device including a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 2] 1 is a schematic cross-sectional view of a transistor device including a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 3] 1 is a schematic cross-sectional view of a transistor device including a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 4] 1 is a schematic cross-sectional view of a transistor device including a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 5A] 1 is an expanded view of a transistor device showing the sublayers of a multi-layer environmental barrier in greater detail according to some embodiments of the present invention. [Figure 5B] 1 is an expanded view of a transistor device showing the sublayers of a multi-layer environmental barrier in greater detail according to some embodiments of the present invention. [Figure 5C] 1 is an expanded view of a transistor device showing the sublayers of a multi-layer environmental barrier in greater detail according to some embodiments of the present invention. [Figure 5D] 1 is an expanded view of a transistor device showing the sublayers of a multi-layer environmental barrier in greater detail according to some embodiments of the present invention. [Figure 5E] 1 is an expanded view of a transistor device showing sublayers of a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 6A] 6A-6C are STEM images showing cross-sectional views of transistor devices including a multi-layer environmental barrier according to some embodiments of the present invention. In particular, Figure 6A is a cross-sectional view of a HEMT device. [Figure 6B] 6A and 6B are STEM images showing a cross-sectional view of a transistor device including a multi-layer environmental barrier according to some embodiments of the present invention, and FIG. 6B is an enlarged view of the passivation layer and multi-layer environmental barrier shown in FIG. [Figure 6C] 6A and 6B are STEM images showing cross-sectional views of a transistor device including a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 7A] 1A-1D are cross-sectional views illustrating intermediate fabrication steps in a method of fabricating a multi-layer environmental barrier on a transistor device according to some embodiments of the present invention. [Figure 7B] 1A-1D are cross-sectional views illustrating intermediate fabrication steps in a method of fabricating a multi-layer environmental barrier on a transistor device according to some embodiments of the present invention. [Figure 7C] 1A-1D are cross-sectional views illustrating intermediate fabrication steps in a method of fabricating a multi-layer environmental barrier on a transistor device according to some embodiments of the present invention. [Figure 7D] 1A-1D are cross-sectional views illustrating intermediate fabrication steps in a method of fabricating a multi-layer environmental barrier on a transistor device according to some embodiments of the present invention. [Figure 8A] 1 is a schematic cross-sectional view illustrating a number of exemplary packages including transistor devices according to embodiments of the present invention to provide a packaged transistor amplifier. [Figure 8B] 1 is a schematic cross-sectional view illustrating a number of exemplary packages including transistor devices according to embodiments of the present invention to provide a packaged transistor amplifier. [Figure 8C]1 is a schematic cross-sectional view illustrating a number of exemplary packages including transistor devices according to embodiments of the present invention to provide a packaged transistor amplifier. [Figure 9] 1 is a schematic plan view of a III-nitride based transistor die according to an embodiment of the present invention showing metallization on the surface of its semiconductor layer structure. [Figure 10] 1 is an expanded view of a transistor device illustrating the stress in each of the sublayers of a multi-layer environmental barrier according to some embodiments of the present invention. [Figure 11] 1 is a graph showing stress versus temperature in a multi-layer environmental barrier according to several embodiments of the present invention versus a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0098] Packages for some semiconductor devices may not provide a hermetic seal for environmental protection in some applications. The environment may include the operating environment (i.e., when operating under bias in a user application) or the manufacturing environment (i.e., under processing conditions that may include different ionic contaminant profiles, such as integration, packaging techniques, etc.). Therefore, an encapsulation structure or environmental barrier may be provided over the semiconductor device to protect against humidity and / or other conditions of the environment (also referred to as a die-level environmental barrier). As used herein, a "die" or chip may refer to a small block or body of semiconductor material or other substrate on which electronic circuit elements are fabricated. A die may include multiple individual "unit cell" transistor structures that may be electrically connected in parallel or series in some implementations. A semiconductor die as described herein may include a semiconductor body and metal and / or insulating layers formed thereon.

[0099] One implementation of a die-level environmental barrier may be a top or final passivation film, which is typically a single layer deposited by chemical vapor deposition (CVD). The material selection for the final passivation film may be determined by the desired diffusion barrier properties, and its function is to prevent various contaminant species present in humid environments from reaching the active area of ​​the semiconductor die. For example, in addition to water vapor, high-humidity environments may also contain trace elements of various atomic, molecular, and ionic contaminant species. Examples of various ionic species may include, but are not limited to, halogens (e.g., Cl-, F-, Br-, etc.), molecular ions (e.g., OH-, NO2-, NO3-, PO4-, SO4-, etc.), cations (e.g., Na+, K+, Au+, Ti+, etc.), and weak organic acids (e.g., carbonates, acetates, etc.). Such ionic species may be a source of degradation for electrical devices under bias because an electric field can accelerate ionic migration or diffusion through the moisture barrier layer. For example, a PECVD SiN layer may provide diffusion barrier properties with respect to water molecules, but may be susceptible to moisture ingress due to defects (such as pinholes and / or columnar structures), as well as oxidation, etching, and / or corrosion in the presence of contaminant halogens (e.g., F and Cl). The presence of such contaminants can be frequent and can come from multiple sources.

[0100] Some embodiments of the present invention may arise from the recognition that, given the wide variety of possible contaminant species, the selection of protective film materials may represent a non-ideal trade-off. Accordingly, embodiments of the present invention provide a protective film, also referred to herein as a multilayer environmental barrier film, stack, or structure, or simply a multilayer environmental barrier, that includes multiple stacked sublayers of various insulating materials (e.g., dielectric materials) with different properties. A multilayer environmental barrier may include respective insulating sublayers with different diffusion barrier properties to protect the semiconductor die from not only water molecules but also various ionic species that may be present in the environment. That is, stacking sublayers of various insulating materials with different diffusion coefficients (e.g., with respect to water molecules) can provide a humidity barrier that targets the migration of various ionic trace atoms in addition to water molecules in the environment. It will be understood that the layers or sublayers described herein may be uniform or varying in thickness and / or continuous or discontinuous.

[0101] As discussed herein, a multilayer environmental barrier is a low-defect, highly conformal material stack. In particular, a multilayer environmental barrier may include two or more sublayers of different materials and / or thicknesses (e.g., as alternating or repeating layer structures in some embodiments) to target different contaminant species and provide a more robust moisture diffusion barrier for semiconductor devices. Some embodiments described herein may provide a multilayer environmental barrier that includes additional sublayers of different insulating materials, either replacing or in combination with SiN sublayers (e.g., alternating with SiN sublayers), that may reduce defect formation and / or slow down the effects of halogens, thereby improving the diffusion barrier properties of the stack. In some embodiments, at least one of the sublayers may include a material having a higher density than SiN, which may impede the ingress of moisture and / or other contaminants. More generally, the selection of different properties for the sublayers and / or additional interfaces defined between the sublayers described herein may provide an increased barrier against the propagation of defects or contaminants.

[0102] FIG. 1 is a schematic cross-sectional view of a semiconductor device or die 100 including a multi-layer environmental barrier according to some embodiments of the present invention. As shown in FIG. 1, a multi-layer environmental barrier film or stack 160 is provided on a semiconductor body 190 to protect the semiconductor body 190 from moisture and / or other conditions of the environment. The semiconductor body 190 may be provided on a substrate (shown as 122 in subsequent figures), such as a silicon carbide (SiC) substrate. The semiconductor body 190 may, in some embodiments, be a SiC-based and / or III-nitride-based material. A portion of the semiconductor body 190 may define a channel region of a transistor device. Metal layers and / or other structures of such a transistor device are not shown in FIG. 1.

[0103] In some embodiments, an optional (indicated by dashed lines) passivation layer or layer structure 150 may be provided on a surface of semiconductor body 190, and a multi-layer environmental barrier 160 may be provided on the passivation layer on a side opposite semiconductor body 190. Passivation structure 150 may be configured to reduce parasitic capacitance, reduce charge trapping, and / or otherwise enhance electronic properties of one or more layers of semiconductor body 190. When present, passivation structure 150 may include, for example, one or more layers of SiN deposited by CVD. More generally, passivation structure 150 may be a multi-layer stack using a deposition method other than atomic layer deposition (ALD).

[0104] The multilayer environmental barrier 160 includes two or more sublayers 160a-160d of insulating materials with different properties formed in a layered structure. In some embodiments, the sublayers 160a-160d may be alternately stacked in a periodic or other repeating layer structure. For example, the multilayer stack 160 may include a two-layer stack (each period including two sublayers 160a, 160b, e.g., AlOx-SiOx), a three-layer stack (each period including three sublayers 160a, 160b, 160c, e.g., AlOx-SiOx-HfOx), or a four-layer stack (each period including four sublayers 160a, 160b, 160c, 160d, e.g., AlOx-SiOx-HfOx-ZrOx). More generally, the multilayer environmental barriers 160 described herein are not limited with respect to the number of sublayers 160a-160d in each repeating structure or period. Similarly, the multilayer environmental barrier 160 described herein is not limited with respect to the number of repeating structures or periods in the stack. The multilayer stack 160 may include a combination of different repeating layer structures, such as a repeating structure of a four-layer stack over a two-layer stack, in some instances with one or more intervening layers. The repeating layer structures may be periodic or aperiodic. In some embodiments, the multilayer environmental barrier 160 may include at least two repeating layer structures or periods, at least 10 repeating layer structures or periods, or at least 20 repeating layer structures or periods. Each repeating layer structure may have a thickness greater than about 5 nanometers (nm) (about 50 angstroms (Å)), e.g., about 10 nm (100 Å). Thus, the multilayer environmental barrier 160 may have a total thickness of about 500 Å to about 8000 Å, e.g., greater than about 1000 Å, greater than about 1500 Å, or greater than about 2000 Å.

[0105] The different properties of two or more of the sublayers 160a-160d within each periodic or repeating layer structure may provide respective diffusion barrier properties. The respective diffusion barrier properties may be defined by the material composition and / or thickness of each sublayer 160a-160d. For example, an insulating sublayer of a relatively denser material (e.g., aluminum oxide or other insulating metal oxides or nitrides having a higher density than silicon nitride) and / or a relatively greater thickness may provide better protection against the ingress of water / moisture and / or various ionic species that may be present in the environment. An insulating sublayer of another material (e.g., a semiconductor oxide or nitride such as silicon oxide) may provide better protection against etchants and / or other subsequent fabrication conditions. As used herein, a "non-metallic" insulating material or layer may refer to an insulating material or layer that does not contain a metal, but may contain a metalloid or semi-metal, such as, but not limited to, bismuth (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te), etc. Examples of non-metallic insulating materials or layers may include, but are not limited to, metalloid oxides (e.g., BOx, SiOx, GeOx, AsOx, SbOx, TeOx) and metalloid nitrides (e.g., SiN).

[0106] The top sublayer 160d of the stack 160 (or an additional capping layer 170 on the top sublayer 160d) may be a non-metallic insulating material or layer (e.g., a semi-metallic insulating material such as silicon oxide or silicon nitride) that protects the underlying layers from subsequent chemical processing conditions (e.g., basic etch chemistries). Additionally, each interface between a multilayer stack of sublayers 160a-160d having different properties can provide a barrier that prevents defects and / or contaminants from one sublayer from propagating to the next sublayer in the stack 160. Thus, stacking multiple sublayers 160a-160d of different materials and / or thicknesses (e.g., in a repeating layer structure), each configured based on a respective contaminant or environmental condition, can provide protection against multiple contaminant species.

[0107] That is, a multilayer environmental barrier 160 including a combination of sublayers 160a-160d with different diffusion barrier properties can be tailored to protect against the ingress of a wider range of contaminant species than any one sublayer. Such contaminant species may include, but are not limited to, halogens (Cl, F, Br), molecular ions (OH, NO, NO, PO, SO, etc.), cations (Na, K, Au, Ti, etc.), and weak organic acids (carbonates, acetates, etc.). For example, sublayer 160a may include a material composition and / or thickness that provides a low diffusion coefficient for water, sublayer 160b may include a material composition and / or thickness that provides a low diffusion coefficient for halogen-based ionic species, sublayer 160c may include a material composition and / or thickness that provides a low diffusion coefficient for non-halogen-based ionic species, and sublayer 160d may include a material composition and / or thickness that provides protection against elemental chemical compounds. In some embodiments, the different sublayers 160a-160d may be deposited using the same deposition technique, such as ALD, which may allow for fabrication of the entire multilayer stack structure 160 in the same process chamber or without otherwise breaking vacuum in the process chamber.

[0108] The combination of different material compositions, thicknesses, and / or other properties of each sublayer 160a-160d may be varied or otherwise customized for different applications or environments and / or may provide a combination of properties for use in multiple applications or environments. For example, a multilayer environmental barrier structure 160 as described herein may include sublayers 160a-160d having respective compositions that vary in response to environmental conditions or contaminants, which may be specific to a particular package type, such as the exemplary package types shown in Figures 8A-8C. It will be understood that the package types shown herein are provided by way of example and not limitation. Additional exemplary package types that may be associated with particular contaminants include, but are not limited to, through-hole based, surface-mount based, chip carrier, pin grid array, flat, small outline integrated circuit (SOIC), chip scale, ball grid array, transistor / diode / small pin count IC, and / or multi-chip packages, including ceramic or plastic packages. As another example, the multi-layer environmental barrier structure 160 as described herein may include sub-layers 160a-160d, each configured to provide a diffusion barrier for a respective condition or contaminant, to provide a multi-layer environmental barrier 160 including a combination of sub-layers 160a-160d that may be universally applied in a number of different environments or applications.

[0109] 2, 3, and 4 are schematic cross-sectional views of transistor devices including multi-layer environmental barriers according to some embodiments of the present invention. As shown in FIGS. 2, 3, and 4, transistor devices 200, 300, and 400 are formed on a substrate 122, such as a silicon carbide substrate. The illustrated devices 200, 300, and 400 represent unit cell transistor structures of a semiconductor die, where hundreds or thousands of unit cell transistor structures may be formed on the semiconductor substrate 122 and electrically connected (e.g., in parallel). The substrate 122 may be a semi-insulating SiC substrate. However, embodiments of the present invention may utilize any suitable substrate, such as sapphire (Al2O3), aluminum nitride (AlN), aluminum gallium nitride (AlGaN), gallium nitride (GaN), silicon (Si), GaAs, LAO, zinc oxide (ZnO), OAO, indium phosphide (InP), etc. The substrate 122 may be a SiC wafer, and the devices 200, 300, 400 may be formed, at least in part, via wafer-level processing, and the wafer may then be diced or otherwise singulated to provide dies including a plurality of unit cell transistor structures.

[0110] Semiconductor body 190 may be a semiconductor layer structure including one or more layers formed by epitaxial growth. The layers of semiconductor body 190 may include one or more wide bandgap materials, such as, for example, one or more III-nitride-based layers. For example, semiconductor body 190 may be formed from one or more layers of GaN or AlGaN. However, other III-nitride materials may be used. As another example, both substrate 122 and semiconductor body 190 may be formed from SiC.

[0111] Source region 215 and drain region 205 are formed in semiconductor body 190, for example, by implanting appropriate ions into the surface of semiconductor body 190 to achieve the desired doping concentration. Source contact 115 is formed by one or more metal layers on the surface of semiconductor body 190 above source region 215. Similarly, drain contact 105 is formed by one or more metal layers on the surface of semiconductor body 190 above drain region 205. Source and drain contacts 115 and 105 may provide low resistance ohmic contacts to source and drain regions 215 and 205, respectively. Gate 110 is formed by one or more metal layers on the surface of semiconductor body 190 between source region 215 and drain region 205.

[0112] Figure 2 shows a metal semiconductor field effect transistor (MESFET) device 200, where the region of semiconductor body 190 between source and drain regions 215 and 205 provides the conductive channel or channel region of MESFET 200. Figure 3 shows a metal oxide semiconductor field effect transistor (MOSFET) device 300, where the region of semiconductor body 190 between source and drain regions 215 and 205 provides the channel region of MOSFET 300, with gate 110 separated from the channel region by gate oxide layer 109. Figure 4 shows a high electron mobility transistor (HEMT) device 400, where semiconductor body 190 includes a low bandgap channel layer 124 on a substrate 122 and a high bandgap barrier layer 126 on the channel layer 124 opposite substrate 122. A 2DEG conduction channel 40 can be induced in a region of semiconductor body 190 between source and drain regions 215 and 205 along a heterointerface between channel layer 124 and barrier layer 126. In some embodiments, substrate 122 comprises SiC, channel layer 124 comprises GaN, and barrier layer 126 comprises AlGaN. A metal field plate 128 can be provided and, in some embodiments, can be electrically connected to gate 110 (which can reduce the peak electric field, thereby increasing the breakdown voltage and reducing high-field charge trapping effects) or to source contact 115 (which can reduce the gate-drain capacitance (C gd ), increase the gain, and / or improve the linearity of the device 400).

[0113] One or more insulator layers (e.g., one or more passivation layers) 150 are formed on the surface of semiconductor body 190. Passivation layer 150 may passivate surface states and / or otherwise improve electrical properties at the surface or along the interface with semiconductor body 190. Passivation layer 150 may include SiN and, in some embodiments, may be deposited by a CVD process (such as PECVD) or other non-ALD process. While primarily discussed herein with respect to SiN passivation layer 150, it will be understood that passivation layer 150 is not limited to SiN.

[0114] Transistor devices 200, 300, and 400 each include a multi-layer environmental barrier 160. An optional capping layer, such as the non-metal oxide-based or nitride-based capping layer 170 of FIG. 1, is not shown for ease of illustration. The illustrations of FIGS. 2, 3, and 4 are intended to illustrate that multi-layer environmental barrier 160 is not limited to use with any particular transistor structure, but rather can be utilized as an environmental barrier for any suitable semiconductor device. As such, further details regarding the operation of devices 200, 300, and 400 will not be described in detail herein.

[0115] The multilayer environmental barrier 160 includes multiple insulating sublayers (e.g., dielectric sublayers) having different properties (e.g., different material compositions and / or thicknesses). As shown in FIGS. 2, 3, and 4, the multilayer environmental barrier layer 160 conformally covers various elements of the transistor devices 200, 300, and 400. In some embodiments, the multiple sublayers of the multilayer environmental barrier 160 may be oxide layers of different materials deposited using the same process tool chamber or without otherwise breaking vacuum in the process chamber. For example, each sublayer of the multilayer environmental barrier 160 may be deposited using ALD, which may enable the construction of the structure 160 including the sublayers with a high degree of conformality and thickness uniformity in the same process chamber.

[0116] The use of multiple sublayers of different material compositions and / or thicknesses as described herein may provide substantially improved environmental barrier properties compared to some conventional environmental barriers, such as those comprising alternating oxide and nitride sublayers. Without being bound by any particular theory, it is recognized that such SiN sublayers may be susceptible to oxidation, etching, and / or corrosion in the presence of contaminant halogens such as F and Cl. Additionally, it is recognized that ALD-based layers may provide improved conformality, which may be advantageous and / or important for moisture protection. However, SiN is typically deposited by CVD, which may result in defects (e.g., pinholes, columnar structures). Furthermore, the deposition of conventional alternating oxide and nitride sublayers in the same can be problematic due to cross-contamination issues. It is further recognized that thicker and / or denser insulating films or sublayers (e.g., insulating metal oxides) may provide improved contaminant ingress protection. For example, AlO-, HfO-, and / or ZrO-based layers may have a higher density than SiN-based layers and may provide better moisture protection. Thus, in some embodiments, one or more sublayers of different insulating materials may be alternated with (or replace) conventional oxide or nitride sublayers to provide a multi-layer environmental barrier with different diffusion barrier properties, i.e., improved resistance to oxidation, etching, and / or corrosion with respect to multiple different contaminants or combinations of different contaminants.

[0117] Multi-material environmental barrier stacks can be customized to address wet environments with different contaminant compositions, e.g., to provide barriers against elements or chemicals other than (or in addition to) water. In some embodiments, at least one of the sublayers may have a different density and / or thickness than the material of at least one other sublayer of the multi-layer environmental barrier. For example, the respective insulating material of at least one of the sublayers may have a density greater than SiN. Additionally, non-metallic insulating films or sublayers may be included in the stack to provide desired chemical processing protection. Thus, the combination of stacked sublayers of different material compositions and / or different thicknesses as described herein (e.g., in a repeating or periodic layer structure) can provide greater protection against contaminant ingress and / or damage while simultaneously providing protection against subsequent manufacturing processes.

[0118] 5A, 5B, 5C, 5D, and 5E are enlarged views of a transistor device showing in more detail various combinations of sublayers in a multi-layer environmental barrier according to some embodiments of the present invention. Two-layer periodic structures 160', 160'', 160''', 160' include first and second sublayers alternately stacked on an optional passivation layer or layer structure 150. (4) , 160 (5) 5A-5E, these structures 160', 160'', 160''', 160 (4) , 160 (5) are shown by way of example only and are not intended to be limiting of the multi-layer environmental barriers 160', 160'', 160''', 160's described herein. (4) , 160 (5) , 160 (6) It will be appreciated that (collectively 160) may include more than two sub-layers having different properties (e.g., defining a three-layer structure, a four-layer structure) and / or may be stacked in a non-repeating layer structure or a periodic or aperiodic repeating layer structure.

[0119] In the example of FIG. 5A, the multilayer environmental barrier 160′ includes a stack of sublayers 160a′, 160b′ of respective insulating materials, alternating to define a periodic, repeating layer structure, with each period including a first sublayer 160a′ and a second sublayer 160b′. One of the insulating materials of each of the first and second sublayers 160a′, 160b′ may have a relatively higher density than the other. One or more of the sublayers 160a′, 160b′ may have a density greater than that of SiN. Another of the sublayers 160a′, 160b′ may have a density equal to or less than that of SiN. In FIG. 5A, the first sublayer 160a′ includes a relatively high-density insulating material, and the second insulating sublayer 160b′ includes a relatively low-density material. For example, the first insulating sublayer 160a' may include a metallic insulating material such as aluminum oxide (AlO), hafnium oxide (HfO), or zirconium oxide (ZrO), or other metal-rich insulating materials. That is, examples of metallic insulating materials or layers may include, but are not limited to, metal oxides (e.g., AlO, HfO, ZrO) or metal nitrides. The second insulating sublayer 160b' may include a non-metallic insulating material, such as a semiconductor oxide or nitride, such as silicon oxide (SiO) or silicon nitride (SiN), or other metal-deficient insulating materials. As noted above, examples of non-metallic insulating materials or layers may include, but are not limited to, metalloid oxides (e.g., BOx, SiOx, GeOx, AsOx, SbOx, TeOx) and metalloid nitrides (e.g., SiN). Materials described herein with respect to compound formulas (e.g., SiO) may include any compound of different stoichiometry or constituent elements, and amorphous or crystalline states of the material. Typical densities of SiO, SiN, AlO, ZrO, and HfO are 2.65, 3.17, 3.95, 5.68, and 9.68 grams per cubic centimeter (g / cm), respectively. 3 ) in terms of material density: HfO > ZrO > AlO > SiN > SiO. Generally, denser films may provide better protection against water or other contaminant ingress. For example, HfO and ZrO are denser than AlO, SiN, and SiO and therefore may better hinder contaminant ingress.

[0120] In the example of FIG. 5B, the multilayer environmental barrier 160″ includes a stack of sublayers 160a″, 160b″ of respective oxide materials that are alternately stacked to define a periodic, repeating layer structure, with each period including a first oxide sublayer 160a″ and a second oxide sublayer 160b″. The oxide materials of the first and second oxide sublayers 160a″, 160b″ may differ from each other in material composition. For example, the first oxide sublayer 160a″ may include AlO, HfO, or ZrO, while the second oxide sublayer 160b″ may include SiO. FIG. 5C shows a more specific example of a multilayer environmental barrier 160′″ that includes a first sublayer 160a′″ of an insulating metal oxide material or layer (e.g., AlO, HfO, or ZrO) and a second sublayer 160b′″ of an insulating non-metal oxide material or layer (e.g., SiO) that are alternately stacked in a periodic, repeating layer structure. Thus, the multi-layer environmental barrier 160''' including alternating first and second sub-layers 160a''' and 160b''' may reduce the susceptibility of the non-metal oxide sub-layer 160b''' to oxidation, etching, and / or corrosion. In the example of FIG. 5D, the multi-layer environmental barrier 160 (4) Each period is a first nitride sublayer 160a (4) and second nitride sublayer 160b (4) Sublayers 160a of nitride material are alternately stacked to define a periodic repeating layer structure including: (4) , 160b (4) and sublayer 160a (4) , 160b (4) Each nitride material may have a different material composition. Figure 5E shows first sublayers 160a of insulating metal oxide materials (e.g., AlO, HfO, or ZrO) stacked alternately in a periodic, repeating layer structure. (5) and a second sublayer 160b of a metallic material (e.g., Al, Au). (5) Multi-layer environmental barrier 160 (5) 1 shows another example of a metal sublayer 160b (5) may provide a more effective barrier to moisture ingress.

[0121] 5A-5E, at least two of the sublayers of each period of the multi-layer environmental barrier 160 may have different thicknesses. For example, the first sublayers 160a' / 160a'' / 160a''' / 160a (4) / 160a (5) / 160a (6) (collectively 160a) and the thickness T1 of the second sublayer 160b' / 160b'' / 160b''' / 160b (4) / 160b (5) / 160b (6) The ratio of the thickness T2 of the sublayers 160a, 160b (collectively 160b) to the thickness T2 may be greater than 2:1, greater than 5:1, greater than 8:1, or greater than 10:1 in some embodiments. The ratio of the thicknesses of the sublayers 160a, 160b may depend on or be based on the respective densities of the different insulating materials. For example, in the illustrated two-layer periodic layer structure, the sublayer 160a' of the first, denser material may be deposited to have a thickness T1 greater than the thickness T2 of the sublayer 160b' of the second, less dense material. Similarly, a multilayer environmental barrier 160 including a three-layer or four-layer periodic layer structure may include three or four sublayers, respectively, and at least two of the sublayers in each period may have different thicknesses.

[0122] 5A-5E are illustrated with various sublayer material combinations, it will be understood that multi-layer environmental barriers according to embodiments of the present invention are not limited to these particular materials. For example, in some embodiments, sublayers 160a, 160b may include alternating organic and inorganic materials to define multi-layer environmental barrier 160. In particular, in FIG. 5B, one of oxide layers 160a'', 160b'' may be replaced by an organic material sublayer to define multi-layer environmental barrier 160'' of alternating organic / oxide sublayers. Similarly, in FIG. 5B, nitride layer 160a (4) , 160b (4) One of the layers is a multilayer environmental barrier 160 of alternating organic / nitride sublayers. (4) may be replaced by organic material sublayers to define

[0123] More generally, the multi-layer environmental barrier 160 shown in Figures 5A-5E may include two or more sub-layers 160a, 160b having different material compositions and the same thickness, the same material composition and different thicknesses, or different material compositions and different thicknesses. The two or more sub-layers 160a, 160b may be stacked in a repeating or non-repeating layer structure. The repeating layer structure may be periodic (having two or more periods) or aperiodic.

[0124] In the particular embodiment of the multilayer environmental barrier 160 shown in FIGS. 5A-5C, the first sublayer 160a of each period may be AlO, and the second sublayer 160b of each period may be SiO. The SiO sublayer may be amorphous (e.g., silica) or crystalline (e.g., SiO). Similarly, the AlO sublayer may be amorphous (e.g., alumina) or crystalline (e.g., AlO). AlO may be relatively stable and, compared to some nitride materials (e.g., SiN), may be relatively easy to fabricate using widely available deposition tools. AlO may have a higher density than SiN and therefore may provide an improved moisture barrier. The AlO sublayer may be several times thicker than the SiO sublayer, for example, because the deposition rate and / or density for AlO may be several times that of SiO. For example, the thickness T2 of the SiO sublayer may be less than about one-quarter or less than about one-fifth the thickness T1 of the AlO sublayer in some embodiments. In certain examples, the thicknesses T1 and T2 of the AlO and SiO sublayers, respectively, in a multilayer environmental barrier as described herein may be about 2-8 nm and 1 nm, thereby providing a thickness ratio of AlO to SiO of, for example, about 2:1 or greater, about 5:1 or greater, or about 8:1 or greater.

[0125] 5A-5E , a non-metallic insulating layer, such as SiO or SiN, may be included as or on the top sublayer 160 b of the multilayer environmental barrier 160. For example, the SiO may protect underlying sublayers of the multilayer environmental barrier structure 160 during further chemical processing, which may rely on basic (non-acidic) chemistries. In some embodiments, the non-metallic insulating layer may be implemented by the top sublayer 160 b of the multilayer environmental barrier 160. In other embodiments, the non-metallic insulating layer may be implemented by an additional SiO or SiN capping layer 170 formed on the top sublayer 160 b of the multilayer environmental barrier 160. That is, the surface of the multilayer environmental barrier 160 opposite the passivation layer 150 may be or have a non-metallic insulating layer thereon.

[0126] In some embodiments, two or more sublayers of the multilayer environmental barrier 160 may be formed by a conformal deposition process, such as ALD. ALD (sub)layers or ALD materials may refer to layers or materials formed by ALD, including, but not limited to, thermal ALD and plasma-enhanced ALD (PEALD) processes. The use of ALD to form several (or all) sublayers in the multilayer stack 160 may enable sublayers with substantially uniform thicknesses that conformally extend along the underlying surface, are thinner, and have better step coverage than can be achieved by CVD. For example, ALD may achieve up to 100% conformality, compared with CVD sidewall coverage of approximately 80% of the topside or planar thickness. As described herein, the conformality of a layer along a particular surface may be expressed as a percentage of the layer's thickness when deposited on a planar surface. ALD processes can also be advantageous in forming multilayer stacks by enabling the fabrication of multiple thin sublayers in the same chamber without additional wafer movement (i.e., without breaking vacuum) and without resetting between substeps (e.g., to avoid cross-contamination).

[0127] Figures 6A, 6B, and 6C are STEM images showing cross-sectional views of transistor devices including a multi-layer environmental barrier formed from ALD oxide sublayers according to some embodiments of the present invention. In particular, Figure 6A is a cross-sectional view of a HEMT device 600. Figure 6B is an expanded view of the passivation layer 150 and multi-layer environmental barrier 160 shown in Figure 6A. Figure 6C is an expanded view of the multi-layer environmental barrier 160 shown in Figure 6B.

[0128] As shown in FIGS. 6A-6C, the multilayer environmental barrier 160 can be a two-layer stack including alternating sublayers of ALD SiO and ALD AlO. The ALD process can enable the deposition of the AlO and SiO sublayers with substantially uniform thickness and high conformality (e.g., greater than 80% and up to about 100% of the planar surface thickness). In particular, FIG. 6B shows that the AlO / SiO environmental barrier 160 substantially conforms to the shape of the underlying passivation layer 150 formed over the gate 110 and field plate 128. Each of the AlO and SiO sublayers has a substantially uniform thickness and conformally extends along the shape defined by the passivation layer 150 and the underlying gate 110 and field plate 128 structures.

[0129] The AlO sublayers may have a relatively high density and therefore may provide improved moisture robustness and improved protection against oxidation, etching, and / or corrosion by contaminant halogens compared to SiN. The alternating SiO sublayers may define multiple AlO / SiO interfaces with the AlO layers, which can reduce or prevent defects and / or contaminants from one sublayer from propagating to the next sublayer in the stack 160. The SiO sublayers may also provide protection in subsequent processing (e.g., against basic etch chemistries). Additionally or alternatively, the multilayer environmental barrier 160 may include ALD HfO, ZrO, and / or SiN sublayers. In the example apparatus 600 shown in FIGS. 6A-6C, the top or terminal layer in the multilayer environmental barrier 160 is the SiO sublayer. However, in other embodiments, an additional SiO or SiN capping layer 170 may be formed on the top sublayer of the multilayer environmental barrier 160.

[0130] 7A, 7B, 7C, and 7D are cross-sectional views illustrating intermediate fabrication steps in a method for fabricating a multi-layer environmental barrier in a semiconductor device according to some embodiments of the present invention. As shown in FIG. 7A, a transistor structure includes a gate 110, a source contact 115, and a drain contact 105 on a semiconductor body 190 (in this example shown with respect to HEMT device 400 of FIG. 4, which includes a channel layer 124 and a barrier layer 126 on a substrate 122). A passivation layer or layer structure 150, such as a SiN-based passivation layer, is formed on the gate 110 and on portions of the semiconductor body 190 between the gate and the source and drain contacts 115 and 105.

[0131] A metal field plate 128 is formed on the passivation layer 150. Although shown as including a stepped profile that extends conformally along the passivation layer 150, with a first stepped portion adjacent or overlapping the gate 110 and a second stepped portion adjacent the drain contact 105, the field plate 128 may be implemented in various configurations in accordance with embodiments of the present invention. For example, the field plate 128 may have a substantially flat profile that extends along the portion of the passivation layer 150 between the gate 110 and the drain contact 105 or between the gate 110 and the source contact 115, and / or may be spaced laterally from the gate 110 such that it does not overlap the gate 110 in the vertical (Z) direction.

[0132] 7B and 7C, an ALD process is performed to conformally deposit a first insulating sublayer 160a on the surface of the passivation layer 150 and a second insulating sublayer 160b on the surface of the first insulating sublayer 160a. For example, the first insulating sublayer 160a may include a metallic insulating material such as AlO, HfO, ZrO, or other metal oxide or insulating layer having a density greater than SiN. In some embodiments, the second insulating sublayer 160b may include a non-metallic insulating material such as SiO, SiN, or other non-metal oxide or insulating layer having a density equal to or less than SiN.

[0133] The ALD process may rely on alternating, self-limiting reactions between gaseous reactants and exposed solid surfaces to deposit highly conformal insulating sublayers 160a, 160b with substantially uniform thicknesses that may be controllable at the submonolayer level. Specifically, a semiconductor body 190, including features 105, 110, 115, 128, and 150 formed thereon, is exposed to two reactants A (in FIG. 7B) and B (in FIG. 7C) in a sequential, non-overlapping fashion in a process chamber. In FIG. 7B, reactant A reacts with a finite number of reactive sites on the exposed surfaces of the semiconductor body 190 and features to define a first sublayer 160a, with growth halting once the finite number of sites is consumed in a self-limiting fashion. The remaining amount of reactant A is evacuated from the chamber, and reactant B is introduced in FIG. 7C without breaking the vacuum in the chamber. Reactant B similarly reacts with a finite number of reactive sites on the exposed surface to define a second sublayer 160b, and once the finite number of sites is consumed, growth stops and the remaining amount of reactant B is pumped out of the chamber. Alternating exposure to reactants A and B deposits a thin film multilayer environmental barrier 160 comprising alternating sublayers 160a and 160b, as shown in Figure 7D.

[0134] ALD processes deposit sublayers 160a, 160b with substantially uniform thickness and high conformality over complex underlying shapes or structures. For example, ALD may achieve conformality of up to 100% of the planar thickness of sublayers 160a, 160b. ALD processes can also be advantageous in forming multilayer stacks 160 by enabling fabrication of multiple thin sublayers 160a, 160b in the same chamber without additional wafer movement (i.e., without breaking vacuum) and without resetting between substeps (e.g., to avoid cross-contamination).

[0135] In some embodiments, at lower temperatures, ALD processes such as those shown in FIGS. 7B and 7C may produce amorphous films, which may then be crystallized. For example, in some embodiments, first sublayer 160a may be deposited as amorphous AlO (also referred to as AlO), which may be crystallized to form AlO. Second sublayer 160b may be deposited as amorphous SiO (also referred to as SiO), which may be crystallized to form SiO. A non-metal oxide layer, such as SiO or SiN, may be formed as the top sublayer 160b of multilayer environmental barrier 160 or on top sublayer 160b (e.g., as capping layer 170) using an ALD or non-ALD process.

[0136] As noted above, the multilayer environmental barrier structure 160 as described herein may include sublayers with respective compositions selected based on environmental conditions / contaminants, which may be application-specific. For example, the environmental conditions / contaminants may be specific to a particular semiconductor package type, including ceramic or plastic packages, such as open-cavity, overmolded, thermally enhanced, through-hole-based, surface-mount-based, chip carrier, pin grid array, flat, small-outline integrated circuit (SOIC), chip-scale, ball grid array, transistor / diode / small pin count IC, and / or multi-chip packages. Thus, some embodiments described herein may provide a multilayer environmental barrier structure 160 including sublayers of respective materials that may be targeted to accommodate specific package technologies.

[0137] 8A, 8B, and 8C are schematic cross-sectional views illustrating several exemplary package types 800A, 800B, and 800C, each of which may have its own particular ionic or other contaminant content. Figures 8A-8C illustrate packaging of a transistor device 1000, which may include any of the transistor structures 200, 300, and 400 described herein.

[0138] In particular, Figure 8A is a schematic side view of a package 800A for a III-nitride-based RF transistor amplifier. As shown in Figure 8A, the packaged RF transistor amplifier 800A includes an RF transistor amplifier die 1000 packaged in an open cavity package structure 810A. The package structure 810A includes a metal gate lead 822A, a metal drain lead 824A, a metal submount 830, sidewalls 840, and a lid 842.

[0139] Submount 830 may include a material configured to aid in thermal management of package 800A. For example, submount 830 may include copper and / or molybdenum. In some embodiments, submount 830 may be comprised of multiple layers and / or may include vias / interconnects. In an exemplary embodiment, submount 830 may be a multi-layer copper / molybdenum / copper metal flange including a core molybdenum layer with copper cladding layers on each major surface thereof. In some embodiments, submount 830 may include a metal heat sink that is part of a lead frame or metal slug. Sidewall 840 and / or lid 842 may be formed from or include an insulating material in some embodiments. For example, sidewall 840 and / or lid 842 may be formed from or include a ceramic material. In some embodiments, sidewall 840 and / or lid 842 may be formed from, for example, Al2O3. The lid 842 may be adhered to the sidewall 840 using epoxy glue. The sidewall 840 may be attached to the submount 830 via brazing, for example. The gate lead 822A and the drain lead 824A may be configured to pass through the sidewall 840, although embodiments of the present invention are not limited thereto.

[0140] The RF transistor amplifier die 1000 is mounted on top of the metal submount 830 in an air-filled cavity 812 defined by the metal submount 830, ceramic sidewalls 840, and ceramic lid 842. The gate and drain terminals 132, 134 of the RF transistor amplifier die 1000 are on the top side of the semiconductor structure 190, while the source terminal 136 is on the bottom side of the semiconductor structure 190. The source terminal 136 may be mounted to the metal submount 830 using, for example, a conductive die attach material (not shown). The metal submount 830 may provide an electrical connection to the source terminal 136 and may also function as a heat dissipation structure to dissipate heat generated in the RF transistor amplifier die 1000.

[0141] An input matching circuit 850 and / or an output matching circuit 852 may also be mounted within the package 800A. The matching circuits 850, 852 may include impedance matching and / or harmonic termination circuits. The impedance matching circuit may be used to match the impedance of the fundamental component of the RF signal input to or output from the RF transistor amplifier to the impedance at the input or output, respectively, of the RF transistor amplifier die 1000. The harmonic termination circuit may be used to ground harmonics of the fundamental RF signal that may be present at the input or output of the RF transistor amplifier die 1000. Two or more input matching circuits 850 and / or output matching circuits 852 may be provided. As shown schematically in FIG. 8A , the input and output matching circuits 850, 852 may be mounted on a metal submount 830. Gate lead 822A may be connected to an input matching circuit 850 by one or more bond wires 854, which may be connected to the gate terminal 132 of RF transistor amplifier die 1000 by one or more additional bond wires 854. Similarly, drain lead 824A may be connected to an output matching circuit 852 by one or more bond wires 854, which may be connected to the drain terminal 134 of RF transistor amplifier die 1000 by one or more additional bond wires 854. Bond wires 854, which are inductive elements, may form part of the input and / or output matching circuits.

[0142] A multi-layer environmental barrier 160 as described herein may be formed on the top side of the semiconductor structure 190 and patterned to expose the gate and drain terminals 132, 134. The multi-layer environmental barrier 160 may include, for example, two or more sub-layers of respective insulating materials in a repeating layer structure, as described above. The composition and / or thickness of the sub-layers, the number of sub-layers, and / or the number of periods may vary based on the ionic content or other contaminants that may be present in the particular package type 800A, 800B, 800C.

[0143] 8B is a schematic side view of a packaged III-nitride-based RF transistor amplifier 800B including a transistor device 1000 packaged in a printed circuit board-based packaging structure 810B. The packaged RF transistor amplifier 800B is very similar to the packaged RF transistor amplifier 800A of FIG. 8A, except that the gate and drain leads 822A, 824A of the packaging structure 810A are replaced with printed circuit board-based leads 822B, 824B in the packaging structure 810B.

[0144] The package structure 810B includes a submount 830, a ceramic sidewall 840, and a ceramic lid 842, each of which may be substantially identical to the like-numbered elements of the package structure 810A discussed above. The package structure 810B further includes a printed circuit board 820. Conductive traces on the printed circuit board 820 form a metal gate lead 822B and a metal drain lead 824B. The printed circuit board 820 may be attached to the submount 830 via, for example, conductive glue. The printed circuit board 820 includes a central opening, and the RF transistor amplifier die 1000 is mounted within this opening in the submount 830. The other components of the RF transistor amplifier 800B may be the same as the like-numbered components of the RF transistor amplifier 800A, and therefore further description thereof will be omitted.

[0145] 8C is a schematic side view of another packaged III-nitride-based RF transistor amplifier 800C. RF transistor amplifier 800C differs from RF transistor amplifier 800A by including a different packaging structure 810C. Package structure 810C includes a metal submount 830 (which may be similar or identical to submount 830 of package structure 810A) and metal gate and drain leads 822C, 824C. RF transistor amplifier 800C also includes a plastic overmold 860 that at least partially encloses RF transistor amplifier die 1000, leads 822C, 824C, and metal submount 830. Other components of RF transistor amplifier 800C may be the same as the similarly numbered components of RF transistor amplifier 800A, and therefore will not be described further.

[0146] 9 is a schematic plan view of a transistor device or die 1000 showing metallization on the surface of a semiconductor structure 190. Multilayer environmental barrier 160 and / or other dielectric layers provided as described herein to separate various conductive elements of the metallization structure from one another are not shown in FIG. 9 to simplify the drawing.

[0147] 9, a transistor device or die 1000 may include multiple transistor structures 900 connected in parallel to device terminals or electrodes (e.g., input, output, and ground terminals). For example, each of the gate 110, drain 105, and source 115 contacts may extend in a first direction (e.g., the Y direction) to define gate, drain, and / or source "fingers," which may be connected by one or more respective buses (e.g., gate bus 112 and drain bus 114 on the top surface of semiconductor structure 190).

[0148] 9, gate fingers 110, drain fingers 105, and source fingers 115 extend parallel to one another, with gate fingers 110 extending in a first direction from gate bus 112 and drain fingers 105 extending in a direction opposite the first direction from drain bus 114. Each gate finger 110 may be positioned between a drain finger 105 and a source finger 115 to define a unit cell 900, such as a unit cell transistor structure 200, 300, 400 described herein. Gate fingers 110, drain fingers 105, and source fingers 115 (and connecting buses) may define portions of the gate-connected, drain-connected, and source-connected electrodes of the device, respectively, as defined by top-side or front-side metallization structures. It can be seen that the unit cell transistors 900 are electrically connected together in parallel, with the gate fingers 110 electrically connected to a common gate bus 112, the drain fingers 105 electrically connected to a common drain bus 114, and the source fingers 115 electrically connected together (e.g., via respective via openings 146 and a backside metal layer on the backside of the substrate 122).

[0149] One of the device's terminals (e.g., the source terminal connected to the source contact 115) may be configured to be coupled to a reference signal, such as electrical ground. In some embodiments, a conductive through-substrate via connection or structure (e.g., a backside via opening formed through the backside) may penetrate the substrate 122 and the epitaxial layers 124, 126, thereby ejecting a portion of one of the contacts 105, 115 and enabling contact with a pad or terminal on the backside of the substrate (e.g., to couple the source contact 115 to ground). In other embodiments, a ground connection to one of the device's terminals (e.g., the source terminal) may be provided outside the active area, e.g., in a peripheral region. In some embodiments, a backmetal layer on the backside of the substrate 122 may provide a backside ground plane, e.g., in applications where proximity to ground may be desired.

[0150] Further embodiments of the present invention arise from the recognition that moisture protection can be improved by increasing the thickness of the environmental barrier film. However, in some single-layer environmental barrier films, increased thickness also increases uniaxial static film stress during operation, which can reduce or degrade device lifetime. For example, as discussed herein, SiN deposited by CVD may be used as an environmental barrier film. CVD-based SiN films may contain a certain type of stress (e.g., tensile or compressive) that can be tailored by adjusting deposition conditions (e.g., temperature), but the magnitude of the stress may increase with the thickness of the SiN layer. Increased stress can adversely affect device characteristics, for example, in the transistor channel region. In particular, in HEMT devices, stress can affect carrier density in the 2DEG channel, which can result in device performance degradation.

[0151] As used herein, the term "stress" may refer to the force exerted between adjacent particles of a material (e.g., induced by an intrinsic force from an overlying or underlying layer), while "strain" may refer to a measure of deformation of a material (e.g., due to stress from a layer). Embodiments of the present invention may provide a stress-compensated multilayer encapsulation structure or environmental barrier configured to reduce or minimize stress while also providing moisture protection comparable to or better than some conventional environmental barrier films in some embodiments. For example, uniaxial stress can be reduced or minimized by providing multiaxial stress (e.g., uniaxial, biaxial, or triaxial) in multilayer thin films as described herein. Overall stress may be compensated for by fabricating sublayers of a multilayer environmental barrier to provide different types and / or directional stresses in each sublayer, such that each sublayer may compensate for the stress provided by the sublayers above and / or below it in the stack.

[0152] As used herein, a layer or sublayer that "compensates" for the stress of another layer or sublayer may include a stress that opposes (with respect to type and / or direction) or otherwise at least partially compensates for or counteracts a particular type and / or direction of stress in the other layer or sublayer. That is, a multilayer environmental barrier film as described herein may include sublayers having respective stresses that vary in type (e.g., tensile or compressive) and / or direction (e.g., X, Y, and / or Z directions). For example, advanced deposition techniques such as atomic layer deposition (ALD) may be used to form multilayer films having sublayers of different materials, whereby each sublayer has a respective stress that differs from that of the sublayer above or below. ALD may be used to form sublayers of different materials in various combinations, including two-layer, three-layer, and four-layer stacks. Multilayer environmental barriers as described herein may be configured to provide stress reduction alone or in combination with the diffusion barrier properties (e.g., moisture protection) described herein.

[0153] 10 is an expanded view of a transistor device showing in more detail an exemplary combination of stress compensation sublayers in a multi-layer environmental barrier formed on a semiconductor body according to some embodiments of the present invention. First and second stressor sublayers 160a are alternately stacked on an optional passivation layer or layer structure 150. (6) , 160b (6) 160 double-layer periodic structures including (6) 10, this structure 160 (6) are shown by way of example only and are not intended to be limiting of the above-described multi-layer environmental barriers 160', 160'', 160''', 160 (4) , 160 (5) Regarding multi-layer environmental barrier 160 (6)It will be understood that (collectively 160) may include three or more stressor sublayers having different respective stresses (e.g., defining a three-layer structure, a four-layer structure), and / or may be stacked directly on the semiconductor body 190 and gate 110, drain 105 and source 115 contacts, or on optional intervening passivation layers 150, in a non-repeating layer structure or a periodic or aperiodic repeating layer structure.

[0154] In the example of FIG. 10, a multi-layer environmental barrier 160 (6) Each period has a different stress type and / or direction. (6) and second sublayer 160b (6) Stressor sublayers 160a of each material alternately stacked to define a periodic repeating layer structure including (6) , 160b (6) The first and second stressor sublayers 160a include a stack of (6) , 160b (6) Each of the materials in the first stressor sublayer 160a may be configured to provide a stress that at least partially counteracts or compensates for the type and / or direction of stress in the other. (6) may be an AlO film, and the second stressor sublayer 160b (6) and may be SiO films (e.g., having tensile and compressive stresses, respectively) and may be formed alternately as a bilayer stack in a repeating layer structure using a relatively simple and stable ALD process.

[0155] As shown in FIG. 10, the first stressor sublayer 160a (6) may contain tensile stress (indicated by opposite arrows pointing away from each other along the X direction), whereas the second stressor sublayer 160b (6) is the first stressor sublayer 160a (6)The multilayer environmental barrier 160 may include compressive stresses (indicated by the facing arrows pointing towards each other along the X direction) that can at least partially compensate for the tensile stresses of the (6) The overall or collective stress of each stressor sublayer 160a is reduced or minimized. (6) , 160b (6) The material, thickness and / or manufacturing process of each sub-layer 160a (6) , 160b (6) The stress in each sublayer may be selected such that stress in the sublayer, etc., is at least partially counteracted by the sublayer immediately above and / or below. As such, it will be understood that the stress direction of each sublayer is shown by way of example only and can be varied to provide a desired type and / or direction of stress by varying deposition conditions and post-treatments (e.g., annealing). More generally, although sublayers may be described and illustrated herein with respect to a particular stress type (e.g., tensile or compressive) and / or stress direction (e.g., X, Y, and / or Z directions), the sublayers may have stress types opposite and / or different directions from those shown, depending on the selected fabrication process and / or conditions.

[0156] In the example of FIG. 10, the first stressor sublayer 160a (6) The material of sublayer 160a (6) may be selected and deposited to have tensile stress, e.g., as induced by intrinsic forces from underlying layers. For example, in some embodiments, one or more selective passivation layers 150 (e.g., CVD-based SiN) may be added to the multi-layer environmental barrier 160 to passivate surface states and / or otherwise improve electrical properties along the surface of the semiconductor body 190. (6) The passivation layer 150 may be formed on the surface of the semiconductor body 190 before the gate 110, source 115, and drain 105 contacts. However, the passivation layer 150 may introduce additional stress (e.g., compressive stress from the SiN-based passivation layer 150).

[0157] Still referring to FIG. 10, the second stressor sublayer 160b (6) The material of sublayer 160b (6) However, for example, the underlying first sublayer 160a (6) In some embodiments, the passivation layer 150 may be omitted and the multi-layer environmental barrier 160 may be used. (6) Stressor sublayer 160a (6) , 160b (6) The stressor sublayer 160a of the multi-layer environmental barrier 160 may be formed directly on the surface of the semiconductor body 190 and the gate 110, the source contact 115, and the drain contact 105, for example, conformally with substantially uniform thicknesses T1 and T2, respectively. (6) , 160b (6) It will be understood that the sub-layers may be implemented in the stack in any order, such that the stress of each sub-layer at least partially opposes or compensates for the stress of the layer above or below it in the stack.

[0158] Multi-layer Environmental Barrier 160 (6) Stressor sublayer 160a defining a repeating layer structure of (6) , 160b (6) may have the same or different thicknesses from one another. In some embodiments, the multi-layer environmental barrier 160 (6) At least two of the sublayers of each period may have different thicknesses. In particular, Figure 10 shows a two-layer periodic layer structure, in which the first tensile stress material sublayer 160a (6) However, the second compressive stress material sublayer 160b (6) Similarly, the multilayer environmental barrier 160 may be deposited with a thickness T1 greater than the thickness T2 of the multilayer environmental barrier 160. (6) may each include three or four sublayers, where at least two of the sublayers in each period may differ in thickness and / or stress.

[0159] First sublayer 160a (6) the thickness T1 of the second sublayer 160b (6) The ratio of the thickness T2 of the first sublayer 160a to the thickness T3 of the second sublayer 160b may be varied depending on or based on the magnitude of the stress in each sublayer and the compensating stress of the sublayer above or below it. (6) the thickness T1 of the second sublayer 160b (6) The ratio of the thickness T2 of the stressor sublayer 160a to the thickness T2 of the stressor sublayer 160a may be about 1:1, about 1:2, about 1:5, about 1:8, or about 1:10 or more. (6) , 160b (6) The thickness ratio of the stressor sublayer 160a (6) , 160b (6) The strain of each of the different materials may depend on or be based on the stress and effect it provides to layers above or below it. It will be understood that the relative sizes or dimensions are shown by way of example only and are not intended to be limiting with respect to atomic size, density, or other properties of the layers. Also, while shown primarily for simplicity with respect to uniaxial or biaxial strain (e.g., in the X and / or Y directions), it will be understood that the sublayers described herein may be strained in additional directions and / or in directions other than those specifically shown (e.g., triaxial strain in the X, Y, and Z directions).

[0160] In some embodiments, the multi-layer environmental barrier 160 (6) may be configured to provide stress reduction in combination with diffusion barrier properties (e.g., moisture protection). (6) the thickness T1 of the second sublayer 160b (6) The ratio of thickness T1 to thickness T2 may be about 2:1, about 5:1, about 8:1, or about 10:1 or more, as described above with respect to the embodiments of FIGS. 5A-5E.

[0161] For example, as described above with reference to FIG. 5A, first stressor sublayer 160a (6) may comprise a relatively dense material (e.g., AlO, HfO, ZrO, or other metal-rich insulating material), and the second stressor sublayer 160b (6)may comprise a relatively low density material (e.g., SiO, SiN, or other metal-poor insulating material). (6) , 160b (6) may have a density higher than SiN, while stressor sublayer 160a (6) , 160b (6) Another of the first dense material sublayer 160a may have a density equal to or less than that of SiN. When configured to provide stress reduction in combination with moisture protection, the first dense material sublayer 160a (6) may be deposited first at a greater thickness T1, followed by the second, lower density material sublayer 160b. (6) is deposited to a smaller thickness T2, thereby forming the first stressor sublayer 160a (6) but the second stressor sublayer 160b (6) and the semiconductor body 190 .

[0162] In some embodiments, the first and second stressor sublayers 160a, as described above with reference to FIG. 5B, (6) , 160b (6) may be oxide materials stacked alternately to define a periodic repeating layer structure. For example, as described above with reference to FIG. 5C, first and second stressor sublayers 160a (6) , 160b (6) may include insulating metal oxide materials or layers (e.g., AlO, HfO, or ZrO) and insulating non-metal (e.g., metalloid) oxide materials or layers (e.g., SiO) alternately stacked in a periodic, repeating layer structure, where the metal oxide sublayers may improve the susceptibility of the non-metal oxide sublayers to oxidation, etching, and / or corrosion. In some embodiments, first and second stressor sublayers 160a may be formed as described above with reference to FIG. 5D. (6) , 160b (6) may include respective nitride materials stacked alternately to define a periodically repeating layer structure, and the respective nitride materials of the sub-layers may differ from each other in material composition.

[0163] Multi-layer Environmental Barrier 160 (6) Stressor sublayer 160a (6) , 160b (6) may not be limited to insulating layers. For example, as described above with reference to FIG. 5E, one or more metal layers may be formed in the stack to provide desired tensile or compressive stress in one or more desired directions, based on, for example, material selection and / or deposition process as described herein. In this manner, the multilayer environmental barrier 160 (6) are first sublayers 160a of insulating metal oxide material (e.g., AlO, HfO, or ZrO) alternately stacked in a periodic repeating layer structure. (6) and a second sublayer 160b of a metallic material (e.g., Al, Au). (6) and metal sublayer 160b (6) may provide a more effective barrier to moisture ingress.

[0164] A multi-layer environmental barrier 160 according to an embodiment of the present invention (6) It will be appreciated that the stressor sublayer 160a is not limited to the specific sublayer material combinations described with respect to the above examples. For example, in some embodiments, the stressor sublayer 160a (6) , 160b (6) Multi-layer environmental barrier 160 (6) More generally, the multi-layer environmental barrier 160 may comprise alternating organic and inorganic materials stacked to define a (6) may include any combination of sublayers configured to at least partially counteract the stresses of the sublayers above and / or below it.

[0165] In some embodiments, the multi-layer environmental barrier 160 (6) The two or more sublayers may be formed by a conformal deposition process such as ALD (including, but not limited to, thermal ALD and plasma-enhanced ALD (PEALD) processes). For example, the stressor sublayer 160a shown in FIG. (6) , 160b (6)7A-7D, the ALD process deposits a first stressor sublayer 160a on a transistor structure including a gate 110, a source contact 115, and a drain contact 105 on a semiconductor body 190 (shown for a HEMT device). (6) (more generally shown as 160a) is conformally deposited on the surface of the first insulating sublayer 160a, and a second stressor sublayer 160b is deposited on the surface of the first insulating sublayer 160a. (6) (more generally shown as 160b). More specifically, by alternating exposure to reactant A (as shown in FIG. 7B) and reactant B (as shown in FIG. 7C), a thin-film multilayer environmental barrier 160 including alternating stressor sublayers 160a and 160b in a repeating (e.g., two-layer) layer structure is deposited with substantially uniform thickness and high conformality over complex underlying shapes or structures, as shown in FIG. 7D. Additional reactants may be included in the alternating exposures to deposit three- or four-layer repeating layer structures. In some embodiments, at lower temperatures, the ALD process shown in FIGS. 7B and 7C may produce amorphous stressor sublayer films, which may then be crystallized. For example, the first stressor sublayer 160a may be deposited as amorphous AlO, which may be crystallized to form AlO. The second stressor sublayer 160b may be deposited as amorphous SiOx, which may be crystallized to form SiO2.

[0166] Although primarily described in the examples above with respect to ALD-based fabrication, the multi-layer environmental barrier 160 (6) Stressor sublayer 160a (6) , 160b (6) It will be appreciated that the multilayer film 160 may be formed by deposition methods other than ALD. For example, in some embodiments, the multilayer film 160 may be formed by deposition methods other than ALD. (6) However, CVD may be used to form a thinner CVD-based sublayer 160a. (6) , 160b(6) may be too porous to provide the desired moisture barrier performance, whereas a thicker CVD-based sublayer 160a (6) , 160b (6) Also, although the quality of the CVD-based barrier film 160 may be improved by fabrication at higher temperatures, such temperatures may be detrimental to the properties and / or operation of the devices in the underlying semiconductor layer structure 190.

[0167] 11 is a graph showing normalized stress measurements over heating and cooling temperature changes for a conventional monolayer film formed by CVD (also referred to herein as a CVD-based monolayer film) and a multilayer environmental barrier formed by ALD in accordance with some embodiments of the present invention, where the initial stress is normalized to zero. For example, a highly accelerated life testing (HAST) process may involve heating and cooling a device over an operating temperature range of up to about 400 degrees Celsius (°C) or more.

[0168] As shown in FIG. 11 , a conventional CVD-based monolayer film (e.g., a SiN-based film) may exhibit a stress change 1110 of approximately 235 megapascals (MPa) during heating and cooling over a normalized operating temperature range from room temperature (25° C.) to a maximum device operating temperature. In contrast, FIG. 11 shows that an ALD-based multilayer AlOx and SiOx environmental barrier film according to some embodiments of the present invention may exhibit a stress change 1160 of only approximately 40 MPa during heating and cooling over the same room temperature to maximum device operating temperature range. Thus, environmental barrier films according to some embodiments of the present invention may exhibit reduced stress (and smaller changes in stress) over the temperature range that may be experienced in device operation due to the overall compensating stress provided by their multiple stressor sublayers compared to CVD-based monolayer SiN films. That is, multilayer environmental barrier films according to embodiments of the present invention may exhibit lower levels of stress and / or less stress change (and therefore greater stability) over device operating conditions than some conventional monolayer films, which may reduce the operating lifetime of the device.

[0169] The multilayer environmental barrier and monolayer films shown in the graph of Figure 11 may have different thicknesses and / or other properties that provide one or more similar diffusion barrier properties (e.g., similar or equivalent moisture protection). For example, conventional techniques may provide environmental barrier films using CVD-based SiNx, which may require a larger thickness (e.g., about 5000 Å to about 10,000 Å) to provide the desired level of moisture protection and therefore may result in a higher uniaxial stress (e.g., a difference of about 235 MPa before and after heating and cooling in this example). In contrast, multilayer environmental barrier films such as those described herein (e.g., including alternating layers of ALD-based AlOx and SiOx) can provide significantly reduced stress (less than or even negligible due to measurement tolerances) at comparable or superior moisture robustness, in some instances at a smaller overall thickness (e.g., about 500 Å to about 3500 Å, e.g., about 1000 Å to about 3000 Å or about 1500 Å to about 2500 Å). In other words, the collective stress of the sublayers 160a, 160b of the multilayer environmental barrier 160 can be less than the collective stress of one or more SiN layers that provide similar diffusion barrier properties over a temperature range from about room temperature (25°C) to maximum device operating temperature in some instances. The sublayers can be deposited using non-ALD techniques in some instances.

[0170] Multilayer environmental barrier stacks (e.g., two-layer stacks, three-layer stacks, four-layer stacks, etc.) according to embodiments of the present invention can therefore provide comparable or superior diffusion barrier properties at lower collective stress and / or smaller thickness compared to SiN films. As noted above, the multilayer environmental barrier is not limited to alternating AlOx and SiOx sublayers, but may alternatively include HfO, ZrO, and / or SiN sublayers, and / or other sublayers, depending on the desired compensation stress and / or orientation.

[0171] Embodiments of the present invention, including multilayer environmental barrier structures as described herein, may provide improved performance in passive and / or active RF devices. However, embodiments of the present invention are not limited to RF applications and may be used in a variety of other applications, including any semiconductor IC technology that may require moisture robustness. For example, embodiments of the present invention may be used in applications having operating frequencies ranging from below about 6 GHz to Ku-band (6-18 GHz) and Ka-band designs (e.g., 26-40 GHz). Certain embodiments of the present invention may be used in various cellular infrastructure (CIFR) RF power products (including, but not limited to, 5 W, 10 W, 20 W, 40 W, 60 W, 80 W, and different frequency bands), including macro (e.g., 20-80 W and different frequency bands) average power applications, for example, 5G and base station applications. Embodiments of the present invention may also be applied to radar, monolithic microwave integrated circuit (MMIC) type applications, dielectric crossover devices, and split-gate devices. More generally, embodiments of the present invention may be used in any semiconductor IC technology requiring moisture robustness and / or stress reduction.

[0172] The present invention will now be described with reference to the accompanying drawings, in which embodiments of the invention are shown. However, the present invention should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Like numbers refer to like elements throughout.

[0173] When an element, such as a layer, region, or substrate, is described as being "on" or extending "upon" another element, it will be understood that the element can be directly on or extending directly onto the other element, or intervening elements may be present. In contrast, when an element is described as being "directly on" or extending "directly onto" another element, there are no intervening elements present. When an element is described as being "connected" or "coupled" to another element, it will also be understood that the element can be directly connected or coupled to the other element, or there may be intervening elements present. In contrast, when an element is described as being "directly connected" or "directly coupled" to another element, there are no intervening elements present.

[0174] It will also be understood that, although terms such as "first," "second," etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, a first element can be referred to as a second element, and similarly, a second element can be referred to as a first element, without departing from the scope of the present invention.

[0175] Additionally, relative terms such as "lower" or "bottom" and "upper" or "upper" may be used herein to describe the relationship of one element to another element depicted in the figures. It will be understood that the relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the figures. For example, if a device in one of the figures is inverted, an element described as being on the "lower" side of the other element would be oriented on the "upper" side of the other element. Thus, the exemplary term "lower" encompasses both an orientation of "below" and "upper," depending on the particular orientation of the figure. Similarly, if a device in one of the figures is inverted, an element described as being "below" or "lower" of the other element would be oriented "upper" of the other element. Thus, the exemplary terms "lower" or "lower" can encompass both an orientation of upper and lower.

[0176] The terms used in the description of the invention herein are for the purpose of describing particular embodiments only and are not intended to limit the invention. As used in the description of the invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the term "and / or," as used herein, refers to and includes any and all possible combinations of one or more of the associated listed items. It will be further understood that the terms "comprises" and / or "comprising," when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0177] Embodiments of the invention are described herein with reference to cross-section illustrations that are schematic illustrations of idealized embodiments (and intermediate structures) of the invention. As such, variations from the shapes of the illustrations as a result, for example, of manufacturing techniques and / or tolerances, are expected. Thus, embodiments of the invention should not be construed as limited to the particular shapes of regions illustrated herein and include, for example, deviations in shape that result from manufacturing. For example, an implanted region illustrated as a rectangle typically has rounded or curved features at its edges and / or a gradient of implant concentration rather than a binary transition from implanted to unimplanted. Similarly, buried regions formed by implantation may, in some implantations, result in a region between the buried region and the surface through which the implantation occurs. Thus, the regions illustrated in the figures are schematic in nature, and their shapes are not intended to represent the actual shape of a region of a device, nor are they intended to limit the scope of the invention.

[0178] Unless otherwise specified, all terms used in disclosing embodiments of the invention, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which the invention pertains and are not necessarily limited to the specific definitions known at the time of the invention being described. Accordingly, these terms may include equivalent terms developed after such time. It will be further understood that terms as defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in this specification and in the context of the relevant art, and not in an idealized or overly formal sense unless expressly so defined herein. All publications, patent applications, patents, and other references mentioned herein are incorporated by reference in their entirety.

[0179] In the drawings and specification, exemplary embodiments of the invention have been disclosed and, although specific terms have been employed, they are used in a generic and descriptive sense only and not for purposes of limitation.

Claims

1. 1. A semiconductor die comprising: a semiconductor body; a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier including first and second sub-layers of first and second oxide materials, respectively, the first oxide material having a higher density and a greater thickness than the second oxide material; 1. A semiconductor die comprising:

2. The semiconductor die of claim 1 , wherein the first and second sub-layers comprise atomic layer deposition (ALD) layers.

3. The semiconductor die of claim 1 , wherein at least one of the first or second oxide materials has a density greater than silicon nitride.

4. The semiconductor die of claim 1 , wherein at least one of the first or second oxide materials comprises an insulating metal oxide.

5. 5. The semiconductor die of claim 4, wherein the first and second sub-layers are included in a repeating layer structure, and the first and second oxide materials comprise the insulating metal oxide and non-metal oxide, respectively.

6. The semiconductor die of claim 5 , wherein the insulating metal oxide comprises at least one of aluminum oxide, zirconium oxide, or hafnium oxide.

7. The semiconductor die of claim 5 , wherein the insulating metal oxide comprises aluminum oxide and the non-metal oxide comprises silicon oxide.

8. The semiconductor die of claim 5 , wherein a ratio of a thickness of the first sublayer to a thickness of the second sublayer is 2:1 or greater, 5:1 or greater, or 8:1 or greater.

9. The semiconductor die of claim 4 , further comprising a passivation layer between the semiconductor body and the multi-layer environmental barrier, the passivation layer comprising silicon nitride.

10. 10. The semiconductor die of claim 9, wherein a surface of the multi-layer environmental barrier opposite the passivation layer comprises a layer of silicon oxide or silicon nitride.

11. The semiconductor die of claim 1 , wherein the first oxide material has a different diffusion coefficient with respect to water than the second oxide material.

12. a gate, a source contact, and a drain contact on the semiconductor body; a passivation layer extending over the gate, the source contact, and the drain contact; Furthermore, 10. The semiconductor die of claim 1, wherein the first and second sublayers extend conformally over the passivation layer with substantially uniform respective thicknesses along the gate, the source contact, and the drain contact.

13. 10. The semiconductor die of claim 1, wherein the first and second sublayers are included in a repeating layer structure, and the multi-layer environmental barrier includes at least two of the repeating layer structures, at least ten of the repeating layer structures, or at least twenty of the repeating layer structures.

14. 14. The semiconductor die of claim 13, wherein the multi-layer environmental barrier has a total thickness between 500 Angstroms and 3000 Angstroms.

15. The repeating layer structure is a two-layer structure in which the first and second sublayers are stacked; a three-layer structure in which the first sublayer, the second sublayer, and the third sublayer are stacked; and / or a four-layer structure in which the first sublayer, the second sublayer, the third sublayer, and the fourth sublayer are stacked; 14. The semiconductor die of claim 13, comprising:

16. 1. A semiconductor die comprising: a semiconductor body; a multi-layer environmental barrier on the semiconductor body, the multi-layer environmental barrier comprising a repeating layer structure comprising two or more sub-layers of respective insulating materials; Equipped with at least one of the respective insulating materials has a density greater than silicon nitride, and the two or more sub-layers include atomic layer deposition (ALD) layers.

17. 17. The semiconductor die of claim 16, wherein the multi-layer environmental barrier comprises at least two of the repeating layer structures, at least ten of the repeating layer structures, or at least twenty of the repeating layer structures.

18. 17. The semiconductor die of claim 16, wherein the density and thickness of the at least one of the respective insulating materials is greater than the density and thickness of at least one other of the respective insulating materials.

19. 20. The semiconductor die of claim 18, wherein the at least one of the respective insulating materials comprises a metal oxide and the at least one other of the respective insulating materials comprises a non-metal oxide.

20. 20. The semiconductor die of claim 19, wherein the metal oxide comprises aluminum oxide, zirconium oxide, or hafnium oxide.

21. 21. The semiconductor die of claim 20, wherein the non-metal oxide comprises silicon oxide.

22. 22. The semiconductor die of claim 21, further comprising a passivation layer between the semiconductor body and the multi-layer environmental barrier, the passivation layer comprising silicon nitride.

23. 20. The semiconductor die of claim 17, wherein a ratio of a thickness of a first sublayer to a second sublayer of the two or more sublayers is 2:1 or greater, 5:1 or greater, or 8:1 or greater.

24. a gate, a source contact, and a drain contact on the semiconductor body; a passivation layer extending over the gate, the source contact, and the drain contact; Furthermore, 17. The semiconductor die of claim 16, wherein the two or more sublayers extend conformally over the passivation layer with substantially uniform respective thicknesses along the gate, the source contact, and the drain contact.

25. 17. The semiconductor die of claim 16, wherein at least two of the respective insulating materials have different diffusion coefficients with respect to water.

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