Semiconductor device

Abstract

To provide a semiconductor device that operates as a diode without being affected by negative potential.SOLUTION: A semiconductor device 1 includes a P-type substrate 10 to which a ground potential is supplied, a first PN junction diode D1, a first P-type well 31, a first N-type well 21, and an N-type well 40 for circuit elements. The first P-type well 31 is provided with a first PN junction diode D1, and the cathode of the first PN junction diode D1 is connected via a wiring layer. The first N-type well 21 is provided in the P-type substrate 10, and the first P-type well 31 is provided with a first constant potential. The N-type well 40 for circuit elements is provided in the P-type substrate 10, and a negative potential lower than the ground potential is supplied.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and the like. [Background technology]

[0002] Conventionally, semiconductor devices have been known in which P-type and N-type regions are formed on a semiconductor substrate to function as diodes and transistors. Patent Document 1 discloses a method of surrounding a diode with an N-well to which a power supply potential is applied and a grounded P-well, etc., in order to prevent the occurrence of a latch-up phenomenon in a MOS transistor when a negative potential occurs. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-055844 Summary of the Invention [Problem to be solved by the invention]

[0004] The technique of Patent Document 1 does not take into consideration preventing the latch-up phenomenon while suppressing a decrease in the degree of freedom in designing an IC chip. [Means for solving the problem]

[0005] One aspect of the present disclosure relates to a semiconductor device including: a P-type substrate to which a ground potential is supplied; a first PN junction diode; a first P-type well in which the first PN junction diode is provided and to which a cathode of the first PN junction diode is connected via a wiring layer; a first N-type well provided in the P-type substrate and in which the first P-type well is provided and to which a first constant potential is supplied; and an N-type well for a circuit element provided in the P-type substrate and to which a negative potential lower than the ground potential is supplied. [Brief explanation of the drawings]

[0006] [Figure 1] 1 is a cross-sectional view of a substrate illustrating an example of a semiconductor device according to an embodiment of the present invention; [Figure 2] FIG. 2 is a diagram illustrating the first PN junction diode in more detail. [Figure 3] 10A to 10C are diagrams illustrating an example of the operation of the present embodiment. [Figure 4] 10A to 10C are diagrams illustrating an example of the effect of the present embodiment. [Figure 5] FIG. 2 is a diagram illustrating an example of a temperature sensor circuit. [Figure 6] FIG. 10 is a diagram illustrating the temperature dependence of a predetermined voltage and a threshold voltage. [Figure 7] 10 is a cross-sectional view of a substrate illustrating another example of the semiconductor device according to the present embodiment. [Figure 8] 10 is a cross-sectional view of a substrate illustrating another example of the semiconductor device according to the present embodiment. [Figure 9] FIG. 2 is a diagram illustrating an example of an H-bridge circuit according to the semiconductor device of the present embodiment. [Figure 10] FIG. 10 is a diagram illustrating an example of a chopping operation of an H-bridge circuit. [Figure 11] FIG. 10 is a diagram illustrating another example of the chopping operation of the H-bridge circuit. [Figure 12] FIG. 10 is a diagram illustrating a current path that occurs during a dead time. [Figure 13] FIG. 10 is a diagram illustrating the operation of a temperature sensor circuit in a comparative example. [Figure 14] FIG. 2 is a diagram illustrating an example of a reference voltage generating circuit. DETAILED DESCRIPTION OF THE INVENTION

[0007] Preferred embodiments of the present disclosure will be described in detail below. Note that the embodiments described below do not unduly limit the scope of the claims, and not all of the configurations described in the embodiments are necessarily essential components.

[0008] FIG. 1 is a conceptual diagram illustrating a cross section of a substrate of a semiconductor device 1 according to this embodiment. The substrate of the semiconductor device 1 according to this embodiment is a P-type substrate 10, which is a silicon substrate containing impurities such as boron. The substrate serves as a base substrate for forming various elements and is connected to ground via a P-type region 10-P. That is, in the semiconductor device 1 according to this embodiment, a ground potential is supplied to the P-type substrate 10. For ease of explanation, FIG. 1 mainly shows a cross section at the time when the so-called front-end process is completed, and wiring layers, insulating layers, etc. formed in the so-called back-end process are omitted as appropriate. The same applies to FIGS. 7, 8, 10, 11, and 12, which will be described later.

[0009] A first N-type well 21 and an N-type well 40 for a circuit element are formed on a P-type substrate 10. The well is a region into which impurities are implanted and is provided below a circuit element or another well. The well in this embodiment may be realized by a so-called buried diffusion layer in which N-type or P-type impurities are implanted by ion implantation or the like and then thermally diffused under predetermined conditions, or may be realized by a so-called epitaxial layer formed by vapor phase growth.

[0010] In FIG. 1, a P-type region and an N-type region are formed in the N-type well 40 for circuit elements to function as elements. For example, in the example shown in FIG. 1, an N-type region 40-N and a predetermined P-type well 50 are formed in the N-type well 40 for circuit elements, and a P-type region 50-P and an N-type region 50-N are formed in the predetermined P-type well 50. The P-type region 50-P is provided to provide the potential of the predetermined P-type well 50. The N-type region 50-N is set to have the same potential as ground potential. By applying a positive potential to the gate indicated by A1, an N-type channel is formed in the predetermined P-type well 50, and a current of a level corresponding to the gate potential flows between the N-type region 50-N and the N-type region 40-N. As a result, an element functioning as an N-type MOS transistor is formed in the N-type well 40 for circuit elements in FIG. 1, with the N-type region 50-N as the source and the N-type region 40-N as the drain. As will be described later, the transistors formed in the N-type well 40 for circuit elements are specifically exemplified as DMOS (Double-Diffused Metal-Oxide-Semiconductor), but since a wide range of well-known techniques can be adopted, more specific structures are not shown.

[0011] Although the use of the semiconductor device 1 of this embodiment is not particularly limited, for example, when the semiconductor device 1 is used as an IC (Integrated Circuit) for a high-voltage regulator, a decay current occurs, and therefore a negative potential lower than the ground potential may be supplied to the circuit element N-type well 40. As will be described later, the technique related to the semiconductor device 1 of this embodiment is particularly effective when a negative potential is supplied to the circuit element N-type well 40.

[0012] 1, an N-type region 21-N and a first P-type well 31 are formed in the first N-type well 21. The N-type region 21-N is connected to a first stable power supply via a contact (not shown). In this embodiment, the potential of the first stable power supply is referred to as a first constant potential. That is, the first N-type well 21 is supplied with the first constant potential from the first stable power supply. The specific magnitude of the first constant potential will be described later.

[0013] 2, a P-type region 31-P and a diode N-type well 61 are formed in the first P-type well 31. An N-type region 61-N and a P-type region 61-P are formed in the diode N-type well 61. The components formed in the first P-type well 31 realize the function of a first PN junction diode D1. In the embodiments described later, for convenience of explanation, the "diode N-type well 61" may be read as the "first diode N-type well 61."

[0014] More specifically, as can be seen from the dotted-line frame in A20 of FIG. 2, a PNP transistor is formed by the P-type region 31-P, the N-type region 61-N, and the P-type region 61-P. More specifically, A20 of FIG. 2 shows a bipolar transistor in which the P-type region 31-P functions as the collector, the N-type region 61-N functions as the base, and the P-type region 61-P functions as the emitter. Here, the first PN junction diode D1 is formed by shorting the collector and base, causing the collector and emitter to function as a diode, a so-called diode connection. This allows the semiconductor device 1 to be manufactured without adding a dedicated manufacturing process for the diode. In other words, the first PN junction diode D1 can be formed using the same manufacturing process as the transistor formed in the circuit element N-type well 40.

[0015] In this case, the P-type region 61-P serving as an emitter is connected to a node on the anode side via a contact or the like (not shown). The wiring connected to the P-type region 31-P serving as a collector and the wiring connected to the N-type region 61-N serving as a base are short-circuited by a wiring layer (not shown) and connected to a node on the cathode side. The wiring layer is formed, for example, by a so-called back-end process.

[0016] In this embodiment, the cathode of the first PN junction diode D1 is referred to as the first cathode. The potential of the node connected to the first cathode, indicated by A2 in FIG. 1, is referred to as the first cathode potential. The magnitude of the aforementioned first constant potential is preferably higher than the magnitude of the first cathode potential. In other words, it is a potential equal to or higher than the first cathode potential of the first PN junction diode D1. In this case, the potential of the first N-type well 21 is higher than the potential of the first P-type well 31. In other words, because a reverse voltage is applied to the PN junction between the first P-type well 31 and the first N-type well 21, no current flows from the first cathode to the first N-type well 21. In the following examples, the potential of the node connected to the first cathode is exemplified as the ground potential. In this case, the node connected to the first cathode can also be referred to as a ground node.

[0017] As described above, the semiconductor device 1 of this embodiment includes a P-type substrate 10 to which a ground potential is supplied, a first PN junction diode D1, a first P-type well 31, a first N-type well 21, and an N-type well 40 for circuit elements. The first P-type well 31 is provided with a first PN junction diode D1, and the cathode of the first PN junction diode D1 is connected via a wiring layer. The first N-type well 21 is provided in the P-type substrate 10, and the first P-type well 31 is provided therein and is supplied with a first constant potential. The N-type well 40 for circuit elements is provided in the P-type substrate 10 and is supplied with a negative potential lower than the ground potential.

[0018] As described above, the semiconductor device 1 of this embodiment includes the P-type substrate 10, the first PN junction diode D1, the first P-type well 31, the first N-type well 21, and the circuit element N-type well 40, and thus can function as a diode, a transistor, or the like. Furthermore, since a ground potential is supplied to the P-type substrate 10, a negative potential is supplied to the circuit element N-type well 40, and a first constant potential is supplied to the first N-type well 21, a parasitic current path that does not interfere with the operation of the first PN junction diode D1 can be intentionally established. Specifically, for example, when a negative potential is supplied to the circuit element N-type well 40 as described above, a current flows from the P-type region 10-P connected to the ground node toward the N-type region 40-N, as shown by A31 in FIG. 3 . Furthermore, as shown in the dotted line frame in A32, the semiconductor device 1 of this embodiment can be treated as having a parasitic NPN bipolar transistor consisting of the N-type region 40-N, the P-type region 10-P, and the N-type region 21-N. As a result, the current shown in A31 corresponds to the base current of the NPN bipolar transistor, so the NPN bipolar transistor turns on, and a current path from the N-type region 21-N to the N-type region 40-N is generated as shown in A33.

[0019] 3 is a current flowing from the N-type region 21-N of the first N-type well 21, and therefore there is no current path from the first N-type well 21 to the first P-type well 31, and therefore the current generated at A33 in Fig. 3 does not affect the operation of the first PN junction diode D1 included in the first P-type well 31. In other words, even if a negative potential is supplied to the above-mentioned N-type well 40 for circuit elements, no current flows from the anode and cathode of the first PN junction diode D1 to the negative potential, and therefore the current does not affect the operation of the first PN junction diode D1.

[0020] This makes it possible to keep constant the current flowing through the first PN junction diode D1 when a negative potential is supplied to the above-described circuit element N-type well 40. In other words, when a negative potential is supplied to the circuit element N-type well 40, the accuracy of the current flowing through a predetermined diode, which is a diode to which the method of this embodiment is not applied, may decrease, and details will be described later with reference to FIGS.

[0021] This allows the first PN junction diode D1 to operate stably while improving the layout flexibility of the IC chip. The layout of an IC chip without applying the method of this embodiment is shown in A40 in FIG. 4. Specifically, there are circuit blocks shown in A41 and A42, and a negative potential may occur in each circuit block. That is, the element (not shown) included in the circuit block shown in A41 in FIG. 3 corresponds to the element included in the circuit element N-type well 40 in FIG. 1. Similarly, the element (not shown) included in the circuit block shown in A42 in FIG. 4 corresponds to the element included in the circuit element N-type well 40 in FIG. 1. A diode not applying the method of this embodiment would have had to be placed in the circuit block at the position shown in A43. The circuit block shown in A43 is separated from the circuit blocks shown in A41 and A42 by the distance shown in A44. The distance A44 is the distance at which the parasitic resistance becomes large enough that the amount of current flowing through the parasitic NPN bipolar transistor, caused by a negative potential for example, becomes negligible relative to the operation of a given diode. Therefore, a space of the size shown in A45 is required to arrange the circuit blocks A41, A42, and A43.

[0022] In this regard, when the method of this embodiment is applied, the layout of an IC chip can be as shown in A140 in FIG. 4. Specifically, suppose there are circuit blocks A141 and A142. The circuit block A141 is similar to the circuit block A41, and the circuit block A142 is similar to the circuit block A42. In this case, as described above, the operation of the first PN junction diode D1 to which the method of this embodiment is applied does not change due to the generation of a negative potential. Therefore, the first PN junction diode D1 according to the method of this embodiment can be placed in the circuit block at the position indicated by A143. As a result, only the space indicated by A145 is required to place the circuit blocks A141, A142, and A143. In this way, by applying the method of this embodiment, the degree of freedom in designing an IC chip is improved.

[0023] The first constant potential may also be equal to or higher than the first cathode potential, which is the potential of the cathode of the first PN junction diode D1. In this way, the potential of the first N-type well 21 becomes higher than the potential of the first P-type well 31, which is the first cathode, and a reverse voltage can be applied to the PN junction between the first P-type well 31 and the first N-type well 21. This prevents current from flowing from the first cathode to the first N-type well 21. This allows the first N-type well 21 at the first constant potential to block the current path from the first cathode to the negative potential of the circuit element N-type well 40.

[0024] The first PN junction diode D1 may also include a diode N-type well 61 provided in the first P-type well 31, an N-type region 61-N provided in the diode N-type well 61 and corresponding to the cathode, and a P-type region 61-P provided in the diode N-type well 61 and corresponding to the anode. In this way, the first PN junction diode D1 can be formed using the P-type region and N-type region formed in the process of forming the transistor, thereby simplifying the manufacturing process of the semiconductor device 1.

[0025] The technique of this embodiment can be applied, for example, so that the first PN junction diode D1 corresponds to a diode included in a temperature sensor circuit. That is, in the semiconductor device 1 of this embodiment, the first PN junction diode D1 is a diode used in the temperature sensor circuit. This allows accurate measurement of the temperature of a circuit block in which a negative potential may occur. Specifically, as described above, for example, in the layout diagram shown in A40 of FIG. 4, by placing a temperature sensor circuit at the position of the circuit block shown in A43, it is possible to measure the temperature regardless of whether a negative potential occurs. However, due to the distance shown in A44, the difference between the temperature detected by the temperature sensor and the actual temperature of the device placed in the circuit block shown in A41 becomes large.

[0026] In this regard, by applying the technique of this embodiment, a temperature sensor circuit can be placed in the circuit block indicated by A143 in the layout diagram indicated by A140 in FIG. 4 . This allows accurate measurement of the temperature of the device included in the circuit block indicated by A141 and the temperature of the device included in the circuit block indicated by A142. More specifically, when a negative potential occurs in the circuit block indicated by A141, a stable current flows through the diode included in the temperature sensor circuit in the circuit block indicated by A143, preventing a decrease in temperature measurement accuracy. The same applies when a negative potential occurs in the circuit block indicated by A142. More specifically, when a negative potential occurs in the circuit block indicated by A141, a current due to the negative potential flows through the N-type region 40-N of the circuit element N-type well 40 included in the circuit block indicated by A141. In this case, the current path from the anode and cathode of the first PN junction diode D1 included in the circuit block indicated by A143 to the N-type region 40-N is blocked by the first N-type well 21 at the first constant potential. As a result, the current flowing through the first PN junction diode D1 does not fluctuate, preventing a decrease in the accuracy of temperature measurement.

[0027] Specifically, the method of this embodiment can be applied to, for example, the temperature sensor circuit shown in A50 in Fig. 5. In other words, in the temperature sensor circuit shown in A50, the method of this embodiment can be applied so that the diode shown in A51 corresponds to the first PN junction diode D1 of this embodiment. The temperature sensor circuit shown in A50 in Fig. 5 further includes a current source 80 and a comparator 100 in addition to the diode shown in A51.

[0028] In the temperature sensor shown as A50 in FIG. 5, the anode of the diode shown as A51 is connected to a first node N1 and the cathode is connected to ground. The first node N1 is connected to a current source 80. The comparator 100 is connected to a first terminal T1 and a second terminal T2. The first terminal T1 is connected to the first node N1, and a predetermined voltage Va, which is the voltage of the first node N1, is input to the first terminal T1. The second terminal T2 is connected to a predetermined power supply line (not shown), and a threshold voltage Vb, described below, is input to the second terminal T2. The predetermined power supply line (not shown) will be described later. The current source 80 is provided between the first stable power supply (not shown in FIG. 5) and the first node N1. The cathode of the diode shown as A51 is connected to ground. In other words, the node shown as A52 is the node on the anode side of the diode shown as A51, and the node shown as A53 is the node on the cathode side of the diode shown as A51 and also the ground node.

[0029] The comparator 100 generates a binary output signal based on the relationship between the input predetermined voltage Va and the threshold voltage Vb. For example, the comparator 100 is configured to output a high-level predetermined signal when the predetermined voltage Va is lower than the threshold voltage Vb. In this way, for example, a control circuit (not shown) that receives the predetermined signal can determine that the sensed temperature is higher than the reference temperature and perform control to shut down the circuit that is the measurement target of the temperature sensor circuit.

[0030] Although the temperature sensor shown in A50 is configured to include a single diode, this is not limiting and the temperature sensor may include a circuit in which multiple diodes are connected in series. For example, the temperature sensor circuit shown in A60 in FIG. 5 includes a circuit in which the diode shown in A61 and the diode shown in A64 are connected in series. The anode of the diode shown in A61 is connected to the first node N1, the cathode of the diode shown in A61 is connected to the anode of the diode shown in A64, and the cathode of the diode shown in A64 is connected to ground. In other words, the node shown in A62 is the node on the anode side of the diode shown in A61, and the node shown in A63 is the node on the cathode side of the diode shown in A61. Similarly, the node shown in A65 is the node on the anode side of the diode shown in A64, and the node shown in A66 is the node on the cathode side of the diode shown in A65 and also the ground node. The method of this embodiment can be applied so that the diode shown in A61 and the diode shown in A64 each correspond to the first PN junction diode D1 of this embodiment.

[0031] The temperature sensor circuit shown in A60 of Fig. 5 includes the circuit in which the diode shown in A61 and the diode shown in A64 are connected in series, as well as the current source 80 and the comparator 100 described above. The explanation of the current source 80 and the comparator 100 in the temperature sensor circuit shown in A60 of Fig. 5 is similar to the explanation of the current source 80 and the comparator 100 in the temperature sensor circuit shown in A50, and therefore will be omitted. Note that the temperature sensor circuit shown in A60 is an example configured to include a circuit in which two diodes are connected in series, but the temperature sensor circuit may also be configured to include a circuit in which three or more diodes are connected in series.

[0032] The predetermined voltage Va in the temperature sensor circuit shown as A50 in FIG. 5 is generated by a voltage drop caused by a constant current flowing through the diode shown as A51. The magnitude of this voltage drop decreases with increasing temperature due to the nature of PN junction diodes. The predetermined voltage Va in the temperature sensor circuit shown as A60 in FIG. 5 is generated by a voltage drop caused by a constant current flowing through the diode shown as A61 and a voltage drop caused by a constant current flowing through the diode shown as A62. In this way, by connecting diodes in series, the magnitude of the predetermined voltage Va can be adjusted to a desired value.

[0033] The threshold voltage Vb is generated by regulating the voltage output from a temperature-independent voltage generating circuit, such as a bandgap reference circuit, to a desired level. In other words, the predetermined power supply line is a power supply line connected to the temperature-independent voltage generating circuit. The threshold voltage Vb may also be generated using a reference voltage generating circuit 200, which will be described later with reference to FIG. 14.

[0034] From the above, the relationship between the predetermined voltage Va and the threshold voltage Vb in the temperature sensor circuit of FIG. 5 is as shown in FIG. 6. In FIG. 6, with temperature on the horizontal axis and voltage on the vertical axis, the predetermined voltage Va decreases linearly with increasing temperature, while the threshold voltage Vb is represented by a straight line parallel to the horizontal axis. As a result, these two voltage lines intersect at temperature TE. That is, as described above with reference to FIG. 5, when the ambient temperature of the temperature sensor circuit reaches temperature TE, the comparator 100 outputs a high-level predetermined signal. In this way, by setting temperature TE to a reference temperature that requires the circuit being measured by the temperature sensor circuit to be shut down, overheating of the circuit block being measured by the temperature sensor can be prevented. In other words, the predetermined voltage Va and the threshold voltage Vb are set so that temperature TE can be set to the desired temperature.

[0035] As described above, in the semiconductor device 1 of this embodiment, the temperature sensor circuit includes a first PN junction diode D1 provided between the first node N1 and the ground node, a current source 80 that supplies a current to the first node N1, and a comparator 100 whose first terminal T1 is connected to the first node N1 and whose second terminal T2 receives the threshold voltage Vb. This configuration allows for the construction of a temperature sensor circuit in which the comparator 100 compares a voltage (predetermined voltage Va) generated by flowing a current from the current source 80 to the first PN junction diode D1 with the threshold voltage Vb, while stabilizing the operation of the first PN junction diode D1.

[0036] 5, the diode indicated by A61 and the diode indicated by A64 may be configured as separate circuit blocks in the chip layout, although this is not shown. In this case, the semiconductor device 1 may be configured as shown in the cross-sectional view of FIG. 7, for example. In FIG. 7, in addition to the first PN junction diode D1 configured as in FIG. 1, a second PN junction diode D2 is also configured.

[0037] The second PN junction diode D2 may be configured in the same manner as the first PN junction diode D1. That is, the second N-type well 22 in FIG. 7 corresponds to the first N-type well 21, the second P-type well 32 corresponds to the first P-type well 31, and the second diode N-type well 62 corresponds to the first diode N-type well 61. Similarly, the N-type region 22-N corresponds to the N-type region 21-N, the P-type region 32-P corresponds to the P-type region 31-P, the N-type region 62-N corresponds to the N-type region 61-N, and the P-type region 62-P corresponds to the P-type region 61-P. The N-type region 22-N is connected to a second stable power supply via a contact (not shown). The potential supplied from the second stable power supply is referred to as a second constant potential.

[0038] In Fig. 7, by connecting the node on the cathode side of the first PN junction diode D1 to the node on the anode side of the second PN junction diode D2, the first PN junction diode D1 can be made to correspond to the diode shown in A61 of Fig. 5, and the second PN junction diode D2 can be made to correspond to the diode shown in A64 of Fig. 5. As a result, the node shown in A72 of Fig. 7 corresponds to the node shown in A62 of Fig. 5, the node shown in A73 of Fig. 7 corresponds to the node shown in A63 of Fig. 5, the node shown in A75 of Fig. 7 corresponds to the node shown in A65 of Fig. 5, and the node shown in A76 of Fig. 7 corresponds to the node shown in A66 of Fig. 5.

[0039] In this embodiment, the cathode of the second PN junction diode D2 is sometimes referred to as the second cathode, and the potential of the node connected to the second cathode (the node indicated by A76 in FIG. 7) is sometimes referred to as the second cathode potential. The magnitude of the second constant potential described above is preferably higher than the magnitude of the second cathode potential. As a result, the potential of the second N-type well 22 is higher than the potential of the second P-type well 32. In other words, since a reverse voltage is applied to the PN junction between the second P-type well 32 and the second N-type well 22, no current flows from the second cathode to the second N-type well 22.

[0040] Alternatively, the first PN junction diode D1 and the second PN junction diode D2 may be configured within one circuit block. In this case, the semiconductor device 1 may be configured as shown in the cross-sectional view of FIG. 8, for example. The example of FIG. 8 differs from the example of FIG. 7 in that both the first P-type well 31 and the second P-type well 32 are provided in the first N-type well 21. Furthermore, the example of FIG. 8 does not require the N-type region 22-N, and is therefore advantageous over the example of FIG. 7 in that an increase in chip area can be suppressed.

[0041] Also in the example of Fig. 8, by connecting the node on the cathode side of the first PN junction diode D1 to the node on the anode side of the second PN junction diode D2, the first PN junction diode D1 can be made to correspond to the diode shown in A61 of Fig. 5, and the second PN junction diode D2 can be made to correspond to the diode shown in A64 of Fig. 5. As a result, the node shown in A82 of Fig. 8 corresponds to the node shown in A62 of Fig. 5, the node shown in A83 of Fig. 8 corresponds to the node shown in A63 of Fig. 5, the node shown in A85 of Fig. 8 corresponds to the node shown in A65 of Fig. 5, and the node shown in A86 of Fig. 7 corresponds to the node shown in A66 of Fig. 5.

[0042] In the example of FIG. 8, the potential of the node indicated by A83 is the first cathode potential, and the potential of the node indicated by A86 is the second cathode potential. The first constant potential is preferably higher than the first cathode potential and higher than the second cathode potential. This establishes a relationship in which the potential of the first N-type well 21 is higher than the potential of the first P-type well 31, and the potential of the first N-type well 21 is higher than the potential of the first P-type well 31. As a result, a reverse voltage is applied to the PN junction between the first P-type well 31 and the first N-type well 21, and a reverse voltage is applied to the PN junction between the second P-type well 32 and the first N-type well 21, so no current flows from the first cathode to the first N-type well 21, and no current flows from the second cathode to the first N-type well 21.

[0043] As described above, the semiconductor device 1 of this embodiment includes the second PN junction diode D2 connected in series to the first PN junction diode D1, and the second P-type well 32 in which the second PN junction diode D2 is provided and to which the cathode of the second PN junction diode D2 is connected via a wiring layer. The first N-type well 21 is provided with the first P-type well 31 in which the first PN junction diode D1 is provided, and the second P-type well 32 in which the second PN junction diode D2 is provided. The first constant potential supplied to the first N-type well 21 is equal to or greater than the first cathode potential, which is the potential of the cathode of the first PN junction diode D1, and equal to or greater than the second cathode potential, which is the potential of the cathode of the second PN junction diode D2. This configuration allows for a diode that operates stably even when a negative potential occurs, while suppressing an increase in chip area.

[0044] The technique of this embodiment can also be applied to a case where a semiconductor device 1 including a bridge circuit shown in FIG. 9 generates a negative potential. More specifically, the bridge circuit shown in FIG. 9 is, for example, an H-bridge circuit, including a high-side P-type transistor indicated by A91, a low-side N-type transistor indicated by A92, a high-side P-type transistor indicated by A93, and a low-side N-type transistor indicated by A94. The bridge circuit of FIG. 9 drives an external load M externally connected to the semiconductor device 1. In this embodiment, a stepping motor including an inductor is illustrated as an example of the external load M, but the external load M is not limited to this. When the external load M is a stepping motor, the bridge circuit can be considered to constitute part of a motor driver circuit. In other words, when driving a stepping motor as the external load M, DMOS transistors capable of passing a large current can be used as the transistors indicated by A91, A92, A93, and A94.

[0045] The transistors A91, A92, A93, and A94 may each be controlled by a pre-driver circuit (not shown). The pre-driver circuit may be configured, for example, with a CMOS inverter circuit. The pre-driver circuit is controlled by a control signal output from a control circuit (not shown) and level-shifted via a level shifter (not shown). In FIG. 9, the diode A191 is a convenient illustration of a diode parasitic on the transistor A91. Similarly, the diode A192 is a diode parasitic on the transistor A92, the diode A193 is a diode parasitic on the transistor A93, and the diode A194 is a diode parasitic on the transistor A94.

[0046] For example, when the external load M is a stepping motor, a common technique is to drive the external load M using a chopping operation with a bridge circuit configured as shown in FIG. 9. For example, the external load M is driven by repeatedly performing the operation shown in M10 and the operation shown in M30 in FIG. 10. The period of operation shown in M10 in FIG. 10 is called the charge period, and the period of operation shown in M30 is called the fast decay period. Furthermore, the transistors shown in M11 and M31 in FIG. 10 correspond to the transistor shown in A91 in FIG. 9. Similarly, the transistors shown in M12 and M32 in FIG. 10 correspond to the transistor shown in A92 in FIG. 9, the transistors shown in M13 and M33 in FIG. 10 correspond to the transistor shown in A93 in FIG. 9, and the transistors shown in M14 and M34 in FIG. 10 correspond to the transistor shown in A94 in FIG. 9.

[0047] For convenience of the following explanation, the cross-sectional structure of the transistor designated M12 in FIG. 10 is shown as M110 in FIG. 10. Similarly, the cross-sectional structure of the transistor designated M32 in FIG. 10 is shown as M130 in FIG. 10. Similarly, the cross-sectional structure of the transistor designated M22 in FIG. 11 (described later) is shown as M120 in FIG. 11. As described above, since the transistor M12 is N-type, the N-type region 40-N in FIG. 10 functions as the drain of an N-type DMOS transistor and is supplied with a negative potential, as described later. Thus, in the semiconductor device 1 of this embodiment, the circuit element N-type well 40 is an N-type well in which the drain regions (N-type regions 40-N) of the N-type DMOS transistors (M12, M22, M32) are provided. This allows for the construction of a semiconductor device 1 that includes an N-type DMOS and a diode and allows the diode to operate stably even when a negative potential occurs.

[0048] As shown in M10 in Figure 10, during the charge period, the transistors M11 and M14 are turned on, and a charge current shown in M15 flows. Also, while the operation shown in M10 is being performed, the transistors M12 and M13 are off. In other words, no current flows through the transistor M12 during the charge period, as shown in the cross-sectional view of M110.

[0049] Furthermore, as shown in M30 in Figure 10, during the fast decay period, the transistors M31 and M34 are turned off, while the transistors M32 and M33 are turned on. This causes a decay current to flow as shown in M35. During the fast decay period, a current flows through the ground, N-type region 50-N, P-type well, and N-type region 40-N in the transistor M32, as shown in the cross-sectional view of M130. Thus, it is believed that no events that generate negative potential occur during the charge period or fast decay period.

[0050] However, when the bridge circuit configured as shown in FIG. 9 drives an external load M through chopping operation, there is an additional period during which the operation shown in M20 of FIG. 11 is performed. The period during which the operation shown in M20 of FIG. 11 is performed is called dead time. Note that the transistor shown in M21 of FIG. 11 corresponds to the transistor shown in A91 of FIG. 9. Similarly, the transistor shown in M22 of FIG. 11 corresponds to the transistor shown in A92 of FIG. 9, the transistor shown in M23 of FIG. 11 corresponds to the transistor shown in A93 of FIG. 9, and the transistor shown in M24 of FIG. 11 corresponds to the transistor shown in A94 of FIG. 9.

[0051] During the dead time indicated by M20 in FIG. 11, the transistors M21, M22, M23, and M24 are all off. The dead time is a period established to prevent a shoot-through current from flowing from the power supply to ground, which would occur if both the transistor M21 and the transistor M22 were on. During the dead time, similar to the fast decay period, a negative potential is generated in the external load M due to the energy stored in the inductor, and a decay current is generated due to the negative potential. However, because the transistors M21, M22, M23, and M24 are all off, these transistors cannot pass the decay current. In this case, as indicated by M25 in FIG. 11, the decay current flows in the following order: ground, the parasitic diode of the transistor M22, the external load M, and the parasitic diode of the transistor M23. In this case, the path of the decay current passing through the parasitic diode of the transistor shown as M22 can be, as shown in M125 in FIG. 11, a current path through ground, P-type region 50-P, and N-type region 40-N, or a current path through ground, P-type region 10-P, and N-type region 40-N. In other words, in the semiconductor device 1 of this embodiment, the negative potential is a potential set by the decay current of the inductor (external load M) connected to the drain (N-type region 40-N) of the N-type DMOS transistor. This allows for the semiconductor device 1 to stably operate as a diode when a negative potential that generates a decay current of the inductor occurs in the N-type DMOS.

[0052] As a comparative example, assume that a diode element, to which the method of this embodiment is not applied, is located near the transistor M22. "Nearby" here refers to a distance that provides a parasitic resistance sufficient to generate current, as described later in FIG. 12. Specifically, as shown in the dotted-line frame F10 in FIG. 11, assume that an element functions as a PN junction diode by diode-connecting an NPN bipolar transistor. In this case, for example, a P-type well shown in F12 is provided in the N-type well shown in F11. An N-type region 91-N is provided in the N-type well shown in F11, and a P-type region 92-P and an N-type region 92-N are provided in the P-type well shown in F12. The emitter and base are short-circuited to form the anode, and the collector is used as the cathode. This allows current to flow in the direction shown in F13 as a diode.

[0053] In this case, it can be considered that an NPN bipolar transistor exists as a parasitic element due to the N-type region 40-N, the P-type region 10-P, and the N-type region 91-N. Furthermore, the phenomenon in which a decay current flows from the P-type region 10-P to the N-type region 40-N due to a negative potential corresponds to the base current of an NPN bipolar transistor. Therefore, the parasitic NPN bipolar transistor turns on, creating a path for current to flow from the N-type region 91-N to the N-type region 40-N, as shown by M128 in FIG. 12. In other words, while a current would normally flow in the direction indicated by F13 in FIG. 11 as a diode element, the negative potential during the dead time causes the current that should flow as a diode element, as shown by F10, to flow as if it were included in the decay current.

[0054] This will be explained in more detail with reference to FIG. 13, whereby the diode element shown by F10 will no longer function as intended. With the H-bridge circuit configured as shown in FIG. 9, the voltage at the node (terminal) shown by M95 in FIG. 9 changes over time, as shown in the graph of F20 in FIG. 13, for example. In FIG. 13, the period from timing t0 to timing t1 corresponds to the charge period shown by M10 in FIG. 10. Also, in FIG. 13, the period from timing t1 to timing t2 corresponds to the dead time shown by M20 in FIG. 11. Also, in FIG. 13, the period after timing t2 corresponds to the fast decay period shown by M30 in FIG. 10. As mentioned above, a negative potential is generated during the period from timing t1 to timing t2.

[0055] For example, when the diode shown in F10 of FIG. 11 functions as the temperature-sensitive diode of the temperature sensor circuit shown in FIG. 5 and is subjected to the above-mentioned negative potential, the relationship between the predetermined voltage Va and the threshold voltage Vb changes as shown in the graph F30 of FIG. 13. More specifically, as described above in FIG. 11, the negative potential during the dead time causes current to flow through the P-type region 91-P, creating a current path from the anode of the diode shown in F10 of FIG. 11 to the N-type region 40-N, reducing the amount of current that the diode should normally pass. Furthermore, since the predetermined voltage Va drops below its intended voltage value as shown in F31 of FIG. 13, if the temperature is detected as TE even when the actual temperature is lower than TE, the comparator 100 outputs a high-level predetermined signal, as described above. As a result, the control circuit (not shown) that receives the predetermined signal determines that the sensed temperature is higher than the reference temperature, which may result in an unintended shutdown. For example, suppose the diode shown in F10 in Fig. 11 is used as the temperature sensor circuit in Fig. 5, and the bridge circuit shown in Fig. 9 is used with the stepping motor described above as the external load M. In this case, if the current flowing through the diode shown in F10 in Fig. 11 is the first current, and the decay current flowing through the drain of the N-type DMOS due to a negative potential is the second current, the magnitude of the second current is thought to be 1000 times or more the magnitude of the first current, so the first current will not actually flow.

[0056] In this regard, by applying the technique of this embodiment, as described above with reference to FIG. 3, when the above-mentioned negative potential occurs, a current flows through the P-type region 21-P provided in the first N-type well 21, while the magnitude of the current flowing through the first PN junction diode D1 provided in the first P-type well 31 can be prevented from changing. This makes it possible to stabilize the operation of the first PN junction diode D1. As a result, when the first PN junction diode D1 according to the technique of this embodiment is used as a diode in a temperature sensor, it is possible to stably measure temperature even when a negative potential occurs.

[0057] The technique of this embodiment may also be applied to, for example, a reference voltage generation circuit 200 shown in Fig. 14. More specifically, the reference voltage generation circuit 200 is a BGR (Bandgap Reference) circuit that generates and outputs a reference voltage that remains constant even when temperature fluctuates, using, for example, the bandgap voltage of a semiconductor. Note that the reference voltage generation circuit 200 in Fig. 14 may also be a semiconductor integrated circuit combined with, for example, a rectifier circuit, a regulator, and the like (not shown).

[0058] 14, the reference voltage generating circuit 200 includes an operational amplifier OP, a bipolar transistor BP1, and a bipolar transistor BP2. The operational amplifier OP is a differential amplifier circuit having a first input terminal which is an inverting input terminal and a second input terminal which is a non-inverting input terminal. For example, the operational amplifier OP can be configured by a differential circuit having a differential pair of transistors and an output circuit that outputs an output voltage based on a signal from the differential circuit. The operational amplifier OP differentially amplifies a first input voltage input to a first input terminal (not shown) and a second input voltage input to a second input terminal (not shown), and outputs an output voltage to an output terminal.

[0059] The bipolar transistor BP1 is a PNP-type bipolar transistor, and by shorting the base and collector, the PN junction between the emitter and base functions as a diode element. In other words, the method of this embodiment can be applied so that the diode element based on this PN junction corresponds to the first PN junction diode D1 of this embodiment. The emitter of the bipolar transistor BP1 in FIG. 14 serves as the anode and is connected to node NA1, which is the node of the first input terminal of the operational amplifier OP, and the base and collector serve as the cathode and are connected to node NS, which is the node of the substrate potential of the P-type substrate 10.

[0060] The bipolar transistor BP2 is a PNP-type bipolar transistor, and like the bipolar transistor BP1, the PN junction between the emitter and base functions as a diode element. Therefore, like the bipolar transistor BP1, the method of this embodiment can also be applied to the bipolar transistor BP2. The emitter of the bipolar transistor BP2 serves as the anode and is connected to the other end of the resistor RA1, and the base and collector serve as the cathode and are connected to the node NS. The other end of the resistor RA1 is connected to the node NA2, which is the node of the second input terminal of the operational amplifier OP.

[0061] 14, the reference voltage generating circuit 200 includes a transistor TA1 and a transistor TA2. The transistor TA1 is a P-type MOS transistor and is provided, for example, between a node NR, which is a rectified voltage node of a rectifier circuit (not shown), and a first input terminal of an operational amplifier OP. More specifically, the transistor TA1 has a source connected to the node NR, a gate connected to a node NA3, which is a node of the output terminal of the operational amplifier OP, and a drain connected to a node NA1. The transistor TA2 is a P-type MOS transistor and is provided, for example, between the node NR and a second input terminal of the operational amplifier OP. More specifically, the transistor TA2 has a source connected to the node NR, a gate connected to the node NA3, and a drain connected to a node NA2.

[0062] 14, the reference voltage generating circuit 200 includes a transistor TA3 and an output resistor RA3. The transistor TA3 is a P-type MOS transistor and is provided, for example, between a node NR and an output node NQ that outputs a reference voltage. More specifically, the transistor TA3 has a source connected to the node NR, a gate connected to a node NA3, and a drain connected to the output node NQ. The output resistor RA3 has one end connected to the output node NQ and the other end connected to a node NS.

[0063] 14, the reference voltage generating circuit 200 includes a resistor RX2 provided between a first input terminal of the operational amplifier OP and a node NS, and a resistor RY2 provided between a second input terminal of the operational amplifier OP and the node NS. One end of the resistor RX2 is connected to the node NA1, and the other end is connected to the node NS. One end of the resistor RY2 is connected to the node NA2, and the other end is connected to the node NS.

[0064] As described above, the reference voltage generating circuit 200 of FIG. 14 includes transistors TA1 and TA2 between node NR and the first and second input terminals of the operational amplifier OP, and the gates of these transistors TA1 and TA2 are controlled by the output of the operational amplifier OP. This allows feedback control so that the first and second input terminals are at the same voltage due to the virtual grounding of the operational amplifier OP. This allows current to flow through bipolar transistor BP1, which is connected in series with transistor TA1, and bipolar transistor BP2, which is connected in series with transistor TA2, due to feedback control, thereby outputting a reference voltage based on the bandgap voltage. Furthermore, since the reference voltage generating circuit 200 further includes the aforementioned transistor TA3 and output resistor RA3, a current equivalent to the current flowing through transistors TA1 and TA2 flows through transistor TA3 and then through output resistor RA3 under control of the output of the operational amplifier OP. This allows the reference voltage generating circuit 200 to output a reference voltage set by this current and the resistance value of output resistor RA3.

[0065] More specifically, the current flowing through transistor TA2 can be expressed by a specific relationship (omitted) using the base-emitter voltage of bipolar transistor BP1, the base-emitter voltage difference, the resistance of resistor RA1, the resistance of resistor RX2, and the resistance of resistor RY2. The base-emitter voltage difference is the difference between the base-emitter voltage of bipolar transistor BP1 and the base-emitter voltage of bipolar transistor BP2. The base-emitter voltage difference can be expressed by a specific relationship (omitted) using the emitter area ratio of bipolar transistor BP1 to bipolar transistor BP2, Boltzmann's constant, absolute temperature, and electron charge.

[0066] The current flowing through transistor TA2 is mirrored and flows through transistor TA3. This mirrored current then flows through output resistor RA3, generating a reference voltage based on the value of the current flowing through transistor TA2 and the resistance of output resistor RA3. In this way, by appropriately combining the temperature characteristics of the base-emitter voltage of bipolar transistor BP1, the base-emitter voltage difference, the resistance of resistor RA1, the resistance of resistor RX2, and the resistance of resistor RY2, it is possible to generate a reference voltage with a flat temperature characteristic.

[0067] As described above, in the semiconductor device 1 of this embodiment, the first PN junction diode D1 is a diode used in the reference voltage generation circuit 200. This prevents the reference voltage output from the reference voltage generation circuit 200 from fluctuating due to the generation of a negative potential. In a reference voltage generation circuit 200 that does not employ the method of this embodiment, the current value flowing through the bipolar transistor BP1 may fluctuate due to the generation of the negative potential described above. This may cause fluctuations in the base-emitter voltage of the bipolar transistor BP1, resulting in fluctuations in the reference voltage output from the reference voltage generation circuit 200. While it is possible to increase the parasitic resistance by designing the layout to separate the circuit block including the reference voltage generation circuit 200 from circuit blocks that may generate a negative potential, this does not eliminate the cause of the reference voltage fluctuation and limits the flexibility of the layout of the IC chip. In contrast, by employing the method of this embodiment, the cause of fluctuations in the current value flowing through the bipolar transistor BP1 can be eliminated. This improves the flexibility of the layout of the IC chip including the reference voltage generation circuit 200.

[0068] As described above, the semiconductor device of this embodiment includes a P-type substrate to which ground potential is supplied, a first PN junction diode, a first P-type well, and an N-type well for circuit elements. The first P-type well is provided with a first PN junction diode, and the cathode of the first PN junction diode is connected via a wiring layer. The first N-type well is provided in the P-type substrate and is supplied with a first constant potential. The N-type well for circuit elements is provided in the P-type substrate and is supplied with a negative potential lower than ground potential.

[0069] By doing so, in the semiconductor device of this embodiment, the path through which the parasitic NPN transistor can be turned on when a negative potential is supplied can be a current path from the first N-type well to the N-type well for circuit elements. As a result, even if a negative potential is supplied to the N-type well for circuit elements, current does not flow from the anode and cathode of the first PN junction diode to the negative potential, and the operation of the first PN junction diode is not affected. This allows the first PN junction diode to operate stably while improving the degree of freedom in the layout of the IC chip.

[0070] The first constant potential may be equal to or higher than the first cathode potential, which is the potential of the cathode of the first PN junction diode.

[0071] In this way, the potential of the first N-type well becomes higher than the potential of the first P-type well, and a reverse voltage can be applied to the PN junction between the first P-type well and the first N-type well, thereby blocking the current path from the first cathode to the negative potential of the N-type well for circuit elements by the first N-type well 21 at the first constant potential.

[0072] The N-type well for circuit elements may also be an N-type well in which the drain region of an N-type DMOS transistor is provided.

[0073] In this way, a semiconductor device can be constructed that includes an N-type DMOS and a diode, and that allows the diode to operate stably even when a negative potential occurs.

[0074] The negative potential may also be a potential set by the decay current of an inductor connected to the drain of an N-type DMOS transistor.

[0075] By doing so, it is possible to construct a semiconductor device that operates as a stable diode even when a negative potential that causes a decay current of the inductor occurs in the N-type DMOS.

[0076] The first PN junction diode may also be a diode used in a temperature sensor circuit.

[0077] In this way, the temperature of the circuit block in which a negative potential may occur can be accurately measured.

[0078] The temperature sensor circuit may also include a first PN junction diode provided between the first node and a ground node, a current source that supplies a current to the first node, and a comparator having a first terminal connected to the first node and a second terminal to which a threshold voltage is input.

[0079] By doing this, it is possible to construct a temperature sensor circuit that uses a comparator to compare the voltage generated by flowing current from a current source to the first PN junction diode with the threshold voltage, while stabilizing the operation of the first PN junction diode.

[0080] The first PN junction diode may be a diode used in a reference voltage generating circuit.

[0081] In this way, it is possible to prevent the reference voltage output from the reference voltage generating circuit from fluctuating in response to the generation of a negative potential.

[0082] The first PN junction diode may also include an N-type well for the diode provided in the first P-type well, an N-type region provided in the N-type well for the diode and corresponding to the cathode, and a P-type region provided in the N-type well for the diode and corresponding to the anode.

[0083] In this way, the first PN junction diode can be formed using the P-type region and N-type region formed in the step of forming the transistor, and therefore the manufacturing process of the semiconductor device can be simplified.

[0084] The semiconductor device may also include a second PN junction diode connected in series to the first PN junction diode, and a second P-type well in which the second PN junction diode is provided and to which the cathode of the second PN junction diode is connected via a wiring layer. The first N-type well may include a first P-type well in which the first PN junction diode is provided, and a second P-type well in which the second PN junction diode is provided. The first constant potential supplied to the first N-type well may be a potential equal to or greater than a first cathode potential, which is the potential of the cathode of the first PN junction diode, and a potential equal to or greater than a second cathode potential, which is the potential of the cathode of the second PN junction diode.

[0085] In this way, it is possible to configure a diode that operates stably against the occurrence of a negative potential while suppressing an increase in chip area.

[0086] Although the present embodiment has been described in detail above, it will be readily apparent to those skilled in the art that many modifications are possible without substantially departing from the novel features and advantages of the present disclosure. Therefore, all such modifications are intended to be included within the scope of the present disclosure. For example, a term described at least once in the specification or drawings together with a different term having a broader or equivalent meaning may be replaced with that different term anywhere in the specification or drawings. Furthermore, all combinations of the present embodiment and modifications are also included within the scope of the present disclosure. Furthermore, the configuration and operation of the semiconductor device, etc., are not limited to those described in the present embodiment, and various modifications are possible. [Explanation of symbols]

[0087] 1... semiconductor device, 10... P-type substrate, 10-P, 31-P, 32-P, 50-P, 61-P, 62-P, 91-P, 92-P... P-type region, 21... first N-type well, 21-N, 22-N, 40-N, 50-N, 61-N, 62-N, 91-N, 92-N... N-type region, 22... second N-type well, 31... first P-type well, 32... second P-type well, 40... N-type well for circuit element, 50... predetermined P-type well, 61... N-type well for diode (N-type well for first diode), 62... N-type well for second diode, 80... current source, 100... comparator 200...reference voltage generating circuit, BP1...bipolar transistor, BP2...bipolar transistor, D1...first PN junction diode, D2...second PN junction diode, M...external load, NA1, NA2, NA3, NR, NS...nodes, N1...first node, NQ...output node, OP...operational amplifier, RA1, RX2, RY2...resistors, RA3...output resistor, T1...first terminal, T2...second terminal, TA1, TA2, TA3...transistors, TE...temperature, t0, t1, t2...timing, Va...predetermined voltage, Vb...threshold voltage

Claims

1. a P-type substrate to which a ground potential is supplied; a first PN junction diode; a first P-type well in which the first PN junction diode is provided and to which a cathode of the first PN junction diode is connected via a wiring layer; a first N-type well provided in the P-type substrate, the first P-type well provided therein, and to which a first constant potential is supplied; an N-type well for circuit elements provided in the P-type substrate and supplied with a negative potential lower than the ground potential; A semiconductor device comprising:

2. 2. The semiconductor device according to claim 1, The first constant potential is The semiconductor device is characterized in that the potential is equal to or higher than a first cathode potential, which is the potential of the cathode of the first PN junction diode.

3. 2. The semiconductor device according to claim 1, The N-type well for circuit elements is A semiconductor device comprising an N-type well in which a drain region of an N-type DMOS transistor is provided.

4. 4. The semiconductor device according to claim 3, The negative potential is The semiconductor device is characterized in that the potential is set by a decay current of an inductor connected to the drain of the N-type DMOS transistor.

5. 5. The semiconductor device according to claim 1, The first PN junction diode is A semiconductor device that is a diode used in a temperature sensor circuit.

6. 6. The semiconductor device according to claim 5, The temperature sensor circuit the first PN junction diode provided between a first node and a ground node; a current source that supplies a current to the first node; a comparator having a first node connected to a first terminal and a second terminal to which a threshold voltage is input; A semiconductor device comprising:

7. 5. The semiconductor device according to claim 1, The first PN junction diode is 1. A semiconductor device comprising a diode used in a reference voltage generating circuit.

8. 5. The semiconductor device according to claim 1, The first PN junction diode is an N-type well for a diode provided in the first P-type well; an N-type region provided in the N-type well for the diode and corresponding to the cathode; a P-type region provided in the N-type well for the diode and corresponding to an anode; A semiconductor device comprising:

9. 5. The semiconductor device according to claim 1, a second PN junction diode connected in series with the first PN junction diode; a second P-type well in which the second PN junction diode is provided, and to which the cathode of the second PN junction diode is connected via the wiring layer; Including, the first N-type well is provided with the first P-type well in which the first PN junction diode is provided, and the second P-type well in which the second PN junction diode is provided; the first constant potential supplied to the first N-type well is a potential equal to or higher than a first cathode potential, which is the potential of the cathode of the first PN junction diode, and is a potential equal to or higher than a second cathode potential, which is the potential of the cathode of the second PN junction diode.

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