Serial communication cable failure prediction device and method

Abstract

To provide a failure prediction device capable of finding a failure before a communication cable of a high-speed serial data communication completely fails, and prompting a user to replace the cable.SOLUTION: In a failure prediction device that receives a high-speed serial differential transmission signal transmitted from a transmission-side device via a serial communication cable and performs prediction of a failure by inspecting the received signal in a process of converting an analog stage to a digital stage, the failure prediction device includes a reception-side Phy including at least an analog comparator, a serial-parallel converter, an embedded clock decoding circuit, and a failure-causing error determination circuit. The embedded clock decoding circuit notifies the failure-causing error determination circuit of a reception code that does not exist in an encoding table prepared in advance as a reception error, and the failure-causing error determination circuit removes an error that is considered to be caused by noise based on the notification and detects an error that is estimated to be caused by a failure.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates generally to a device for predicting failures in serial communication cables, and more particularly to a device for predicting or diagnosing failures in communication cables in high-speed serial communication. [Background technology]

[0002] In electronic devices, communication cables, which are subject to deformations such as bending and stretching, are components that frequently fail. The main cause of failure is a break in the transmission line, but before this occurs, deterioration of transmission characteristics occurs. In the case of analog transmission, deterioration of transmission characteristics appears as an increase in noise, so users can know about cable deterioration in advance and can replace the cable before it reaches a critical failure.

[0003] However, in recent digital data transmissions, error correction codes are used, which make it possible to restore correct data even from data that has errors mixed in. As a result, it has become difficult for users to know the degree of cable deterioration, and there have been many cases where the cable suddenly became unusable.

[0004] There are various digital data transmission standards. Among them, the most common is the embedded clock type high-speed serial communication, which transmits data and clock components only over the data signal line without separating the clock and data lines, because it is easy to increase the communication rate.

[0005] In high-speed serial communications using the embedded clock method, a data string is converted into a data string (symbol) in which "0" or "1" does not occur consecutively for more than a certain period of time, and a clock component is incorporated into the data signal by ensuring that data changes occur at regular intervals during communications. There are several methods for generating data strings, but the most common conversion method is called 8B10B.

[0006] The 8B10B conversion method converts 8-bit data into a 10-bit data string. There are no set rules for the conversion, but one known example is a method in which the top 3 bits of 8-bit data are converted into 4 bits (3B4B conversion) and the bottom 5 bits are converted into 6 bits (5B6B conversion) (see Figures 3A and 3B).

[0007] There are 552 types of data strings after 8B10B conversion, plus 24 control codes called K codes (Figure 3C). The total number of 10-bit data strings is 1024, so 448 (=1024-552-24) are data strings that are not used for data transmission.

[0008] When a data string that is not used is received by the receiver, it is passed on to subsequent processing as invalid data. In recent digital data transmissions, it is common for error correction codes to be inserted into packets or frames. Therefore, even if there are a small number of errors in the received data, they are corrected or corrected in subsequent processing, resulting in error-free data communication. However, this processing can also delay the detection of cable deterioration.

[0009] The prior art includes the following:

[0010] First, a state determination device that improves consistency between the level of risk of failure and the period until a failure actually occurs, and a failure prediction system using the same have been proposed (Patent Document 1).

[0011] That is, Patent Document 1 discloses a state determination device that calculates a state index value indicating the state of a target device using internal information of the target device, and determines the state of the target device based on the calculated state index value, and includes: information collection means that collects the internal information of the target device together with usage information; regression model setting means that sets a regression model; state index value calculation means that calculates the state index value using the regression model set by the regression model setting means and the internal information of the target device collected by the information collection means; and grace period calculation means that indicates an expected grace period from the time when the state index value calculation means calculates the state index value until a failure occurs. a grace period index value calculation means for calculating the grace period index value using the usage information collected by the information collection means and the calculation formula data stored in the calculation formula data storage means; a failure risk calculation means for calculating a failure risk from the state index value calculated by the state index value calculation means and the grace period index value calculated by the grace period index value calculation means; and a determination means for determining the state of the target equipment based on the failure risk calculated by the failure risk calculation means.

[0012] Furthermore, a machine learning device that learns failure conditions has been proposed, enabling accurate failure prediction depending on the situation (Patent Document 2).

[0013] That is, Patent Document 2 discloses a machine learning device that learns conditions associated with failures of industrial machinery, characterized in that it comprises: a state observation unit that observes state variables including at least one of output data from sensors that detect the state of the industrial machinery or the surrounding environment, internal data of control software that controls the industrial machinery, and calculation data obtained based on the output data or the internal data while the industrial machinery is operating or stationary; a judgment data acquisition unit that acquires judgment data that determines whether or not the industrial machinery has a failure or the degree of the failure; and a learning unit that learns conditions associated with failures of the industrial machinery in accordance with a training dataset created based on a combination of the state variables and the judgment data. [Prior art documents] [Patent documents]

[0014] [Patent Document 1] Japanese Patent Application Laid-Open No. 2011-013440 [Patent Document 2] Japanese Patent Application Publication No. 2017-033526 Summary of the Invention [Problem to be solved by the invention]

[0015] However, in conventional high-speed serial communications, data transmission is often performed with error correction codes. Therefore, even in situations where data reception errors occur due to deterioration of the communications cable, the error data is restored using error correction technology, making it difficult for users who handle the data after error correction to notice the deterioration of the cable.

[0016] FIG. 10 shows an example of a conventional transmission / reception system in which an image of a subject 1001 captured by an image sensor in a transmitting device is transmitted to a receiving device via a communication cable using high-speed serial communication, and the image is displayed on a display connected to the receiving device.

[0017] In FIG. 10, a transmitting / receiving system 1000 includes a transmitting device 1010 and a receiving device 1020 connected by a communication cable 1090 , and a display 1009 . The transmitting device 1010 has an image sensor 1011, a packet generator 1012, a transmitting link block 1013, and a transmitting Phy block 1014. It also transmits video data to the receiving device via a communication cable 1090 connected to a connector 1015. The receiving device 1020 has a connector 1021, a receiving Phy block 1022, a receiving Link block 1023, a CPU 1024, and a storage 1025.

[0018] The video data captured from the subject 1001 is transmitted using a high-speed video serial communication standard such as HDMI (registered trademark) or SDI via a transmission link or transmission Phy block corresponding to the standard, and a data packet containing an error correction code is generated. The data is then transmitted from the transmitting device 1010 to the receiving device 1020 via a communication cable 1090.

[0019] If the communication cable 1090 deteriorates, the signal quality deteriorates in this cable section, and the receiving device 1020 receives incorrect data. However, as a result of data recovery processing including error correction performed by the receiving Phy block 1022, the receiving Link block 1023, or software running on the CPU 1024, the correct display can be achieved without being affected by the deterioration of signal quality (the definitions of Phy and Link are described later).

[0020] Therefore, in high-speed serial communications using the embedded clock method, there is a need for technology that can predict the cause of a fatal cable failure before it occurs during the process of converting signals received via a cable into digital data. [Means for solving the problem]

[0021] Therefore, one embodiment of the present invention provides a serial communication cable failure prediction device that receives a high-speed serial differential transmission signal transmitted from a transmitting device via a serial communication cable, inspects the received signal during the process of converting it from analog to digital, and predicts a failure.The failure prediction device includes a receiving Phy that has at least an analog comparator, a serial-to-parallel converter, an embedded clock decoding circuit, and a failure-caused error determination circuit, and the embedded clock decoding circuit notifies the failure-caused error determination circuit of a received code that does not exist in a pre-prepared encoding table as a reception error, and the failure-caused error determination circuit removes errors that are thought to be caused by noise based on the notification and detects errors that are thought to be caused by a failure.

[0022] The embedded clock encoding circuit is characterized by employing an encoding method for a data string in which "0" or "1" does not occur consecutively for more than a certain number of times, such as 8B10B, 128B130B, or 64B66B.

[0023] The fault-caused error determination circuit includes at least an error interval counter for counting the interval between errors and a fault candidate counter for counting errors that are fault candidates, and the fault-caused error determination circuit (1) initializes the fault candidate counter when the error interval counter reaches the upper error interval limit, (2) increments the fault candidate counter when it determines that the error interval counter is equal to or greater than the lower error interval limit and less than the upper error interval limit when a signal error occurs, and (3) sends a fault alert when the fault candidate counter reaches a predetermined threshold. [Effects of the Invention]

[0024] According to the serial communication cable failure prediction device of one embodiment of the present invention, it is possible to detect defects in communication cables, particularly those used for high-speed serial data communication, before they completely fail, and to prompt the user to replace the cable. [Brief explanation of the drawings]

[0025] [Figure 1] 1 is an explanatory diagram illustrating an example of the overall configuration of a system including a serial communication cable failure prediction device according to an embodiment of the present invention; [Figure 2] 2 is an explanatory diagram illustrating an example of the circuit configuration of a receiving-side Phy block in a serial communication cable failure prediction device according to one embodiment of the present invention. FIG. [Figure 3A] 1 is an explanatory diagram illustrating an example of a coding table employed in an embedded clock composite circuit of a serial communication cable failure prediction device according to one embodiment of the present invention; [Figure 3B] 1 is an explanatory diagram illustrating an example of a coding table employed in an embedded clock composite circuit of a serial communication cable failure prediction device according to one embodiment of the present invention; [Figure 3C] 1 is an explanatory diagram illustrating an example of a coding table employed in an embedded clock composite circuit of a serial communication cable failure prediction device according to one embodiment of the present invention; [Figure 4] 4 is a flowchart illustrating the processing operation of a serial communication cable failure prediction device and the like according to an embodiment of the present invention. [Figure 5] 1 is an explanatory diagram illustrating an example of a sequence for detecting an error that may cause a failure in a serial communication cable failure prediction device according to an embodiment of the present invention; [Figure 6] FIG. 10 is an explanatory diagram illustrating an example of the circuit configuration of a receiving-side Phy block in a serial communication cable failure prediction device according to another embodiment of the present invention. [Figure 7] FIG. 10 is an explanatory diagram illustrating an example of the overall configuration of a system including a serial communication cable failure prediction device according to another embodiment of the present invention. [Figure 8] 10 is a flowchart illustrating a processing operation of a serial communication cable failure prediction device and the like according to another embodiment of the present invention. [Figure 9] 10 is a flowchart illustrating a processing operation of a serial communication cable failure prediction device and the like according to another embodiment of the present invention. [Figure 10] FIG. 1 is an explanatory diagram illustrating an example of the overall configuration of a conventional video data transmission / reception system having an error correction function for a serial communication cable. [Figure 11A] 1 is an explanatory diagram illustrating the concept of LVDS (a basic transmission method for high-speed communication) and eye patterns. [Figure 11B] FIG. 1 is an explanatory diagram illustrating how degradation of LVDS appears. [Figure 11C] 1 is an explanatory diagram illustrating how the opening of an eye pattern narrows in LVDS, increasing the likelihood of signal misidentification at the time of bit transition. DETAILED DESCRIPTION OF THE INVENTION

[0026] (Definition of terms: Phy and Link) First, let's explain the terms Phy and Link. The International Organization for Standardization (OSI) divides communication processing into seven layers, and the functions of the two layers closest to the physical layer correspond to Phy and Link. Phy corresponds to the physical layer, and Link corresponds to the data link layer. In high-speed serial communication technology, the physical layer (Phy layer) and data link layer (Link layer) are generally implemented on a hardware basis. As mentioned above, the embedded clock method is generally used for physical layer communication in high-speed serial communication. Here, the hardware implemented to perform physical layer communication is called the Phy block (or simply "Phy"), and the hardware implemented to perform link layer communication is called the Link block (or simply "Link").

[0027] (Definition of term: Forecast) Next, the concept of "prediction" envisioned by the present invention will be described. In the present invention, "prediction" is a concept that includes fault diagnosis and fault determination, which enable the detection of minor faults that were previously undetectable. Therefore, in the present invention, "prediction" constitutes part of the concepts of diagnosis, determination, or discrimination, and even when simply referring to prediction, it does not exclude the processing concepts of diagnosis, determination, or discrimination.

[0028] (Basic concept of the present invention) The physical layer of digital high-speed serial data communications often uses two pairs of cables and LVDS (Low-Voltage Differential Signaling), which expresses signal values ​​based on the relative magnitude of the two signal levels. Data values ​​can be determined by comparing the relative magnitude of the signals, so a feature of this method is that signal values ​​can be determined quickly using a simple analog comparator.

[0029] Furthermore, in high-speed serial communications, a technology called embedded clock is used to embed a clock component in the data itself in order to increase the data transmission speed.

[0030] In LVDS communications, when the signal quality is good, the opening of the signal waveform, known as the eye pattern, is large. However, when the signal quality deteriorates due to cable degradation, the opening becomes smaller, making it difficult to receive data correctly. This is shown in Figures 11A to 11C. Figure 11A clearly shows the eye pattern in LVDS communications. As the LVDS signal deteriorates, the opening of the eye pattern gradually narrows, as shown in Figure 11B. Figure 11C shows a state in which the opening of the eye pattern becomes even narrower, resulting in increased signal misrecognition during bit conversion.

[0031] While such signal degradation can be observed using existing measuring equipment, one feature of the LVDS data transfer method is that signal values ​​are determined solely by an analog comparator, making it unrealistic to implement an expensive signal quality monitor circuit like a measuring instrument in a receiver. For this reason, in one embodiment of the present invention, the Phy block, a digital circuit section located immediately after the analog comparator, focuses on error codes found in the decoder section for the embedded clock data stream, and the digital circuit section is used to detect quality degradation in the physical signal section.

[0032] In addition, in one embodiment of the present invention, the occurrence of error codes is monitored, and if an error occurs multiple times in a relatively short period of time, even if it is not a continuous error, it is considered to be an error caused by cable deterioration, and a group of these errors is output as a failure prediction signal to prompt the user to replace the cable.

[0033] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A serial communication cable failure prediction device according to an embodiment of the present invention will be specifically described below with reference to the drawings.

[0034] [Example 1] An example of the overall configuration of a system including a serial communication cable failure prediction device according to one embodiment of the present invention is shown in Figure 1. This system identifies errors that may cause cable failure, and if an error is detected, it displays a message to the user urging them to replace the cable.

[0035] As shown in FIG. 1, a system 100 including a serial communication cable failure prediction device according to one embodiment of the present invention includes a transmitting device 110 and a receiving device 120 connected by a communication cable 190, and a display 109.

[0036] The transmitting device 110 includes an image sensor 111 for capturing an image of a subject 101, a packet generator 112, a transmitting link block 113, and a transmitting Phy block 114. The transmitting device 110 transmits video data to the receiving device 120 via a communication cable 190 connected to a connector 115. The receiving device 120 includes a connector 121, a receiving Phy block 122, a receiving Link block 123, a CPU 124, and a storage 125.

[0037] The receiving-side Phy block 122 is also provided with a fault-caused error determination circuit 1221, which characterizes the receiving-side device 120 according to one embodiment of the present invention. In this respect, the receiving-side device 120 is also referred to as a serial communication cable fault prediction device 120 or a fault prediction device 120.

[0038] The fault-caused error determination circuit 1221 determines whether an error contained in the received data is an error that is presumed to be caused by a fault (the specific determination method will be described later). An error that is presumed to be caused by a fault will also be called a "fault-caused error." In addition to faults, other factors that can cause data errors include noise, etc.

[0039] When the fault-caused error determination circuit 1221 determines that the error is presumed to be caused by a fault, it notifies the CPU of "fault-caused error detection" through a fault prediction detection signal. Upon receiving this signal, the CPU can display a warning lamp (not shown) or a message on the display 109 or the like to prompt the user to replace the cable.

[0040] 2 shows a circuit diagram of a receiving-side Phy block that detects cable degradation in a serial communication cable failure prediction device according to one embodiment of the present invention. In the figure, the receiving-side Phy block 200 includes an analog comparator 201, a serial-to-parallel converter 202, an 8B10B converter 203, an asynchronous buffer 204, a data rearrangement circuit 205, a Link layer interface 206, a PLL clock data recovery unit 210, a failure-induced error determination circuit 220, and a Phy controller unit 230.

[0041] 2, an 8B10B converter 203 is used, but the present invention is not limited to this, and converters employing various encoding methods such as 128B130B, 64B66B, etc. can be used. In this sense, the 8B10B converter 203 can be positioned as a higher-level concept, namely, an "embedded clock decoding circuit."

[0042] The data input to the receiving Phy block 200 is in LVDS format and is transmitted via two pairs of signal lines. The relative signal levels of these two pairs of signal lines are determined by an analog comparator circuit 201. The data passes through a serial-to-parallel converter 202 and is decoded in an 8B10B converter, so a data value toggle always occurs in one data string (10 bits). By using this data value toggle portion for clock phase adjustment, the PLL clock data recovery unit 210 can generate a clock synchronized with the received data.

[0043] The clock synchronized with the received data is then supplied to a serial-to-parallel converter 202 , an 8B10B converter 203 , and an asynchronous buffer 204 .

[0044] The serial-to-parallel converter 202 samples the signal value of the analog comparator 201 using a received data synchronous clock and transmits the sampled signal in 10-bit data units to the 8B10B converter 203. The 8B10B converter 203 restores the original 8-bit data from the 10-bit coded data using an 8B10B coding table such as those shown in Figures 3A to 3C.

[0045] In addition to the normal data, the received data string contains a code called a control code that indicates the beginning of a packet and a code that compensates for differences in clock frequency. The restored data, including these codes, is stored in the asynchronous buffer 204.

[0046] 3A to 3C, there are 448 types of unused data strings (error codes) in the 10-bit encoded data. When such a data string is detected, an error detection signal is sent to the fault-induced error determination circuit 220, and the invalid data is stored in the asynchronous buffer 204.

[0047] The data stored in the asynchronous buffer 204 is rearranged in the data rearrangement circuit 205 in synchronization with the clock on the link layer side, and the data is sent to the receiving circuit (receiving side Link) of the upper link layer via the link layer interface 206.

[0048] The fault-induced error determination circuit 220, under the control of the Phy controller 230, receives heterogeneous codes not associated by the 8B10B converter 203 as error candidates presumed to be caused by a fault, and performs error determination. At this time, an error interval counter (Err_Int_Cntr) and a fault candidate error counter (Fail_Cand_Cntr) operate appropriately (more specifically, this will be described later with reference to FIGS. 4 and 5).

[0049] 4 shows the processing operation of a serial communication cable failure prediction device according to one embodiment of the present invention. It is a flow diagram for determining errors presumed to be caused by a failure by removing errors (noise) other than failure-caused errors that can be considered as noise from the error detection signal generated by the 8B10B converter 203. Here, an example of a mechanism for detecting errors in the 8B10B converter 203 is when a decoded code (error code) that does not exist in the encoding tables shown in FIGS. 3A to 3C is detected.

[0050] In one embodiment, consecutive errors occurring in a short period of time that should be considered as a single error are excluded, and multiple errors occurring in a relatively short period of time are determined to be fault-caused errors. Two types of counters are used for this determination: an error interval counter (Err_Int_Cntr) and a fault candidate error counter (Fail_Cand_Cntr). The counter values ​​of both counters are "0" immediately after reset release.

[0051] In high-speed serial communications, after reset is released, a phase called link-up is carried out to determine the data transfer rate and communication method between the transmitter and receiver. In this phase, an error occurrence is used to establish the communication method between the two parties, so the error is excluded from the scope of error detection.

[0052] When the system transitions to a normal communication state, it begins failure prediction judgment. It continues to increment the error interval counter (Err_Int_Cntr) with each clock. When the counter reaches its maximum value, it retains the maximum value. When the counter value exceeds the error interval upper limit, it is assumed that no errors caused by a failure have been found, and Fail_Cand_Cntr is initialized to "0".

[0053] If an error occurs and the error interval counter (Err_Int_Cntr) is less than the error interval lower limit, it is considered to be a series of errors in a short period of time, Err_Int_Cntr is set to "0", and processing continues.

[0054] If the error interval counter (Err_Int_Cntr) is greater than or equal to the lower limit of the error interval and less than the upper limit, it is considered a fault-caused error candidate.If the failure candidate error counter (Fail_Cand_Cntr) is less than the failure candidate error counter threshold, Fail_Cand_Cnt is incremented and processing continues.If the failure candidate error counter threshold is reached, it is assumed that a failure has been detected and a failure detection signal is asserted.

[0055] The above processing flow will be explained in accordance with the flow chart in FIG. 4. After processing starts in step S401, the process proceeds to step S402, where reset release is initiated, and in step S403, the error interval counter (Err_Int_Cntr) and the failure candidate error counter (Fail_Cand_Cntr) are set to "0."

[0056] Next, in step S404, the process waits for a clock, and in step S405, it is determined whether the communication state is normal communication. If the answer is No in this step, the process returns to step S404 and waits for the next clock, but if the answer is Yes, the process proceeds to step S406, where the error interval counter (Err_Int_Cntr) is incremented. However, if the error interval counter (Err_Int_Cntr) has reached its maximum value as a counter, that maximum value is maintained.

[0057] Next, the process proceeds to step S407, where it is determined whether the error interval counter (Err_Int_Cntr) is less than a predetermined error interval upper limit value, and if No, it is determined that no failure-caused error was found, and the failure candidate error counter (Fail_Cand_Cntr) is set to "0" (step S408).Then, the process proceeds to step S409, where it is determined whether an error was detected, and if No in this step, the process returns to step S404.

[0058] On the other hand, if the answer is Yes in step S409, the process proceeds to step S410, where it is determined whether the error interval counter (Err_Int_Cntr) is equal to or greater than a predetermined lower limit of the error interval; if the answer is No in the same step, the process proceeds to step S411, where it is determined that the error is a short-term series of consecutive errors and is not caused by a malfunction, the error interval counter (Err_Int_Cntr) is set to "0", and the process returns to step S404.

[0059] If the result of step S410 is Yes, the process proceeds to step S412, where it is determined whether the failure candidate error counter (Fail_Cand_Cntr) is equal to or greater than the failure candidate error counter threshold value. In one embodiment, the failure candidate error counter threshold value is set to 3, but the present invention is not limited to this value.

[0060] If the answer is No in step S412, the process proceeds to step S413, where the error interval counter (Err_Int_Cntr) is set to "0" and the failure candidate error counter (Fail_Cand_Cntr) is incremented, and the process then returns to step S404.

[0061] If the answer is Yes in step S412, the process proceeds to step S414, where the failure prediction detection signal is asserted, and the flow ends (step S415).

[0062] 5 shows an example of a sequence for detecting a fault-caused error in a serial communication cable fault prediction device according to one embodiment of the present invention. The figure shows the process of identifying a fault-caused error from detected errors using an error interval counter and a fault candidate error counter.

[0063] Although the present invention is not limited to this, in one embodiment the threshold value of the fault candidate error counter is set to 3. During a period in which no faults are present, the error interval counter continues to increment. When an error occurs, a determination is made as to whether the value of the error interval counter is equal to or greater than the error interval lower limit.

[0064] If the error interval is less than the lower limit, it is considered to be a single error, and the fault candidate error counter is not incremented. On the other hand, if the error interval is equal to or greater than the lower limit, the fault candidate counter is incremented. If the value of the error interval counter exceeds the upper limit of the error interval, it is considered that no fault-caused errors have been found, and the fault candidate error counter is initialized (reset). Here, in one embodiment of the present invention, the lower limit of the error interval is 10, the upper limit of the error interval is 1000, and the maximum value when the number of bits of the error interval counter is 10 is 1023.

[0065] If an error whose error interval counter value is greater than or equal to the lower limit and less than the upper limit occurs consecutively the number of times equal to the threshold value of the fault candidate counter (here, three times), it is determined to be a fault-caused error (timing indicated by a star in the figure).

[0066] In one embodiment of the present invention, the description is based on the assumption of an 8B10B encoding method, but the present invention is not limited to this, and the effects of the present invention are similar in other embodiments that use encoding methods for embedded clocks such as 128B130B or 64B66B used in PCI Express and Ethernet.

[0067] [Example 2] In HDMI (registered trademark) and Ethernet standards of 2.5 Gbps or higher, a forward error correction (FEC) circuit is implemented in the receiving Phy block. Figure 6 shows an example of a circuit configuration in which such a forward error correction circuit 609 is implemented in the receiving Phy block 600. Note that, except for the forward error correction circuit 609, the components of the receiving Phy block 600 (601-606, 610, 620, 621, 622, 630) correspond to the components of the receiving Phy block 200 (201-206, 210, 220, 221, 222, 230).

[0068] 6, the 8B10B converter 603 determines an error when it receives a data string that does not exist in the encoding table, but if the data string in which the error occurred exists in the encoding table, it cannot be detected as an error. The forward error correction circuit 609 corrects errors in the entire data packet, including the invalid data detected by the 8B10B converter 603, enabling more accurate error detection.

[0069] Therefore, in one embodiment of the present invention, when the forward error correction circuit 609 detects an error, including cases where the error is correctable, it sends an error detection signal to the fault-induced error determination circuit 620 .

[0070] In this case, the method of determining a fault-induced error in the fault-induced error determination circuit 622 is the same as the processing flow (steps S401 to S415) described with reference to FIG.

[0071] [Example 3] In the first and second embodiments, the error interval is measured by hardware, but if the upper limit of the error interval is to be set to a long period, the number of bits required for the counter becomes very large. Therefore, Fig. 7 shows a system including a failure prediction device that is a measure to avoid this problem.

[0072] In Figure 7, the receiving Phy block 722 is equipped with a counter with the bit width required to determine the lower limit of the error interval, and is configured to only remove consecutive errors over a short period of time, and if any other errors are found, notify the CPU that a fault candidate error has been detected.

[0073] Other than the above-mentioned characteristic operations of the receiving side Phy block 722 and CPU 724, the system 700 and its configuration (701, 709, 710, 711 to 715, 720, 721, 723 to 725, 790) are similar to the system 100 and its configuration (101, 109, 110, 111 to 115, 120, 121, 123 to 125, 190).

[0074] Next, a processing flow performed in the failure prediction device 720 according to the embodiment shown in FIG. 7 will be described with reference to FIGS.

[0075] In the flow shown in FIG. 8, the error interval counter 7222 implemented in the receiving Phy block 722 only needs to have a number of bits to determine whether or not the lower limit has been exceeded, so there is no need to worry about the number of bits becoming too large.

[0076] The CPU that received the notification also calculates the error occurrence interval from the recorded information on the occurrence time of the previous failure candidate error, and then updates the occurrence time of the failure candidate error to the current time.If the error occurrence interval is equal to or greater than the error interval upper limit, it assumes that no failure candidate error has been found and sets the information in the failure candidate error counter (Fail_Cand_Cntr) to "0."If the error occurrence interval is less than the error interval upper limit, it assumes that the failure candidate error has been found and increments the failure candidate error counter (Fail_Cand_Cntr).

[0077] The above processing flow will be explained in accordance with the flow of Figure 8. After processing starts in step S801, the process proceeds to step S802, where reset release is initiated, and in step S803, the error interval counter (Err_Int_Cntr) is set to "0".

[0078] Next, in step S804, the process waits for a clock, and in step S805, it is determined whether the communication state is normal communication. If the answer is No in this step, the process returns to step S804 and waits for the next clock, but if the answer is Yes, the process proceeds to step S806, where the error interval counter (Err_Int_Cntr) is incremented. However, if the error interval counter (Err_Int_Cntr) has reached the maximum value allowed by the bit width of the counter, that maximum value is maintained.

[0079] Next, the process proceeds to step S807, where it is determined whether an error has been detected. If the result is No, the process returns to step S804, but if the result is Yes, the process proceeds to step S808.

[0080] In step S808, it is determined whether the error interval counter (Err_Int_Cntr) is equal to or greater than the lower limit of the error interval. If the answer is No, it is determined that there have been consecutive errors in a short period of time, and the error interval counter (Err_Int_Cntr) is set to "0" (step S809), and the process returns to step S804. However, if the answer is Yes in step S808, the process proceeds to step S810.

[0081] In step S810, a failure prediction detection signal is sent to the CPU 724, and this flow ends (step S811).

[0082] 9, upon receiving a fault candidate error detection notification from the receiving Phy block 722, the CPU 724 determines whether the error is due to a fault. In one embodiment, the error interval counter (Err_Int_Cntr) information is obtained on the hardware side as a counter value, but can be obtained on the software side controlling the CPU 724 by calculating the difference from the time of the previous error occurrence. In this sense, in the flow shown in FIG. 9, Err_Int_Cntr is referred to as the error occurrence interval (Err_Int_Cntr).

[0083] If the value of the failure candidate error counter (Fail_Cand_Cntr) reaches a threshold value, it is determined that a failure has been detected, and a message requesting cable replacement or the like is output.

[0084] The above processing flow will be explained in accordance with the flow of Figure 9. After processing starts in step S901, the process proceeds to step S902, where reset release is initiated (as an example, the error occurrence interval (Err_Int_Cntr) and the failure candidate error counter (Fail_Cand_Cntr) are set to "0").

[0085] Next, in step S904, it is determined whether the communication state is normal communication. If the result is No in this step, the process returns to step S904 and enters a standby state. If the result is Yes, the process proceeds to step S905, where the failure candidate error occurrence time is set to the current time. Then, the error occurrence interval (Err_Int_Cntr) is set to "0".

[0086] Next, the process proceeds to step S906, where it is determined whether or not there is a fault candidate error. If No, the process returns to step S906, but if Yes, the process proceeds to step S907.

[0087] In step S907, the error occurrence interval (Err_Int_Cntr) is calculated, and the time when the fault candidate error occurred is set as the current time.

[0088] Next, the process proceeds to step S908, where it is determined whether the error occurrence interval (Err_Int_Cntr) is less than the error interval upper limit value. If the answer is No, it is assumed that no fault-caused error was found, and the failure candidate error counter (Fail_Cand_Cntr) is set to "0" (step S909), and the process returns to step S906. However, if the answer is Yes in step S908, the process proceeds to step S910, where it is determined whether the failure candidate error counter (Fail_Cand_Cntr) is greater than or equal to the failure candidate error counter threshold value. Here, in one embodiment of the present invention, the upper error interval limit is 10 ms.

[0089] If the answer is No in step S910, the process proceeds to step S911, where the failure candidate error counter (Fail_Cand_Cntr) is incremented, and the process returns to step S906.

[0090] If the answer is Yes in step S910, the process proceeds to step S912, where a message requesting a cable exchange or the like is output, and the flow ends (step S913).

[0091] While the serial communication cable failure prediction device and the like according to one embodiment of the present invention have been described above based on specific examples, the present invention can be applied not only to a transmission / reception system in which an image of a subject captured by an image sensor in a transmitting device is transmitted to a receiving device via a communication cable using high-speed serial communication and displayed on a display connected to the receiving device, but also to a system in which various data are transmitted via a serial communication cable. Furthermore, the present invention can also be embodied as a method or program for implementing a system or device, or as a storage medium on which a program is recorded (for example, an optical disk, a magneto-optical disk, a CD-ROM, a CD-R, a CD-RW, a magnetic tape, a hard disk, or a memory card).

[0092] Furthermore, the implementation form of the program is not limited to application programs such as object code compiled by a compiler or program code executed by an interpreter, but may also be in the form of a program module incorporated into an operating system.

[0093] Furthermore, it is not necessary for all processing of the program to be performed solely by the CPU on the control board, but it can also be configured so that some or all of the program is performed by another processing unit (such as a DSP) implemented on an expansion board or expansion unit added to the board as needed.

[0094] All of the features described in this specification (including the claims, abstract, and drawings) and / or all steps of any disclosed method or process may be combined in any combination, except combinations in which these features are mutually exclusive.

[0095] Furthermore, each feature described in this specification (including the claims, abstract, and drawings) may be replaced by alternative features serving the same, equivalent, or similar purpose, unless expressly denied. Thus, unless expressly denied, each disclosed feature is only one example of a generic series of identical or equivalent features.

[0096] Furthermore, the present invention is not limited to the specific configuration of any of the above-described embodiments, but extends to any novel feature or combination thereof described in this specification (including the claims, abstract, and drawings), or any novel method or process step or combination thereof described. [Explanation of symbols]

[0097] 100 Serial communication cable failure prediction system 101 Subject 109 Display 110 Transmitting device 111 Image Sensor 112 Packet Generation Unit 113 Sender Link Block 114 Transmitting Phy Block 115 Connector 120 Receiving device (failure prediction device) 121 Connector 122 Receiver Phy Block 1221 Fault-caused error detection circuit 123 Receiver Link Block 124 CPU 125 Storage (DRAM, etc.)

Claims

1. A failure prediction device that receives a high-speed serial differential transmission signal transmitted from a transmitting device via a serial communication cable, inspects the received signal during a process of converting the signal from an analog stage to a digital stage, and predicts a failure, the failure prediction device includes a receiving Phy including at least an analog comparator, a serial-to-parallel converter, an embedded clock decoding circuit, and a failure-caused error determination circuit; the embedded clock decoding circuit notifies the fault-caused error determination circuit of a received code that does not exist in a pre-prepared encoding table as a reception error; The fault-caused error determination circuit removes errors that are considered to be caused by noise based on the notification and detects errors that are considered to be caused by a fault. A failure prediction device characterized by:

2. 2. The failure prediction device according to claim 1, wherein the embedded clock encoding circuit employs one of 8B10B, 128B130B, and 64B66B encoding methods.

3. the fault-caused error determination circuit includes at least an error interval counter for counting an interval between errors, and a fault candidate counter for counting errors that are fault candidates; The fault-caused error determination circuit (1) initializing the fault candidate counter when the error interval counter reaches an error interval upper limit; (2) when a signal error occurs, incrementing the fault candidate counter when it is determined that the error interval counter is equal to or greater than the error interval lower limit and less than the error interval upper limit; (3) When the fault candidate counter reaches a predetermined threshold, a fault alert is sent.

3. The failure prediction device according to claim 1 or 2.

4. The failure prediction device according to any one of claims 1 to 3, further comprising an FEC (Forward Error Correction) circuit, wherein an error in the signal in the failure-caused error determination circuit is detected by signal processing in the FEC circuit.

5. 4. The failure prediction device according to claim 1, further comprising a CPU, wherein the failure prediction is carried out by the CPU and the failure-caused error determination circuit in a shared manner.

6. receiving a high-speed serial differential transmission signal transmitted from a transmitting device via a serial communication cable; 1. A failure prediction method for predicting a failure by inspecting a received signal during a process of converting the received signal from an analog stage to a digital stage in a receiving side Phy including at least an analog comparator, a serial-to-parallel converter, an embedded clock decoding circuit, and a failure-caused error determination circuit, causing the embedded clock decoding circuit to notify the fault-induced error determination circuit of a received code that does not exist in a pre-prepared encoding table as a reception error; The fault-caused error determination circuit is caused to remove errors that are considered to be caused by noise based on the notification and detect errors that are considered to be caused by a fault. A method characterized by:

Images