Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor capable of suppressing an occurrence of delamination in a laminated body in a multilayer ceramic capacitor having a high breakdown voltage specification.SOLUTION: A first main surface side external electrode 411A has a first concave part 510A concaved toward a laminated body 10 side. A second main surface side external electrode 412A has a second concave part 520A concaved toward the laminated body 10 side. A third main surface side external electrode 411B has a third concave part 530B concaved toward the laminated body 10 side. A fourth main surface side external electrode 412B has a fourth concave part 540B concaved toward the laminated body 10 side. In a cross-sectional view along a length direction L and a stacking direction T, an intersection point 300 of a first imaginary line 100 connecting the first concave part 510A and the fourth concave part 540B and a second imaginary line 200 connecting the second concave part 520A and the third concave part 530B is located between a first capacitor portion CAP1 and a second capacitor portion CAP2 in the length direction L, and an external electrode 40 has a tensile stress as a residual stress.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] BACKGROUND ART Conventionally, a multilayer ceramic capacitor having a structure in which a plurality of capacitor portions connected in series are formed, that is, a multilayer ceramic capacitor having a series structure, has been known as a multilayer ceramic capacitor that can withstand high voltages (see Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 10-261546 Summary of the Invention [Problem to be solved by the invention]

[0004] In a multilayer ceramic capacitor with a series structure, large electrostriction occurs even between the capacitor elements connected in series, and a force (tensile stress) is generated in the laminate in the stacking direction from the center of the laminate toward the main surface. Furthermore, if the external electrodes have tensile stress as residual stress, a force (tensile stress) remains in the laminate from the center of the laminate toward the ends of the external electrodes. Of these forces, the force in the stacking direction from the center of the laminate toward the main surface is combined, and if this combined force becomes large, delamination of the laminate may occur.

[0005] An object of the present invention is to provide a multilayer ceramic capacitor with high voltage resistance that can prevent delamination from occurring in the laminate. [Means for solving the problem]

[0006] The multilayer ceramic capacitor of the present invention comprises a laminate including a plurality of dielectric layers and a plurality of internal electrode layers stacked alternately in a height direction, and including first and second main surfaces opposing each other in the height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; and a pair of external electrodes arranged spaced apart from each other at both ends in the length direction of the laminate, wherein the internal electrode layers include a first internal electrode layer extended to the first end surface, a second internal electrode layer extended to the second end surface, and an intermediate electrode layer not extended to either the first end surface or the second end surface, and the laminate includes a first capacitor portion formed by the first internal electrode layer and the intermediate electrode layer facing each other, and a second capacitor portion formed by the second internal electrode layer and the intermediate electrode layer facing each other, and the external electrodes are formed by the first external electrode layer arranged on the first end surface side. and a second external electrode disposed on the second end face side, the first external electrode having a first main surface side external electrode disposed on the first main surface side and a second main surface side external electrode disposed on the second main surface side, the second external electrode having a third main surface side external electrode disposed on the first main surface side and a fourth main surface side external electrode disposed on the second main surface side, the first main surface side external electrode having a first recess recessed towards the laminate, and the second main surface side external electrode having a second recess recessed towards the laminate the third main surface side external electrode has a third recess recessed toward the laminate, the fourth main surface side external electrode has a fourth recess recessed toward the laminate, in a cross-sectional view along the length direction and the height direction, an intersection of a first imaginary line connecting the first recess and the fourth recess and a second imaginary line connecting the second recess and the third recess is located between the first capacitor portion and the second capacitor portion in the length direction, and the external electrodes have tensile stress as residual stress. [Effects of the Invention]

[0007] According to the present invention, it is possible to provide a multilayer ceramic capacitor with high voltage resistance that can suppress the occurrence of delamination in the laminate. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is an external perspective view of a double-structure multilayer ceramic capacitor according to an embodiment of the present invention; [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. 1, illustrating the schematic configuration of a double-structure laminate according to the embodiment. [Figure 3] FIG. 3 is a cross-sectional view taken along the line III-III in FIG. 2. [Figure 4A] FIG. 3 is a cross-sectional view taken along line IVA-IVA in FIG. 2, along a first internal electrode layer and a second internal electrode layer. [Figure 4B] 4 is a cross-sectional view taken along line IVB-IVB of FIG. 2, taken along the intermediate electrode layer. [Figure 5A] FIG. 2 is a diagram showing a part of a method for manufacturing the multilayer ceramic capacitor according to the embodiment, illustrating a first step of forming external electrodes on the laminate. [Figure 5B] FIG. 4 is a diagram showing a part of the method for manufacturing the multilayer ceramic capacitor according to the embodiment, illustrating a second step of forming external electrodes on the laminate. [Figure 5C] FIG. 4 is a diagram showing a part of the method for manufacturing the multilayer ceramic capacitor according to the embodiment, illustrating a third step of forming external electrodes on the laminate. [Figure 6] FIG. 2 is an LT cross-sectional view schematically showing the double-structure multilayer ceramic capacitor according to the embodiment, illustrating forces acting inside. [Figure 7] FIG. 10 is an LT cross-sectional view schematically showing a triple-structure multilayer ceramic capacitor according to a first modified example. [Figure 8] FIG. 10 is an LT cross-sectional view schematically showing a four-layer structure multilayer ceramic capacitor according to a second modified example. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited to these.

[0010] A dual-structure multilayer ceramic capacitor 1 according to an embodiment will be described with reference to the drawings. The dual-structure multilayer ceramic capacitor 1 according to this embodiment has a small rate of change in capacitance due to temperature change and is a temperature-compensating capacitor used for matching filters and high-frequency circuits. However, the dual-structure multilayer ceramic capacitor 1 according to the present disclosure is not limited to this. FIG. 1 is an external perspective view of the dual-structure multilayer ceramic capacitor 1 according to an embodiment. FIG. 2 is a cross-sectional view taken along II-II in FIG. 1 and is a diagram illustrating a schematic configuration of a dual-structure laminate according to an embodiment. FIG. 3 is a cross-sectional view taken along III-III in FIG. 2. FIG. 4A is a cross-sectional view taken along IVA-IVA in FIG. 2 and is a cross-sectional view taken along the first internal electrode layer and the second internal electrode layer. FIG. 4B is a cross-sectional view taken along IVB-IVB in FIG. 2 and is a cross-sectional view taken along the intermediate electrode layer.

[0011] The drawings may be simplified and schematic for the purpose of explaining the invention, and the dimensional ratios of the depicted components or between the components may not match those described in the specification. Furthermore, components described in the specification may be omitted from the drawings, or the number of components may be omitted. For example, the number of internal electrode layers shown in Figures 2 and 3 is seven for the sake of convenience, but this does not represent the actual number of internal electrode layers 30. The same applies to Figures 6 to 8. Terms used in the present invention that specify shapes and geometric conditions, as well as their degrees of similarity, such as "parallel," "orthogonal," and "identical," as well as values ​​of lengths and angles, are not limited to their strict meanings but are interpreted to encompass a range within which similar functions can be expected.

[0012] 1, the multilayer ceramic capacitor 1 according to the embodiment has a substantially rectangular parallelepiped shape. The multilayer ceramic capacitor 1 includes a laminate 10 having a substantially rectangular parallelepiped shape and a pair of external electrodes 40 disposed at both ends of the laminate 10 while being spaced apart from each other.

[0013] In Fig. 1, arrow T indicates the stacking direction as the height direction of the multilayer ceramic capacitor 1 and the laminate 10. This stacking direction T is also the thickness direction of the multilayer ceramic capacitor 1 and the laminate 10. In Fig. 1, arrow L indicates the length direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T. In Fig. 1, arrow W indicates the width direction of the multilayer ceramic capacitor 1 and the laminate 10, which is perpendicular to the stacking direction T and the length direction L. A pair of external electrodes 40 is disposed at one end and the other end of the length direction L of the laminate 10, respectively.

[0014] 1 to 4B show an XYZ Cartesian coordinate system. The length direction L of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the X direction. The width direction W of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Y direction. The stacking direction T of the multilayer ceramic capacitor 1 and the laminate 10 corresponds to the Z direction. Here, the cross section shown in FIG. 2 is also referred to as an LT cross section. The cross section shown in FIG. 3 is also referred to as a WT cross section. The cross sections shown in FIGS. 4A and 4B are also referred to as LW cross sections.

[0015] As shown in Figures 1 to 4B, the laminate 10 includes a first main surface TS1 and a second main surface TS2 facing in the stacking direction T, a first end surface LS1 and a second end surface LS2 facing in a length direction L perpendicular to the stacking direction T, and a first side surface WS1 and a second side surface WS2 facing in a width direction W perpendicular to the stacking direction T and the length direction L.

[0016] As shown in FIG. 1, the laminate 10 has a substantially rectangular parallelepiped shape. The dimension of the laminate 10 in the length direction L is not necessarily longer than the dimension in the width direction W. The corners and ridges of the laminate 10 are preferably rounded. A corner is a portion where three surfaces of the laminate intersect, and a ridge is a portion where two surfaces of the laminate intersect. Incidentally, unevenness may be formed on part or all of the surfaces constituting the laminate 10.

[0017] The dimensions of the laminate 10 are not particularly limited, but if the dimension of the laminate 10 in the length direction L is defined as the L dimension, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the dimension of the laminate 10 in the stacking direction T is defined as the T dimension, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the dimension of the laminate 10 in the width direction W is defined as the W dimension, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0018] As shown in Figures 2 and 3, the laminate 10 has an inner layer portion 11, and a first main surface side outer layer portion 12 and a second main surface side outer layer portion 13 arranged to sandwich the inner layer portion 11 in the stacking direction T.

[0019] The inner layer portion 11 includes a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in the stacking direction T. The inner layer portion 11 includes the internal electrode layer 30 located closest to the first principal surface TS1 to the internal electrode layer 30 located closest to the second principal surface TS2 in the stacking direction T. In the inner layer portion 11, the plurality of internal electrode layers 30 are arranged opposite each other with the dielectric layer 20 interposed therebetween. The inner layer portion 11 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0020] The multiple dielectric layers 20 are made of a dielectric material. As described above, the multilayer ceramic capacitor 1 according to this embodiment is a temperature-compensated capacitor, and the dielectric material is a CaZrO3-based (hereinafter sometimes abbreviated as CZ-based) or Ca(Sr,Zr)O3-based (hereinafter sometimes abbreviated as CSZ-based) dielectric material. CZ-based and CSZ-based dielectric materials contain perovskite compounds containing at least Ca and Zr. CZ-based dielectric materials are materials based on CaZrO3, as well as CaZrO3 solid solutions in which part of Ca, part of Zr, or part of Ca and Zr is replaced with an appropriate element. The dielectric material contains at least one of Ca (calcium), Zr (zirconium), and Ti (titanium). As an example, the dielectric layer 20 contains a perovskite-type compound containing Ca and Zr and optionally Sr and Ti. Specifically, the dielectric layer 20 contains CaZrO3 (calcium zirconate), CaTiO3 (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), titanium oxide (TiO2), etc. Normally, multilayer ceramic capacitor 1 generates oxygen vacancies when fired in a reducing atmosphere. However, CaZrO3, in particular, has a wide band gap that can suppress the generation of oxygen vacancies. As a result, high reliability can be achieved. Furthermore, the dielectric material may contain these main components plus secondary components such as Mn compounds, Fe compounds, Cr compounds, Co compounds, and Ni compounds.

[0021] The dielectric layer 20 of this embodiment uses a material containing at least one of Ca (calcium), Zr (zirconium), and Ti (titanium), and therefore has a relative dielectric constant of approximately 20 to 300 and a smaller capacitance than high-dielectric-constant materials. Furthermore, the dielectric layer 20 of this embodiment has the characteristic that the relative dielectric constant changes almost linearly with temperature, providing excellent heat resistance and high-frequency characteristics. Furthermore, the dielectric layer 20 of this embodiment exhibits negligible change in capacitance value over time, resulting in small capacitor loss and excellent stability even at high temperatures, high power, and high frequencies. Additionally, the dielectric layer 20 exhibits small changes in its dielectric constant over time and with application of voltage. The dielectric material is not limited to this, and may be a high-dielectric-constant ceramic such as a BaTiO3 (BT)-based material.

[0022] The thickness of the dielectric layer 20 is preferably 0.2 μm or more and 15 μm or less. In particular, the thickness of the dielectric layer 20 is preferably 3 μm or more and 10 μm or less. The number of laminated dielectric layers 20 is preferably 15 or more and 1200 or less. Note that this number of dielectric layers 20 is the total number of the dielectric layers 20 in the inner layer portion 11 and the number of the dielectric layers 20 in each of the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13.

[0023] The multiple internal electrode layers 30 include multiple first internal electrode layers 31, multiple second internal electrode layers 32, and intermediate electrode layers 33. The first internal electrode layers 31 and the second internal electrode layers 32 are arranged adjacent to each other while being spaced apart in the length direction L, and the first internal electrode layers 31 and the second internal electrode layers 32 and the intermediate electrode layers 33 are arranged alternately in the stacking direction T with the dielectric layer 20 sandwiched therebetween.

[0024] The first internal electrode layer 31 is extended to the first end face LS1 and connected to a first external electrode 40A (described later). The second internal electrode layer 32 is extended to the second end face LS2 and connected to a second external electrode 40B (described later). The intermediate electrode layer 33 is not extended to either the first end face LS1 or the second end face LS2, and is not connected to either the first external electrode 40A or the second external electrode 40B (described later). The first internal electrode layer 31, the intermediate electrode layer 33, and the second internal electrode layer 32 included in the multiple internal electrode layers 30 form a series-connected capacitor element. Note that, hereinafter, when it is not necessary to distinguish between the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be collectively referred to as the internal electrode layer 30.

[0025] As shown in FIGS. 2 and 4A , the first internal electrode layer 31 has a first opposing portion EA and a first lead portion D1. The first opposing portion EA is a region facing the intermediate electrode layer 33 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The first internal electrode layer 31 has a first opposing portion EA connected to the first lead portion D1 and facing the internal electrode layer 30 arranged adjacent to the first internal electrode layer 31 in the stacking direction T. The first lead portion D1 is a portion extending from the first opposing portion EA to the first end face LS1 and exposed at the first end face LS1. The first internal electrode layer 31 has a first lead portion D1, one end of which is extended to the first end face LS1 and connected to the first external electrode 40A.

[0026] As shown in FIGS. 2 and 4A, the second internal electrode layer 32 has a second opposing portion EB and a second lead portion D2. The second opposing portion EB is a region facing the intermediate electrode layer 33 arranged adjacent to the second internal electrode layer 32 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second internal electrode layer 32 has a second opposing portion EB connected to the second lead portion D2 and facing the internal electrode layer 30 arranged adjacent to the second internal electrode layer 32 in the stacking direction T. The second lead portion D2 is a portion drawn from the second opposing portion EB to the second end face LS2 and is exposed at the second end face LS2. The second internal electrode layer 32 has a second lead portion D2, one end of which is drawn to the second end face LS2 and connected to the second external electrode 40B.

[0027] 2 and 4B, the intermediate electrode layer 33 has a first electrode layer side facing portion ECA, a second electrode layer side facing portion ECB, and a connecting portion E0. The first electrode layer side facing portion ECA is a region facing the first internal electrode layer 31 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The second electrode layer side facing portion ECB is a region facing the second internal electrode layer 32 arranged adjacent to the first internal electrode layer 31 in the stacking direction T with the dielectric layer 20 sandwiched therebetween, and is located inside the laminate 10. The connecting portion E0 is a portion that connects the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB, and is located between the first electrode layer side facing portion ECA and the second electrode layer side facing portion ECB.

[0028] In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is disposed away from the first end face LS1. In the multilayer ceramic capacitor 1 according to this embodiment, the end of the intermediate electrode layer 33 on the first end face LS1 side is disposed closer to the first end face LS1 than the end 40AE of the first external electrode 40A. However, this is not limiting, and the end of the intermediate electrode layer 33 on the first end face LS1 side may be disposed closer to the second end face LS2 than the end 40AE of the first external electrode 40A.

[0029] An end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed spaced apart from the second end face LS2. In the multilayer ceramic capacitor 1 according to this embodiment, the end portion of the intermediate electrode layer 33 on the second end face LS2 side is disposed closer to the second end face LS2 than the end portion 40BE of the second external electrode 40B. However, this is not limiting, and the end portion of the intermediate electrode layer 33 on the second end face LS2 side may be disposed closer to the first end face LS1 than the end portion 40BE of the second external electrode 40B.

[0030] 2, in the multilayer ceramic capacitor 1 according to the embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the embodiment, the first internal electrode layer 31 and the second internal electrode layer 32 are stacked alternately with the intermediate electrode layer 33 interposed between them, with the dielectric layer 20 interposed therebetween.

[0031] In the multilayer ceramic capacitor 1 of this embodiment, the first opposing portion EA and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a portion that generates the capacitance CAP1. Hereinafter, the portion that generates the capacitance CAP1 will be referred to as the first capacitor portion CAP1.

[0032] In the multilayer ceramic capacitor 1 of this embodiment, the second opposing portion EB and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 face each other via the dielectric layer 20, thereby forming a portion that generates the capacitance CAP2. Hereinafter, the portion that generates the capacitance CAP2 will be referred to as the second capacitor portion CAP2.

[0033] That is, the laminate 10 includes a first capacitor portion CAP1 formed by opposing first internal electrode layers 31 and intermediate electrode layers 33, and a second capacitor portion CAP2 formed by opposing second internal electrode layers 32 and intermediate electrode layers 33. In FIG. 2, the rectangular regions of the first capacitor portion CAP1 and the second capacitor portion CAP2 in the LT cross section are indicated by two-dot chain lines. A connecting portion E0 connects the first capacitor portion CAP1 and the second capacitor portion CAP2 in series. The multilayer ceramic capacitor 1 of this embodiment is a multilayer ceramic capacitor 1 with a so-called double series structure in which two capacitor portions (the first capacitor portion CAP1 and the second capacitor portion CAP2) are connected in series.

[0034] The first capacitor part CAP1 has a portion 1a on the second end face LS2 side. This portion 1a on the second end face LS2 side refers to a portion of the first capacitor part CAP1 that corresponds to the end face opposite the second end face LS2 and the vicinity of the portion that corresponds to the end face.

[0035] The second capacitor part CAP2 has a portion 2a on the first end face LS1 side. This portion 2a on the first end face LS1 side refers to a portion of the second capacitor part CAP2 that corresponds to the end face facing the first end face LS1 and the vicinity of the portion that corresponds to the end face.

[0036] The shapes of the first opposing portion EA, the second opposing portion EB, the first electrode layer side opposing portion ECA, and the second electrode layer side opposing portion ECB are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shapes of the first lead portion D1 and the second lead portion D2 are not particularly limited, but are preferably rectangular. However, the corners of the rectangular shape may be rounded or the corners of the rectangular shape may be formed at an angle. The shape of the connecting portion E0 is not particularly limited, but is preferably rectangular.

[0037] The width direction W dimension of the first opposing portion EA and the width direction W dimension of the first lead portion D1 may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the second opposing portion EB and the width direction W dimension of the second lead portion D2 may be the same dimension, or one of the dimensions may be smaller. The width direction W dimension of the first electrode layer side opposing portion ECA and the second electrode layer side opposing portion ECB and the width direction W dimension of the connecting portion E0 may be the same dimension, or one of the dimensions may be smaller.

[0038] The first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 are made of an appropriate conductive material, such as a metal such as Ni, Cu, Ag, Pd, or Au, or an alloy containing at least one of these metals. When an alloy is used, the first internal electrode layer 31, the second internal electrode layer 32, and the intermediate electrode layer 33 may be made of, for example, an Ag-Pd alloy.

[0039] The thickness of each of the first internal electrode layers 31, the second internal electrode layers 32, and the intermediate electrode layers 33 is preferably, for example, 0.2 μm or more and 2.0 μm or less. The total number of the first internal electrode layers 31, the second internal electrode layers 32, and the intermediate electrode layers 33 is preferably 10 or more and 1000 or less.

[0040] As shown in FIGS. 2 and 3 , the first main surface side outer layer portion 12 is located on the first main surface TS1 side of the laminate 10. The first main surface side outer layer portion 12 is an assembly of multiple dielectric layers 20 located between the first main surface TS1 and the internal electrode layer 30 closest to the first main surface TS1. On the other hand, the second main surface side outer layer portion 13 is located on the second main surface TS2 side of the laminate 10. The second main surface side outer layer portion 13 is an assembly of multiple dielectric layers 20 located between the second main surface TS2 and the internal electrode layer 30 closest to the second main surface TS2. The dielectric layers 20 used in the first main surface side outer layer portion 12 and the second main surface side outer layer portion 13 may both be the same as the dielectric layers 20 used in the internal layer portion 11.

[0041] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a first capacitor portion CAP1, a second capacitor portion CAP2, and a connecting portion E0 of the intermediate electrode layer 33 that connects the first capacitor portion CAP1 and the second capacitor portion CAP2 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. FIGS. 4A and 4B show the ranges of the series capacitor-forming portion 11E in the width direction W and the length direction L. Of the series capacitor-forming portion 11E, the first capacitor portion CAP1 and the second capacitor portion CAP2 are also referred to as effective capacitor portions.

[0042] The laminate 10 has side surface-side outer layer portions. The side surface-side outer layer portions include a first side surface-side outer layer portion WG1 and a second side surface-side outer layer portion WG2. The first side surface-side outer layer portion WG1 is a portion including the dielectric layer 20 located between the series capacitor-forming portion 11E and the first side surface WS1. The second side surface-side outer layer portion WG2 is a portion including the dielectric layer 20 located between the series capacitor-forming portion 11E and the second side surface WS2. FIGS. 3, 4A, and 4B show the ranges in the width direction W of the first side surface-side outer layer portion WG1 and the second side surface-side outer layer portion WG2. The side surface-side outer layer portions are also referred to as W gaps or side gaps.

[0043] The laminate 10 has an end surface side outer layer portion. The end surface side outer layer portion has a first end surface side outer layer portion LG1 and a second end surface side outer layer portion LG2. The first end surface side outer layer portion LG1 is a portion located between the series capacitor forming portion 11E and the first end surface LS1 and including the dielectric layers 20 and the first lead portion D1. That is, the first end surface side outer layer portion LG1 is an assembly of the portions of the multiple dielectric layers 20 on the first end surface LS1 side and the multiple first lead portions D1. The second end surface side outer layer portion LG2 is a portion located between the series capacitor forming portion 11E and the second end surface LS2 and including the dielectric layers 20 and the second lead portion D2. That is, the second end surface side outer layer portion LG2 is an assembly of the portions of the multiple dielectric layers 20 on the second end surface LS2 side and the multiple second lead portions D2. 2, 4A, and 4B show the range of the first end-side outer layer portion LG1 and the second end-side outer layer portion LG2 in the length direction L. The end-side outer layer portions are also called L gaps or end gaps.

[0044] The series capacitor forming portion 11E of the laminate 10 has a series connection region. The series connection region is a portion located between the first capacitor portion CAP1 and the second capacitor portion CAP2, and includes the dielectric layer 20 and the coupling portion E0. That is, the series connection region is an assembly of the central portions of the multiple dielectric layers 20 in the length direction L and the multiple coupling portions E0. The series connection region is also referred to as a middle gap.

[0045] As shown in Figures 1 and 2, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0046] The first external electrode 40A and the second external electrode 40B have the same basic configuration. The first external electrode 40A and the second external electrode 40B have shapes that are approximately plane-symmetric with respect to a WT cross section at the center of the longitudinal direction L of the multilayer ceramic capacitor 1. Therefore, in the following, when it is not necessary to distinguish between the first external electrode 40A and the second external electrode 40B, the first external electrode 40A and the second external electrode 40B may be collectively referred to as the external electrodes 40.

[0047] The first external electrode 40A is disposed on the first end face LS1. The first external electrode 40A is in contact with the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. This electrically connects the first external electrode 40A to the first internal electrode layers 31. The first external electrode 40A may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the first external electrode 40A is formed to extend from the first end face LS1 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0048] The second external electrode 40B is disposed on the second end face LS2. The second external electrode 40B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. This electrically connects the second external electrode 40B to the second internal electrode layers 32. The second external electrode 40B may also be disposed on a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2. In this embodiment, the second external electrode 40B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0049] As described above, in the laminate 10, the first capacitor portion CAP1 is formed by the first opposing portion EA of the first internal electrode layer 31 and the first electrode layer side opposing portion ECA of the intermediate electrode layer 33 facing each other via the dielectric layer 20. The second capacitor portion CAP2 is formed by the second opposing portion EB of the second internal electrode layer 32 and the second electrode layer side opposing portion ECB of the intermediate electrode layer 33 facing each other via the dielectric layer 20.

[0050] The coupling portion E0 connects the first capacitor portion CAP1 and the second capacitor portion CAP2 in series, and therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first outer electrode 40A connected to the first internal electrode layer 31 and the second outer electrode 40B connected to the second internal electrode layer 32.

[0051] 2, the first external electrode 40A has a first base electrode layer 50A and a first plating layer 60A disposed on the first base electrode layer 50A. The second external electrode 40B has a second base electrode layer 50B and a second plating layer 60B disposed on the second base electrode layer 50B.

[0052] The first base electrode layer 50A is disposed on the first end face LS1. The first base electrode layer 50A is connected to the first lead portions D1 of each of the first internal electrode layers 31 exposed at the first end face LS1. In this embodiment, the first base electrode layer 50A is formed to extend from the first end face LS1 to a portion of the first main surface TS1, a portion of the second main surface TS2, and a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0053] The second base electrode layer 50B is disposed on the second end face LS2. The second base electrode layer 50B is in contact with the second lead portions D2 of each of the second internal electrode layers 32 exposed at the second end face LS2. In this embodiment, the second base electrode layer 50B is formed to extend from the second end face LS2 to a portion of the first main surface TS1 and a portion of the second main surface TS2, as well as a portion of the first side surface WS1 and a portion of the second side surface WS2.

[0054] The first base electrode layer 50A and the second base electrode layer 50B include at least one selected from a baked layer, a thin film layer, and the like.

[0055] The first base electrode layer 50A and the second base electrode layer 50B of this embodiment are baked layers. The baked layers preferably contain a metal component and either a glass component or a ceramic component, or both. The metal component includes at least one selected from, for example, Cu, Ni, Ag, Pd, an Ag-Pd alloy, and Au. The glass component includes at least one selected from, for example, B, Si, Ba, Mg, Al, and Li. The ceramic component may be the same ceramic material as that of the dielectric layer 20, or a different ceramic material. The ceramic component may include at least one selected from, for example, CaZrO3 (calcium zirconate), CaTiO (calcium titanate), SrTiO3 (strontium titanate), BaZrO3 (proton-conducting metal oxide), and titanium oxide (TiO2).

[0056] The baked layer is formed by, for example, applying a conductive paste containing glass and metal to the laminate 10 and baking it. The baked layer can be formed by co-firing a pre-fired laminate chip, which is the material for the laminate 10 having multiple internal electrode layers and dielectric layers, with a conductive paste applied to the laminate chip. Alternatively, the baked layer can be formed by first firing the laminate chip to obtain the laminate 10, and then applying a conductive paste to the laminate 10 and baking it. In the above configuration, the baked layer is preferably formed by baking a material to which a ceramic material is added instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as the dielectric layer 20 as the added ceramic material. The baked layer may be multiple layers.

[0057] The thickness of the first base electrode layer 50A located on the first end face LS1 in the longitudinal direction L is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the first base electrode layer 50A in the stacking direction T and width direction W.

[0058] The thickness of the second base electrode layer 50B located on the second end face LS2 in the longitudinal direction L is preferably, for example, approximately 2 μm or more and 220 μm or less at the center of the second base electrode layer 50B in the stacking direction T and width direction W.

[0059] When the first base electrode layer 50A is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the first base electrode layer 50A provided on this portion, corresponding to the stacking direction T, is preferably, for example, approximately 3 μm or more and 40 μm or less, at the center of the first base electrode layer 50A provided on this portion in the length direction L and width direction W.

[0060] When the first base electrode layer 50A is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the first base electrode layer 50A provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the first base electrode layer 50A provided on this portion in the length direction L and stacking direction T.

[0061] When the second base electrode layer 50B is provided on a portion of at least one of the first main surface TS1 or the second main surface TS2, the thickness of the second base electrode layer 50B provided on this portion in the stacking direction T is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided on this portion in the length direction L and width direction W.

[0062] When the second base electrode layer 50B is provided on a portion of at least one of the first side surface WS1 or the second side surface WS2, the thickness of the second base electrode layer 50B provided on this portion in the width direction W is preferably, for example, approximately 3 μm or more and 40 μm or less at the center of the second base electrode layer 50B provided on this portion in the length direction L and stacking direction T.

[0063] The first plating layer 60A is disposed so as to cover the first base electrode layer 50A.

[0064] The second plating layer 60B is disposed so as to cover the second base electrode layer 50B.

[0065] The first plating layer 60A and the second plating layer 60B may contain at least one selected from, for example, Cu, Ni, Sn, Ag, Pd, an Ag-Pd alloy, Au, etc. The first plating layer 60A and the second plating layer 60B may each be formed of multiple layers. The first plating layer 60A and the second plating layer 60B preferably have a two-layer structure in which a Sn plating layer is formed on a Ni plating layer.

[0066] In this embodiment, the first plating layer 60A has a first Ni plating layer 61A and a first Sn plating layer 62A located on the first Ni plating layer 61A.

[0067] In this embodiment, the second plating layer 60B has a second Ni plating layer 61B and a second Sn plating layer 62B located on the second Ni plating layer 61B.

[0068] The Ni plating layer prevents the first base electrode layer 50A and the second base electrode layer 50B from being eroded by solder when mounting the multilayer ceramic capacitor 1. The Sn plating layer improves the wettability of the solder when mounting the multilayer ceramic capacitor 1, thereby facilitating mounting of the multilayer ceramic capacitor 1. The thickness of each of the first Ni plating layer 61A, the first Sn plating layer 62A, the second Ni plating layer 61B, and the second Sn plating layer 62B is preferably 1 μm or more and 15 μm or less.

[0069] The external electrode 40 of this embodiment may have, for example, a conductive resin layer containing conductive particles and a thermosetting resin. The conductive resin layer may be disposed so as to cover the baked layer. When the conductive resin layer is disposed so as to cover the baked layer, the conductive resin layer is disposed between the baked layer and the plating layer (first plating layer 60A, second plating layer 60B). The conductive resin layer may completely cover the baked layer or may cover only a portion of the baked layer.

[0070] The conductive resin layer containing a thermosetting resin is more flexible than a conductive layer made of, for example, a plating film or a fired conductive paste. Therefore, even if the multilayer ceramic capacitor 1 is subjected to a physical shock or a shock due to a thermal cycle, the conductive resin layer functions as a buffer layer. Therefore, the conductive resin layer suppresses the occurrence of cracks in the multilayer ceramic capacitor 1.

[0071] The metal constituting the conductive particles may be Ag, Cu, Ni, Sn, Bi, or an alloy containing any of these. The conductive particles preferably contain Ag. The conductive particles may be, for example, Ag metal powder. Ag has the lowest resistivity among metals, making it suitable as an electrode material. Furthermore, Ag is a noble metal, so it is resistant to oxidation and has high weather resistance. Therefore, Ag metal powder is suitable as the conductive particles.

[0072] The conductive particles may also be metal powders whose surfaces are coated with Ag. When using metal powders whose surfaces are coated with Ag, the metal powder is preferably Cu, Ni, Sn, Bi, or an alloy powder thereof. In order to maintain the properties of Ag while making the base metal inexpensive, it is preferable to use Ag-coated metal powders.

[0073] Furthermore, the conductive particles may be Cu or Ni that has been subjected to an anti-oxidation treatment. Furthermore, the conductive particles may be metal powder whose surface is coated with Sn, Ni, or Cu. When using metal powder whose surface is coated with Sn, Ni, or Cu, the metal powder is preferably Ag, Cu, Ni, Sn, Bi, or an alloy powder thereof.

[0074] The shape of the conductive particles is not particularly limited. The conductive particles may be spherical, flat, or other shapes, but it is preferable to use a mixture of spherical metal powder and flat metal powder.

[0075] The conductive particles contained in the conductive resin layer mainly play a role in ensuring the electrical conductivity of the conductive resin layer. Specifically, the conductive particles come into contact with each other to form electrical paths within the conductive resin layer.

[0076] The resin constituting the conductive resin layer may include at least one selected from various known thermosetting resins, such as epoxy resin, phenolic resin, urethane resin, silicone resin, and polyimide resin. Among these, epoxy resin, which has excellent heat resistance, moisture resistance, and adhesion, is one of the most suitable resins. Furthermore, the resin of the conductive resin layer preferably includes a curing agent in addition to the thermosetting resin. When an epoxy resin is used as the base resin, the curing agent for the epoxy resin may be any of various known compounds, such as phenolic, amine, acid anhydride, imidazole, active ester, and amide-imide compounds.

[0077] The conductive resin layer may be formed of a plurality of layers. The thickness of the thickest part of the conductive resin layer is preferably 10 μm or more and 150 μm or less.

[0078] The above is the basic configuration of the multilayer ceramic capacitor 1 according to the embodiment. If the lengthwise dimension of the multilayer ceramic capacitor 1 including the laminate 10 and the external electrodes 40 is defined as L, then the L dimension is preferably 0.2 mm or more and 10 mm or less. If the lengthwise dimension of the multilayer ceramic capacitor 1 is defined as T, then the T dimension is preferably 0.1 mm or more and 10 mm or less. If the widthwise dimension of the multilayer ceramic capacitor 1 is defined as W, then the W dimension is preferably 0.1 mm or more and 10 mm or less.

[0079] The multilayer ceramic capacitor 1 of this embodiment having the above basic configuration has the following features in the external electrodes 40, that is, the first external electrode 40A and the second external electrode 40B.

[0080] As shown in FIG. 2, the first external electrode 40A of this embodiment includes a first end face side external electrode 400A arranged on the first end face LS1, a first main face side external electrode 411A arranged on the first main face TS1, and a second main face side external electrode 412A arranged on the second main face TS2, and as shown in FIGS. 4A and 4B, a first side face side external electrode 421A arranged on the first side face WS1 and a second side face side external electrode 422A arranged on the second side face WS2.

[0081] 2, the first end face side external electrode 400A of the first external electrode 40A has a first end face side base electrode layer 500A arranged on the first end face LS1 and a first end face side plating layer 600A formed above the first end face side base electrode layer 500A. The first end face side base electrode layer 500A is part of the first base electrode layer 50A. The first end face side plating layer 600A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0082] 2, the first main surface-side external electrode 411A of the first external electrode 40A has a first main surface-side base electrode layer 511A disposed on the first main surface TS1 and a first main surface-side plating layer 611A formed above the first main surface-side base electrode layer 511A. The first main surface-side base electrode layer 511A is part of the first base electrode layer 50A. The first main surface-side plating layer 611A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0083] 2, the second main surface-side external electrode 412A of the first external electrode 40A has a second main surface-side base electrode layer 512A disposed on the second main surface TS2 and a second main surface-side plating layer 612A formed above the second main surface-side base electrode layer 512A. The second main surface-side base electrode layer 512A is part of the first base electrode layer 50A. The second main surface-side plating layer 612A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0084] 4A and 4B, the first side-face-side external electrode 421A of the first external electrode 40A has a first side-face-side base electrode layer 521A disposed on the first side face WS1 and a first side-face-side plating layer 621A formed above the first side-face-side base electrode layer 521A. The first side-face-side base electrode layer 521A is part of the first base electrode layer 50A. The first side-face-side plating layer 621A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0085] 4A and 4B, the second side-face-side external electrode 422A of the first external electrode 40A has a second side-face-side base electrode layer 522A disposed on the second side face WS2 and a second side-face-side plating layer 622A formed above the second side-face-side base electrode layer 522A. The second side-face-side base electrode layer 522A is part of the first base electrode layer 50A. The second side-face-side plating layer 622A is part of the first plating layer 60A and has a first Ni plating layer 61A and a first Sn plating layer 62A on the first Ni plating layer 61A.

[0086] As shown in FIG. 2, the second external electrode 40B of this embodiment includes a second end face side external electrode 400B arranged on the second end face LS2, a third main face side external electrode 411B arranged on the first main face TS1, and a fourth main face side external electrode 412B arranged on the second main face TS2, and as shown in FIGS. 4A and 4B, a third side face side external electrode 421B arranged on the first side face WS1 and a fourth side face side external electrode 422B arranged on the second side face WS2.

[0087] 2, the second end surface side external electrode 400B of the second external electrode 40B has a second end surface side base electrode layer 500B arranged on the second end surface LS2 and a second end surface side plating layer 600B formed above the second end surface side base electrode layer 500B. The second end surface side base electrode layer 500B is part of the second base electrode layer 50B. The second end surface side plating layer 600B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0088] 2, the third main surface-side external electrode 411B of the second external electrode 40B has a third main surface-side base electrode layer 511B disposed on the first main surface TS1 and a third main surface-side plating layer 611B formed above the third main surface-side base electrode layer 511B. The third main surface-side base electrode layer 511B is part of the second base electrode layer 50B. The third main surface-side plating layer 611B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0089] 2, the fourth main surface-side external electrode 412B of the second external electrode 40B has a fourth main surface-side base electrode layer 512B disposed on the second main surface TS2 and a fourth main surface-side plating layer 612B formed above the fourth main surface-side base electrode layer 512B. The fourth main surface-side base electrode layer 512B is part of the second base electrode layer 50B. The fourth main surface-side plating layer 612B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0090] 4A and 4B, the third side-side external electrode 421B of the second external electrode 40B has a third side-side base electrode layer 521B disposed on the first side surface WS1 and a third side-side plating layer 621B formed above the third side-side base electrode layer 521B. The third side-side base electrode layer 521B is part of the second base electrode layer 50B. The third side-side plating layer 621B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B.

[0091] 4A and 4B, the fourth side surface side external electrode 422B of the second external electrode 40B has a fourth side surface side base electrode layer 522B arranged on the second side surface WS2 and a fourth side surface side plating layer 622B formed above the fourth side surface side base electrode layer 522B. The fourth side surface side base electrode layer 522B is part of the second base electrode layer 50B. The fourth side surface side plating layer 622B is part of the second plating layer 60B and has a second Ni plating layer 61B and a second Sn plating layer 62B on the second Ni plating layer 61B. The maximum thickness of each of the first principal surface side base electrode layer 511A, the second principal surface side base electrode layer 512A, the third principal surface side base electrode layer 511B, and the fourth principal surface side base electrode layer 512B is not limited, but is preferably, for example, 15 μm or more and 40 μm or less.

[0092] As shown in FIG. 2, the first main surface side external electrode 411A of the first external electrode 40A has a first recess 510A recessed toward the laminate 10. The first recess 510A is formed on the surface of the first main surface side external electrode 411A. The first recess 510A has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., in the direction from the front to the back of the paper surface of FIG. 2. The first recess 510A is preferably formed over the entire length of the first main surface side external electrode 411A along the width direction W. The first recess 510A may be located approximately in the vicinity of the center of the first main surface side external electrode 411A in the length direction L, or may be located on the inside or outside of the length direction L.

[0093] The first recess 510A of this embodiment is formed by recessing the first principal surface side base electrode layer 511A and the first principal surface side plating layer 611A toward the first principal surface TS1 of the laminate 10. In the LT cross-sectional view, the first recess 510A preferably has a rounded bottom, and both edges in the length direction L that transition to the surface of the first principal surface side external electrode 411A also preferably have a gently rounded shape. The depth of the first recess 510A is not limited, but is preferably, for example, 3 μm to 35 μm. Note that the depth here refers to the shortest distance between a line connecting the surfaces of the first principal surface side external electrode 411A on both sides of the first recess 510A in the length direction L and the deepest part of the first recess 510A. The width of the first recess 510A (the dimension corresponding to the length direction L) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0094] As shown in FIG. 2, the second main surface side external electrode 412A of the first external electrode 40A has a second recess 520A recessed toward the laminate 10. The second recess 520A is formed on the surface of the second main surface side external electrode 412A. The second recess 520A has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., in the direction from the front to the back of the paper surface of FIG. 2. The second recess 520A is preferably formed over the entire length of the second main surface side external electrode 412A along the width direction W. The second recess 520A may be located approximately in the vicinity of the center of the second main surface side external electrode 412A in the length direction L, or may be located on the inside or outside of the length direction L.

[0095] The second recess 520A of this embodiment is formed by recessing the second principal surface side base electrode layer 512A and the second principal surface side plating layer 612A toward the second principal surface TS2 of the laminate 10. In the LT cross-sectional view, the second recess 520A preferably has a rounded bottom, and both edges in the length direction L that transition to the surface of the second principal surface side external electrode 412A are also formed with a gently rounded shape. The depth of the second recess 520A is not limited, but is preferably, for example, 3 μm to 35 μm. Note that the depth here refers to the shortest distance between a line connecting the surfaces of the second principal surface side external electrode 412A on both sides of the second recess 520A in the length direction L and the deepest part of the second recess 520A. The width of the second recess 520A (the dimension corresponding to the length direction L) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0096] As shown in FIG. 2, the third main surface side external electrode 411B of the second external electrode 40B has a third recess 530B recessed toward the laminate 10. The third recess 530B is formed on the surface of the third main surface side external electrode 411B. The third recess 530B has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., in the direction from the front to the back of the paper surface of FIG. 2. The third recess 530B is preferably formed over the entire length of the third main surface side external electrode 411B along the width direction W. The third recess 530B may be located approximately in the vicinity of the center of the third main surface side external electrode 411B in the length direction L, or may be located on the inside or outside of the length direction L.

[0097] The third recess 530B of this embodiment is formed by recessing the third principal surface side base electrode layer 511B and the third principal surface side plating layer 611B toward the first principal surface TS1 side of the laminate 10. In the LT cross-sectional view, the third recess 530B preferably has a rounded bottom, and both edges in the length direction L that transition to the surface of the third principal surface side external electrode 411B are also preferably gently rounded. The depth of the third recess 530B is not limited, but is preferably, for example, 3 μm to 35 μm. Note that the depth here refers to the shortest distance between a line connecting the surfaces of the third principal surface side external electrode 411B on both sides of the third recess 530B in the length direction L and the deepest part of the third recess 530B. The width of the third recess 530B (the dimension corresponding to the length direction L) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0098] As shown in FIG. 2, the fourth main surface side external electrode 412B of the second external electrode 40B has a fourth recess 540B recessed toward the laminate 10. The fourth recess 540B is formed on the surface of the fourth main surface side external electrode 412B. The fourth recess 540B has a groove shape extending in the width direction W perpendicular to the LT cross section, i.e., in the direction from the front to the back of the paper surface of FIG. 2. The fourth recess 540B is preferably formed over the entire length of the fourth main surface side external electrode 412B in the width direction W. The fourth recess 540B may be located approximately in the vicinity of the center of the fourth main surface side external electrode 412B in the length direction L, or may be located on the inside or outside of the length direction L.

[0099] The fourth recess 540B of this embodiment is formed by recessing the fourth principal surface side base electrode layer 512B and the fourth principal surface side plating layer 612B toward the second principal surface TS2 of the laminate 10. In an LT cross-sectional view, the fourth recess 540B preferably has a rounded bottom, and both edges in the length direction L that transition to the surface of the fourth principal surface side external electrode 412B are also formed with a gently rounded curve. The depth of the fourth recess 540B is not limited, but is preferably, for example, 3 μm to 35 μm. Note that the depth here refers to the shortest distance between a line connecting the surfaces of the fourth principal surface side external electrode 412B on both sides of the fourth recess 540B in the length direction L and the deepest part of the fourth recess 540B. The width of the fourth recess 540B (the dimension corresponding to the length direction L) is not limited, but is preferably, for example, 50 μm to 400 μm.

[0100] The depth of the first recess 510A is not limited, but is preferably 10% to 80% of the maximum thickness of the first principal surface side external electrode 411A in the stacking direction T, and may be, for example, 40% to 80% or 60% to 80%. The depth of the second recess 520A is not limited, but is preferably 10% to 80% of the maximum thickness of the second principal surface side external electrode 412A in the stacking direction T, and may be, for example, 40% to 80% or 60% to 80%. The depth of the third recess 530B is not limited, but is preferably 10% to 80% of the maximum thickness of the third principal surface side external electrode 411B in the stacking direction T, and may be, for example, 40% to 80% or 60% to 80%. The depth of the fourth recess 540B is not limited, but is preferably 10% to 80% of the maximum thickness of the fourth main surface side external electrode 412B in the thickness corresponding to the stacking direction T, and may be, for example, 40% to 80%, or 60% to 80%.

[0101] FIG. 2, which shows the LT cross section of the multilayer ceramic capacitor 1, shows a first imaginary line 100 and a second imaginary line 200. The first imaginary line 100 is an imaginary line connecting the first recess 510A and the fourth recess 540B in the LT cross section of the multilayer ceramic capacitor 1. The first imaginary line 100 connects the deepest part of the first recess 510A and the deepest part of the fourth recess 540B. The second imaginary line 200 is an imaginary line connecting the second recess 520A and the third recess 530B in the LT cross section of the multilayer ceramic capacitor 1. The second imaginary line 200 connects the deepest part of the second recess 520A and the deepest part of the third recess 530B. FIG. 2 also shows an intersection 300 between the first imaginary line 100 and the second imaginary line 200.

[0102] In this embodiment, the intersection 300 of the first imaginary line 100 and the second imaginary line 200 is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the length direction L. The intersection 300 of the first imaginary line 100 and the second imaginary line 200 is located in the above-mentioned series connection region (intermediate gap).

[0103] In this embodiment, the first imaginary line 100 intersects with a portion 1a of the first capacitor portion CAP1 on the second end face LS2 side, and also intersects with a portion 2a of the second capacitor portion CAP2 on the first end face LS1 side.

[0104] In this embodiment, the second imaginary line 200 intersects with a portion 1a of the first capacitor portion CAP1 on the second end face LS2 side, and also intersects with a portion 2a of the second capacitor portion CAP2 on the first end face LS1 side.

[0105] In the multilayer ceramic capacitor 1 of this embodiment, the external electrodes 40, i.e., the first external electrode 40A and the second external electrode 40B, both have tensile stress as residual stress. This tensile stress is generated when the baked layers (first underlying electrode layer 50A, second underlying electrode layer 50B) of the external electrodes 40 formed on the surfaces of the laminate 10 contract during cooling, and acts, for example, from the main surface side external electrodes toward the centers of the end surface side external electrodes.

[0106] The tensile stress as the residual stress of the first external electrode 40A and the second external electrode 40B is, for example, 10 MPa or more, or 50 MPa or more.

[0107] The depth and width of each of the recesses described above can be measured, for example, by the following method. The multilayer ceramic capacitor 1 is polished from the first side surface WS1 or the second side surface WS2 to a position approximately halfway along the width direction W. This exposes the LT cross section at the center of the multilayer ceramic capacitor 1 in the width direction W. Next, a digital microscope is used to measure the depth and width of the recesses in the LT cross section exposed by polishing. This allows the depth and width of each recess to be confirmed.

[0108] As described above, in the multilayer ceramic capacitor 1 of this preferred embodiment, the first external electrode 40A and the second external electrode 40B have tensile stress. This tensile stress can be measured by the following method. First, a metal stripper for Sn removal is used, and the multilayer ceramic capacitor 1 is immersed in the liquid for a predetermined time, followed by rinsing with water to remove the Sn plating layer. Next, a metal stripper for Ni removal is used, and the multilayer ceramic capacitor 1 is immersed in the liquid for a predetermined time, followed by rinsing with water to remove the Ni plating layer. Thereafter, stress is measured using X-ray diffraction (μ-XRD) on the surfaces near the ends of the base electrode layer located on the first main surface TS1 and the second main surface TS2 of the multilayer ceramic capacitor 1 (near the ends 40AE and 40BE in FIG. 2).

[0109] Next, a method for manufacturing the multilayer ceramic capacitor 1 of this embodiment will be described. The method for manufacturing the multilayer ceramic capacitor 1 of this embodiment is not limited as long as it satisfies the above-mentioned requirements. However, a suitable manufacturing method includes the following steps. Each step will be described in detail below.

[0110] A dielectric sheet for the dielectric layer 20 and a conductive paste for the internal electrode layer 30 are prepared. The dielectric sheet and the conductive paste for the internal electrode contain a binder and a solvent. The binder and the solvent may be known.

[0111] On the dielectric sheets, a conductive paste for the internal electrode layers 30 is printed in a predetermined pattern by, for example, screen printing or gravure printing. In this way, dielectric sheets on which the patterns of the first internal electrode layers 31 and the second internal electrode layers 32 are formed, and dielectric sheets on which the patterns of the intermediate electrode layers 33 are formed are respectively prepared.

[0112] A predetermined number of dielectric sheets on which the patterns of the internal electrode layers 30 are not printed are stacked to form a portion that will become the first main surface-side outer layer portion 12 on the first main surface TS1 side. Dielectric sheets on which the patterns of the first internal electrode layers 31 and the second internal electrode layers 32 are formed and dielectric sheets on which the patterns of the intermediate electrode layers 33 are formed are stacked alternately in sequence on top of that. This forms a portion that will become the internal layer portion 11. A predetermined number of dielectric sheets on which the patterns of the internal electrode layers 30 are not printed are stacked on top of this portion that will become the internal layer portion 11 to form a portion that will become the second main surface-side outer layer portion 13 on the second main surface TS2 side. In this way, a laminated sheet is produced.

[0113] The laminated sheets are pressed in the height direction by means of a hydrostatic press or the like to produce a laminated block.

[0114] The laminated block is cut to a predetermined size to obtain a plurality of laminated chips, and at this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0115] The laminated chip is fired to produce the laminate 10. The firing temperature depends on the materials of the dielectric layers 20 and the internal electrode layers 30, but is preferably 900°C or higher and 1400°C or lower.

[0116] A conductive paste that will become a base electrode layer is applied to both end surfaces of the laminate 10 .

[0117] In this embodiment, the base electrode layer is a baked layer. A conductive paste containing a glass component and a metal is applied to the laminate 10 by a method such as dipping. A baking process is then performed to form the base electrode layer. The baking temperature at this time is preferably 700°C or higher and 900°C or lower.

[0118] When the unfired laminated chip and the conductive paste applied to the laminated chip are simultaneously fired, the fired layer is preferably formed by firing a material containing a ceramic material instead of a glass component. In this case, it is particularly preferable to use the same type of ceramic material as that of the dielectric layer 20 as the added ceramic material. In this case, the conductive paste is applied to the unfired laminated chip, and the laminated chip and the conductive paste applied to the laminated chip are simultaneously fired to form the laminate 10 with the fired layer.

[0119] Thereafter, a plating layer is formed on the surface of the base electrode layer. In this embodiment, a first plating layer 60A is formed on the surface of the first base electrode layer 50A. Furthermore, a second plating layer 60B is formed on the surface of the second base electrode layer 50B. In this embodiment, a Ni plating layer and an Sn plating layer are formed as the plating layers. Either electrolytic plating or electroless plating may be used for the plating process.

[0120] However, electroless plating has the disadvantage of requiring pretreatment with a catalyst to improve plating deposition speed, which makes the process more complicated. Therefore, electrolytic plating is usually preferred. The Ni plating layer and Sn plating layer are formed sequentially, for example, by barrel plating.

[0121] When a conductive resin layer is provided as the base electrode layer, the conductive resin layer may be disposed so as to cover the baked layer. When providing the conductive resin layer, a conductive resin paste containing a thermosetting resin and a metal component is applied onto the baked layer, and then heat-treated at a temperature of 250 to 550°C or higher. This causes the thermosetting resin to thermally harden, forming a conductive resin layer. The atmosphere during this heat treatment is preferably an N2 atmosphere. Furthermore, to prevent the resin from scattering and the various metal components from oxidizing, the oxygen concentration is preferably 100 ppm or less.

[0122] Here, in order to obtain the groove-shaped recesses described above in each of the main surface side external electrodes of the external electrodes 40 as in the embodiment, for example, the following method can be mentioned.

[0123] 5A to 5C are schematic diagrams illustrating steps for forming base electrode layers (first base electrode layer 50A, second base electrode layer 50B) in this method. As shown in FIG. 5A, a base electrode paste 50P that will become the base electrode layer is applied by dipping to the ends of the laminate 10 in the longitudinal direction L. Next, as shown in FIG. 5B, the laminate 10 is passed relatively between a pair of rod-shaped jigs 90 arranged facing each other. The passing direction here is the front-to-back direction of the paper in FIG. 5B. As a result, as shown in FIG. 5C, groove-shaped recesses G are formed on both sides of the base electrode paste 50P by the tips of the pair of rod-shaped jigs 90. These recesses G become the first recess 510A, second recess 520A, third recess 530B, and fourth recess 540B described above. Thereafter, a Ni plating layer and a Sn plating layer are formed on the base electrode layer.

[0124] It should be noted that recesses can also be formed by appropriately adjusting the viscosity of base electrode paste 50P or by devising a dipping method.

[0125] Through the above manufacturing steps, the multilayer ceramic capacitor 1 is manufactured.

[0126] The multilayer ceramic capacitor 1 according to the embodiment has a so-called series structure, which is a two-connected structure. In this multilayer ceramic capacitor 1, large electrostriction occurs between the series-connected capacitor parts, and a force (tensile stress) in the stacking direction T from the center of the laminate 10 toward the first main surface TS1 and the second main surface TS2 may occur inside the laminate 10. Furthermore, the external electrodes 40 have tensile stress as residual stress due to shrinkage of the baked layer, etc., and the tensile stress of the external electrodes 40 may generate a force (tensile stress) inside the laminate 10 from the center of the laminate 10 toward the ends of the external electrodes 40.

[0127] FIG. 6 is a schematic LT cross-sectional view of the multilayer ceramic capacitor 1 to illustrate the above-mentioned forces. In FIG. 6, arrow K1 indicates the component of force in the stacking direction T due to electrostriction generated between the first capacitor portion CAP1 and the second capacitor portion CAP2. This stacking direction component force K1 is a tensile stress acting from the center of the laminate 10 toward the first main surface TS1 and the second main surface TS2. In FIG. 6, arrows K2 indicate forces acting from the center of the laminate 10 toward the ends of the first external electrode 40A and the second external electrode 40B due to the residual stress of the external electrodes 40. The residual stress of the external electrodes 40 is indicated by arrows K3 inside the first external electrode 40A and the second external electrode 40B. The residual stress K3 in the external electrodes 40 is a tensile stress that occurs when the baked layers (first base electrode layer 50A, second base electrode layer 50B) of the external electrodes 40 formed on the surface of the laminate 10 contract during cooling, as described above. In the first external electrode 40A, the residual stress in the external electrode 40 acts from the first main surface side external electrode 411A and the second main surface side external electrode 412A toward the center of the first end face side external electrode 400A. In the second external electrode 40B, the residual stress in the external electrode 40 acts from the third main surface side external electrode 411B and the fourth main surface side external electrode 412B toward the center of the second end face side external electrode 400B. Furthermore, in Figure 6, the dashed arrow K4 indicates the force component in the stacking direction of the force K2 that is directed from the center of the laminate 10 toward the end of the external electrode 40 due to the residual stress in the external electrode 40.

[0128] Here, a force K1 of the stacking direction component due to electrostriction and a force K4 of the stacking direction component of a force K2 directed from the center of the laminate 10 to the end of the external electrode 40 due to the residual stress of the external electrode 40 are combined, and if this combined force of the stacking direction component increases, there is a possibility that delamination will occur in the laminate 10. However, because each main surface side external electrode has a recess as in the multilayer ceramic capacitor 1 of this embodiment, the residual stress in the external electrode 40 directed from the main surface side external electrode to the end face side external electrode is partially broken by the recess, and the force is weakened.

[0129] Specifically, the residual stress K3 in the first external electrode 40A extending from the first main surface side external electrode 411A to the first end surface side external electrode 400A is partially interrupted by the first recess 510A, thereby weakening the force. The residual stress K3 in the first external electrode 40A extending from the second main surface side external electrode 412A to the first end surface side external electrode 400A is partially interrupted by the second recess 520A, thereby weakening the force. The residual stress K3 in the second external electrode 40B extending from the third main surface side external electrode 411B to the second end surface side external electrode 400B is partially interrupted by the third recess 530B, thereby weakening the force. The residual stress K3 in the second external electrode 40B extending from the fourth main surface side external electrode 412B to the second end surface side external electrode 400B is partially interrupted by the fourth recess 540B, thereby weakening the force.

[0130] Therefore, the force K2 acting from the center of the laminate 10 to the end of the external electrode 40 due to the residual stress of the external electrode 40 is weakened, and the force that tends to cause delamination, i.e., the force K4 with the component in the stacking direction described above, is weakened. As a result, the occurrence of delamination is suppressed.

[0131] The multilayer ceramic capacitor 1 according to the above embodiment has the following advantages.

[0132] (1) The multilayer ceramic capacitor 1 according to the embodiment includes a laminate 10 including a plurality of dielectric layers 20 and a plurality of internal electrode layers 30 alternately stacked in a stacking direction T, a first main surface TS1 and a second main surface TS2 facing the stacking direction T, a first side surface WS1 and a second side surface WS2 facing a width direction W perpendicular to the stacking direction T, and a first end surface LS1 and a second end surface LS2 facing a length direction L perpendicular to the stacking direction T and the width direction W, and a pair of external electrodes 40 arranged spaced apart from each other at both ends of the length direction L of the laminate 10, The internal electrode layer 30 includes a first internal electrode layer 31 drawn to the first end face LS1, a second internal electrode layer 32 drawn to the second end face LS2, and an intermediate electrode layer 33 drawn to neither the first end face LS1 nor the second end face LS2. The laminate 10 includes a first capacitor section CAP1 formed by the first internal electrode layer 31 and the intermediate electrode layer 33 facing each other, and a second capacitor section CAP2 formed by the second internal electrode layer 32 and the intermediate electrode layer 33 facing each other. The external electrode 40 includes a first external electrode 41 disposed on the first end face LS1 side. 0A and a second external electrode 40B arranged on the second end face LS2 side, the first external electrode 40A has a first main surface side external electrode 411A arranged on the first main surface TS1 side and a second main surface side external electrode 412A arranged on the second main surface TS2 side, the second external electrode 40B has a third main surface side external electrode 411B arranged on the first main surface TS1 side and a fourth main surface side external electrode 412B arranged on the second main surface TS2 side, the first main surface side external electrode 411A has a first recess 510A recessed towards the laminate 10 side, and the second main surface side external electrode 412A has a recess 510A recessed towards the laminate The third main surface side external electrode 411B has a third recess 530B recessed toward the laminate 10, and the fourth main surface side external electrode 412B has a fourth recess 540B recessed toward the laminate 10, and in a cross-sectional view along the length direction L and the stacking direction T, an intersection 300 of a first imaginary line 100 connecting the first recess 510A and the fourth recess 540B and a second imaginary line 200 connecting the second recess 520A and the third recess 530B is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the length direction L, and the external electrode 40Residual stress is tensile stress.

[0133] This makes it possible to prevent delamination from occurring in the laminate 10 in the multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0134] (2) In the multilayer ceramic capacitor 1 according to the embodiment, it is preferable that the first imaginary line 100 intersects with the portion 1a of the first capacitor portion CAP1 on the second end face LS2 side and with the portion 2a of the second capacitor portion CAP2 on the first end face LS1 side, and the second imaginary line 200 intersects with the portion 1a of the first capacitor portion CAP1 on the second end face LS2 side and with the portion 2a of the second capacitor portion CAP2 on the first end face LS1 side.

[0135] This makes it possible to prevent delamination from occurring in the laminate 10 in the multilayer ceramic capacitor 1 with high voltage resistance specifications.

[0136] The present invention is not limited to the double-structure multilayer ceramic capacitor 1 according to the above embodiment, but can be widely applied to multilayer ceramic capacitors having a series structure. A first modified example having a triple structure and a second modified example having a quadruple structure will be described below.

[0137] (First Modification) The multilayer ceramic capacitor 1 according to the first modification is a multilayer ceramic capacitor with a triplet structure. The multilayer ceramic capacitor 1 according to the first modification will be described below with reference to FIG. 7. In the following description, detailed description of the same configuration as in the above-described embodiment may be omitted. FIG. 7 is an LT cross-sectional view schematically showing the multilayer ceramic capacitor 1 according to the first modification. The manufacturing method of the first modification is the same as in the above-described embodiment, and description thereof will be omitted.

[0138] In the multilayer ceramic capacitor 1 of the first modified example, the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 , a plurality of second internal electrode layers 32 , and an intermediate electrode layer 33 .

[0139] As shown in FIG. 7, the intermediate electrode layer 33 according to the first modification includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332.

[0140] The first intermediate electrode layer 331 has a first electrode layer side facing portion EC1A, a first intermediate electrode layer facing portion EC1B, and a first connecting portion E10. The first electrode layer side facing portion EC1A is a region facing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first intermediate electrode layer facing portion EC1B is a region facing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and is located inside the laminate 10. The first connecting portion E10 is a portion connecting the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B, and is located between the first electrode layer side facing portion EC1A and the first intermediate electrode layer facing portion EC1B.

[0141] The second intermediate electrode layer 332 has a second electrode layer side facing portion EC2A, a second intermediate electrode layer facing portion EC2B, and a second connecting portion E20. The second electrode layer side facing portion EC2A faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T. The second intermediate electrode layer facing portion EC2B faces the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T. The second connecting portion E20 connects the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B, and is arranged between the second electrode layer side facing portion EC2A and the second intermediate electrode layer facing portion EC2B.

[0142] 7, in the multilayer ceramic capacitor 1 according to the first modification, the first internal electrode layer 31 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the first modification, the second internal electrode layer 32 and the first intermediate electrode layer 331 are arranged adjacent to each other in the length direction L.

[0143] In the multilayer ceramic capacitor 1 of the first modified example, the first internal electrode layer 31 and the second intermediate electrode layer 332, and the second internal electrode layer 32 and the first intermediate electrode layer 331 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0144] In the first modified example, the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a first capacitor portion CAP1 that generates a capacitance CAP1. The second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer, thereby forming a second capacitor portion CAP2 that generates a capacitance CAP2. The first intermediate electrode layer opposing portion EC1B and the second intermediate electrode layer opposing portion EC2B face each other via the dielectric layer 20, thereby forming a third capacitor portion CAP3 that generates a capacitance CAP3. The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the third capacitor portion CAP3 in series. The multilayer ceramic capacitor 1 of the first modification is a multilayer ceramic capacitor having a so-called triple series structure in which three capacitor sections (first capacitor section CAP1, second capacitor section CAP2, third capacitor section CAP3) are formed in series connection.

[0145] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a first capacitor portion CAP1, a second capacitor portion CAP2, a third capacitor portion CAP3, a portion connecting the first capacitor portion CAP1 and capacitance CAP3 in series, and a portion connecting the second capacitor portion CAP2 and third capacitor portion CAP3 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. Of the series capacitor-forming portion 11E, the first capacitor portion CAP1, the second capacitor portion CAP2, and the third capacitor portion CAP3 are also referred to as effective capacitor portions.

[0146] The series capacitor forming portion 11E of the laminate 10 has a first series connection region and a second series connection region. The first series connection region is a portion located between the first capacitor portion CAP1 and the third capacitor portion CAP3 and including the dielectric layer 20 and the first coupling portion E10. The second series connection region is a portion located between the second capacitor portion CAP2 and the third capacitor portion CAP3 and including the dielectric layer 20 and the second coupling portion E20. That is, the first series connection region is a collection of portions of the multiple dielectric layers 20 that overlap with the first coupling portion E10 when viewed from the stacking direction T, and the multiple first coupling portions E10. The second series connection region is a collection of portions of the multiple dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T, and the multiple second coupling portions E20.

[0147] As shown in FIG. 7, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0148] The first coupling portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second coupling portion E20 connects the second capacitor portion CAP2 and the third capacitor portion CAP3 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first outer electrode 40A connected to the first internal electrode layer 31 and the second outer electrode 40B connected to the second internal electrode layer 32.

[0149] In the multilayer ceramic capacitor 1 according to the first modification, as in the above-described embodiment, each of the main surface side external electrodes has a groove-shaped recess recessed toward the laminate 10. That is, the first main surface side external electrode 411A of the first external electrode 40A has a first recess 510A, and the second main surface side external electrode 412A has a second recess 520A. The third main surface side external electrode 411B of the second external electrode 40B has a third recess 530B, and the fourth main surface side external electrode 412B has a fourth recess 540B. As shown in FIG. 7 , in the LT cross section, an intersection 300 of a first imaginary line 100 connecting the first recess 510A and the fourth recess 540B with a second imaginary line 200 connecting the second recess 520A and the third recess 530B is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the longitudinal direction L. Furthermore, in the multilayer ceramic capacitor 1 of the first modified example, similarly to the above-described embodiment, the external electrodes 40, that is, the first external electrode 40A and the second external electrode 40B both have tensile stress as residual stress.

[0150] (3) In the multilayer ceramic capacitor 1 of the first modified example, the intermediate electrode layer 33 includes a first intermediate electrode layer 331 and a second intermediate electrode layer 332, and the first intermediate electrode layer 331 has a first electrode layer side opposing portion ECA facing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and a first intermediate electrode layer opposing portion EC1B facing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and the second intermediate electrode layer 332 has a second electrode layer side opposing portion ECB facing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, and a second intermediate electrode layer opposing portion EC2B facing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T.

[0151] Even in such a high-voltage-resistant multilayer ceramic capacitor 1 having a triple structure, the occurrence of delamination in the laminate 10 can be suppressed.

[0152] (Second Modification) The multilayer ceramic capacitor 1 according to the second modification is a multilayer ceramic capacitor with a four-row structure. The multilayer ceramic capacitor 1 according to the second modification will be described below with reference to FIG. 8. In the following description, detailed description of the same configuration as in the above-described embodiment and first modification will be omitted. FIG. 8 is an LT cross-sectional view schematically showing the multilayer ceramic capacitor 1 according to the second modification. The manufacturing method of the second modification is the same as that of the above-described embodiment, and description thereof will be omitted.

[0153] In the multilayer ceramic capacitor 1 of the second modified example, the plurality of internal electrode layers 30 include a plurality of first internal electrode layers 31 , a plurality of second internal electrode layers 32 , and an intermediate electrode layer 33 .

[0154] As shown in FIG. 8, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333.

[0155] The first intermediate electrode layer 331 has a first electrode layer side opposing portion EC1A opposing the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, a first intermediate electrode layer opposing portion EC1B opposing the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and a first connecting portion E10.

[0156] The second intermediate electrode layer 332 has a second electrode layer side opposing portion EC2A that faces the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, a second intermediate electrode layer opposing portion EC2B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and a second connecting portion E20.

[0157] The third intermediate electrode layer 333 has a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T, a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T, and a third connecting portion E30.

[0158] 8, in the multilayer ceramic capacitor 1 according to the second modification, the first internal electrode layer 31, the third intermediate electrode layer 333, and the second internal electrode layer 32 are arranged adjacent to each other in the length direction L. In the multilayer ceramic capacitor 1 according to the second modification, the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are arranged adjacent to each other in the length direction L.

[0159] In the multilayer ceramic capacitor 1 of the second modified example, the first internal electrode layer 31, the third intermediate electrode layer 333 and the second internal electrode layer 32, and the first intermediate electrode layer 331 and the second intermediate electrode layer 332 are stacked alternately with the dielectric layer 20 interposed therebetween.

[0160] In the second modified example, the first opposing portion EA and the first electrode layer side opposing portion EC1A face each other via the dielectric layer 20, thereby forming a first capacitor portion CAP1 that generates a capacitance CAP1. The second opposing portion EB and the second electrode layer side opposing portion EC2A face each other via the dielectric layer 20, thereby forming a second capacitor portion CAP2 that generates a capacitance CAP2. The first intermediate electrode layer opposing portion EC1B and the third intermediate electrode layer opposing portion EC3A face each other via the dielectric layer 20, thereby forming a third capacitor portion CAP3 that generates a capacitance CAP3. The second intermediate electrode layer opposing portion EC2B and the fourth intermediate electrode layer opposing portion EC3B face each other via the dielectric layer 20, thereby forming a fourth capacitor portion CAP4 that generates a capacitance CAP4. The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the fourth capacitor portion CAP4 in series. The third coupling portion E30 connects the third capacitor portion CAP3 and the fourth capacitor portion CAP4 in series. The multilayer ceramic capacitor 1 of the second modified example is a multilayer ceramic capacitor with a so-called four-series structure in which four capacitor portions (the first capacitor portion CAP1, the second capacitor portion CAP2, the third capacitor portion CAP3, and the fourth capacitor portion CAP4) are connected in series.

[0161] The laminate 10 has a series capacitor-forming portion 11E. The series capacitor-forming portion 11E includes a first capacitor portion CAP1, a second capacitor portion CAP2, a third capacitor portion CAP3, and a fourth capacitor portion CAP4, a portion connecting the first capacitor portion CAP1 and the third capacitor portion CAP3 in series, a portion connecting the second capacitor portion CAP2 and the fourth capacitor portion CAP4 in series, and a portion connecting the third capacitor portion CAP3 and the fourth capacitor portion CAP4 in series. The series capacitor-forming portion 11E is configured as a part of the inner layer portion 11. Of the series capacitor-forming portion 11E, the first capacitor portion CAP1, the second capacitor portion CAP2, the third capacitor portion CAP3, and the fourth capacitor portion CAP4 are also referred to as effective capacitor portions.

[0162] The series capacitor forming portion 11E of the laminate 10 has a first series connection region, a second series connection region, and a third series connection region. The first series connection region is a portion located between the first capacitor portion CAP1 and the third capacitor portion CAP3 and including the dielectric layer 20 and the first coupling portion E10. The second series connection region is a portion located between the second capacitor portion CAP2 and the fourth capacitor portion CAP4 and including the dielectric layer 20 and the second coupling portion E20. The third series connection region is a portion located between the third capacitor portion CAP3 and the fourth capacitor portion CAP4 and including the dielectric layer 20 and the third coupling portion E30. In other words, the first series connection region is an aggregate of portions of the multiple dielectric layers 20 that overlap the first coupling portion E10 when viewed from the stacking direction T, and multiple first coupling portions E10. The second series connection region is an assembly of the plurality of second coupling portions E20 and portions of the plurality of dielectric layers 20 that overlap with the second coupling portion E20 when viewed from the stacking direction T. The third series connection region is an assembly of the plurality of third coupling portions E30 and portions of the plurality of dielectric layers 20 that overlap with the third coupling portion E30 when viewed from the stacking direction T.

[0163] As shown in FIG. 8, the external electrode 40 has a first external electrode 40A arranged on the first end face LS1 side of the laminate 10, and a second external electrode 40B arranged on the second end face LS2 side of the laminate 10.

[0164] The first connecting portion E10 connects the first capacitor portion CAP1 and the third capacitor portion CAP3 in series. The second connecting portion E20 connects the second capacitor portion CAP2 and the fourth capacitor portion CAP4 in series. The third connecting portion E30 connects the third capacitor portion CAP3 and the fourth capacitor portion CAP4 in series. Therefore, the characteristics of a capacitor due to the series connection capacitance are exhibited between the first external electrode 40A connected to the first internal electrode layer 31 and the second external electrode 40B connected to the second internal electrode layer 32.

[0165] In the multilayer ceramic capacitor 1 according to the second modification, as in the above-described embodiment and the first modification, each main surface side external electrode has a groove-shaped recess that is recessed toward the laminate 10. That is, the first main surface side external electrode 411A of the first external electrode 40A has a first recess 510A, and the second main surface side external electrode 412A has a second recess 520A. The third main surface side external electrode 411B of the second external electrode 40B has a third recess 530B, and the fourth main surface side external electrode 412B has a fourth recess 540B. 8, in the LT cross section, an intersection 300 of a first imaginary line 100 connecting the first recess 510A and the fourth recess 540B and a second imaginary line 200 connecting the second recess 520A and the third recess 530B is located between the first capacitor portion CAP1 and the second capacitor portion CAP2 in the longitudinal direction L. In the multilayer ceramic capacitor 1 of the first modified example, similar to the above-described embodiment, the external electrodes 40, i.e., the first external electrode 40A and the second external electrode 40B, both have tensile stress as residual stress.

[0166] (4) In the multilayer ceramic capacitor 1 according to the second modification, the intermediate electrode layer 33 includes a first intermediate electrode layer 331, a second intermediate electrode layer 332, and a third intermediate electrode layer 333. The first intermediate electrode layer 331 has a first electrode layer-side opposing portion ECA that faces the first internal electrode layer 31 arranged adjacent to it in the stacking direction T, and a first intermediate electrode layer-side opposing portion EC1B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T. The second intermediate electrode layer 332 has a first electrode layer-side opposing portion EC1B that faces the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T. The second intermediate electrode layer 333 has a second electrode layer side opposing portion ECB opposing the second internal electrode layer 32 arranged adjacent to it in the stacking direction T, and a second intermediate electrode layer opposing portion EC2B opposing the third intermediate electrode layer 333 arranged adjacent to it in the stacking direction T, and the third intermediate electrode layer 333 has a third intermediate electrode layer opposing portion EC3A opposing the first intermediate electrode layer 331 arranged adjacent to it in the stacking direction T, and a fourth intermediate electrode layer opposing portion EC3B opposing the second intermediate electrode layer 332 arranged adjacent to it in the stacking direction T.

[0167] Even in such a high-voltage-resistant multilayer ceramic capacitor 1 having a four-layer structure, it is possible to prevent delamination from occurring in the laminate 10.

[0168] The present invention is not limited to the configurations of the above-described embodiments, and can be appropriately modified and applied within the scope of the present invention. Note that the present invention also includes a combination of two or more of the individual desirable configurations described in the above-described embodiments.

[0169] For example, the multilayer ceramic capacitor 1 may be a two-terminal type having two external electrodes, or may be a multi-terminal type having many external electrodes. [Explanation of symbols]

[0170] 1. Multilayer ceramic capacitors 10 Laminate 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 32 Second internal electrode layer 33 Intermediate electrode layer 40 External electrode 40A First outer electrode 40B Second external electrode 100 First virtual line 200 Second virtual line 300 intersection 331 First intermediate electrode layer 332 second intermediate electrode layer 333 Third intermediate electrode layer 411A First main surface side external electrode 412A Second main surface side external electrode 411B Third main surface side external electrode 412B Fourth main surface side external electrode 510A First recess 520A Second recess 530B Third recess 540B Fourth recess CAP1 First capacitor section CAP2 Second capacitor section 1a: A portion of the first capacitor section on the second end face side 2a: a portion of the second capacitor section on the first end face side ECA, EC1A 1st electrode layer side opposing part ECB, EC2A 2nd electrode layer side opposing part EC1B First intermediate electrode layer facing portion EC2B Second intermediate electrode layer facing portion EC3A Third intermediate electrode layer facing portion EC3B Fourth intermediate electrode layer facing portion L lengthwise T Stacking direction (height direction) W width direction LS1 First end face LS2 Second end face TS1 First principal surface TS2 Second principal surface WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including a plurality of dielectric layers and a plurality of internal electrode layers alternately stacked in a height direction, and including a first main surface and a second main surface opposing each other in the height direction, a first side surface and a second side surface opposing each other in a width direction perpendicular to the height direction, and a first end surface and a second end surface opposing each other in a length direction perpendicular to the height direction and the width direction; a pair of external electrodes disposed at opposite ends of the laminate in the longitudinal direction and spaced apart from each other; the internal electrode layers include a first internal electrode layer drawn to the first end face, a second internal electrode layer drawn to the second end face, and an intermediate electrode layer drawn to neither the first end face nor the second end face, The laminate is a first capacitor portion formed by the first internal electrode layer and the intermediate electrode layer facing each other; a second capacitor portion formed by the second internal electrode layer and the intermediate electrode layer facing each other, The external electrode is a first external electrode disposed on the first end face side; a second external electrode disposed on the second end face side, the first external electrode has a first main surface side external electrode arranged on the first main surface side and a second main surface side external electrode arranged on the second main surface side, the second external electrode has a third main surface side external electrode arranged on the first main surface side and a fourth main surface side external electrode arranged on the second main surface side, the first main surface side external electrode has a first recess recessed toward the laminate; the second main surface side external electrode has a second recess recessed toward the laminate; the third main surface side external electrode has a third recess recessed toward the laminate; the fourth main surface side external electrode has a fourth recess recessed toward the laminate, in a cross-sectional view along the length direction and the height direction, an intersection of a first imaginary line connecting the first recess and the fourth recess and a second imaginary line connecting the second recess and the third recess is located between the first capacitor portion and the second capacitor portion in the length direction, The external electrodes have a tensile stress as a residual stress.

2. the first imaginary line intersects with a portion of the first capacitor portion on the second end face side and also intersects with a portion of the second capacitor portion on the first end face side, 2 . The multilayer ceramic capacitor according to claim 1 , wherein the second imaginary line intersects with a portion of the first capacitor portion on the second end face side and also intersects with a portion of the second capacitor portion on the first end face side.

3. the intermediate electrode layer includes a first intermediate electrode layer and a second intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first internal electrode layer in the height direction, and a first intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the first internal electrode layer in the height direction, 2. The multilayer ceramic capacitor according to claim 1, wherein the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the height direction, and a second intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the first internal electrode layer in the height direction.

4. the intermediate electrode layers include a first intermediate electrode layer, a second intermediate electrode layer, and a third intermediate electrode layer; the first intermediate electrode layer has a first electrode layer side opposing portion opposing the first internal electrode layer arranged adjacent to the first internal electrode layer in the height direction, and a first intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the first internal electrode layer in the height direction, the second intermediate electrode layer has a second electrode layer side opposing portion opposing the second internal electrode layer arranged adjacent to the second internal electrode layer in the height direction, and a second intermediate electrode layer opposing portion opposing the third intermediate electrode layer arranged adjacent to the second internal electrode layer in the height direction, 2. The multilayer ceramic capacitor according to claim 1, wherein the third intermediate electrode layer has a third intermediate electrode layer opposing portion opposing the first intermediate electrode layer arranged adjacent to the third intermediate electrode layer in the height direction, and a fourth intermediate electrode layer opposing portion opposing the second intermediate electrode layer arranged adjacent to the third intermediate electrode layer in the height direction.

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