Information processing device and image processing device

Abstract

To provide an information processing device and an image processing device that can easily simplify control of power supply to a nonvolatile memory.SOLUTION: An information processing device 20 includes a nonvolatile memory 171, a control unit 16, and a power supply control unit 21. The control unit 16 controls the nonvolatile memory 171. The power supply control unit 21 stops a power supply to the nonvolatile memory 171 from a power supply unit when the control unit 16 is not accessing the nonvolatile memory 171.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to an information processing device and an image processing device. [Background technology]

[0002] As a related art, there is known an information processing device in which a control unit (CPU) accesses a nonvolatile memory to read data (programs) and the like (see, for example, Patent Document 1). The information processing device of the related art is equipped with a power supply unit that supplies power to the nonvolatile memory. Here, a switch is provided in the power supply path from the power supply unit to the nonvolatile memory, and the on / off control of the switch is performed by a power management circuit.

[0003] In the above-mentioned related art, when a program stored in a nonvolatile memory is to be executed, the control unit controls the power management circuit to turn on a switch and start supplying power to the nonvolatile memory, and when a program stored in a memory other than the nonvolatile memory is to be executed, the control unit controls the power management circuit to turn off the switch and stop supplying power to the nonvolatile memory. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 10-136061 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the information processing device relating to the above-mentioned related technology, when the control unit accesses the non-volatile memory, it controls the power management circuit and then accesses the non-volatile memory, which requires relatively complex control and hinders simplification of the configuration.

[0006] An object of the present invention is to provide an information processing apparatus and an image processing apparatus that can easily simplify the control of power supply to a nonvolatile memory. [Means for solving the problem]

[0007] According to one aspect of the present invention, an information processing device includes a nonvolatile memory, a control unit, and a power supply control unit. The control unit controls the nonvolatile memory. The power supply control unit stops the power supply to the nonvolatile memory from the power supply unit when the control unit is not accessing the nonvolatile memory.

[0008] An image processing device according to another aspect of the present invention includes the information processing device described above and a main body having an image processing function. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide an information processing device and an image processing device that can easily simplify the control of power supply to a nonvolatile memory. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a schematic block diagram of an image processing device according to the first embodiment. [Figure 2] FIG. 2 is a schematic diagram showing the appearance of the image processing device according to the first embodiment. [Figure 3] FIG. 3 is a schematic block diagram illustrating an example of an information processing device of the image processing device according to the first embodiment. [Figure 4] FIG. 4 is a timing chart showing an example of an operation when data is read from the nonvolatile memory in the information processing device of the image processing device according to the first embodiment. [Figure 5] FIG. 5 is a timing chart showing an example of an operation when writing data to a nonvolatile memory in the information processing device of the image processing device according to the first embodiment. [Figure 6] FIG. 6 is a schematic circuit diagram showing a specific example of the information processing device of the image processing device according to the first embodiment. [Figure 7] FIG. 7 is a timing chart showing an example of the operation of the information processing device of the image processing device according to the first embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The following description will discuss preferred embodiments of the present invention with reference to the accompanying drawings. The preferred embodiments are merely examples of the present invention and are not intended to limit the technical scope of the present invention.

[0012] (Embodiment 1) [1] Overall configuration of image processing device First, the overall configuration of an image processing device 10 according to this embodiment will be described with reference to FIGS.

[0013] The image processing device 10 according to this embodiment is, for example, a multifunction peripheral having multiple functions, such as a scanning function for acquiring image data from an original, a printing function for forming an image based on the image data, a facsimile function, and a copying function. The image processing device 10 may be a printer, scanner, facsimile machine, copier, etc., as long as it has an image processing function including at least one of the function for forming an image and the function for acquiring image data.

[0014] As shown in Fig. 1, the image processing device 10 includes an automatic document feeder 11, an image reading unit 12, an image forming unit 13, a paper feeder 14, an operation and display unit 15, a control unit 16, a storage unit 17, and a power supply unit 3. The automatic document feeder 11 is an ADF (Auto Document Feeder), and is therefore represented as "ADF" in Fig. 1 and will also be referred to as "ADF 11" in the following description. In this embodiment, as shown in Fig. 2, the image processing device 10 includes a housing 101. The ADF 11, the image reading unit 12, the image forming unit 13, the paper feeder 14, the operation and display unit 15, the control unit 16, the storage unit 17, and the power supply unit 3 are provided in the housing 101.

[0015] The image processing device 10 includes a main body 1 having an image processing function. The main body 1 is provided with an ADF 11, an image reading unit 12, an image forming unit 13, a paper feed unit 14, and an operation display unit 15. The image processing device 10 also includes an information processing device 20 for controlling the main body 1. The control unit 16 and the storage unit 17 are provided in the information processing device 20. In other words, the image processing device 10 includes the information processing device 20, the main body 1 having an image processing function, and a power supply unit 3.

[0016] The ADF 11 transports a document whose image is to be read by the image reading unit 12. The ADF 11 includes a document setting unit, a plurality of transport rollers, a document holder, a paper discharge unit, and the like.

[0017] The image reading unit 12 reads an image from a document and outputs image data corresponding to the read image to the information processing device 20. The image reading unit 12 includes a document table, a light source, a plurality of mirrors, an optical lens, a CCD (Charge Coupled Device), and the like.

[0018] The image forming unit 13 forms an image on a sheet by electrophotography based on image data read by the image reading unit 12 and output from the information processing device 20. The image forming unit 13 also forms an image on a sheet based on image data input from an information processing device external to the image processing device 10, such as a personal computer.

[0019] Image forming section 13 has four image forming units corresponding to the four colors of C (cyan), M (magenta), Y (yellow), and K (black), an optical scanning device, an intermediate transfer belt, a secondary transfer roller, a fixing device, a developing device, etc. Each image forming unit has a photosensitive drum, a charging roller, a primary transfer roller, a drum cleaning unit, etc. Image forming section 13 may be configured to form an image on a sheet by an image forming method other than the electrophotographic method, such as an inkjet method.

[0020] The image forming unit 13 forms an image on a sheet using toner as a developer. Specifically, the surface of the photosensitive drum, which has been charged by a charging roller, is irradiated with laser light based on image data from an optical scanning device. This forms an electrostatic latent image on the surface of the photosensitive drum. The developing device has a developing roller, a magnet roller, etc., and performs a developing process to develop the electrostatic latent image formed on the surface of the photosensitive drum. When the image forming unit 13 forms an image using an inkjet method, ink (another example of a developer) is supplied instead of toner. After the image formation in the image forming unit 13, the sheet is discharged (supplied) to an auxiliary device or the like for post-processing.

[0021] The paper feed unit 14 supplies sheets to the image forming unit 13. The paper feed unit 14 has a paper feed cassette, a manual feed tray, a sheet transport path, a plurality of transport rollers, etc. The image forming unit 13 forms an image on the sheets supplied from the paper feed unit 14. The sheets supplied to the image forming unit 13 are, for example, paper, but are not limited to paper and may be, for example, a resin film, etc.

[0022] The operation display unit 15 is a user interface in the image processing device 10. The operation display unit 15 has a display unit such as a liquid crystal display that displays various information in response to control instructions from the control unit 16 of the information processing device 20, and an operation unit such as a switch or touch panel that inputs various information to the control unit 16 of the information processing device 20 in response to user operations. Furthermore, the image processing device 10 may also include, for example, an audio output unit and an audio input unit as a user interface in addition to or instead of the operation display unit 15.

[0023] The control unit 16 mainly comprises a computer system having one or more processors and one or more memories, and performs overall control of the image processing device 10. In the image processing device 10, the one or more processors execute programs to realize the functions of the control unit 16. In this embodiment, as an example, the control unit 16 includes a CPU (Central Processing Unit).

[0024] The storage unit 17 includes one or more non-volatile memories 171. The non-volatile memories 171 are a type of semiconductor memory that stores data (information) in an electrically rewritable state, and are memory elements that can maintain their stored contents even without an external power supply. The storage unit 17 stores in advance data (information), such as control programs for causing the control unit 16 to execute various processes. Furthermore, the storage unit 17 is used as a temporary storage memory (work area) for the various processes executed by the control unit 16.

[0025] Here, at least one of reading data stored in nonvolatile memory 171 and writing data to nonvolatile memory 171 is performed by control unit 16. That is, control unit 16 can access nonvolatile memory 171 of storage unit 17, and performs at least one of reading data stored in nonvolatile memory 171 and writing data to nonvolatile memory 171. As an example in this embodiment, control unit 16 can execute both processes of reading and writing data from and to nonvolatile memory 171.

[0026] The power supply unit 3 is a device that generates (outputs) power for the operation of the image processing device 10. The power supply unit 3 is electrically connected to one or more electrical loads and supplies power to the one or more electrical loads. In this embodiment, the main body 1 of the image processing device 10, and the control unit 16 and storage unit 17 (including non-volatile memory 171) of the information processing device 20 are the "electrical loads," and the power supply unit 3 supplies power to each unit of the image processing device 10 as an electrical load. In other words, the one or more electrical loads to which power is supplied from the power supply unit 3 include the ADF 11, image reading unit 12, image forming unit 13, paper feeding unit 14, operation display unit 15, control unit 16, and storage unit 17.

[0027] In this embodiment, the power supply unit 3 is electrically connected to an AC plug and converts an AC voltage of 100V (or 200V) applied to the AC plug into, for example, a DC voltage of 24V and a DC voltage of 3.3V (or 5V). In other words, when the AC plug is connected to an outlet (power socket), AC power is applied to the power supply unit 3 from an AC power source such as a system power supply, and the power supply unit 3 generates DC power from this AC power.

[0028] The power supply unit 3 supplies a DC 24V voltage to a "second load" such as the ADF 11, the image reading unit 12, and the image forming unit 13. On the other hand, the power supply unit 3 supplies a DC 3.3V (or 5V) voltage to a "first load" such as the control unit 16.

[0029] The power supply unit 3, for example, receives a control signal from the control unit 16 and determines the state of power supply to one or more electrical loads (ADF 11, image reading unit 12, image forming unit 13, paper feed unit 14, operation display unit 15, control unit 16, etc.). Specifically, the main body 1 has multiple operating modes including a normal mode and an energy-saving mode. The energy-saving mode is a mode in which power consumption in the main body 1 is reduced compared to the normal mode. When the main body 1 operates in the normal mode, the power supply unit 3 supplies power to both the first load (control unit 16, etc.) and the second load (ADF 11, etc.). On the other hand, when the main body 1 operates in the energy-saving mode, the power supply unit 3 supplies power only to the first load of the first and second loads. Therefore, in the energy-saving mode, the control unit 16 outputs a control signal (sleep signal) to the power supply unit 3 to switch the state of power supply from the power supply unit 3.

[0030] The image processing device 10 further includes a communication unit etc. The communication unit is an interface that executes data communication between the image processing device 10 and an external device connected via a communication network such as the Internet or a LAN (Local Area Network).

[0031] Incidentally, as a related technology of the information processing device 20 used in this type of image processing device 10, there is known an information processing device in which a control unit (CPU) accesses a nonvolatile memory to read data (programs), etc. The information processing device of the related technology is equipped with a power supply unit that supplies power to the nonvolatile memory. Here, a switch is provided in the power supply path from the power supply unit to the nonvolatile memory, and the on / off control of the switch is performed by a power management circuit.

[0032] In the above-mentioned related art, when a program stored in a nonvolatile memory is to be executed, the control unit controls the power management circuit to turn on a switch and start supplying power to the nonvolatile memory, and when a program stored in a memory other than the nonvolatile memory is to be executed, the control unit controls the power management circuit to turn off the switch and stop supplying power to the nonvolatile memory.

[0033] However, in the information processing device relating to the above-mentioned related technology, when the control unit accesses the non-volatile memory, it controls the power management circuit and then accesses the non-volatile memory, which requires relatively complex control and hinders simplification of the configuration.

[0034] In contrast to this, this embodiment provides an information processing device 20 and an image processing device 10 that can easily simplify the control of power supply to the nonvolatile memory, using the configuration described below.

[0035] [2] Configuration of information processing device Next, the configuration of the information processing device 20 according to this embodiment will be described with reference to Fig. 3 to Fig. 5. Fig. 3 is a block diagram showing the schematic configuration of the information processing device 20.

[0036] As shown in FIG. 3, the information processing device 20 includes a control unit 16, a nonvolatile memory 171, and a power supply control unit 21.

[0037] The control unit 16 controls the nonvolatile memory 171. As described above, the control unit 16 accesses the nonvolatile memory 171 and performs at least one of reading and writing data (in this embodiment, both). Here, the nonvolatile memory 171 is a device that is controlled in synchronization with a clock signal CLK output by the control unit 16, and examples thereof include a device such as an SPI NOR FLASH memory or an eMMC (embedded multi media card).

[0038] Although the nonvolatile memory 171 is a storage element that can maintain its stored contents even without an external power supply, when the control unit 16 controls (reads and / or writes) the nonvolatile memory 171, power needs to be supplied to the nonvolatile memory 171. At this time, power is supplied to the nonvolatile memory 171 from the memory power supply Vcc2.

[0039] The continuous power supply Vcc1 is a power supply (constant voltage source) for the entire system (image processing device 10) generated by the power supply unit 3, and has, for example, a DC voltage of 3.3 V (or 5 V) that is applied to a first load including the control unit 16. The continuous power supply Vcc1 is always on (in a state where it outputs voltage) while the image processing device 10 is in operation.

[0040] On the other hand, the memory power supply Vcc2 is a power supply (constant voltage source) for the nonvolatile memory 171 that supplies power to the nonvolatile memory 171. The memory power supply Vcc2 is a power supply generated from the constant power supply Vcc1 generated by the power supply unit 3, for example. In this embodiment, as an example, the memory power supply Vcc2 outputs a voltage of DC 3.3V (or 5V) similar to the constant power supply Vcc1.

[0041] The power supply control unit 21 controls the power supply from the power supply unit 3 to the nonvolatile memory 171. Specifically, the power supply control unit 21 receives the constant power supply Vcc1 as input and controls the on / off of the memory power supply Vcc2. When the memory power supply Vcc2 is on, the power supply control unit 21 supplies power from the memory power supply Vcc2 to the nonvolatile memory 171. When the memory power supply Vcc2 is off, the power supply control unit 21 stops the power supply from the memory power supply Vcc2 to the nonvolatile memory 171.

[0042] Here, the power supply control unit 21 stops the power supply from the power supply unit 3 to the nonvolatile memory 171 when the control unit 16 is not accessing the nonvolatile memory 171. That is, the power supply control unit 21 monitors whether the control unit 16 is accessing the nonvolatile memory 171, and controls the on / off of the memory power supply Vcc2 based on the monitoring result.

[0043] When the control unit 16 is accessing the nonvolatile memory 171, the power supply control unit 21 turns on the memory power supply Vcc2 to supply power from the power supply unit 3 (memory power supply Vcc2) to the nonvolatile memory 171. On the other hand, when the control unit 16 is not accessing the nonvolatile memory 171, the power supply control unit 21 turns off the memory power supply Vcc2 to stop the power supply from the power supply unit 3 (memory power supply Vcc2) to the nonvolatile memory 171.

[0044] According to this configuration, when there is no access from the control unit 16 to the nonvolatile memory 171, the power supply to the nonvolatile memory 171 is cut off (stopped), thereby reducing power consumption compared to when power is continuously supplied to the nonvolatile memory 171. Furthermore, the power supply control unit 21 can control the power supply to the nonvolatile memory 171 simply by monitoring the access status from the control unit 16 to the nonvolatile memory 171, which can be achieved with relatively simple control and also makes it easier to simplify the configuration. As a result, it is possible to provide an information processing device 20 and an image processing device 10 in which the control of the power supply to the nonvolatile memory 171 can be easily simplified.

[0045] More specifically, the power supply control unit 21 controls the power supply from the power supply unit 3 to the nonvolatile memory 171 based on a signal output from the control unit 16 to the nonvolatile memory 171. That is, the power supply control unit 21 monitors the status of access from the control unit 16 to the nonvolatile memory 171 by intercepting the signal output from the control unit 16 to the nonvolatile memory 171. This eliminates the need for a dedicated control circuit such as a power management circuit, making it easier to simplify the configuration.

[0046] In this embodiment, the signal is a clock signal CLK for synchronizing the nonvolatile memory 171. That is, as shown in FIG. 3, the control unit 16 and the nonvolatile memory 171 are connected by a signal line for outputting the synchronization clock signal CLK from the control unit 16 to the nonvolatile memory 171. The power supply control unit 21 is connected to a branch line branching from this signal line, thereby becoming able to intercept the clock signal CLK output from the control unit 16 to the nonvolatile memory 171. With this configuration, the control unit 16 can access the nonvolatile memory 171 without being aware of the control of the power supply to the nonvolatile memory 171.

[0047] Hereinafter, the operation of the power supply control unit 21 when the control unit 16 accesses the nonvolatile memory 171 will be described with reference to FIGS.

[0048] FIG. 4 is a timing chart showing an example of the memory power supply Vcc2, the clock signal CLK, the operation of the control unit 16, and the status and operation of the nonvolatile memory 171 when the control unit 16 reads data from the nonvolatile memory 171.

[0049] 4, at time t1, when the control unit 16 starts outputting the clock signal CLK to the nonvolatile memory 171, the power supply control unit 21 turns on the memory power supply Vcc2 to start supplying power to the nonvolatile memory 171. When the memory power supply Vcc2 is turned on, the nonvolatile memory 171 first executes a startup sequence. While the nonvolatile memory 171 is executing the startup sequence, the status of the nonvolatile memory 171 becomes "Busy."

[0050] At time t2, the control unit 16 confirms that the nonvolatile memory 171 has started up and that the status of the nonvolatile memory 171 has become "Ready", and then executes control to read data from the nonvolatile memory 171 ("Read Control" and "Read Data").

[0051] At time t3, the control unit 16 confirms that the control of the nonvolatile memory 171 is completed and the status of the nonvolatile memory 171 has become "Ready", and stops outputting the clock signal CLK (time t4). In response to the clock signal CLK being stopped, the power supply control unit 21 turns off the memory power supply Vcc2 to stop the power supply to the nonvolatile memory 171 (time t5).

[0052] FIG. 5 is a timing chart showing an example of the memory power supply Vcc2, the clock signal CLK, the operation of the control unit 16, and the status and operation of the nonvolatile memory 171 when the control unit 16 writes data to the nonvolatile memory 171.

[0053] 5, at time t1, when the control unit 16 starts outputting the clock signal CLK to the nonvolatile memory 171, the power supply control unit 21 turns on the memory power supply Vcc2 to start supplying power to the nonvolatile memory 171. When the memory power supply Vcc2 is turned on, the nonvolatile memory 171 first executes a startup sequence. While the nonvolatile memory 171 is executing the startup sequence, the status of the nonvolatile memory 171 becomes "Busy."

[0054] At time t2, the control unit 16 confirms that the nonvolatile memory 171 has started up and that the status of the nonvolatile memory 171 has become "Ready", and then executes control of writing data to the nonvolatile memory 171 ("Write Control" and "Write Data").

[0055] At time t3, the control unit 16 confirms that the control of the nonvolatile memory 171 is completed and the status of the nonvolatile memory 171 has become "Ready", and stops outputting the clock signal CLK (time t4). In response to the clock signal CLK being stopped, the power supply control unit 21 turns off the memory power supply Vcc2 to stop the power supply to the nonvolatile memory 171 (time t5).

[0056] [3] Specific examples of information processing devices Next, a specific example of the information processing device 20 will be described with reference to Fig. 6 and Fig. 7. Fig. 6 is a schematic circuit diagram showing an example of the configuration of the information processing device 20.

[0057] As shown in FIG. 6, the power supply control unit 21 includes a first transistor Tr1, a second transistor Tr2, resistors R1 and R2, a capacitor C1, a diode D1, and the like.

[0058] The first transistor Tr1 and the second transistor Tr2 are MOSFETs (Metal-Oxide-Semiconductor Field Effect Transistors) that are turned on / off in response to a drive signal applied to their gate terminals. The first transistor Tr1 is inserted between the gate terminal of the second transistor Tr2 and the circuit ground, and switches between conduction and cut-off between the gate terminal of the second transistor Tr2 and the circuit ground. The second transistor Tr2 is inserted between the constant power supply Vcc1 and the memory power supply Vcc2, and switches between conduction and cut-off between the constant power supply Vcc1 and the memory power supply Vcc2.

[0059] The resistor R1 and capacitor C1 are electrically connected in parallel between the gate terminal of the first transistor Tr1 and the circuit ground, and the resistor R2 is inserted between the gate terminal and the source terminal of the second transistor Tr2.

[0060] The gate terminal of the first transistor Tr1 is connected via a diode D1 to a signal line for a clock signal CLK between the control unit 16 and the nonvolatile memory 171. The diode D1 is inserted with the gate terminal side of the first transistor Tr1 as the cathode so that the clock signal CLK passes toward the gate terminal of the first transistor Tr1.

[0061] The control unit 16 and the nonvolatile memory 171 are connected by a signal line for transmitting the clock signal CLK as well as a signal line for transmitting a control (or data) signal Sig other than the clock signal CLK. The control (or data) signal Sig other than the clock signal CLK can be transmitted and received bidirectionally between the control unit 16 and the nonvolatile memory 171. The anode of the diode D1 is connected to the signal line for the clock signal CLK among these signal lines.

[0062] In the power supply control unit 21 configured as described above, the second transistor Tr2 functions as a switching element that directly controls the on / off of the memory power supply Vcc2. That is, when the second transistor Tr2 is on, the continuous power supply Vcc1 and the memory power supply Vcc2 are connected, and the memory power supply Vcc2 is turned on. Conversely, when the second transistor Tr2 is off, the continuous power supply Vcc1 and the memory power supply Vcc2 are disconnected, and the memory power supply Vcc2 is turned off.

[0063] The first transistor Tr1 is an element for controlling the second transistor Tr2. That is, when the first transistor Tr1 is on, the second transistor Tr2 is on. Conversely, when the first transistor Tr1 is off, the second transistor Tr2 is off.

[0064] Furthermore, the diode D1, resistor R1, and capacitor C1 form a circuit for keeping the first transistor Tr1 on while the clock signal CLK is being output from the control unit 16. In other words, while the clock signal CLK is being output from the control unit 16, the first transistor Tr1 is on.

[0065] FIG. 7 is a timing chart showing an example of the clock signal CLK, the gate voltage Vg1 of the first transistor Tr1, the gate voltage Vg2 of the second transistor Tr2, and the memory power supply Vcc2 for the power supply control unit 21 shown in FIG.

[0066] 7, when the clock signal CLK switches from L (Low) to H (High) at time t1, a voltage is applied to the parallel circuit of resistor R1 and capacitor C1 via diode D1, and charge accumulates in capacitor C1. At this time, the gate voltage Vg1 of the first transistor Tr1 rises and exceeds the threshold voltage Vth1, turning on the first transistor Tr1, which in turn turns on the second transistor Tr2. When the second transistor Tr2 turns on, conduction is established between the continuous power supply Vcc1 and the memory power supply Vcc2, turning on the memory power supply Vcc2.

[0067] Then, at time t2, when the clock signal CLK switches from H level to L level, the diode D1 prevents the reverse flow of charge, and the charge accumulated in the capacitor C1 is gradually discharged through the resistor R1. As a result, the gate voltage Vg1 of the first transistor Tr1 gradually decreases due to the time constant determined by the RC circuit consisting of the resistor R1 and the capacitor C1.

[0068] While the control unit 16 is outputting the clock signal CLK, the clock signal CLK periodically alternates between H level and L level, so when the clock signal CLK switches from L level to H level again, charge is accumulated in the capacitor C1, and the gate voltage Vg1 of the first transistor Tr1 rises. The time constants of the resistor R1 and the capacitor C1 are determined so that the gate voltage Vg1 of the first transistor Tr1 does not fall below the threshold voltage Vth1 during the period until the clock signal CLK switches from L level to H level again.

[0069] Therefore, while the control unit 16 is outputting the clock signal CLK, the first transistor Tr1 is kept on and the second transistor Tr2 is also kept on, so that there is electrical continuity between the regular power supply Vcc1 and the memory power supply Vcc2, and the memory power supply Vcc2 is kept on.

[0070] Meanwhile, at time t3, when the control unit 16 stops outputting the clock signal CLK, the clock signal CLK is fixed at the L level. As a result, the charge accumulated in the capacitor C1 is gradually discharged through the resistor R1, and the gate voltage Vg1 of the first transistor Tr1 gradually decreases and eventually falls below the threshold voltage Vth1. Then, at time t4, when the gate voltage Vg1 of the first transistor Tr1 falls below the threshold voltage Vth1, the second transistor Tr2 turns off, disconnecting the continuous power supply Vcc1 from the memory power supply Vcc2, and turning off the memory power supply Vcc2.

[0071] [4] Variation The components included in the information processing device 20 may be distributed across multiple housings. For example, the power supply control unit 21 may be provided separately from the control unit 16 and the nonvolatile memory 171.

[0072] 6, the specific configuration of the information processing device 20 (particularly the power supply control unit 21) is not limited to that shown in Fig. 6 and can be modified as appropriate as long as the same functions can be realized. For example, the power supply control unit 21 may be configured to switch between conduction and cut-off between the constant power supply Vcc1 and the memory power supply Vcc2 using an electromagnetic relay instead of the second transistor Tr2. [Explanation of symbols]

[0073] 1 Main unit 3 Power supply section 10 Image processing device 16 Control Unit 20 Information processing equipment 21 Power supply control unit 171 Non-volatile memory CLK Clock signal

Claims

1. a non-volatile memory; a control unit that controls the nonvolatile memory; a power supply control unit that stops the supply of power from a power supply unit to the nonvolatile memory when the control unit is not accessing the nonvolatile memory, Information processing device.

2. the power supply control unit controls the power supply from the power supply unit to the nonvolatile memory based on a signal output from the control unit to the nonvolatile memory. The information processing device according to claim 1 .

3. the signal is a clock signal for synchronizing the non-volatile memory; The information processing device according to claim 2 .

4. An information processing device according to any one of claims 1 to 3; a main body having an image processing function; Image processing device.

Images