Substrate and electronic device including the same

Abstract

To effectively reduce power loss in power supply wiring.SOLUTION: A substrate includes: electronic components mounted on a first surface; a power supply unit that supplies power to the electronic components mounted on either the first surface or a second surface opposite the first surface; and power wiring that electrically connects the electronic components and the power supply unit formed inside. A resistive member connected in parallel to the power wiring is mounted on at least one of the first surface and the second surface.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a substrate and an electronic device including the same. [Background technology]

[0002] Conventionally, a substrate is known that mounts a power supply unit and a semiconductor integrated circuit (LSI: Large Scale Integration), which is an electronic component that receives power from the power supply unit (see, for example, Patent Document 1). The LSI and power supply unit are connected by power wiring formed in layers within the substrate. By mounting the LSI and power supply unit on the same substrate, the distance of the power wiring connecting them can be shortened, which is thought to reduce power loss. Patent Document 1 also states that the electrical resistance of the power supply pattern and ground pattern can be kept low by devising the shape of the ground pattern. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2013-219182 Summary of the Invention [Problem to be solved by the invention]

[0004] Incidentally, power loss can be reduced by thickening the power wiring. However, due to its structure, it is difficult to increase the thickness of power wiring formed in layers within a board, and in this respect, the effect of reducing power loss is small. Furthermore, although Patent Document 1 claims that it is possible to maintain low electrical resistance in the power pattern and ground pattern, there are restrictions on the shape of the ground pattern. For this reason, it is expected that the effect of reducing power loss may be difficult to achieve depending on the structure of the board.

[0005] In one aspect, the substrate and electronic device including the substrate disclosed in this specification aim to effectively reduce power loss in power supply wiring. [Means for solving the problem]

[0006] In one embodiment, the substrate has electronic components mounted on a first surface, a power supply unit that supplies power to the electronic components mounted on either the first surface or a second surface that is the reverse side of the first surface, and power wiring formed inside the substrate that electrically connects the electronic components and the power supply unit, and a resistive element connected in parallel to the power wiring is mounted on at least one of the first surface and the second surface.

[0007] In another aspect, the electronic device is an electronic device in which a package substrate is mounted on a printed circuit board, and the package substrate has electronic components mounted on a first surface, a power supply unit that supplies power to the electronic components mounted on either the first surface or a second surface that is the reverse side of the first surface, power wiring that electrically connects the electronic components and the power supply unit is formed inside, and a resistive element connected in parallel to the power wiring is mounted on at least one of the first surface and the second surface. [Effects of the Invention]

[0008] According to the substrate disclosed in this specification and the electronic device including the same, it is possible to effectively reduce power loss in the power supply wiring. [Brief explanation of the drawings]

[0009] [Figure 1] Fig. 1A is a cross-sectional view schematically illustrating an electronic device in which a package substrate according to a first embodiment is mounted on a printed circuit board, and Fig. 1B is an enlarged cross-sectional view illustrating a state in which a resistor member according to the first embodiment is attached to a power supply wiring. [Figure 2] Fig. 2(A) is a circuit diagram showing a power supply wiring formed on a package substrate of the first embodiment, which is conveniently divided into a plurality of resistor sections. Fig. 2(B) is a circuit diagram further simplified from the circuit diagram shown in Fig. 2(A). [Figure 3] Fig. 3(A) is a cross-sectional view schematically showing an electronic device in which a package substrate according to the second embodiment is mounted on a printed circuit board, and Fig. 3(B) is a plan view of the package substrate according to the second embodiment. [Figure 4] FIG. 4 is a cross-sectional view taken along line AA in FIG. 3(B). [Figure 5] Fig. 5(A) is a circuit diagram showing a power supply wiring formed on a package substrate of the second embodiment, which is conveniently divided into a plurality of resistor portions. Fig. 5(B) is a circuit diagram showing a power supply wiring shown in Fig. 5(A) in which a resistor member is arranged in parallel. [Figure 6] FIG. 6 is a cross-sectional view of the package substrate of the third embodiment taken along the line corresponding to the line AA in FIG. 3(B). [Figure 7] FIG. 7 is a circuit diagram in which a resistance member is arranged in parallel with a power supply wiring formed on a package substrate according to the third embodiment. [Figure 8] FIG. 8 is a cross-sectional view of the package substrate of the fourth embodiment taken along the line corresponding to the line AA in FIG. 3(B). [Figure 9] FIG. 9 is a circuit diagram in which a resistance member is arranged in parallel with a power supply wiring formed on a package substrate according to the fourth embodiment. [Figure 10] FIG. 10 is a cross-sectional view schematically showing an electronic device in which the package substrate of the fifth embodiment is mounted on a printed circuit board. [Figure 11] FIG. 11 is a cross-sectional view schematically showing an electronic device in which the package substrate of the sixth embodiment is mounted on a printed circuit board. [Figure 12] FIG. 12 is a cross-sectional view schematically showing an electronic device in which the package substrate of the seventh embodiment is mounted on a printed circuit board. [Figure 13] FIG. 13 is an enlarged cross-sectional view showing a state in which a resistance member is attached to a power supply wiring in the eighth embodiment. [Figure 14]Fig. 14(A) is a plan view of a package substrate of a ninth embodiment, Fig. 14(B) is a plan view of a package substrate of a modified example of the ninth embodiment, and Fig. 14(C) is a cross-sectional view schematically showing an electronic device in which the package substrate of a tenth embodiment is mounted on a printed circuit board. [Figure 15] Fig. 15(A) is an explanatory diagram showing the dimensions of each part in the embodiment, and Fig. 15(B) is an explanatory diagram showing the dimensions of the resistance member used in the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, the dimensions, ratios, etc. of each part in the drawings may not be illustrated to be exactly the same as the actual ones. The scales of the drawings may differ. Furthermore, in some drawings, for the sake of convenience of explanation, components that actually exist may be omitted or dimensions may be exaggerated.

[0011] (First embodiment) An electronic device 100 according to a first embodiment will be described with reference to Figures 1(A), 1(B), 2(A), and 2(B). In the following description, three mutually orthogonal directions of the electronic device 100 are set as shown in Figure 1(A). The X direction corresponds to the first direction, and the Y direction corresponds to the second direction.

[0012] [Electronic equipment] The electronic device 100 includes a printed circuit board 1 and a package substrate 10 mounted on the printed circuit board 1. The package substrate 10 is mounted on the printed circuit board 1 via first solder balls 2.

[0013] <Package substrate> The package substrate 10 has a first surface 10a and a second surface 10b that is the reverse side of the first surface 10a. The first surface 10a and the second surface 10b each face in the Z direction. A power supply module 20 serving as a power supply unit and an LSI chip 30 serving as an electronic component are mounted on the first surface 10a of the package substrate 10. The power supply module 20 and the LSI chip 30 are disposed facing each other with a gap S1 between them. The LSI chip 30 is mounted on the first surface 10a via second solder balls 30a. The LSI chip 30 operates by receiving power from the power supply module 20. The electronic component may be any conventionally known component, such as a CPU (Central Processing Unit), as long as it operates by receiving power from the power supply module 20.

[0014] The package substrate 10 has resist layers 12 on the top and bottom layers in the Z direction. The first surface 10a and the second surface 10b are formed on the resist layers 12, respectively.

[0015] The package substrate 10 is mounted on the printed circuit board 1 with the second surface 10b facing the mounting surface of the printed circuit board 1.

[0016] The package substrate 10 includes power wiring 14 that electrically connects the power supply module 20 and the LSI chip 30 and supplies power from the power supply module 20 to the LSI chip 30. The power wiring 14 includes multiple wiring layers 14a stacked along the Z direction. The multiple wiring layers 14a facilitate current flow and reduce power loss in the power wiring 14. The wiring layers 14a are connected by connection lines extending in the Z direction. The multiple wiring layers 14a include a first outermost layer 14a1 and a second outermost layer 14a2. The first outermost layer 14a1 is the layer closest to the first surface 10a and is formed so as to contact the resist layer 12 that forms the first surface 10a. The second outermost layer 14a2 is the layer closest to the second surface 10b and is formed so as to contact the resist layer 12 that forms the second surface 10b.

[0017] The package substrate 10 includes a ground layer 16 and signal wiring 18 therein. The signal wiring 18 connects the LSI chip 30 and the printed circuit board 1. The signal wiring 18 includes a layer portion 18a extending in the X-direction. A plurality of ground layers 16 are provided. Some of the ground layers 16 are provided so as to be interposed between the layer portions 18a of the signal wiring 18. One of the ground layers 16 is provided between the layer portion 18a of the signal wiring 18 and the first outermost layer 14a1. Another of the ground layers 16 is provided between the layer portion 18a of the signal wiring 18 and the second outermost layer 14a2. Providing the ground layers 16 in this manner can provide a noise countermeasure for the signal wiring 18. As described later, a resistive member 40 is connected to the first outermost layer 14a1 and the second outermost layer 14a2. The ground layer 16 is effective as a noise countermeasure for the signal wiring 18 that is close to the resistance member 40 .

[0018] The package substrate 10 includes a resistive member 40 mounted on the first surface 10a. The resistive member 40 is connected in parallel to the power supply wiring 14. The resistive member 40 reduces the electrical resistance of the power supply path between the power supply module 20 and the LSI chip 30, thereby reducing power loss.

[0019] <Resistance material> The resistive element 40 may be made of any material or shape, as long as it forms a circuit parallel to the power wiring 14 and reduces the electrical resistance of the power supply path between the power supply module 20 and the LSI chip 30. For example, a chip-shaped resistive element can be used to mount the resistive element 40 on the package substrate 10, which is convenient because it allows the use of conventional manufacturing equipment, such as a chip mounter. It is also convenient because it allows the use of conventional mounting methods. It is desirable for the resistive element 40 to have low electrical resistance. Therefore, the resistive element 40 may be made of, for example, gold, silver, copper, aluminum, tungsten, iron, tantalum, or an alloy containing any of these metals. Copper has excellent electrical conductivity and is therefore suitable for use as the material for the resistive element 40. The resistive element 40 may be made of a material that exhibits an electrical resistance 10 times or less that of copper. The electrical resistance of the resistive element 40 varies depending on the material and shape, but the electrical resistance of each resistive element 40 is preferably 1 mΩ or less.

[0020] 1(B), the resistance member 40 is attached to a pair of electrode pads 41 provided on the first outermost layer 14a1 so as to be exposed from the resist layer 12. By connecting the resistance member 40 to the first outermost layer 14a1, the length of the path connecting the resistance member 40 and the power supply wiring 14 can be shortened, and an increase in the electrical resistance value can be suppressed.

[0021] <Principle of reducing electrical resistance> Here, the principle of reducing the electrical resistance value of the power supply path by arranging the resistive member 40 will be described with reference to Figures 2(A) and 2(B). Figure 2(A) is a circuit diagram that schematically shows how the power supply wiring 14 formed on the package substrate 10 is conveniently divided into a plurality of resistor portions Rp11 to Rp57. Figure 2(B) is a circuit diagram that further simplifies the circuit diagram shown in Figure 2(A).

[0022] Although the power supply wiring 14 is not a resistive element, for convenience it can be considered to be a series of multiple resistor sections. In the example shown in Fig. 2(A), the power supply wiring 14 is assumed to be a series of resistor sections Rp11 to Rp57 arranged in 5 rows and 7 columns for convenience. In the example shown in Fig. 2(A), the column direction is set to the direction in which the power supply module 20 and the LSI chip 30 face each other. The first character of the subscript of the resistor section Rp indicates the row number, and the second character indicates the column number.

[0023] In FIG. 2A, Rp11 to Rp51 belonging to the first column are set to part A, and the rest are set to part B. The electrical resistance value of part A is represented as RpA, and the electrical resistance value of part B is represented as RpB. As a result, if the electrical resistance value of the power supply wiring 14 is R0, then (Formula 1) R0=RpA+RpB It can be expressed as:

[0024] Here, consider the case where the resistance member 40 is connected in parallel to the portion A. If the electrical resistance value of the resistance member 40 is Rc, the electrical resistance value RpA' of the portion A to which the resistance member 40 is connected is given by (Equation 2) RpA´=RpA·Rc / (RpA+Rc) This becomes:

[0025] The electrical resistance value RpA' calculated by Equation 2 is smaller than the electrical resistance value RpA of portion A to which the resistive member 40 is not connected. The electrical resistance value R0 of the power supply wiring 14 to which the resistive member 40 is connected can be found by replacing RpA with RpA' in Equation 1. Therefore, the electrical resistance value R0 of the power supply wiring 14 to which the resistive member 40 is connected is smaller than when the resistive member 40 is not connected.

[0026] In this way, the electrical resistance value of the power supply path can be reduced by providing the resistance member 40. As a result, power loss is reduced.

[0027] (Second embodiment) Next, a second embodiment will be described with reference to Figures 3(A) to 5(B). An electronic device 101 of the second embodiment includes a package substrate 50 instead of the package substrate 10 of the first embodiment. While the package substrate 10 of the first embodiment has one resistor component 40 mounted thereon, the package substrate 50 includes multiple resistor components 40. Other elements of the second embodiment are the same as those of the first embodiment, and therefore common components are denoted by the same reference numerals in the drawings, and detailed description thereof will be omitted.

[0028] A plurality of resistance members 40 are arranged on the first surface 10a of the package substrate 50. The plurality of resistance members 40 are arranged in parallel along the X direction. The plurality of resistance members 40 are also arranged in parallel along the Y direction.

[0029] 5(A), similar to FIG. 2(A) used to explain the first embodiment, schematically shows a state in which the power supply wiring 14 formed on the package substrate 50 is divided into a plurality of resistance portions Rp11 to Rp57 for convenience. In the second embodiment, a plurality of resistance members 40 are connected to the power supply wiring 14. FIG. 5(B) shows an equivalent circuit of the package substrate 50. That is, the resistance members 40 are connected in parallel to the resistance portions Rp21, Rp41, Rp23, Rp43, Rp25, Rp45, Rp27, and Rp47 that are virtually set in the power supply wiring 14.

[0030] By connecting a plurality of resistive elements 40 to the power supply wiring 14, the electrical resistance value of the power supply path can be reduced. As a result, power loss can be reduced. In addition, by arranging a plurality of resistive elements 40 in parallel along the X direction or the Y direction, many resistive elements 40 can be arranged effectively.

[0031] (Third embodiment) Next, a third embodiment will be described with reference to Figures 6 and 7. The third embodiment includes a package substrate 60 instead of the package substrate 50 of the second embodiment. The package substrate 60 includes two resistor components 42 instead of the multiple resistor components 40 mounted on the package substrate 50. Other elements of the third embodiment are the same as those of the first and second embodiments, so the common components are denoted by the same reference numerals in the drawings and detailed description thereof will be omitted.

[0032] Two resistive elements 42 are disposed on the first surface 10a of the package substrate 60. The dimension L

[42] of the resistive elements 42 along the X-axis direction is greater than the dimension of the resistive elements 40 in the second embodiment along the X-axis direction. The resistive elements 42 are configured by connecting a plurality of the resistive elements 40 in the second embodiment in the X-axis direction. That is, the resistive elements 42 are configured in a bar shape with a plurality of portions with electrical resistance Rc connected in the X-axis direction. The dimension L

[42] can be set to 25% or more of the distance S1 (see FIG. 1(A) etc.) between the power supply module 20 and the LSI chip along the X-axis. Note that while two resistive elements 42 are depicted in FIG. 6, the number of resistive elements 42 may be one, or three or more. That is, the number of resistive elements 42 may be one or two or more.

[0033] 7 shows an equivalent circuit of the package substrate 60. The resistance member 42 is connected to the power supply wiring 14 so as to be parallel to the resistance units Rp21 to Rp27 corresponding to the second row and the resistance units Rp41 to Rp47 corresponding to the fourth row, which are virtually set on the power supply wiring 14.

[0034] By connecting the resistive member 42 to the power supply wiring 14, the electrical resistance value of the power supply path can be reduced. As a result, power loss is reduced. Since the resistive member 42 has a larger dimension along the X-axis direction than the resistive member 40, the number of resistive members to be connected can be reduced.

[0035] (Fourth embodiment) Next, a fourth embodiment will be described with reference to Figures 8 and 9. The fourth embodiment includes a package substrate 70 instead of the package substrate 50 of the second embodiment. The package substrate 70 includes three resistor components 44 instead of the multiple resistor components 40 mounted on the package substrate 50. Since the other elements of the fourth embodiment are no different from those of the other embodiments, the common components are denoted by the same reference numerals in the drawings and detailed description thereof will be omitted.

[0036] Three resistive elements 44 are disposed on the first surface 10a of the package substrate 70. The dimension L

[44] of the resistive elements 44 along the Y-axis direction is greater than the dimension of the resistive elements 40 of the second embodiment along the Y-axis direction. The resistive elements 44 are configured by connecting a plurality of the resistive elements 40 of the second embodiment in the Y-axis direction. That is, the resistive elements 44 are configured in a bar shape with a plurality of portions having electrical resistance Rc connected in the Y-axis direction. The dimension L

[42] can be 25% or more of the dimension W

[30] of the LSI chip 30 along the Y-axis direction (see FIG. 3(B)). Note that although FIG. 8 illustrates three resistive elements 44, the number of resistive elements 44 may be one, two, or four or more. That is, the number of resistive elements 44 may be one, two, or more.

[0037] 9 shows an equivalent circuit of the package substrate 70. The resistance member 44 is connected in parallel to the resistance units Rp12 to Rp52 corresponding to the second row, the resistance units Rp14 to Rp54 corresponding to the fourth row, and the resistance units Rp16 to Rp56 corresponding to the sixth row, which are virtually set on the power supply wiring 14.

[0038] By connecting the resistive member 44 to the power supply wiring 14, the electrical resistance value of the power supply path can be reduced. As a result, power loss is reduced. Since the resistive member 44 has a larger dimension along the Y-axis direction than the resistive member 40, the number of resistive members to be connected can be reduced.

[0039] (Fifth embodiment) Next, a fifth embodiment will be described with reference to FIG. 10 . An electronic device 102 of the fifth embodiment includes a package substrate 80 instead of the package substrate 50 of the second embodiment. The package substrate 80 includes a plurality of resistor elements 40 mounted on the second surface 10b in addition to a plurality of resistor elements 40 mounted on the first surface 10a of the package substrate 50. Since the other elements of the fifth embodiment are no different from those of the other embodiments, the common components are given the same reference numerals in the drawings and detailed description thereof will be omitted. There may be one or more resistor elements 40 mounted on the second surface 10b.

[0040] The resistive member 40 mounted on the second surface 10b is connected to the second outermost layer 14a2. The resistive member 40 on the second surface 10b can be connected to the second outermost layer 14a2 in the same manner as the connection of the resistive member 40 to the first outermost layer 14a1, as shown in FIG. 1(B). That is, the resistive member 40 on the second surface 10b can be connected to the second outermost layer 14a2 using an electrode pad 41. The resistive member 40 on the second surface 10b may be connected to the second outermost layer 14a2 using a via connection instead of using an electrode pad 41. The connection on the second surface 10b is less affected by the arrangement of the signal wiring 18, and is therefore easier to connect using a via connection.

[0041] By connecting the resistance member 40 to the second outermost layer 14a2, the length of the path connecting the resistance member 40 and the power supply wiring 14 can be shortened, and an increase in the electrical resistance value can be suppressed.

[0042] By connecting a plurality of resistive elements 40 to the power supply wiring 14, the electrical resistance value of the power supply path can be reduced. As a result, power loss is reduced. By arranging resistive elements 40 on the second surface 10b in addition to the first surface 10a, a large number of resistive elements 40 can be connected. Note that the resistive element 42 in the third embodiment or the resistive element 44 in the fourth embodiment may be used instead of the resistive element 40.

[0043] (Sixth embodiment) Next, a sixth embodiment will be described with reference to Fig. 11. An electronic device 103 of the sixth embodiment includes a package substrate 81 instead of the package substrate 80 of the fifth embodiment. The package substrate 81 is configured such that the resistive member 40 mounted on the first surface 10a of the package substrate 80 of the fifth embodiment is removed, and the resistive member 40 is disposed only on the second surface 10b.

[0044] Even in this embodiment, the electrical resistance value of the power supply path can be reduced.

[0045] (Seventh embodiment) Next, a seventh embodiment will be described with reference to FIG. 12. An electronic device 104 of the seventh embodiment includes a package substrate 82 instead of the package substrate 50 of the second embodiment. The package substrate 82 replaces some of the multiple resistive elements 40 included in the package substrate 50 of the second embodiment with other resistive elements 46. The other resistive elements 46 may be elements such as capacitors. Use of the resistive elements 40 can reduce DC resistance. Use of the other resistive elements 46 can reduce power supply impedance.

[0046] (Eighth embodiment) Next, an eighth embodiment will be described with reference to FIG. 13. In the first embodiment and the like, the resistive member 40 is attached to a pair of electrode pads 41 provided on the first outermost layer 14a1 so as to be exposed from the resist layer 12, as shown in FIG. 1(B). In contrast, in the eighth embodiment, the resistive member 40 is attached to a single electrode pad 41′ instead of the pair of electrode pads 41. The electrode pad 41′ has a connection area that is approximately equal to the area of ​​the surface of the resistive member 40 facing the first outermost layer 14a1. Even with this connection mode, the electrical resistance value of the power supply path can be reduced. By increasing the connection area, the effect of reducing the power supply resistance value can be more easily achieved.

[0047] (Ninth embodiment) Next, a ninth embodiment will be described with reference to FIG. 14(A). A package substrate 83 in the ninth embodiment includes a signal wiring 18 and a resistive member 40 connected to an LSI chip 30. The resistive member 40 is disposed at a position that avoids overlap with the signal wiring 18 when the package substrate 83 is viewed in a direction perpendicular to the first surface 10a and the second surface 10b (see FIG. 1, etc.), i.e., the Z direction. This serves as a noise countermeasure for the signal wiring 18. The signal wiring 18 may also be modified as shown in FIG. 14(B). In the example shown in FIG. 14(A), the signal wiring 18 extends in the X direction from a side of the LSI chip 30 facing the power supply module 20. In contrast, in the example shown in FIG. 14(B), the signal wiring 18 extends in the Y direction from a side of the LSI chip 30 extending along the X direction, and then extends in the X direction. This prevents the resistive member 40 from overlapping with the signal wiring 18.

[0048] (Tenth embodiment) Next, a tenth embodiment will be described with reference to FIG. 14(C). The tenth embodiment includes a package substrate 84 instead of the package substrate 81 of the sixth embodiment. The package substrate 84 has a configuration in which the power supply module 20, which was provided on the first surface 10a of the package substrate 81 of the sixth embodiment, is moved to the second surface 10b. The positional relationship between the power supply module 20 and the LSI chip 30 as in the tenth embodiment ensures that the first surface 10a and the second surface 10b are available for mounting the resistor 40. Even with this configuration of the package substrate 84, the electrical resistance of the power supply path can be reduced. While the configuration shown in FIG. 14(C) includes the resistor 40 on the second surface 10b, the resistor 40 may be disposed on the first surface 10a or in another configuration, as in other embodiments. [Example]

[0049] Next, examples will be described. In each example, the electrical resistance value of the power supply path between the power supply module 20 and the LSI chip 30 was calculated by simulation.

[0050] (First Example) The first example corresponds to the second embodiment. However, the number of resistive elements 40 in the simulation differs from that of the second embodiment shown in FIG. 3A. The layout and dimensions of each component of the first example are described with reference to FIGS. 3A, 3B, 15A, and 15B. The power supply module 20 and the LSI chip 30 are both mounted on the first surface 10a. The power supply module 20 and the LSI chip 30 face each other in the X direction, with a distance S1 between them set to 20 mm. The LSI chip 30 is roughly square when viewed from the Z direction, with the length W

[30] of one side set to 40 mm. The width W

[14] of the power supply wiring 14 (first outermost layer 14a1) is set to 40 mm, the same as the length W

[30] of one side of the LSI chip 30. The power supply wiring 14 includes eight wiring layers 14a and one core layer. The wiring layer was made of copper foil and had a thickness of 15 μm, and the core layer copper foil had a thickness of 21 μm.

[0051] Next, the resistance element 40 will be described. The resistance element 40 is made of copper. The dimension L

[40] of the resistance element 40 along the X direction is set to 1 mm, the dimension W

[40] along the Y direction is set to 0.5 mm, and the dimension T

[40] along the Z direction is set to 0.5 mm. The electrical resistance value of the resistance element 40 is 0.092 mΩ.

[0052] The resistance members 40 are arranged at intervals S2 of 2 mm along the X direction. In the first example, the pitch Pix of the resistance members 40 along the Y direction was set to 1 mm, 1.33 mm, 2 mm, and 4 mm, as shown in Table 1, and the resistance value of the power supply path was calculated. When the resistance members 40 were not arranged, the resistance value of the power supply path was 234 mΩ. In contrast, when the pitch Pix was 1 mm, the resistance value was 191 mΩ. When the pitch Pix was 1.33 mm, the resistance value was 200 mΩ. When the pitch Pix was 2 mm, the resistance value was 210 mΩ. When the pitch Pix was 4 mm, the resistance value was 221 mΩ.

[0053] [Table 1]

[0054] In this way, it was confirmed that the resistance value is reduced by arranging the resistance members 40 compared to when no resistance members 40 are arranged. Furthermore, it was confirmed that by narrowing the pitch Pix, the number of resistance members 40 can be increased accordingly, and the more resistance members 40 there are, the more the electrical resistance value is reduced.

[0055] (Second Example) Next, a second example will be described with reference to FIGS. 10, 15(A), and 15(B). The second example corresponds to the fifth embodiment. In the second example, a resistance element 40 is arranged on the first surface 10a in the same manner as in the first example. In the second example, a resistance element 40 is also arranged on the second surface 10b in the same manner as in the first surface 10a. In the second example, similar to the first example, the pitch Pix of the resistance elements 40 along the Y direction was set to 1 mm, 1.33 mm, 2 mm, and 4 mm, as shown in Table 2, and the resistance value of the power supply path was calculated. When the resistance element 40 was not arranged, the resistance value of the power supply path was 234 mΩ. In contrast, when the pitch Pix was 1 mm, the resistance value was 139 mΩ. When the pitch Pix was 1.33 mm, the resistance value was 154 mΩ. When the pitch Pix was 2 mm, the resistance value was 174 mΩ. When the pitch Pix was 4 mm, the resistance value was 200 mΩ.

[0056] [Table 2]

[0057] In this way, it was confirmed that by arranging the resistance members 40 also on the second surface 10b and increasing the number of resistance members 40, the electrical resistance value can be reduced more effectively.

[0058] (Third Example) Next, a third example will be described with reference to FIGS. 11, 15A, and 15B. The third example corresponds to the sixth embodiment. In the third example, a resistance element 40 is disposed on the second surface 10b in the same manner as on the first surface 10a in the first example. The resistance element 40 is not disposed on the first surface 10a. In other words, the third example is a configuration in which the resistance element 40 is removed from the first surface 10a of the second example. In the third example, similar to the first example, the pitch Pix of the resistance elements 40 along the Y direction was set to 1 mm, 1.33 mm, 2 mm, and 4 mm, as shown in Table 3, and the resistance value of the power supply path was calculated. The resistance value of the power supply path without the resistance element 40 was 234 mΩ. In contrast, when the pitch Pix was 1 mm, the resistance value was 189 mΩ. When the pitch Pix was 1.33 mm, the resistance value was 199 mΩ. When the pitch Pix was 2 mm, the resistance value was 209 mΩ. When the pitch Pix was 4 mm, the resistance was 221 mΩ.

[0059] [Table 3]

[0060] In this way, even when the resistance member 40 was arranged on the second surface 10b instead of the first surface 10a, it was confirmed that the electrical resistance value was reduced in a manner similar to that of the first embodiment.

[0061] (Fourth Example) Next, a fourth example will be described with reference to FIGS. 3(A), 3(B), 15(A), and 15(B). In the fourth example, a resistance element 40 was disposed on the first surface 10a in the same manner as in the first example. The electrical resistance of the resistance element 40 was set to 0.1 mΩ, 0.3 mΩ, 1 mΩ, and 10 mΩ as shown in Table 4, and the resistance of the power supply path was calculated. When the resistance element 40 was not disposed, the resistance of the power supply path was 234 mΩ. In contrast, when the electrical resistance of the resistance element 40 was set to 0.1 mΩ, the resistance was 191 mΩ. When the electrical resistance of the resistance element 40 was set to 0.3 mΩ, the resistance was 196 mΩ. When the electrical resistance of the resistance element 40 was set to 1 mΩ, the resistance was 208 mΩ. When the electrical resistance of the resistance element 40 was set to 10 mΩ, the resistance was 229 mΩ.

[0062] [Table 4]

[0063] In this way, the resistance of the power supply path is reduced by setting a low resistance value of the resistance member 40. By setting the resistance value of the resistance member 40 to 1 mΩ or less, it was possible to reduce the electrical resistance value by approximately 10% or more.

[0064] [effect] The effects of the substrate disclosed in this specification will be described below.

[0065] The substrate disclosed in this specification includes a resistive element connected in parallel to the power supply wiring 14 connecting the power supply module 20 and the LSI chip 30, thereby reducing the resistance of the power supply path and reducing power loss.

[0066] By connecting the resistance member to the first outermost layer 14a1 or the second outermost layer 14a2, the length of the path connecting the resistance member 40 and the power supply wiring 14 can be shortened, and an increase in the electrical resistance value can be suppressed.

[0067] By providing the ground layer 16 between the layered portion 18a of the signal wiring 18 and the first outermost layer 14a1 or the second outermost layer 14a2, a noise countermeasure for the signal wiring 18 can be achieved.

[0068] The resistance of the resistor member can be reduced by forming the resistor member from gold, silver, copper, aluminum, tungsten, iron, tantalum, or an alloy containing any of these elements.

[0069] By setting the electrical resistance value of the resistance member to 1 mΩ or less, the resistance of the power supply path can be reduced, thereby reducing power loss.

[0070] By arranging the resistance elements in parallel in the X direction or the Y direction, it is possible to arrange a plurality of resistance elements and reduce the resistance of the power supply path, thereby reducing power loss.

[0071] By increasing the dimensions of the resistance member in the X direction and the Y direction, the resistance of the power supply path can be reduced, and power loss can be reduced.

[0072] By arranging the resistive member so as to avoid overlapping with the signal wiring, it is possible to take measures against noise in the signal wiring.

[0073] Although the preferred embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and changes are possible within the scope of the gist of the present invention described in the claims. [Explanation of symbols]

[0074] 1 printed circuit board, 10, 50, 60, 70, 80, 81 to 84 package substrate, 14 power supply wiring, 14a wiring layer, 14a1 first outermost layer, 14a2 second outermost layer, 16 ground layer, 18 signal wiring, 18a layered portion, 20 power supply module (power supply section), 30 LSI chip (electronic component), 40, 42, 44, 46 resistance member

Claims

1. A substrate on which electronic components are mounted on a first surface, a power supply unit that supplies power to the electronic components is mounted on either the first surface or a second surface that is the reverse side of the first surface, and power wiring that electrically connects the electronic components and the power supply unit is formed inside the substrate, a resistor member connected in parallel to the power supply wiring is mounted on at least one of the first surface and the second surface; substrate.

2. the power supply wiring includes a plurality of wiring layers formed in the substrate; the resistance member is connected to a first outermost layer of the plurality of wiring layers that is formed at a position closest to the first surface, and is mounted on the first surface; The substrate of claim 1 .

3. the substrate includes signal wiring connected to the electronic component, and a ground layer provided between a layer portion of the signal wiring and the first outermost layer; The substrate of claim 2 .

4. the power supply wiring includes a plurality of wiring layers formed in the substrate; the resistance member is connected to a second outermost layer of the plurality of wiring layers that is formed at a position closest to the second surface, and is mounted on the second surface; The substrate of claim 1 .

5. the substrate includes signal wiring connected to the electronic component, and a ground layer provided between a layer portion of the signal wiring and the second outermost layer; The substrate of claim 4.

6. the electronic component and the power supply unit are disposed opposite to each other along a first direction when viewed from a direction perpendicular to the first surface and the second surface, A plurality of the resistance members are arranged on at least one of the first surface and the second surface, and the plurality of resistance members are arranged in parallel along the first direction. The substrate of claim 1 .

7. the electronic component and the power supply unit are disposed opposite to each other along a first direction when viewed from a direction perpendicular to the first surface and the second surface, A plurality of the resistance members are arranged on at least one of the first surface and the second surface, and the plurality of resistance members are arranged in parallel along a second direction perpendicular to the first direction. The substrate of claim 1 .

8. the electronic component and the power supply unit are disposed opposite to each other along a first direction when viewed from a direction perpendicular to the first surface and the second surface, a dimension of the resistance member along the first direction that is 25% or more of a distance between the electronic component and the power supply unit along the first direction; The substrate of claim 1 .

9. the electronic component and the power supply unit are disposed opposite to each other along a first direction when viewed from a direction perpendicular to the first surface and the second surface, a dimension of the resistor member along a second direction perpendicular to the first direction is 25% or more of a dimension of the electronic component along the second direction; The substrate of claim 1 .

10. the substrate includes signal wiring connected to the electronic components; the resistance member is disposed at a position that avoids overlapping with the signal wiring when the substrate is viewed in a direction perpendicular to the first surface and the second surface. The substrate of claim 1 .

11. An electronic device in which a package substrate is mounted on a printed circuit board, The package substrate is Electronic components are mounted on a first surface, and a power supply unit that supplies power to the electronic components is mounted on either the first surface or a second surface that is the reverse side of the first surface, and power wiring that electrically connects the electronic components and the power supply unit is formed inside, a resistor member connected in parallel to the power supply wiring is mounted on at least one of the first surface and the second surface; electronic equipment.

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