Semiconductor device and driving method for the same

Abstract

To stabilize an operation of a semiconductor device containing a MOS-controlled diode (MOSD) without increasing the loss of the semiconductor device, even when an abnormality occurs in a gate drive of the MOSD constituting the semiconductor device.SOLUTION: A semiconductor device includes a switching element having a first gate signal applied to its gate terminal, and a diode having a second gate signal applied to its gate terminal, with its anode terminal connected to the main terminal of the switching element and connected in series with the switching element. The diode has the characteristic of switching between a first state, where the amount of charge inside the diode is large and the forward voltage is small, and a second state, where the amount of charge inside the diode is small and the forward voltage is large when the second gate signal is applied. The switching of the switching element by the first gate signal is controlled according to the voltage state of the diode's gate terminal.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for driving the semiconductor device, and is particularly suitable for a semiconductor device using a power semiconductor element. [Background technology]

[0002] In order to improve the efficiency of power conversion equipment, development of multi-gate power devices with multiple gates is progressing, and MOS (Metal-Oxide-Semiconductor) controlled diodes are also being developed as power devices to be used in power electronics such as power conversion equipment.

[0003] This MOS-controlled diode (hereafter abbreviated as "MOSD") is a device in which an insulated gate with a MOS structure is provided in a diode, and the amount of internal charge can be controlled by applying a voltage to this gate electrode (Gd).

[0004] Furthermore, by controlling the gate voltage, the MOSD can switch between a conduction mode, in which there is a large internal charge and low conduction loss, and a recovery mode, in which there is a small internal charge and low recovery loss, making it a device that achieves both low conduction loss and low recovery loss.

[0005] Patent Document 1 shows a MOSD that is connected in series to the main terminal of a switching device that constitutes a semiconductor device and controls the amount of charge inside it with its own gate terminal, and discloses a technology in which the gate Gs of the switching device and the gate Gd of the MOSD are controlled with a predetermined time difference by a PWM signal, thereby reducing both conduction loss and reverse recovery loss. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2015-204723 Summary of the Invention [Problem to be solved by the invention]

[0007] With regard to MOSDs, recovery loss can be reduced by recovering when its own gate Gd is on. However, if the recovery state occurs when the gate Gd is off due to an abnormality in the gate drive circuit, this increases loss and raises concerns about failure, so this state must be prevented.

[0008] The aforementioned Patent Document 1 does not disclose the exchange of gate terminal status signals between paired arms, nor does it disclose how to deal with the situation where the gate Gd does not rise due to an abnormality in the gate drive circuit or the like.

[0009] FIG. 9 is a diagram showing a current gate drive method for a semiconductor device consisting of a pair of arms (upper arm 1 and lower arm 2) that use dual-gate type switching elements in which MOSDs are connected in antiparallel. The turn-on signal to the MOSD gate Gd is estimated from the turn-off of the switching element of the own arm and its dead time. With this method, it is difficult to prevent malfunction of the MOSD gate Gd when there is an abnormality in the signal from the control logic unit (not shown) that inputs the PWM signal to the gate drive circuits (3 for the upper arm and 4 for the lower arm) or when there is an abnormality in the operation of the gate drive circuits themselves.

[0010] Therefore, an object of the present invention is to provide a technique for inhibiting the turning on of the switching element of the paired arm when the gate Gd of the MOSD does not rise from the OFF state due to an abnormality in the gate drive circuit or the like. [Means for solving the problem]

[0011] In order to solve the above problems, one representative semiconductor device of the present invention comprises a switching element having a gate terminal to which a first gate signal is applied, and a diode having a gate terminal to which a second gate signal is applied and having its anode terminal connected to a main terminal of the switching element and connected in series with the switching element, wherein the diode has a characteristic that, when the second gate signal is applied, it switches between a first state in which the amount of charge inside the diode is large and the forward voltage is small, and a second state in which the amount of charge inside the diode is small and the forward voltage is large, and switching of the switching element by the first gate signal is controlled according to the voltage state of the gate terminal of the diode. [Effects of the Invention]

[0012] According to the present invention, even if an abnormality occurs in the gate drive of a MOSD, the operation of the semiconductor device including the MOSD can be stabilized without increasing the loss of the semiconductor device. Problems, configurations, and effects other than those described above will become apparent from the following description of the preferred embodiments. [Brief explanation of the drawings]

[0013] [Figure 1] FIG. 1 is a diagram showing the respective operating modes of a MOSD in a conventional semiconductor device configuration during normal operation and abnormal operation. [Figure 2] FIG. 2 is a diagram showing the operation modes of a MOSD in the configuration of a semiconductor device (single gate type) according to the present invention during normal operation and abnormal operation. [Figure 3] FIG. 3 is a diagram showing the operation modes of a MOSD in the configuration of a semiconductor device (multi-gate type) according to the present invention during normal operation and abnormal operation. [Figure 4] FIG. 4 is a diagram showing an example of the configuration of a gate portion of the semiconductor device according to the first embodiment of the present invention. [Figure 5] FIG. 5 is a diagram showing an example of a specific configuration of the rise inhibition logic (A). [Figure 6]FIG. 6 is a diagram showing another example of the configuration of the gate portion of the semiconductor device according to the first embodiment of the present invention. [Figure 7] Second Embodiment FIG. 7 is a diagram showing an example of the configuration of a gate portion of a semiconductor device according to a second embodiment of the present invention. [Figure 8] FIG. 8 is a diagram illustrating an example of a semiconductor device that performs power conversion using the first or second embodiment. [Figure 9] FIG. 9 is a diagram showing a current gate drive method for a semiconductor device consisting of a pair of arms (upper arm and lower arm) that use dual-gate type switching elements in which MOSDs are connected in antiparallel. DETAILED DESCRIPTION OF THE INVENTION

[0014] Hereinafter, examples 1 and 2 will be described as embodiments of the present invention with reference to the drawings. Note that the present invention is not limited to these examples. In addition, in the drawings, the same parts are denoted by the same reference numerals. [Example]

[0015] The semiconductor elements constituting the semiconductor device according to the present invention are a switching element and a metal-oxide-semiconductor-controlled diode (MOSD) whose anode terminal is connected to the main terminal (collector terminal) of the switching element. Examples of the switching element include typical power semiconductors such as an insulated gate bipolar transistor (IGBT) and a power MOSFET. IGBTs also come in two types: a typical single gate and a multi-gate type designed for low loss. Either type may be used in the present invention.

[0016] 1 to 3 are diagrams showing the operation modes of a MOSD in a semiconductor device during normal operation and abnormal operation. Regarding abnormal operation, Fig. 1 shows the case of a conventional configuration in which no countermeasures are implemented, while Figs. 2 and 3 show the cases in which countermeasures are implemented by the configuration according to the present invention in a single-gate type and a dual-gate type switching element.

[0017] The left side of each of Figures 1 to 3 shows the configuration of the upper and lower arms of the semiconductor device. The anode terminal of the MOSD constituting the upper arm 1 is connected to the main terminal (collector terminal) of the switching element constituting the lower arm 2 to form a series circuit. The cathode terminal of the MOSD is the positive side, and the emitter terminal of the switching element is the negative side, allowing for a configuration in which both terminals are connected to a DC power supply. On the other hand, the connection point between the anode terminal of the MOSD and the main terminal (collector terminal) of the switching element can be taken out as an AC terminal, allowing, for example, an inductive load to be connected between this connection point and the cathode terminal of the MOSD.

[0018] In addition, both the upper arm 1 and the lower arm 2 can have a similar configuration in which a switching element and a MOSD are connected in anti-parallel (a configuration including the portions of the upper arm 1 and the lower arm 2 indicated by dotted lines in Figures 1 to 3).

[0019] In addition, in FIGS. 2 and 3, a determination unit 7, which is a characteristic feature of the present invention and will be described later, is added to the gate Gd of the MOSD for the upper and lower arms. In the waveform diagrams of Figures 2 and 3, Gd * , Gs * and Gc * corresponds to a gate command signal from the command generating unit 5 (FIGS. 4 and 6) described later, and also indicates an output from the determining unit 7 described later.

[0020] First, the operation mode during normal operation will be described. During normal operation, the waveform diagrams on the left side of each of Figures 1 to 3 are waveform diagrams for "normal operation." Figures 1 to 3 all exhibit the same operating mode and are common, so Figure 1 will be mainly used for the explanation.

[0021] For the gate Gd of the MOSD that constitutes the upper arm 1, V Gd By switching from a predetermined voltage (for example, -15V shown in the figure) to another predetermined voltage (for example, +15V shown in the figure), the charge transfers from high injection mode to low injection mode. This reduces the conduction loss (loss during conduction) in the high injection mode, and reduces the recovery loss (loss during recovery) when the switching element constituting the lower arm 2, which is the counterpart arm, is turned on after the transfer to low injection mode. Note that in Figures 2 and 3, V Gd It can be seen that as the voltage changes to another predetermined voltage (for example, +15V shown in the figure), the output of the determining unit 7 also changes to H level.

[0022] Next, a description will be given of how the MOSD leads to operational instability in the case of "abnormal operation" in the conventional configuration shown on the right side of FIG. If some abnormality, such as a gate drive circuit failure including a gate line break, occurs, the V Gd If the voltage does not switch from a predetermined voltage (for example, -15V shown in the diagram) and another predetermined voltage (for example, +15V shown in the diagram) is not established (as shown in the diagram, it remains a solid line, not a dashed line), it will not be possible to transition to low injection mode, and the switching element that makes up the paired arm, lower arm 2, will turn on while the device remains in high injection mode. This will increase the current value during recovery, increasing recovery loss, exceeding the reverse recovery safe operating area (RRSOA) and causing unstable operation. In some cases, this may even lead to destruction of the device.

[0023] In contrast to this, in the case of "abnormal operation" in the configuration of the present invention shown on the right side of Figs. 2 and 3, a manner in which operation is stabilized by taking measures will be described. This invention reduces the V Gd The determination unit 7 detects an abnormal change in (VGd does not rise, the output from the determining unit 7 does not change to H level), and the switching element of the opposing arm, lower arm 2, is inhibited from turning on.

[0024] Specifically, as shown in FIGS. 2 and 3, a gate command signal Gs is applied to the gates Gs and Gc. * and Gc * Even though V is on, the application of gate signals Gs and Gc is prevented, and the switching element is not turned on. This prevents the switching element from being allowed to turn on, and the switching element is safely stopped. Gd The method for detecting abnormal changes will be described later.

[0025] FIG. 4 is a diagram showing an example of the configuration of a gate portion of the semiconductor device according to the first embodiment of the present invention. In the first embodiment, in addition to the configuration of the conventional gate drive circuits (upper arm gate drive circuit 3 and lower arm gate drive circuit 4), a determination unit 7 is provided to determine the voltage state of the gate terminal (Gd) of the MOSD connected in anti-parallel to the switching elements constituting the upper arm 1 and the lower arm 2, and a gate command signal Gs is supplied to the switching elements in response to an output signal from this determination unit 7. * The signal line is provided with a rise inhibit logic (A) 9 for inhibiting the rise of the signal line and an insulating circuit 10 for ensuring insulation from the transmission part to the paired arm.

[0026] The judgment unit 7 judges the voltage state (potential) of the gate terminal (Gd) of the MOSD and, as explained above, detects an abnormality in which Gd does not rise. The judgment output of this judgment unit 7 is input to the rise prohibition logic (A) 9 of the gate drive circuit of the opposing arm via the isolation circuit 10. In other words, when an abnormality occurs in the gate drive of the MOSD, the judgment unit 7 detects an abnormality in which Gd does not rise, and in response to this, the rise prohibition logic (A) 9 of the gate drive circuit of the opposing arm prohibits the turn-on of the switching element of the opposing arm. This allows for safe shutdown without exceeding the reverse recovery safe operating area (RRSOA).

[0027] Furthermore, an isolation circuit 10 is provided in the path from the judgment unit 7 to the rise inhibition logic (A) 9 in the gate drive circuit of the opposing arm, either in the judgment unit 7 or in the gate drive circuit that includes the rise inhibition logic (A) 9, to ensure insulation in the transmission section. However, as shown in Figure 4, it is not necessary to provide an isolation circuit 10 in both gate drive circuits; it is sufficient to provide one in at least one of the gate drive circuits.

[0028] FIG. 5 is a diagram showing an example of a specific configuration of the rise inhibition logic (A) 9. As shown in FIG. This is an example in which the rise inhibition logic (A) 9 is configured with a logic circuit and an RS flip-flop, and the gate command signal (Gs * ) and the gate terminal voltage of the paired arm MOSD (V Gd ) is input to the set terminal (S) of the RS flip-flop. Gd If the ON state of the switching element is not established, a gate command signal (Gs * ) is inhibited from rising by the rise inhibition logic (A) 9. The configuration of the rise inhibition logic (A) 9 shown here is also adopted in other examples of the first embodiment and the second embodiment described later. However, the specific configuration of the rise inhibition logic (A) 9 is not limited to the above configuration.

[0029] FIG. 6 is a diagram showing another example of the configuration of the gate portion of the semiconductor device according to the first embodiment of the present invention, and is an application example in which the switching element is of a dual gate type. 4, there is no change in providing rise inhibition logic for the gate of the switching element, and rise inhibition logic (A) 9 is provided for each of the dual gates (Gs and Gc) of the switching element of the paired arm. The judgment output from the judgment unit 7 is input to each of the rise inhibition logic (A) 9.

[0030] As with the single-gate switching element shown in Fig. 4, an isolation circuit 10 is provided in each gate drive circuit on the path from the determination unit 7 to the rise inhibition logic (A) 9 in the gate drive circuit of the paired arm to ensure insulation in the transmission section. However, as shown in Fig. 6, it is not necessary to provide an isolation circuit 10 in both gate drive circuits; it is sufficient to provide one in at least one of the gate drive circuits. [Example]

[0031] Fig. 7 is a diagram showing an example of the configuration of a gate part of a semiconductor device according to Example 2 of the present invention. Although Fig. 7 shows a configuration corresponding to the single-gate switching element of Example 1 shown in Fig. 4, Example 2 can naturally also be applied to the dual-gate switching element of Example 1 shown in Fig. 6.

[0032] 4 and 6 is that the present embodiment does not include the isolation circuit 10. In the first embodiment, the voltage state (potential) of the gate terminal (Gd) of the MOSD is directly detected, and therefore the isolation circuit 10 is used to ensure isolation from the transmission part to the paired arm.

[0033] Therefore, in the second embodiment, the voltage state of the gate terminal (Gd) of the MOSD is displayed as an estimated value without using the isolation circuit 10, thereby eliminating the need to ensure isolation in the transmission portion to the paired arm.

[0034] Specifically, an estimation unit 8 is provided to estimate the voltage state of the gate terminal (Gd) of the MOSD. The estimation unit 8 estimates the voltage state of the gate terminal (Gd) from a command signal corresponding to the gate signal of the gate terminal (Gd) of the MOSD. For example, as shown in FIG. 7 , the estimation unit 8 estimates the voltage state of the gate terminal (Gd) from the state of the PWM signal input to the command generation unit 5 in the gate drive circuit (upper arm gate drive circuit 3 and lower arm gate drive circuit 4), and outputs the estimated value to the determination unit 7.

[0035] The judgment unit 7 judges that the gate signal of the gate terminal (Gd) does not rise from the estimated value received from the estimation unit 8, and the judgment output is input to the rise prohibition logic (A) 9 of the opposite arm. The rise prohibition logic (A) 9 receives the judgment output of this abnormality and, among the PWM signals input as command signals, * In this case, in the rise prohibition logic (A) 9, the judgement output from the judgement unit 7 and the gate command signal (Gs * ) can be inhibited by using a logical operation with a command signal related to the generation of the output voltage Vout. This inhibits the turning on of the switching element of the paired arm.

[0036] However, in this case, it is not possible to respond to abnormalities such as a failure occurring in the gate driver 6 located after the command generator 5 or a break in the wire from the gate driver 6 to the gate terminal (Gd). On the other hand, since the isolation circuit 10 can be eliminated, the circuit configuration within the gate drive circuit can be simplified.

[0037] FIG. 8 is a diagram illustrating an example of a semiconductor device that performs power conversion using the first or second embodiment. 8, the semiconductor devices according to Example 1 or Example 2, each composed of upper and lower arms, are arranged in parallel for three phases as semiconductor devices that perform power conversion, thereby forming a three-phase inverter that converts DC power from DC power supply 12 into three-phase AC power to drive AC motor 13. Specifically, the upper and lower arms shown in FIGS. 4, 6, and 7 are arranged in parallel for three phases, the P terminal of upper arm 1 is connected to the positive electrode of DC power supply 12, the N terminal of lower arm 2 is connected to the negative electrode of DC power supply 12, and the connection points (AC terminals) between upper arm 1 and lower arm 2 are connected to AC motor 13 as U phase, V phase, and W phase, respectively.

[0038] With regard to the gate drive circuits, an upper arm PWM signal and a lower arm PWM signal are input from control logic unit 11 to upper arm gate drive circuit 3 for upper arm 1 and lower arm gate drive circuit 4 for lower arm 2. The two wires connecting upper arm gate drive circuit 3 and lower arm gate drive circuit 4 are connection lines between determination unit 7 and rise inhibition logic (A) 9 shown in Figures 4, 6, and 7.

[0039] In addition, in FIG. 8, the AC output is three-phase AC, but the semiconductor device according to the first or second embodiment, which is configured with upper and lower arms, may be provided in parallel for two phases to configure a single-phase inverter that converts into single-phase AC power.

[0040] The semiconductor device that performs power conversion as the inverter described above is mounted on a train or other railcar as a drive unit or in-car power supply, and is also expected to be used as a drive unit for AC motors used in a wide range of industrial equipment.

[0041] According to the above-mentioned Examples 1 and 2, the present invention includes at least the following aspects. <Aspect 1> The semiconductor device is composed of a switching element having a gate terminal to which a first gate signal is applied, and a diode having a gate terminal to which a second gate signal is applied and having its anode terminal connected to a main terminal of the switching element and connected in series with the switching element, wherein the diode has a characteristic that, when the second gate signal is applied, it switches between a first state in which the amount of charge inside the diode is large and the forward voltage is small, and a second state in which the amount of charge inside the diode is small and the forward voltage is large, and switching of the switching element by the first gate signal is controlled according to the voltage state of the gate terminal of the diode.

[0042] <Aspect 2> In the semiconductor device according to the first aspect, the voltage state of the gate terminal of the diode is estimated from a command signal related to the generation of the second gate signal.

[0043] <Aspect 3> In the semiconductor device described in the above aspect 1 or aspect 2, whether or not the switching element can be turned on is determined depending on the voltage state of the gate terminal of the diode, and when it is determined that the switching element can be turned off, the rising edge of the first gate signal is prohibited.

[0044] <Aspect 4> In the semiconductor device according to the third aspect, whether or not the switching element is turned on is determined by a logical operation between the voltage state of the gate terminal of the diode and the first gate signal or a command signal related to the generation of the first gate signal.

[0045] <Aspect 5> A semiconductor device using the semiconductor device according to any one of the above aspects 1 to 4, wherein the switching element is a second switching element, the diode is a first diode, an upper arm is formed by connecting the first diode in anti-parallel to the first switching element, which is an element of the same type as the second switching element, and a lower arm is formed by connecting a second diode, which is an element of the same type as the first diode, in anti-parallel to the second switching element, and the upper arm and the lower arm are connected in series.

[0046] <Aspect 6> The semiconductor devices described in aspect 5 above are connected in parallel in two or three rows, and the positive pole sides of the upper arms and the negative pole sides of the lower arms of the two or three rows are used as DC side terminals, and each of the connection points between the upper arms and lower arms of the two or three rows is used as an AC side terminal to form a semiconductor device that performs power conversion.

[0047] <Aspect 7> A railway vehicle equipped with the semiconductor device according to the sixth aspect.

[0048] <Aspect 8> A method for driving a semiconductor device comprising a switching element having a gate terminal to which a first gate signal is applied, and a diode having a gate terminal to which a second gate signal is applied and having its anode terminal connected to a main terminal of the switching element and connected in series with the switching element, wherein a second gate signal is applied to the gate terminal of the diode to switch between a first state in which the amount of charge inside the diode is large and the forward voltage is small, and a second state in which the amount of charge inside the diode is small and the forward voltage is large, and the switching of the switching element by the first gate signal is controlled in accordance with the voltage state of the gate terminal of the diode.

[0049] <Aspect 9> In the method for driving the semiconductor device according to the eighth aspect, the voltage state of the gate terminal of the diode is estimated from a command signal for generating the second gate signal.

[0050] <Aspect 10> A method for driving a semiconductor device according to the eighth or ninth aspect, in which whether or not the switching element can be turned on is determined based on the voltage state of the gate terminal of the diode, and if it is determined that the switching element can be turned off, the rising edge of the first gate signal is prohibited.

[0051] <Aspect 11> A method for driving a semiconductor device according to the tenth aspect, wherein a logical operation is performed between the voltage state of the gate terminal of the diode and a first gate signal or a command signal related to the generation of the first gate signal to determine whether or not to turn on the switching element.

[0052] Although Examples 1 and 2 have been described above as embodiments of the present invention, the present invention is not limited to the above-described examples, and various modifications are possible within the scope of the gist of the present invention. [Explanation of symbols]

[0053] 1...upper arm, 2...lower arm, 3...upper arm gate drive circuit, 4...lower arm gate drive circuit, 5...command generation unit, 6...gate drive unit, 7...determination unit, 8... Estimation unit, 9... Rise inhibition logic (A), 10... Isolation circuit, 11... Control logic unit, 12... DC power supply, 13... AC motor

Claims

1. a switching element having a gate terminal to which a first gate signal is applied; a diode connected in series with the switching element, the diode having a gate terminal to which a second gate signal is applied and an anode terminal connected to a main terminal of the switching element; the diode has a characteristic of switching between a first state in which the amount of charge inside the diode is large and the forward voltage is small and a second state in which the amount of charge inside the diode is small and the forward voltage is large when the second gate signal is applied; The switching of the switching element by the first gate signal is controlled in accordance with the voltage state of the gate terminal of the diode. A semiconductor device characterized by:

2. 2. The semiconductor device according to claim 1, The voltage state of the gate terminal of the diode is estimated from a command signal for generating the second gate signal. A semiconductor device characterized by:

3. 3. The semiconductor device according to claim 1, Whether or not the switching element is turned on is determined according to the voltage state of the gate terminal of the diode, and when it is determined that the switching element is turned on or not, the rising edge of the first gate signal is prohibited. A semiconductor device characterized by:

4. 4. The semiconductor device according to claim 3, Whether or not the switching element is turned on is determined by a logical operation between the voltage state of the gate terminal of the diode and the first gate signal or a command signal related to the generation of the first gate signal. A semiconductor device characterized by:

5. 3. A semiconductor device according to claim 1, wherein the switching element is a second switching element and the diode is a first diode; an upper arm is configured by connecting the first diode in anti-parallel to a first switching element that is the same type as the second switching element; a second diode, which is the same type of element as the first diode, is connected in antiparallel to the second switching element to form a lower arm; The upper arm and the lower arm are connected in series.

6. The semiconductor device according to claim 5 is connected in parallel in two or three rows, the positive electrode side of the upper arm and the negative electrode side of the lower arm of the two or three rows are DC side terminals, A semiconductor device that performs power conversion using each of the connection points between the upper arms and the lower arms of the two or three rows as AC side terminals.

7. A railway vehicle equipped with the semiconductor device according to claim 6.

8. a switching element having a gate terminal to which a first gate signal is applied; a diode connected in series with the switching element, the diode having a gate terminal to which a second gate signal is applied and an anode terminal connected to a main terminal of the switching element, the method comprising: applying the second gate signal to the gate terminal of the diode to switch between a first state in which the amount of charge inside the diode is large and the forward voltage is small and a second state in which the amount of charge inside the diode is small and the forward voltage is large; The switching of the switching element by the first gate signal is controlled in accordance with a voltage state of the gate terminal of the diode.

10. A method for driving a semiconductor device comprising:

9. 9. A method for driving a semiconductor device according to claim 8, comprising: A voltage state of the gate terminal of the diode is estimated from a command signal related to generation of the second gate signal.

10. A method for driving a semiconductor device comprising:

10. 10. A method for driving a semiconductor device according to claim 8, comprising: Whether or not the switching element is turned on is determined according to the voltage state of the gate terminal of the diode, and if it is determined that the switching element is turned on or not, the rising edge of the first gate signal is inhibited.

10. A method for driving a semiconductor device comprising:

11. 11. A method for driving a semiconductor device according to claim 10, comprising: A logical operation is performed between the voltage state of the gate terminal of the diode and the first gate signal or a command signal related to the generation of the first gate signal to determine whether or not the switching element is to be turned on.

10. A method for driving a semiconductor device comprising:

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