Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor with long life and excellent dielectric characteristics.SOLUTION: A multilayer ceramic capacitor comprises a body in which a dielectric layer containing a perovskite-type compound represented by the general formula ABO3 and an internal electrode layer are alternately stacked. The dielectric layer and the internal electrode layer have an intermediate region therebetween. The internal electrode layer and the intermediate region each contain copper. The following relation is satisfied, 1 / (0.55 t+1.54)≤a≤3, where t (μm) is the thickness of the internal electrode layer and a (atom%) is the copper concentration in the internal electrode layer.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to multilayer ceramic capacitors. [Background technology]

[0002] Multilayer ceramic capacitors (MLCCs) have a structure in which dielectric layers and internal electrode layers are alternately stacked, and are used in a variety of electronic devices such as mobile phones and personal computers.

[0003] In recent years, with the increasing functionality and performance of electronic devices, there has been a demand for multilayer ceramic capacitors to be smaller and have larger capacitance, etc. In order to meet such demands, it is effective to thin the dielectric layers and internal electrode layers and increase the number of layers, but thinning the dielectric layers and internal electrode layers can reduce the electric field strength and decrease the insulation reliability, etc.

[0004] Therefore, various studies have been conducted on a configuration that can obtain desired characteristics even when the dielectric layers and internal electrode layers are thinned. One such configuration is known to increase the interface resistance and improve the insulation reliability of the multilayer ceramic capacitor by forming a layer containing a different element between the dielectric layers and the internal electrode layers. For example, Patent Document 1 describes a multilayer ceramic capacitor in which a diffusion-phase grain layer exists between the dielectric layers and the internal electrode layers, and states that insulation deterioration can be suppressed and the life characteristics can be improved. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2006-319205 Summary of the Invention [Problem to be solved by the invention]

[0006] However, depending on the configuration of the multilayer ceramic capacitor, the effect of improving reliability due to the dissimilar elements as described above may not be fully achieved. For example, as the thickness of the internal electrode layers becomes thinner due to the recent trend toward smaller and thinner capacitors, the expected life characteristics may not be achieved, or even if the goal of long life is achieved, the electrostatic characteristics may be insufficient.

[0007] An object of the present disclosure is to provide a multilayer ceramic capacitor that has a long life and excellent dielectric properties, regardless of the thickness of the internal electrode layers. [Means for solving the problem]

[0008] One aspect of the present disclosure is a multilayer ceramic capacitor having an element body in which dielectric layers containing a perovskite compound represented by the general formula ABO3 and internal electrode layers are alternately stacked, and having an intermediate region between the dielectric layers and the internal electrode layers, the internal electrode layers and the intermediate region each containing copper, and satisfying 1 / (0.55t+1.54)≦a≦3, where t (μm) is the thickness of the internal electrode layer and a (atomic %) is the copper concentration in the internal electrode layers. [Effects of the Invention]

[0009] According to one aspect of the present disclosure, a multilayer ceramic capacitor having a long life and excellent dielectric properties can be provided. [Brief explanation of the drawings]

[0010] [Figure 1] 1 is a perspective view showing a multilayer ceramic capacitor according to an embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 3 is an enlarged view of region C in FIG. 2. [Figure 5] FIG. 1 is a diagram showing an example of the results of TEM-EDX analysis of a multilayer ceramic capacitor. [Figure 6] 10A and 10B are diagrams for explaining a method for evaluating the continuity ratio of an internal electrode layer. [Figure 7] 1 is a flowchart illustrating a method for manufacturing a multilayer ceramic capacitor according to an embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0011] Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. In this specification and the drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. The drawings also show X-, Y-, and Z-axes, which are orthogonal to each other, as appropriate. The X-, Y-, and Z-axes define a fixed coordinate system fixed with respect to the multilayer ceramic capacitor. When the outer shape of a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, is a substantially rectangular parallelepiped, the X-, Y-, and Z-axes may correspond to the length, width, and height of the capacitor.

[0012] [Basic structure of multilayer ceramic capacitors] FIG. 1 is a perspective view showing a multilayer ceramic capacitor 100 according to an embodiment of the present disclosure. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1, and FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As shown in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes an element body 10 having a substantially rectangular parallelepiped shape. Two opposing surfaces of the element body 10 are referred to as the upper surface and the lower surface, and four surfaces connecting the upper surface and the lower surface are referred to as side surfaces. Typically, when the multilayer ceramic capacitor is mounted on a circuit board, the surface facing the board is referred to as the lower surface, but this is not limited to this.

[0013] In the example shown in FIGS. 1 to 3, a first external electrode 20a and a second external electrode 20b are provided on two opposing side surfaces of the element body 10, namely, a first side surface 10a and a second side surface 10b (see FIG. 2). The first external electrode 20a extends from the first side surface 10a to four surfaces adjacent to the first side surface 10a, and the second external electrode 20b extends from the second side surface 10b to four surfaces adjacent to the second side surface 10b. The first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the element body 10, not limited to two opposing side surfaces.

[0014] The element body 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The internal electrode layers 12 include a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edges of the first internal electrode layers 12a extend to the surface of the element body 10 on which the first external electrode 20a is provided, i.e., the first side surface 10a in the example of FIGS. 1 to 3. The edges of the second internal electrode layers 12b extend to the surface of the element body 10 on which the second external electrode 20b is provided, i.e., the second side surface 10b in the example of FIGS. 1 to 3. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately connected to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a configuration in which a plurality of capacitor units are stacked. It should be noted that the number of dielectric layers 11 and the number of internal electrode layers 12 in Figures 1 to 3 are merely examples for ease of explanation, and the multilayer ceramic capacitor according to this embodiment may be formed by stacking a greater number of layers.

[0015] The lamination direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked is the first axis. As shown in FIGS. 1 to 3, when the first axis, which is the stacking direction, is a direction along the Z axis in a fixed coordinate system (Z-axis direction), the Z axis is the stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked, and is the direction in which the internal electrode layers face each other. An axis perpendicular to the first axis, which is the stacking direction, is the second axis. As shown in FIGS. 1 to 3, when the second axis perpendicular to the first axis, which is the stacking direction, is a direction along the X axis (X-axis direction), this is the direction in which the internal electrode layers 12 are pulled out, and is the direction in which the first side surface 10a and the second side surface 10b of the element body 10 face each other, or the direction in which the first external electrode 20a and the second external electrode 20b face each other. In the example shown in FIGS. 1 to 3, this electrode pull-out direction (X-axis direction) is a direction along the longitudinal direction of the element body 10. The third axis is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis. As shown in FIGS. 1 to 3, when the third axis, which is perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is a direction along the Y axis (Y-axis direction), it is an axis along the direction in which the third side surface 10c and the fourth side surface 10d of the four side surfaces of the element body 10 face each other, and in the example shown in FIGS. 1 to 3, it is a direction along the width direction of the element body 10. The X-axis direction, the Y-axis direction, and the Z-axis direction are mutually orthogonal. The stacking direction is not limited to the Z direction and can be any direction. Therefore, for example, the first axis, which is the stacking direction, may be the X-axis in the X direction or the Y-axis in the Y direction.

[0016] In the present application, for the purpose of explaining general embodiments, figures illustrating a specific embodiment may be used, and the content described using the coordinate axis system used in one embodiment is applied to the general embodiment by replacing it with a general coordinate system in which the stacking direction is the first axis. For example, the X-axis, Y-axis, and Z-axis used in Figures 1 to 3 in a specific embodiment, in which the stacking direction coincides with the Z-axis, can be replaced with the second axis, third axis, and first axis in the general embodiment.

[0017] The region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region that generates capacitance in the multilayer ceramic capacitor 100, and is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other with a dielectric layer interposed therebetween.

[0018] In the capacitive section 14 formed by laminating the dielectric layers 11 and the internal electrode layers 12, the outermost in the lamination direction (Z-axis direction) is composed of the internal electrode layers 12. A cover layer 13 may be disposed on each of the outer surfaces of the capacitive section 14 in the lamination direction, i.e., on the outer surfaces of the outermost internal electrode layers 12 in the lamination direction. The cover layer 13 is a layer containing a ceramic material that functions as a dielectric, and may have the same composition as the dielectric layers 11 or a different composition.

[0019] The configuration of the element body 10 is not limited to that shown in FIGS. 1 to 3, as long as the first internal electrode layer 12a and the second internal electrode layer 12b are exposed in different regions on the surface of the element body 10 and are electrically connected to different external electrodes. The different regions on the surface of the element body 10 may be surface regions on opposing faces of the surface of the element body 10, surface regions on adjacent faces, or different surface regions on the same face. As long as the different external electrodes are spaced apart from each other, the first internal electrode layer 12a and the second internal electrode layer 12b may extend from the faces exposed in the surface regions of the laminate to other faces. Although not shown in FIGS. 1 to 3, the element body 10 may have multiple intermediate regions 40 (described in detail later) between the dielectric layer 11 and the internal electrode layer 12.

[0020] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without the second internal electrode layer 12b connected to the second external electrode 20b intervening therebetween is referred to as the first end margin 15a. The region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without the first internal electrode layer 12a connected to the first external electrode 20a intervening therebetween is referred to as the second end margin 15b. Each end margin is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without the internal electrode layer connected to a different external electrode intervening therebetween. The first end margin 15a and the second end margin 15b are regions that do not generate capacitance.

[0021] 3, the region provided adjacent to the outside of the capacitive section 14 in the Y-axis direction is called a side margin 16. This is the outer region adjacent to the capacitive section 14 on the side where the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate electrical capacitance.

[0022] The size of the multilayer ceramic capacitor 100 is not particularly limited, and may be, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high; 0.4 mm long, 0.2 mm wide, and 0.2 mm high; 0.6 mm long, 0.3 mm wide, and 0.3 mm high; 1.0 mm long, 0.5 mm wide, and 0.5 mm high; 3.2 mm long, 1.6 mm wide, and 1.6 mm high; or 4.5 mm long, 3.2 mm wide, and 2.5 mm high. However, the above-listed sizes of the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to these sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height; width > length ≥ height; height > length ≥ width; or height > width ≥ length. The ceramic capacitor 100 shown in FIGS. 1 to 3 has a length in the X-axis direction (electrode lead-out direction), a width in the Y-axis direction, and a height in the Z-axis direction (lamination direction).

[0023] (dielectric layer) The dielectric layer 11 contains a ceramic material as a main component, and preferably contains a compound having a perovskite structure represented by the general formula ABO3 (also referred to as a perovskite-type compound) as a main component. The dielectric layer 11 may contain the perovskite-type compound at, for example, 50 atomic % or more, 60 atomic % or more, 80 atomic % or more, 90 atomic % or more, or 95 atomic % or more. The perovskite structure may have an oxygen deficiency relative to the stoichiometric composition. In other words, the ABO3 deviates from the stoichiometric composition. 3-α (0≦α≦1: α represents an amount that deviates from the stoichiometric composition.) In addition, in this specification, "containing a specific component as a main component" means that the specific component is contained in the largest amount in terms of the proportion of substance amount among the components contained.

[0024] Perovskite compounds include barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and BaTiO3, which forms a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z O3 (0≦x≦1, 0≦y≦1, 0≦z≦1), etc. can be used. 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate.

[0025] Among the above compounds, barium titanate (BaTiO3) is preferable. Barium titanate has excellent dielectric properties such as a high dielectric constant and low dielectric loss, and therefore, when the dielectric layer 11 contains barium titanate as a perovskite compound, the capacitance of the multilayer ceramic capacitor 100 can be increased. The ceramic material in the dielectric layer 11 preferably contains barium titanate as a main component, but may be composed solely of barium titanate.

[0026] The dielectric layer 11 may contain additives other than the above-mentioned ceramic materials. Examples of additives include zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (scandium (Sc), cerium (Ce), neodymium (Nd), yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and yttrium (Y). Examples of the glass include a glass containing an oxide containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K) and silicon (Si), a glass containing an oxide containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium and silicon, and the like.

[0027] The dielectric layer 11 may contain copper (Cu). In this case, however, from the viewpoint of ensuring the insulating properties of the dielectric, the concentration of Cu in the dielectric layer 11 is preferably 0.1 atomic % or less.

[0028] (Internal electrode layer) The internal electrode layers 12 contain a metal or an alloy as a main component. The internal electrode layers 12 may contain, for example, a base metal such as nickel (Ni) or tin (Sn), or an alloy containing these, as a main component. The internal electrode layers 12 may also contain, as a main component, a noble metal such as platinum (Pt), palladium (Pd), silver (Ag), or gold (Au), or an alloy containing these. The internal electrode layers 12 preferably contain Ni, and may contain Ni as a main component, because of its excellent electrical properties and ability to reduce costs.

[0029] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different.

[0030] Furthermore, the internal electrode layer 12 contains Cu. When the internal electrode layer 12 contains Ni as a main component, Cu may form an alloy with Ni. When the internal electrode layer 12 contains Cu, the interface resistance between the internal electrode layer and the dielectric layer increases, which has the effect of extending the life of the MLCC.

[0031] The thickness t (mm) of the internal electrode layers 12 may be preferably 0.1 μm or more and 1.5 μm or less, more preferably 0.3 μm or more and 1.0 μm or less. When the thickness of the internal electrode layers 12 is 0.1 μm or more, the function as an internal electrode can be ensured. Furthermore, when the thickness of the internal electrode layers 12 is 1.5 μm or less, the number of laminations of the capacitance section 14 can be increased in a multilayer ceramic capacitor of the same size, thereby increasing the capacitance, which is preferable from the viewpoint of obtaining a smaller multilayer ceramic capacitor with the same performance. From the viewpoint of increasing the number of laminations to increase the capacitance, the thickness t (mm) of the internal electrode layers 12 is preferably, for example, 0.5 μm or less, and more preferably 0.4 μm or less.

[0032] The thickness t of the internal electrode layers 12 can be evaluated, for example, based on observation of a cross section of the multilayer ceramic capacitor 100. More specifically, the multilayer ceramic capacitor is polished along the X-axis or Y-axis direction to expose the YZ plane or XZ plane of the capacitive section 14. The position of the surface exposed by polishing is preferably a surface near the center of the capacitive section 14 in the X-axis or Y-axis direction. The exposed surface is imaged using a laser microscope or the like, and approximately 5 to 10 layers each are selected from the center, upper end, and lower end in the Z-axis direction, which is the lamination direction of the internal electrode layers 12, for a total of 15 to 20 internal electrode layers 12. The thickness (length in the Z-axis direction) of these internal electrode layers 12 is measured at ¼, ½, and ¾ of the width of each internal electrode layer, and the average value can be used as the thickness t (µm) of the internal electrode layers 12. When imaging using a laser microscope or the like, the images may be taken separately for the central portion, upper end portion, and lower end portion in the Z-axis direction, which is the lamination direction of the internal electrode layer 12, or may be taken separately for 1 / 4, 1 / 2, and 3 / 4 portions of the width of the internal electrode layer.

[0033] (middle area) FIG. 4 is an enlarged view of region C in FIG. 2. As shown in FIG. 4, the multilayer ceramic capacitor 100 according to this embodiment has an intermediate region 40 between the dielectric layer 11 and the internal electrode layer 12. FIG. 4 is a schematic diagram illustrating the intermediate region 40 as a continuous layer with a constant thickness, but the intermediate region 40 is not limited to the illustrated form. For example, the intermediate region 40 may be discontinuous, and the thickness may vary depending on the location. The intermediate region 40 may be formed by segregating elements between the dielectric layer 11 and the internal electrode layer 12 in a firing step (described in detail later) in which a laminate obtained by stacking unfired materials for forming the dielectric layer and the internal electrode layer is fired.

[0034] The intermediate region 40 can be identified by observing a cross section of the multilayer ceramic capacitor 100. For example, as described above for evaluating the thickness t of the internal electrode 12, the YZ plane or XZ plane of the capacitive section 14 is exposed. Then, line analysis is performed along the Z-axis direction on the exposed surface using energy dispersive X-ray spectroscopy (EDX) of a transmission electron microscope (TEM), and a graph of the concentration distribution of each element is output. In the graph, the intermediate region 40 can be determined as a region where the distribution range of the main component elements of the internal electrode layer 12 overlaps with the distribution range of the main component elements of the dielectric layer 11, or a region where there is a concentration gradient of the main component elements of the internal electrode layer 12 and the dielectric layer 11. If a strict boundary is required, the region may be determined as a region where the oxygen concentration is 5 atomic % or more and where the titanium (Ti) content of the main component elements of the dielectric layer 11 is 15 atomic % or less.

[0035] FIG. 5(a) shows an example of a graph of concentration distribution obtained by TEM-EDX analysis of the XZ plane exposed by polishing the multilayer ceramic capacitor 100 according to this embodiment. FIG. 5(b) is a portion of the graph in FIG. 5(a) enlarged in the vertical direction (enlarged view of the concentration range from 0 atomic % to 4 atomic %). FIGS. 5(a) and 5(b) show the analysis results of a multilayer ceramic capacitor 100 including a dielectric layer 11 made of barium titanate and an internal electrode layer 12 containing nickel as a main component and Cu. FIGS. 5(a) and 5(b) show a concentration gradient of nickel (Ni), as well as concentration gradients of oxygen (O), titanium (Ti), and barium (Ba), respectively, in the intermediate region 40 between the dielectric layer 11 and the internal electrode layer 12.

[0036] The intermediate region 40 contains Cu. Cu is a heterogeneous element, i.e., an element different from both the main component elements constituting the dielectric layers 11 and the main component elements constituting the internal electrode layers 12. The presence of such a heterogeneous element between the dielectric layers 11 and the internal electrode layers 12 increases the interface resistance between the dielectric layers 11 and the internal electrode layers 12, thereby achieving high insulation reliability over a long period of time. In other words, the life characteristics can be improved.

[0037] The Cu in the intermediate region 40 may be segregated from the internal electrode layers 12 and / or the dielectric layers 11, preferably from the internal electrode layers 12, during the firing step in the manufacture of the multilayer ceramic capacitor 100. Since Cu is more diffusible than other elements, it can be segregated in sufficient amounts between the internal electrode layers 12 and the dielectric layers 11 during the manufacturing process of the multilayer ceramic capacitor 100, which tends to increase the interfacial resistance.

[0038] (Cu concentration) As described above, in the multilayer ceramic capacitor 100 according to the embodiment, Cu is present in the internal electrodes 12 and the intermediate region 40. As a result of extensive research into the Cu concentration and the characteristics of the multilayer ceramic capacitor 100, the inventors have found that a ≧ 1 / (0.55t + 1.54), where t (μm) is the thickness of the internal electrode layers 12 and a (atomic %) is the Cu concentration in the internal electrode layers 12, can provide a multilayer ceramic capacitor 100 with high long-term insulation reliability, i.e., long life characteristics. Furthermore, the inventors have found that a ≦ 3 can provide a multilayer ceramic capacitor 100 with good dielectric properties. In this specification, good dielectric properties can mean that the internal electrode layers 12 have a high continuity ratio and / or sufficient capacitance.

[0039] As described above, the multilayer ceramic capacitor 100 according to this embodiment has a thickness of the internal electrode layer 12 of t (μm), a concentration of Cu in the internal electrode layer 12 of a (atomic %), and 1 / (0.55t+1.54)≦a≦3 This configuration ensures excellent dielectric properties while providing a long life, and achieves high reliability.

[0040] The life characteristics of the multilayer ceramic capacitor 100 can be evaluated based on the length of time required for the insulation resistance to decrease to a predetermined value in a high-temperature load test. For example, a highly accelerated limit test (HALT) can be used for the evaluation. In this test, a predetermined voltage is continuously applied at a predetermined temperature, for example, a voltage of 9.0 V at 150°C, and the time it takes for half of the tested multilayer ceramic capacitors to exceed the leakage current threshold is defined as the HALT 50% life value. A longer HALT 50% life value indicates a longer life.

[0041] The concentration a (atomic %) of Cu in the internal electrode layers 12 may be preferably 2.5 or less, more preferably 2 or less, even more preferably 1.5 or less, and even more preferably 1 or less. By setting the concentration a (atomic %) within the above range, it is possible to prevent a decrease in the continuity rate (%) due to a decrease in the melting point of the internal electrode layers 12 caused by the presence of excessive Cu in the internal electrode layers 12. Furthermore, from the viewpoint of improving life characteristics, the concentration a (atomic %) may be preferably 0.2 or more, more preferably 0.3 or more, and even more preferably 0.5 or more.

[0042] Furthermore, the Cu concentration b (atomic %) in the intermediate region 40 preferably satisfies 1≦b≦4.5. It may more preferably be 1.2≦b≦4, even more preferably 1.3≦b≦3, and even more preferably 1.5≦b≦2.5. When the Cu concentration b (atomic %) in the intermediate region 40 is 1 or more, Cu can be distributed to cover the internal electrode layer 12 with a sufficient area ratio, thereby increasing the interface resistance and achieving long life characteristics. Furthermore, when b (atomic %) is 4.5 or less, deterioration of insulation due to the presence of excessive Cu is avoided, and excellent electrostatic characteristics are obtained. In particular, when b≦2.5, high electrostatic capacitance can be ensured.

[0043] It is preferable that b / (0.55t+1.54) is 0.48 or more and less than 2.5. If b / (0.55t+1.54) is less than 0.48, the HALT life 50% value will be small, which is not preferable. If b / (0.55t+1.54) is 2.5 or more, the capacitance will decrease by 10% or more, which is not preferable.

[0044] From the viewpoint of obtaining high life characteristics, it is preferable that b / (0.55t + 1.54) is 0.48 or more, since the HALT life 50% value exceeds 1000 minutes. Furthermore, it is preferable that b / (0.55t + 1.54) is 1.2 or more, since the HALT life 50% value can be 2000 minutes or more, and it is even more preferable that b / (0.55t + 1.54) is 2.0 or more, since the HALT life 50% value can be 3000 minutes or more.

[0045] From the viewpoint of ensuring sufficient capacitance, b / (0.55t+1.54) may be preferably 3 or less, more preferably 2.5 or less, even more preferably 2.0 or less, even more preferably 1.5 or less, and even more preferably 1.0 or less.

[0046] Furthermore, the Cu concentration b (atomic %) in the intermediate region 40 may be greater than the Cu concentration a (atomic %) in the internal electrode layer 12. For example, the ratio of b to a, i.e., b / a, may be preferably 1.2 or more and 5 or less, more preferably 1.5 or more and 3.5 or less.

[0047] The Cu concentration b (atomic %) in the intermediate region 40 may be a value obtained by TEM-EDX analysis of the surface exposed by polishing, in the same manner as described for confirming the intermediate region 40. In this specification, the Cu concentration b (atomic %) in the intermediate region 40 is the maximum Cu concentration (atomic %) in the region recognized as the intermediate region 40 in the graph of concentration distribution obtained by TEM-EDX analysis. Furthermore, the Cu concentration a (atomic %) in the internal electrode layer 12 is the average Cu concentration (atomic)% in the region on the internal electrode side excluding the intermediate region 40 in the graph of concentration distribution obtained by TEM-EDX analysis. If a strict boundary is required, the region of the internal electrode layer 12 may be a region where the oxygen concentration is less than 5 at%. Both of the concentrations a and b are atomic ratios with respect to all elements contained in the internal electrode layer 12.

[0048] The continuity rate of the internal electrode layers 12 may be preferably 78% or more, more preferably 80% or more, even more preferably 85% or more, and even more preferably 90% or more.

[0049] The continuity ratio of the internal electrode layers 12 can be measured on the surface exposed by polishing in the same manner as described for evaluating the thickness t of the internal electrode layers 12 and checking the intermediate region 40. The exposed XZ or YZ surface is imaged using a laser microscope or the like, and approximately 5 to 10 layers are selected from the center, upper end, and lower end in the Z-axis direction, which is the lamination direction of the internal electrode layers 12, for a total of 15 to 20 layers of internal electrode layers 12. Figure 6 shows a schematic diagram of the captured image. In the captured image, electrode portions 91, 91, ..., which are continuous, uninterrupted portions of the internal electrode layers 12, are identified based on contrast or the like, and the length of each of the electrode portions 91, 91, ... at the center in the Z-axis direction is measured. For example, the lengths L1, L2, ..., Ln of the electrode portions 91, 91, ... are measured for one internal electrode 12, and the sum of these lengths is divided by the length L0 of the measurement area (i.e., (L1 + L2 + ..., + Ln) / L0), which can be used as the continuity ratio (%) of the one internal electrode layer 12. Furthermore, the continuity ratios of the other internal electrode layers 12 in the captured image can be calculated in the same way, and the average value can be used as the continuity ratio (%) of the internal electrode layers 12 in the multilayer ceramic capacitor sample. It is preferable that the total number of internal electrode layers 12 for which the continuity ratio is to be measured includes the same number of first internal electrode layers 12a and second internal electrode layers 12b. Note that images captured by a scanning electron microscope (SEM) can also be used to measure the continuity ratio.

[0050] [Manufacturing method for multilayer ceramic capacitors] Next, a method for manufacturing the multilayer ceramic capacitor 100 described above will be described. One embodiment of the present disclosure is a method for manufacturing a multilayer ceramic capacitor having an element body in which dielectric layers containing a perovskite compound represented by the general formula ABO3 and internal electrode layers are alternately stacked, and having an intermediate region between the dielectric layers and the internal electrode layers. The method may include a lamination step of alternately stacking unsintered dielectric materials that will become the dielectric layers and unsintered internal electrode materials that will become the internal electrode layers to obtain a laminate, and a firing step of firing the laminate. After the firing step, the internal electrode layers and the intermediate region each contain copper, and the relationship 1 / (0.55t+1.54)≦a≦3 is satisfied, where t (μm) is the thickness of the internal electrodes and a (atomic %) is the copper concentration in the internal electrode layers. FIG. 7 is a flowchart illustrating a method for manufacturing the multilayer ceramic capacitor 100 according to one embodiment.

[0051] (Unfired dielectric material preparation step (S1)) In the green dielectric material preparation step (S1), ceramic green sheets (green dielectric material) that will become the dielectric layers 11 when fired are prepared.

[0052] First, ceramic powder for forming the dielectric layer is prepared. The ceramic powder can be a powder of the ceramic material described above for the dielectric layer 11 of the multilayer ceramic capacitor 100. Therefore, the ceramic powder may contain powder of a perovskite-type compound represented by the general formula ABO3 described above, and preferably contains barium titanate. Barium titanate can generally be obtained by reacting a titanium source such as titanium dioxide with a barium source such as barium carbonate. Conventional methods, such as a solid-phase method, a sol-gel method, or a hydrothermal method, can be used to synthesize the ceramic powder that will be the ceramic material that will be the main component of the dielectric layer 11.

[0053] The ceramic powder for forming the dielectric layer may contain additives depending on the purpose. The ceramic powder for forming the dielectric layer is wet-mixed with or without additives, dried, and pulverized. The obtained powder for forming the dielectric layer is then wet-mixed with a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer to prepare a slurry for forming the dielectric layer. The obtained slurry for forming the dielectric layer is applied to a substrate such as a polyethylene terephthalate (PET) film by a die coater method, a doctor blade method, or the like, and dried to obtain a ceramic green sheet (unfired dielectric layer material).

[0054] (Unfired internal electrode material preparation process (S2)) In the green internal electrode material preparation step (S2), green internal electrode materials that will become the internal electrode layers 12, i.e., the first internal electrode layers 12a and the second internal electrode layers 12b, are prepared. The metal that is the main component of the green internal electrode material may be the same metal material as the materials described above for the internal electrode layers 12 of the multilayer ceramic capacitor 100, for example, base metals such as Ni and Sn, or alloys containing these. Furthermore, noble metals such as Pt, Pd, Ag, and Au, or alloys containing these, may also be used. In view of excellent electrical properties and cost reduction, the above metal material preferably contains Ni, and more preferably has Ni as the main component.

[0055] Cu is added to the metal material. Then, the metal material to which Cu has been added, an organic binder, and a solvent are kneaded to obtain a metal paste (unfired internal electrode material). Note that Cu may be added after preparing the metal paste from the metal material as the main component.

[0056] The amount of Cu in the unsintered internal electrode material can be adjusted to satisfy 1 / (0.55t+1.54)≦a≦3, where t (μm) is the thickness of the internal electrode layer 12 after the firing step (S5) and a (atomic %) is the Cu concentration in the internal electrode layer 12 after firing. By adjusting the amount of Cu to be added so that a≧1 / (0.55t+1.54), the interfacial resistance between the dielectric layer 11 and the internal electrode layer 12 can be increased, thereby achieving high insulation reliability over a long period of time, i.e., long life characteristics. Furthermore, by adjusting a≦3, a high continuity ratio and large capacitance can be maintained. In this way, according to this embodiment, a multilayer ceramic capacitor 100 having both excellent life characteristics and electrostatic characteristics can be manufactured.

[0057] Furthermore, in this embodiment, in the manufacturing process of the multilayer ceramic capacitor, the amount of Cu to be added can be adjusted based on the above formula which expresses the relationship between the thickness t (μm) of the internal electrode layer 12 and the concentration a (atomic %) of Cu in the internal electrode layer 12. Therefore, for example, even when manufacturing a multilayer ceramic capacitor with a new design in which the thickness t of the internal electrode layer 12 is changed, it is easy to adjust the amount of Cu to be added. As a result, even when manufacturing a multilayer ceramic capacitor with a new design, a highly reliable product can be obtained.

[0058] The amount of Cu in the unsintered internal electrode material is preferably adjusted so that 0.1≦t≦1.5 is satisfied in the multilayer ceramic capacitor 100 obtained after firing. The amount of Cu added is preferably adjusted so that a≧0.5 is satisfied in the multilayer ceramic capacitor 100 obtained after firing. Furthermore, the amount of Cu added is preferably adjusted so that 1≦b≦4.5 is satisfied in the multilayer ceramic capacitor 100 obtained after firing, where b is the copper concentration in the intermediate region 40 (atomic %).

[0059] Ceramic powder can also be added as a co-material to the metal paste (unsintered internal electrode material). The main component of the ceramic powder is not particularly limited, but it is preferably the same as the ceramic powder used in the unsintered dielectric material preparation step (S1). When ceramic powder is added as a co-material, it can be added when kneading the metal paste.

[0060] (Lamination process (S3)) In the lamination step (S3), the metal paste obtained in the unsintered internal electrode material preparation step (S2) is printed on the surface of the ceramic green sheet obtained in the unsintered dielectric material preparation step (S1) by screen printing, gravure printing, or the like. This allows the first internal electrode pattern to become the first internal electrode layer 12a and the second internal electrode pattern to become the second internal electrode layer 12b to be arranged on the surface of the ceramic green sheet. Note that the method for forming the internal electrode patterns is not limited to printing, and they can also be formed by plating, vacuum deposition, sputtering, CVD, or the like using a mask.

[0061] The ceramic green sheets on which the metal paste has been printed are stacked so that the internal electrode layers 12 are alternately drawn to a pair of external electrodes 20a, 20b arranged in the longitudinal direction (X-axis direction) of the dielectric layer 11. A known technique can be used for this stacking. For example, to form a side margin 16, which is the outer region in the Y-axis direction, in the capacitive section 14 on the side where the internal electrode layer 12 is not drawn, an unfired dielectric material can be placed in the peripheral region where the internal electrode pattern made of metal paste is not printed. Using ceramic green sheets on which the metal paste has been printed as a stacking unit, the number of stacked layers in a stacking unit can be 100 to 500.

[0062] Next, cover sheets, which are unsintered cover materials for forming cover layers, are laminated on the top and bottom of the laminate containing the ceramic green sheets and the internal electrode patterns, i.e., on both sides in the stacking direction (Z-axis direction), to obtain a laminate. The cover sheets may be formed primarily from ceramic powder using a method similar to that for forming the unsintered dielectric material for forming the dielectric layers. Alternatively, the cover sheets may be formed from the same material as the unsintered dielectric material for forming the dielectric layers. The number of cover sheets stacked on each side may be 2 to 10.

[0063] The resulting laminate is pressed in the stacking direction (Z-axis direction) to obtain a pressed body.

[0064] (Singulating process (S4)) Furthermore, the pressure-bonded body can be cut into individual pieces to a predetermined size by dicing with a dicer, laser cutting, etc. As the method for dividing, any existing technology can be used.

[0065] (Firing process (S5)) In the firing step (S5), the singulated laminate is fired. Firing is performed at a hydrogen concentration of 0.03 vol% to 1.0 vol%, preferably 0.05 vol% to 0.3 vol%. The other components of the reducing atmosphere besides hydrogen are nitrogen or argon. In the firing step (S5), Cu pre-added to the unsintered material segregates or diffuses at the interface, forming an intermediate region 40. According to this embodiment, the thickness of the internal electrode layer 12 after firing is t (μm) and the Cu concentration in the internal electrode layer 12 after firing is a (atomic %), such that 1 / (0.55t + 1.54)≦a≦3. Furthermore, the thickness t (mm) of the internal electrode layer 12 after firing may be preferably 0.1 μm to 1.5 μm, more preferably 0.3 μm to 1.0 μm.

[0066] The firing temperature in the firing step (S5) may be preferably 1000° C. or higher and 1350° C. or lower, more preferably 1150° C. or higher and 1300° C. or lower. The firing time in the firing step (S5) may be 30 minutes or higher and 2 hours or lower.

[0067] (External electrode formation process (S6)) In the external electrode forming step, the first external electrode 20a and the second external electrode 20b can be formed by plating etc. In this way, the multilayer ceramic capacitor 100 described above is completed. [Example]

[0068] The present disclosure will be described in more detail below based on examples.

[0069] <Measurement and evaluation> (internal electrode layer thickness) The produced multilayer ceramic capacitor was polished from the external electrode 20 side toward the center (i.e., along the X-axis direction) to the center in the X-axis direction to expose the YZ plane on which the dielectric layers 11 and the internal electrode layers 12 were laminated. The exposed YZ plane was imaged using a laser microscope, and about five layers each from the center, upper end, and lower end in the Z-axis direction, which is the lamination direction of the internal electrode layers, for a total of 15 internal electrode layers 12, were selected, and the thickness (μm) of the internal electrode layers 12 along the Z-axis direction was measured at positions 1 / 4, 1 / 2, and 3 / 4 of the width of each internal electrode layer, and the average value was taken as the thickness t (μm) of the internal electrode layers 12.

[0070] (Copper concentration) Similarly, the YZ plane of the fabricated multilayer ceramic capacitor was exposed. Near the center in the Z-axis direction, a line analysis was performed along the Z-axis direction using transmission electron microscopy and energy dispersive X-ray analysis (TEM-EDX) for a range from one internal electrode layer 12 to the dielectric layer 11 adjacent to that internal electrode layer 12. In the graph of the atomic concentration distribution of each element obtained by the line analysis, the range of the internal electrode layer 12 was defined as a region where the oxygen concentration was less than 5 atomic % and Ni was present as the main component, and the average Cu concentration was calculated, which was defined as the Cu (copper) concentration a (atomic %) in the internal electrode. In addition, in the graph of the atomic concentration distribution obtained by the line analysis, the maximum Cu concentration in a region corresponding to the intermediate region 40, which is a region where the oxygen concentration is 5 atomic % or more and Ti, among the main component elements of the dielectric layer 11, is 15 atomic % or less, was defined as the Cu (copper) concentration b (atomic %) in the intermediate region. The above Cu concentrations a and b are both Cu concentrations (atomic %) relative to all elements detected in the analysis, and are values ​​excluding background noise originating from the measuring device.

[0071] (Continuity rate) Similarly, the YZ plane of the fabricated multilayer ceramic capacitor was exposed. The exposed surface was used as the observation surface and photographed with a laser microscope. Five layers were selected from the center, top end, and bottom end in the Z-axis direction, which is the lamination direction of the internal electrode layers, for a total of 15 internal electrode layers. In the photographed image shown in FIG. 6, the lengths of the continuous, uninterrupted portions 91, 91, ... along the X-axis direction were measured one by one. For each internal electrode 12 (the first internal electrode layer 12a with 15 layers and the second internal electrode layer 12b with 15 layers), the lengths L1, L2, ..., Ln of the electrode portions 91, 91, ... were summed, and the sum was divided by the length L0 of the measurement region (i.e., (L1 + L2 + ..., + Ln) / L0), which was used as the continuity ratio (%) of each internal electrode layer 12. Furthermore, the average value was calculated and used as the continuity ratio (%) of the internal electrode layer 12.

[0072] (capacitance) The fabricated multilayer ceramic capacitor was left at 150°C for 1 hour, and then left under standard conditions (temperature 25°C, 1 atmosphere) for 24 hours, after which the capacitance (μF) was measured using an LCR meter (HP4284A manufactured by Keysight Technologies) under conditions of a voltage of 0.5 V and a frequency of 1 kHz.

[0073] (life characteristics) The life characteristics were evaluated by highly accelerated life testing (HALT). A voltage of 9.0 V was applied to each of the 20 multilayer ceramic capacitors fabricated, at 150°C, and the leakage current was measured over time. The time at which 50% of the samples had a leakage current of 2000 μA was recorded as the HALT 50% life value. Note that a HALT 50% life value of 1000 minutes or more was evaluated as good.

[0074] <Fabrication of multilayer ceramic capacitors> Example 1 A ceramic slurry was prepared by wet-mixing a ceramic powder made of barium titanate with polyvinyl butyral (PVB) resin, a solvent, a plasticizer, a sintering aid powder (a silicon compound), and additives such as rare earth elements. The ceramic slurry was then applied to a substrate film using a doctor blade to form a dielectric green sheet approximately 0.8 μm thick. Furthermore, copper (CuO) powder was added to nickel powder and mixed to prepare a mixed powder. Polyvinyl butyral (PVB) resin, a solvent, and a plasticizer were then added to the mixed powder and kneaded to obtain a metal paste (Cu-containing Ni paste) for forming internal electrode layers. The metal paste was then printed onto a dielectric green sheet to form an internal electrode layer pattern. Five hundred of these dielectric green sheets with the printed metal paste were stacked, and a dielectric green sheet serving as a cover layer was placed on each side of the stacking direction to form a laminate.

[0075] The resulting laminate was pressed and then cut to a predetermined size to obtain individual molded chips. The resulting molded chips were then debindered in an N2 atmosphere, and a metal paste was applied by dipping to form the base layer of the external electrodes. The molded chips were then placed in a firing furnace, and the temperature (firing temperature) was increased to 1200°C in an atmosphere with an H2 concentration of 0.1% by volume and an N2 concentration of 99.9%, and the chips were fired for 10 minutes. External electrodes were formed on the fired molded chips by plating, resulting in multilayer ceramic capacitors (MLCCs) measuring 1.0 mm x 0.5 mm x 0.5 mm. A multilayer ceramic capacitor was obtained.

[0076] For the obtained multilayer ceramic capacitor, the thickness t (μm) of the internal electrode layer, the Cu concentration (atomic %) in the internal electrode layer, and the Cu concentration (atomic %) in the intermediate region were measured as described above. The results are shown in Table 1.

[0077] (Examples 2 to 10, Comparative Examples 1 to 5) In the multilayer ceramic capacitor, that is, after firing, the thickness t (μm) of the internal electrode layer, the concentration a (atomic %) of Cu in the internal electrode layer, and the concentration b (atomic %) of Cu in the intermediate region were each changed to the values ​​shown in Table 1. Except for changing the amount of Cu added to the metal paste for forming the internal electrode layer and the thickness of the internal electrode layer pattern that becomes the internal electrode layer, a multilayer ceramic capacitor was produced in the same manner as in Example 1.

[0078] In Comparative Example 1, Cu was not added to the metal paste for forming the internal electrode layers, so Cu was not detected in the internal electrode layers or the intermediate region. In Comparative Example 2, Cu was added to the metal paste for forming the internal electrode layers, but Cu was not detected in the intermediate region.

[0079] The obtained multilayer ceramic capacitor was subjected to the above-described evaluations.

[0080] [Table 1]

[0081] As shown in Table 1, Examples 1 to 10, which satisfied 1 / (0.55t+1.54)≦a≦3, had high HALT life, continuity ratio, and capacitance. On the other hand, Comparative Example 1, in which neither the internal electrode layer nor the intermediate region contained Cu, Comparative Example 2, in which Cu was not detected in the intermediate region, and Comparative Examples 3 and 5, which did not satisfy 1 / (0.55t+1.54)≦a≦3, all had low HALT life. Furthermore, Comparative Example 4, which satisfied 1 / (0.55t+1.54)≦a≦3 but did not satisfy b≧1, had a high HALT life, but had low continuity ratio and capacitance, and was found to have insufficient electrostatic properties.

[0082] Although the embodiments have been described in detail above, the present disclosure is not limited to the above embodiments. Furthermore, the above embodiments can be subject to various changes, modifications, substitutions, additions, deletions, and combinations within the scope of the claims.

[0083] Aspects of the present disclosure are, for example, as follows.

[0084] <1> The device has an element body in which dielectric layers containing a perovskite compound represented by the general formula ABO3 and internal electrode layers are alternately stacked, an intermediate region between the dielectric layer and the internal electrode layer; the internal electrode layers and the intermediate region each contain copper; The thickness of the internal electrode layer is t (μm), and the concentration of copper in the internal electrode layer is a (atomic %). 1 / (0.55t+1.54)≦a≦3 Multilayer ceramic capacitors meet these requirements.

[0085] <2> Furthermore, 0.1≦t≦1.5 is satisfied. <1> The multilayer ceramic capacitor according to claim 1.

[0086] <3> Furthermore, a≧0.5 is satisfied. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0087] <4> Furthermore, the copper concentration in the intermediate region satisfies 1≦b≦4.5, where b (atomic %) is the copper concentration in the intermediate region. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0088] <5> Furthermore, when the copper concentration in the intermediate region is b (atomic %), b / (0.55t+1.54) satisfies 0.48 or more and less than 2.5. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0089] <6> The internal electrode layers contain nickel. <1> or <2> The multilayer ceramic capacitor according to claim 1.

[0090] <7> The perovskite compound represented by the general formula ABO3 contains barium titanate. <1> or <2> The multilayer ceramic capacitor according to claim 1. [Explanation of symbols]

[0091] 10 Base 10a First side 10b Second side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13 Cover Layer 14 Capacity part 15a First End Margin 15b Second End Margin 16 Side Margin 20a 1st external electrode 20b 2nd external electrode 91 Electrode section 100 Multilayer ceramic capacitors

Claims

1. General formula ABO ３ and internal electrode layers are alternately stacked, an intermediate region between the dielectric layer and the internal electrode layer; the internal electrode layers and the intermediate region each contain copper; The thickness of the internal electrode layer is t (μm), and the concentration of copper in the internal electrode layer is a (atomic %). 1 / (0.55t+1.54)≦a≦3 Multilayer ceramic capacitors meet these requirements.

2. 2. The multilayer ceramic capacitor according to claim 1, further satisfying 0.1≦t≦1.

5.

3. 3. The multilayer ceramic capacitor according to claim 1, further satisfying a≧0.

5.

4. 3. The multilayer ceramic capacitor according to claim 1, wherein the copper concentration in said intermediate region is b (atomic %), and the concentration satisfies 1≦b≦4.

5.

5. 3. The multilayer ceramic capacitor according to claim 1, wherein b / (0.55t+1.54) is equal to or greater than 0.48 and less than 2.5, where b is the copper concentration in the intermediate region (atomic %).

6. 3. The multilayer ceramic capacitor according to claim 1, wherein the internal electrode layers contain nickel.

7. The general formula ABO ３ 3. The multilayer ceramic capacitor according to claim 1, wherein the perovskite compound represented by the formula (I) contains barium titanate.

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