Multilayer ceramic capacitor

Abstract

To provide a multilayer ceramic capacitor achieving miniaturization and increased capacitance while maintaining a high level of high-temperature reliability.SOLUTION: A multilayer ceramic capacitor 1 includes an inner layer part comprising a plurality of internal layer dielectric layers 20i and a plurality of internal electrode layers 30 alternately laminated in a lamination direction T. A region A with low continuity of the internal electrode layers 30 is located at an edge of a width direction W of the internal electrode layer 30. The region A has lower line coverage than a central part of the internal electrode layer 30 in the width direction W.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor. [Background technology]

[0002] Conventionally, a multilayer ceramic capacitor comprises a laminate in which dielectric layers and internal electrode layers are alternately stacked, with dielectric layers further stacked on the top and bottom surfaces of the laminate, and a pair of external electrodes formed on both end surfaces of the laminate, and the internal electrode layer is formed by an opposing electrode portion that forms a capacitance and a lead electrode portion that extends from the opposing electrode portion toward the external electrode.

[0003] In recent years, with the advancement of electronics technology, technological developments have been underway to reduce the thickness of the dielectric layers and internal electrode layers as much as possible and increase the number of laminated dielectric layers and internal electrode layers in order to reduce the size and increase the capacitance of multilayer ceramic capacitors. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2001-237137 Summary of the Invention [Problem to be solved by the invention]

[0005] However, when dielectric layers and internal electrode layers are stacked and pressed in the stacking direction during manufacturing, pressure is likely to be applied to the edges of the internal electrode layers, which may cause damage to the thinner dielectric layers in this area. Such damage to the dielectric layers can cause shoot defects and lead to a decrease in high-temperature reliability. Even if the dielectric layers are not damaged, foreign matter can easily get mixed in near the edges of the internal electrode layers, making it difficult to maintain high reliability and causing short circuits.

[0006] An object of the present invention is to provide a multilayer ceramic capacitor that is small in size, has a large capacitance, and yet has high high-temperature reliability. [Means for solving the problem]

[0007] The inventors have found that high-temperature reliability can be improved by providing a region A where the continuity of the internal electrode layer is low at the end of the internal electrode layer in the width direction, and by making the line coverage of the region A lower than the line coverage of the center part of the internal electrode layer in the width direction, and have completed the present invention.

[0008] That is, the present invention provides a laminate including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction perpendicular to the stacking direction, and two end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes connected to the internal electrode layers on the two end surfaces; Equipped with At the end of the internal electrode layer in the width direction, there is a region A where the continuity of the internal electrode layer is low, The region A is a multilayer ceramic capacitor in which the line coverage of the internal electrode layers is lower than that of the central portion in the width direction. [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a multilayer ceramic capacitor that is highly reliable at high temperatures and that prevents short circuits due to damage to the dielectric layers at the widthwise ends of the internal electrode layers or the inclusion of foreign matter. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 1 is a perspective view showing a multilayer ceramic capacitor. [Figure 2] 2 is a cross-sectional view (LT cross section) taken along line II-II of the multilayer ceramic capacitor shown in FIG. [Figure 3]3 is a cross-sectional view (WT cross section) taken along line III-III of the multilayer ceramic capacitor shown in FIG. [Figure 4] 2 is a schematic diagram showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in FIG. [Figure 5] FIG. 4 is an enlarged view of an area V shown in FIG. DETAILED DESCRIPTION OF THE INVENTION

[0011] Hereinafter, embodiments of the multilayer ceramic capacitor of the present invention will be described, but the present invention is not limited thereto. Furthermore, the drawings may be drawn in a simplified and schematic manner to explain the contents of the invention, and the dimensional ratios of the depicted components or between the components may not match the dimensional ratios of those components described in the specification. Furthermore, components described in the specification may be omitted in the drawings, or the number of components may be omitted.

[0012] (multilayer ceramic capacitors) Fig. 1 is a perspective view showing a multilayer ceramic capacitor, Fig. 2 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line II-II, and Fig. 3 is a cross-sectional view of the multilayer ceramic capacitor shown in Fig. 1 taken along line III-III. Fig. 4 is a schematic view showing the structure of an inner layer portion of the multilayer ceramic capacitor shown in Fig. 1. Fig. 5 is an enlarged view of region V shown in Fig. 3. The multilayer ceramic capacitor 1 shown in Figs. 1 to 5 includes a laminate 10 and an external electrode 40. The external electrode 40 includes a first external electrode 41 and a second external electrode 42.

[0013] An XYZ Cartesian coordinate system is shown in Figures 1 to 3 and 5. The X direction is the length direction L of the multilayer ceramic capacitor 1 and the laminate 10, the Y direction is the width direction W of the multilayer ceramic capacitor 1 and the laminate 10, and the Z direction is the lamination direction T of the multilayer ceramic capacitor 1 and the laminate 10. Therefore, the cross section shown in Figure 2 is also called an LT cross section, and the cross section shown in Figure 3 is also called a WT cross section. The length direction L, width direction W, and stacking direction T do not necessarily have to be perpendicular to each other, and may intersect each other.

[0014] The size of the multilayer ceramic capacitor is preferably such that the length L is 0.2 mm to 10 mm, the width W is 0.1 mm to 10 mm, and the stacking direction T is 0.1 mm to 10 mm.

[0015] (Laminate) The laminate 10 has a substantially rectangular parallelepiped shape and has a first main surface TS1 and a second main surface TS2 that face each other in the stacking direction T, a first side surface WS1 and a second side surface WS2 that face each other in the width direction W, and a first end surface LS1 and a second end surface LS2 that face each other in the length direction L. The surface of each surface may be uneven or may be roughened. In addition, when there is no need to particularly distinguish between the first main surface TS1 and the second main surface TS2, they will be collectively referred to as the main surface TS; when there is no need to particularly distinguish between the first end surface LS1 and the second end surface LS2, they will be collectively referred to as the end surface LS; and when there is no need to particularly distinguish between the first side surface WS1 and the second side surface WS2, they will be collectively referred to as the side surface WS.

[0016] It is preferable to round the corners and ridges of the laminate 10. A corner is a portion where three faces of the laminate 10 intersect, and a ridge is a portion where two faces of the laminate 10 intersect.

[0017] 2 and 3, the laminate 10 has a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30 stacked in a stacking direction T. The laminate 10 also has, in the stacking direction T, an inner layer portion 100, and a first outer layer portion 201 and a second outer layer portion 202 arranged to sandwich the inner layer portion 100 therebetween.

[0018] The inner dielectric layer 20i constituting the inner layer portion 100 and the outer dielectric layer 20o constituting the outer layer portion 200 may have different component compositions because the inner layer portion 100 and the outer layer portion 200 are required to have different functions. For example, the inner dielectric layer 20i is required to have a high dielectric constant, and the outer dielectric layer 20o is required to have high moisture resistance, weather resistance, and strength. For this reason, the dielectric layer constituting the inner layer portion 100 will be described as the inner dielectric layer 20i, and the dielectric layer constituting the outer layer portion 200 will be described as the outer dielectric layer 20o, but when there is no need to particularly distinguish between the inner dielectric layer 20i and the outer dielectric layer 20o, they will be collectively described as the dielectric layer 20.

[0019] (inner layer) 4 shows a schematic diagram of the structure of the inner layer portion 100. The inner layer portion 100 includes a plurality of inner dielectric layers 20i and a plurality of internal electrode layers 30. In the inner layer portion 100, the plurality of internal electrode layers 30 are arranged facing each other with the inner dielectric layers 20i interposed therebetween. The inner layer portion 100 is a portion that generates electrostatic capacitance and essentially functions as a capacitor.

[0020] The material of the dielectric layer 20 may be a dielectric ceramic containing, for example, BaTiO3, CaTiO3, SrTiO3, or CaZrO3 as a main component. The material of the dielectric layer 20 may also contain, as a secondary component, a Mn compound, an Fe compound, a Cr compound, a Co compound, or a Ni compound.

[0021] The thickness of the inner dielectric layer 20i is not particularly limited, but is preferably, for example, 0.2 μm or more and 15 μm or less. By reducing the thickness of the inner dielectric layer 20i, the capacitance can be improved.

[0022] (outer layer) The first outer layer portion 201 is disposed on the first main surface TS1 side of the laminate 10, and the second outer layer portion 202 is disposed on the second main surface TS2 side of the laminate 10. More specifically, the first outer layer portion 201 is disposed between the first main surface TS1 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the first main surface TS1, and the second outer layer portion 202 is disposed between the second main surface TS2 and an internal electrode layer 30 of the plurality of internal electrode layers 30 that is closest to the second main surface TS2. The first outer layer portion 201 and the second outer layer portion 202 do not include an internal electrode layer 30.

[0023] The outer layer portion 200 is formed of an insulating material. The first outer layer portion 201 and the second outer layer portion 202 can each be composed of multiple outer dielectric layers 20o, or may be composed of a single outer dielectric layer 20o. The outer dielectric layer 20o can be composed of the same type of dielectric material as the inner dielectric layer 20i, or may contain a different component from the inner dielectric layer 20i depending on the desired function.

[0024] (Internal electrode layer) The multiple internal electrode layers 30 include multiple first internal electrode layers 31 and multiple second internal electrode layers 32. The multiple first internal electrode layers 31 and the multiple second internal electrode layers 32 are alternately arranged in the stacking direction T of the laminate 10.

[0025] The first internal electrode layer 31 includes a counter electrode portion 311 and a lead electrode portion 312 , and the second internal electrode layer 32 includes a counter electrode portion 321 and a lead electrode portion 322 .

[0026] The opposing electrode portion 311 and the opposing electrode portion 321 face each other via the inner dielectric layer 20i in the stacking direction T of the laminate 10. The shapes of the opposing electrode portion 311 and the opposing electrode portion 321 are not particularly limited and may be, for example, approximately rectangular. The opposing electrode portion 311 and the opposing electrode portion 321 are portions that generate electrostatic capacitance and essentially function as capacitors.

[0027] The lead electrode portion 312 extends from the counter electrode portion 311 toward the first end face LS1 of the laminate 10 and is exposed at the first end face LS1. The lead electrode portion 322 extends from the counter electrode portion 321 toward the second end face LS2 of the laminate 10 and is exposed at the second end face LS2. The lengths in the width direction W of the counter electrode portion 311 and the lead electrode portion 312 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed first end face LS1. The lengths in the width direction W of the counter electrode portion 321 and the lead electrode portion 322 may be the same or different. Furthermore, the lengths in the width direction W of these portions may gradually change toward the exposed second end face LS2.

[0028] As a result, the first internal electrode layer 31 is connected to the first external electrode 41, and a gap is provided between the first internal electrode layer 31 and the second end face LS2 of the laminate 10, i.e., the second external electrode 42. In addition, the second internal electrode layer 32 is connected to the second external electrode 42, and a gap is provided between the second internal electrode layer 32 and the first end face LS1 of the laminate 10, i.e., the first external electrode 41.

[0029] The first internal electrode layer 31 and the second internal electrode layer 32 contain metal Ni as a main component. The first internal electrode layer 31 and the second internal electrode layer 32 may contain at least one selected from metals such as Cu, Ag, Pd, Sn, or Au, or alloys containing at least one of these metals, such as Ag-Pd alloys, as a main component or a component other than the main component. Furthermore, the first internal electrode layer 31 and the second internal electrode layer 32 may contain, as a component other than the main component, particles of a dielectric material having the same composition as the ceramic contained in the inner dielectric layer 20i. In this specification, the term "main component metal" refers to the metal component with the highest weight percentage.

[0030] The thickness of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited, but is preferably 0.2 μm or more and 2.0 μm or less, and more preferably 0.30 μm or more and 0.35 μm or less. The number of the first internal electrode layer 31 and the second internal electrode layer 32 is not particularly limited.

[0031] The thicknesses of the inner dielectric layers 20i and the internal electrode layers 30 can be measured by, for example, observing the LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope. Each value may be an average value of measurements taken at multiple locations in the length direction, or may be an average value of measurements taken at multiple locations in the stacking direction.

[0032] As shown in FIG. 3 , the laminate 10 has, in the width direction W, an electrode facing portion W30 where the internal electrode layers 30 face each other, and a first side gap portion WG1 and a second side gap portion WG2 arranged to sandwich the electrode facing portion W30. The first side gap portion WG1 is located between the electrode facing portion W30 and the first side surface WS1, and the second side gap portion WG2 is located between the electrode facing portion W30 and the second side surface WS2. More specifically, the first side gap portion WG1 is located between the end of the internal electrode layer 30 on the first side surface WS1 side and the first side surface WS1, and the second side gap portion WG2 is located between the end of the internal electrode layer 30 on the second side surface WS2 side and the second side surface WS2. The first side gap portion WG1 and the second side gap portion WG2 do not include the internal electrode layer 30, but only include the dielectric layer 20. The first side gap portion WG1 and the second side gap portion WG2 are also called W gaps.

[0033] 2, the laminate 10 has, in the longitudinal direction L, an electrode facing portion L30 where the first internal electrode layer 31 and the second internal electrode layer 32 of the internal electrode layer 30 face each other, a first end gap LG1, and a second end gap LG2. The first end gap LG1 is located between the electrode facing portion L30 and the first end face LS1, and the second end gap LG2 is located between the electrode facing portion L30 and the second end face LS2. More specifically, the first end gap LG1 is located between the end of the second internal electrode layer 32 on the first end face LS1 side and the first end face LS1, and the second end gap LG2 is located between the end of the first internal electrode layer 31 on the second end face LS2 side and the second end face LS2. The first end gap LG1 does not include the second internal electrode layer 32 but includes the first internal electrode layer 31 and the inner dielectric layer 20i, while the second end gap LG2 does not include the first internal electrode layer 31 but includes the second internal electrode layer 32 and the inner dielectric layer 20i. The first end gap LG1 is a portion that functions as an extraction electrode portion to the first end face LS1 of the first internal electrode layer 31, and the second end gap LG2 is a portion that functions as an extraction electrode portion to the second end face LS2 of the second internal electrode layer 32. The first end gap LG1 and the second end gap LG2 are also referred to as L gaps.

[0034] The electrode opposing portion L30 is located with the opposing electrode portion 311 of the first internal electrode layer 31 and the opposing electrode portion 321 of the second internal electrode layer 32. The first end gap portion LG1 is located with the lead-out electrode portion 312 of the first internal electrode layer 31, and the second end gap portion LG2 is located with the lead-out electrode portion 322 of the second internal electrode layer 32.

[0035] The thickness of the laminate 10 may be measured, for example, by observing, with a scanning electron microscope, an LT cross section near the center in the width direction of the laminate exposed by polishing, or a WT cross section near the center in the length direction of the laminate exposed by polishing. Each value may also be an average of measurements taken at multiple locations in the length direction or width direction. Similarly, the length of the laminate 10 can be measured by, for example, observing the LT cross section near the center in the width direction of the laminate exposed by polishing with a scanning electron microscope. Each value may also be the average value of measurements taken at multiple locations in the stacking direction. Similarly, the width of the laminate 10 can be measured by, for example, observing a WT cross section of the laminate exposed by polishing near the center in the longitudinal direction with a scanning electron microscope. Each value may also be an average value of measurements taken at multiple locations in the stacking direction.

[0036] (external electrode) The external electrodes 40 include a first external electrode 41 and a second external electrode 42 .

[0037] The first external electrode 41 is disposed on a first end face LS1 of the laminate 10 and is connected to the first internal electrode layer 31. The first external electrode 41 may extend from the first end face LS1 to a portion of the first main face TS1 and a portion of the second main face TS2. The first external electrode 41 may also extend from the first end face LS1 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0038] The second external electrode 42 is disposed on the second end face LS2 of the laminate 10 and is connected to the second internal electrode layer 32. The second external electrode 42 may extend from the second end face LS2 to a portion of the first main face TS1 and a portion of the second main face TS2. The second external electrode 42 may also extend from the second end face LS2 to a portion of the first side face WS1 and a portion of the second side face WS2.

[0039] The first external electrode 41 has a base electrode layer 415 and a plating layer 416, and the second external electrode 42 has a base electrode layer 425 and a plating layer 426. The first external electrode 41 may be composed of only the plating layer 416, and the second external electrode 42 may be composed of only the plating layer 426.

[0040] The base electrode layer 415 and the base electrode layer 425 may be fired layers containing a metal and glass. The glass may include a glass component containing at least one selected from B, Si, Ba, Mg, Al, Li, etc. A specific example is borosilicate glass. The metal may include Cu as a main component. The metal may include at least one selected from metals such as Ni, Ag, Pd, or Au, or alloys such as Ag-Pd alloys, as a main component or as a component other than the main component.

[0041] The fired layer is a layer formed by applying a conductive paste containing metal and glass to the laminate by a dipping method and firing the layer. The fired layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The fired layer may also be a multi-layer structure.

[0042] Alternatively, the base electrode layer 415 and the base electrode layer 425 may be a resin layer containing conductive particles and a thermosetting resin. The resin layer may be formed on the fired layer described above, or may be formed directly on the laminate without forming a fired layer.

[0043] The resin layer is a layer formed by applying a conductive paste containing conductive particles and a thermosetting resin to the laminate by a coating method and then firing the layer. The resin layer may be fired after firing the internal electrode layer or simultaneously with firing the internal electrode layer. The resin layer may also be a multi-layered layer.

[0044] The thickness of each of the base electrode layer 415 and the base electrode layer 425 as the fired layer or resin layer is not particularly limited, and may be 2 μm or more and 220 μm or less.

[0045] Alternatively, the base electrode layer 415 and the base electrode layer 425 may be a thin film layer of 1 μm or less formed by a thin film forming method such as sputtering or vapor deposition, on which metal particles are deposited.

[0046] The plating layer 416 covers at least a portion of the base electrode layer 415, and the plating layer 426 covers at least a portion of the base electrode layer 425. The plating layer 416 and the plating layer 426 include at least one selected from, for example, metals such as Cu, Ni, Ag, Pd, and Au, and alloys such as Ag-Pd alloys.

[0047] The plating layer 416 and the plating layer 426 may each be formed of multiple layers. Preferably, they have a two-layer structure of Ni plating and Sn plating. The Ni plating layer can prevent the base electrode layer from being eroded by solder when mounting the ceramic electronic component, and the Sn plating layer improves the wettability of the solder when mounting the ceramic electronic component, facilitating mounting. The plating layer 416 and the plating layer 426 may each have a three-layer structure, for example, by stacking Cu plating, Ni plating, and Sn plating. The outermost layer may be Au plating.

[0048] The thickness of each of plating layer 416 and plating layer 426 is not particularly limited, and may be 1 μm or more and 10 μm or less.

[0049] (Area A) As shown in FIG. 5, the multilayer ceramic capacitor 1 according to the present invention has a region A at the end of the internal electrode layer 30 in the width direction W, where the continuity of the internal electrode layer 30 is low, and the region A has a lower line coverage than the central portion C of the internal electrode layer 30 in the width direction W.

[0050] Generally, to achieve miniaturization and increased capacitance of multilayer ceramic capacitors, the thicknesses of the dielectric layers and internal electrode layers are made as thin as possible and the number of laminated dielectric layers and internal electrode layers is increased. However, during manufacturing, when the dielectric layers and internal electrode layers are laminated and pressed in the lamination direction, the pressing pressure is likely to be applied to the edges of the internal electrode layers, which may cause damage to the dielectric layers in this vicinity. Such damage to the dielectric layers can cause shoot defects and lead to reduced high-temperature reliability. Furthermore, even if the dielectric layers are not damaged, foreign matter is likely to be mixed near the edges of the internal electrode layers, making short circuits more likely to occur and making it difficult to maintain high reliability.

[0051] The multilayer ceramic capacitor 1 according to the present invention has a region A where the continuity of the internal electrode layers 30 is low at the end portions of the internal electrode layers 30 in the width direction W, and by making the line coverage of the region A lower than the line coverage of the center portion C of the internal electrode layers 30 in the width direction W, it is possible to suppress the charging of electric charges to the internal electrode layers in the region A and reduce the influence of the electric field on the dielectric layers near the region A. As a result, even if the dielectric layers 20 are damaged or foreign matter is mixed in, the internal electrode layers 30 will not short-circuit, and high reliability can be achieved.

[0052] Region A includes internal electrode existing regions a1 and internal electrode dividing regions a2. The internal electrode existing regions a1 are regions where internal electrode layers exist, and the internal electrode dividing regions a2 are regions between two internal electrode existing regions a1 adjacent to each other in the width direction W.

[0053] The length of the internal electrode separating region a2 is preferably 3 μm or less. If the length of the internal electrode separating region a2 is greater than 10 μm, the line coverage in region A becomes too low, resulting in a decrease in the capacitance of the multilayer ceramic capacitor.

[0054] The length of the region A in the width direction W is preferably 5 μm or more and 20 μm or less. That is, in the WT cross section, the region A is preferably arranged with its length adjusted within a range from a length of 5 μm from an edge of the internal electrode layer 30 in the width direction W to a length of 20 μm from the edge.

[0055] By adjusting the length of the width direction W of region A within such a range, it is possible to reliably prevent the occurrence of short circuits caused by damage to the dielectric layer 20 or the inclusion of foreign matter, and to maintain even higher reliability. If the length of region A is less than 5 μm, it is not possible to fully obtain the effect of region A. On the other hand, if the length of region A exceeds 20 μm, the effective area of ​​the internal electrode layers 30 that form the capacitance of the multilayer ceramic capacitor decreases, resulting in a decrease in the capacitance of the multilayer ceramic capacitor.

[0056] The line coverage of region A is preferably 50% or less, and more preferably 30% to 40%. If the line coverage of region A is greater than 50%, the effect of region A cannot be fully exerted, and if damage to the dielectric layer 20 or intrusion of foreign matter occurs at the end of the internal electrode layer 30 in the width direction W, a short circuit or the like occurs, making it difficult to maintain high-temperature reliability. Furthermore, it is preferable that the difference between the line coverage in region A and the line coverage in central portion C is 30% points or more.

[0057] (Measurement of line coverage) The line coverage is an index showing the continuity of the conductive components that make up the internal electrode layers. The wire coverage is measured by observing the WT cross section of the multilayer ceramic capacitor where the internal electrode layers are exposed. In the width direction W of the inner layer portion 100, two regions, a region A and a central region C, are defined. In the two regions, the area of ​​the internal electrode layer when the internal electrode layer is assumed to be a sheet of uniform thickness is compared with the area occupied by the conductive components that constitute the actual internal electrode layer, and the ratio of the area occupied by the conductive components that constitute the actual internal electrode layer to the area of ​​the internal electrode layer when the internal electrode layer is assumed to be a sheet of uniform thickness is taken as the line coverage. Measurements are performed on multiple internal electrode layers, and the average value of the line coverages of multiple internal electrode layers calculated can be taken as the line coverage. The magnification of the SEM can be 1000x or more and 5000x or less, but 2000x is preferable. Measurement conditions such as accelerating voltage and magnification are fixed during measurement.

[0058] (Manufacturing of multilayer ceramic capacitors) Next, an example of a method for manufacturing a multilayer ceramic capacitor will be described.

[0059] First, ceramic green sheets for forming the dielectric layers and conductive paste for the internal electrode layers are prepared. The conductive paste for the internal electrode layers contains a binder and a solvent, and known organic binders and organic solvents can be used. The conductive paste for the internal electrodes forms the internal electrode layers.

[0060] Next, a conductive paste for internal electrodes is printed in a predetermined pattern on the ceramic green sheets by, for example, screen printing or gravure printing, thereby forming an internal electrode pattern. In order to form the region A, the internal electrode pattern is printed so that the thickness of the conductive paste is thin at positions corresponding to the ends of the internal electrode layer 30 in the width direction W.

[0061] Next, a predetermined number of ceramic green sheets for outer layers without internal electrode patterns are stacked, and then ceramic green sheets with internal electrodes formed thereon are stacked in order, and a predetermined number of ceramic green sheets for outer layers are stacked on top of those to produce a laminate sheet. The ceramic green sheets form the dielectric layers 20 that constitute the multilayer ceramic capacitor 1.

[0062] The resulting laminated sheet is pressed in the lamination direction using a means such as a hydrostatic press to produce a laminated block. The laminated block is then cut to a predetermined size to produce laminated chips. At this time, the corners and ridges of the laminated chips may be rounded by barrel polishing or the like.

[0063] The laminated chip is then fired to produce the laminate 10. The firing temperature at this time depends on the materials of the dielectric and internal electrodes, but is preferably 900°C or higher and 1300°C or lower.

[0064] Next, the first end surface LS1 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the base electrode layer 415 to the first end surface LS1. Similarly, the second end surface LS2 of the laminate 10 is immersed in a conductive paste, which is an electrode material for the base electrode layer, using a dipping method, to apply the conductive paste for the base electrode layer 425 to the second end surface LS2. These conductive pastes are then fired to form the fired layers, the base electrode layer 415 and the base electrode layer 425. The firing temperature is preferably 600°C or higher and 900°C or lower.

[0065] As described above, the base electrode layer 415 and the base electrode layer 425, which are resin layers, may be formed by applying a conductive paste containing conductive particles and a thermosetting resin by a coating method and baking the applied paste, or the base electrode layer 415 and the base electrode layer 425, which are thin films, may be formed by a thin film formation method such as a sputtering method or a vapor deposition method.

[0066] Thereafter, a plating layer 416 is formed on the surface of the base electrode layer 415 to form the first external electrode 41, and a plating layer 426 is formed on the surface of the base electrode layer 425 to form the second external electrode 42. Through the above steps, the multilayer ceramic capacitor 1 is obtained. [Example]

[0067] Various evaluation tests were conducted on the multilayer ceramic capacitor.

[0068] (sample) Dimensions: 3.15mm (length) x 1.65mm (width) x 1.65mm (layering direction) Ceramic material: BaTiO3 ·Capacity: 10μF ·Internal electrode: Ni

[0069] (Evaluation of high temperature reliability) As an evaluation test for high temperature reliability, HALT (Highly Accelerated Limit Test) was performed under the following conditions. Conditions: Temperature 150°C, voltage 150V, 100 hours

[0070] The evaluation criteria were as follows: after the test, a LogIR value of 10 to the power of 10 or more was rated as ◯ (pass); a LogIR value of 10 to the power of 9 or more but less than 10 to the power of 10 was rated as △ (acceptable pass); and a LogIR value of less than 10 to the power of 9 was rated as × (fail).

[0071] (Capacitance evaluation) As an evaluation test of the capacitance, measurements were made using an LCR meter under the following conditions. Conditions: 1kHz, 1V

[0072] The evaluation criteria were as follows: the reference value of capacitance was 10 μF, and values ​​within ±5% of the reference value were rated as ◯ (pass); values ​​outside the ±5% range but within ±15% were rated as △ (acceptable pass); and values ​​outside the ±15% range were rated × (fail).

[0073] [Table 1]

[0074] As shown in Table 1, Examples 1 to 5, which have region A with lower line coverage than the center of the width direction W of the internal electrode layer 30, showed good results. Among them, Examples 1 to 3, in which region A was arranged within a range of 5 μm to 20 μm from the edge of the width direction W of the internal electrode layer 30, were confirmed to have particularly good results in the overall evaluation. It was also confirmed that good results were obtained when the line coverage of region A was 50% or less. For example, it is preferable that the length of region A in the width direction W is 5 μm to 20 μm and the coverage of region A is 50% or less. More preferably, the length of region A in the width direction W is 5 μm to 20 μm and the coverage of region A is 30% to 40%. Furthermore, it is also possible that the length of region A in the width direction W is 5 μm to 20 μm and the coverage of region A is 30 percentage points or more lower than the coverage of the center. This allows high high-temperature reliability to be obtained while maintaining capacity.

[0075] Although the embodiments of the present invention have been described above, the present invention is not limited to the embodiments, and can be embodied in various forms without departing from the gist of the present invention. [Explanation of symbols]

[0076] 1. Multilayer ceramic capacitors 10 Laminate 20 dielectric layer 30 Internal electrode layer 31 First internal electrode layer 311 Counter electrode section 312 Extraction electrode section 32 Second internal electrode layer 321 Counter electrode section 322 Extraction electrode section 40 External electrode 41 First external electrode 415 Base electrode layer 416 plating layer 42 Second external electrode 425 Base electrode layer 426 plating layer 100 Inner layer 200 Outer layer 201 First Outer Layer 202 Second Outer Layer L30 Electrode facing part LG1 First end gap LG2 Second end gap W30 Electrode facing part WG1 First side gap WG2 Second side gap L lengthwise T Stacking direction W width direction LS end face LS1 First end face LS2 Second end face TS main surface TS1 First principal surface TS2 Second principal surface WS side WS1 First Aspect WS2 Second Aspect

Claims

1. a laminate including an inner layer portion including a plurality of inner dielectric layers and a plurality of internal electrode layers alternately stacked in a stacking direction, and outer layer portions sandwiching the inner layer portion from the stacking direction, the laminate having two main surfaces opposing each other in the stacking direction, two side surfaces opposing each other in a width direction perpendicular to the stacking direction, and two end surfaces opposing each other in a length direction perpendicular to the stacking direction and the width direction; a pair of external electrodes connected to the internal electrode layers on the two end surfaces; Equipped with At the end portions in the width direction of the internal electrode layers, there are regions A where the continuity of the internal electrode layers is low, The multilayer ceramic capacitor has a lower line coverage in the region A than in the central portion of the internal electrode layer in the width direction.

2. 2. The multilayer ceramic capacitor according to claim 1, wherein the region A has a length in the width direction of 5 μm or more and 20 μm or less.

3. 3. The multilayer ceramic capacitor according to claim 1, wherein the line coverage of the region A is 50% or less.

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