Semiconductor device and operation test method of semiconductor device

Abstract

To perform an operation test for a multichip using a single semiconductor chip which is still on wafer for a semiconductor package including a plurality of semiconductor chips.SOLUTION: A semiconductor device 10 comprises a first semiconductor chip 20 and a second semiconductor chip 30. The first semiconductor chip 20 includes a logic circuit 24, an I / O 21 connected to the logic circuit 24, an MUX 22 with an output terminal Y connected to the I / O 21 and an input terminal B opened, and a test circuit 23 connected to an input terminal A of the MUX 22. The test circuit 23 outputs a specified value used for controlling "output enable" of the I / O 21 to the MUX 22. The MUX 22 outputs a control signal for controlling "output enable" of the I / O 21 according to the specified value. The I / O 21 outputs 0 or 1 to the logic circuit 24 according to the control signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for testing the operation of the semiconductor device. [Background technology]

[0002] Conventionally, in a semiconductor package including a plurality of semiconductor chips, in addition to testing each chip individually, that is, in the wafer state, it has been essential to test the final multi-chip made up of a plurality of semiconductor chips.

[0003] For example, Patent Document 1 describes an electronic circuit device capable of performing an operation test on semiconductor chips. This electronic circuit device is configured such that a test circuit is provided inside a semiconductor package containing multiple semiconductor chips to perform an operation test on the semiconductor chips, and the operation test is performed in scan mode using the test circuit. This operation test is performed on each chip individually before connecting the multiple semiconductor chips with bumps, and on a multi-chip basis after connecting the multiple semiconductor chips with bumps. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-317352 Summary of the Invention [Problem to be solved by the invention]

[0005] In the technology described in Patent Document 1, a multi-chip operational test cannot be performed unless multiple semiconductor chips are connected by bumps. In this case, even if an abnormal semiconductor chip is detected as a result of the operational test, the entire multi-chip may have to be discarded. For this reason, it is desirable to be able to perform a multi-chip operational test on individual semiconductor chips in a wafer state.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a semiconductor device and an operation test method for a semiconductor device that can perform a multi-chip operation test on a single semiconductor chip in a wafer state in a semiconductor package including multiple semiconductor chips. [Means for solving the problem]

[0007] In order to solve the above problem, a semiconductor device according to the present invention comprises a plurality of semiconductor chips, at least one of which includes a semiconductor integrated circuit, at least one input / output unit connected to the semiconductor integrated circuit, at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal of which is connected to the input / output unit, one of the plurality of input terminals being open, and a test circuit to which the other of the plurality of input terminals is connected, wherein the test circuit outputs a predetermined value used to control an output enable of the input / output unit to the multiplexing unit, the multiplexing unit outputs a control signal for controlling the output enable of the input / output unit in accordance with the predetermined value, and the input / output unit outputs 0 or 1 to the semiconductor integrated circuit in accordance with the control signal.

[0008] A semiconductor device according to the present invention comprises a plurality of semiconductor chips, at least one of which includes a semiconductor integrated circuit, at least one input / output unit, a plurality of input terminals and one output terminal, the output terminal being connected to the semiconductor integrated circuit, at least one multiplexing unit having one of the plurality of input terminals connected to the input / output unit, and a test circuit having the other of the plurality of input terminals connected thereto, wherein the input / output unit outputs a first value to be used in an operation test of the plurality of semiconductor chips to the multiplexing unit, the test circuit outputs a second value to be used in an operation test of the plurality of semiconductor chips to the multiplexing unit, and the multiplexing unit outputs a control signal obtained by multiplexing the first value and the second value to the semiconductor integrated circuit.

[0009] A method for testing the operation of a semiconductor device according to the present invention is a method for testing the operation of a semiconductor device comprising a plurality of semiconductor chips, at least one of which includes a semiconductor integrated circuit, at least one input / output unit connected to the semiconductor integrated circuit, at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal of which is connected to the input / output unit, one of the plurality of input terminals being open, and a test circuit to which the other of the plurality of input terminals is connected, wherein the test circuit outputs a predetermined value to the multiplexing unit to be used for controlling the output enable of the input / output unit, the multiplexing unit outputs a control signal for controlling the output enable of the input / output unit in accordance with the predetermined value, and the input / output unit outputs 0 or 1 to the semiconductor integrated circuit in accordance with the control signal.

[0010] A method for testing the operation of a semiconductor device according to the present invention is a method for testing the operation of a semiconductor device comprising a plurality of semiconductor chips, at least one of which includes a semiconductor integrated circuit, at least one input / output unit, a plurality of input terminals and one output terminal, the output terminal being connected to the semiconductor integrated circuit, at least one multiplexing unit having one of the plurality of input terminals connected to the input / output unit, and a test circuit having the other of the plurality of input terminals connected, wherein the input / output unit outputs a first value to be used in an operation test of the plurality of semiconductor chips to the multiplexing unit, the test circuit outputs a second value to be used in an operation test of the plurality of semiconductor chips to the multiplexing unit, and the multiplexing unit outputs a control signal obtained by multiplexing the first value and the second value to the semiconductor integrated circuit. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a block diagram showing an example of the configuration of a semiconductor device according to a first embodiment. [Figure 2] 4 is a flowchart showing an example of the flow of a method for testing the operation of a semiconductor device according to the first embodiment. [Figure 3]FIG. 10 is a block diagram showing an example of the configuration of a semiconductor device according to a second embodiment. [Figure 4] FIG. 10 is a block diagram showing an example of the configuration of a semiconductor device according to a third embodiment. [Figure 5] 10 is a flowchart showing an example of the flow of a method for testing the operation of a semiconductor device according to a third embodiment. [Figure 6] FIG. 10 is a block diagram showing an example of the configuration of a semiconductor device according to a fourth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0012] An example of an embodiment of the technology of the present invention will be described in detail below with reference to the drawings. Note that components and processes that perform the same operations, actions, and functions are given the same reference numerals throughout the drawings, and duplicated descriptions may be omitted as appropriate. Each drawing is merely a schematic illustration to allow a sufficient understanding of the technology of the present invention. Therefore, the technology of the present invention is not limited to the illustrated examples. Furthermore, in this embodiment, descriptions of configurations that are not directly related to the present invention or well-known configurations may be omitted.

[0013] [First embodiment] FIG. 1 is a block diagram showing an example of the configuration of a semiconductor device 10 according to the first embodiment.

[0014] As shown in Fig. 1, the semiconductor device 10 according to this embodiment includes a first semiconductor chip 20 and a second semiconductor chip 30. The semiconductor device 10 may include multiple semiconductor chips and is not limited to two. Each of the first semiconductor chip 20 and the second semiconductor chip 30 is also called a die, and the semiconductor device 10 is also called a multi-die. The first semiconductor chip 20 and the second semiconductor chip 30 are not connected to each other.

[0015] The first semiconductor chip 20 includes a plurality (N) of I / O (Input / Output) 21, a plurality (N) of MUX (Multiplexer) 22, a test circuit 23, and a logic circuit 24. The I / O 21 is an example of an input / output unit, the MUX 22 is an example of a multiplexing unit, and the logic circuit 24 is an example of a semiconductor integrated circuit. Note that there may be only one of each of the I / O 21 and the MUX 22. The I / O 21 is an IO port for DtoW (Die to Wafer).

[0016] The I / O 21 is connected to the logic circuit 24. The MUX 22 has a plurality of input terminals A and B and one output terminal Y. The output terminal Y of the MUX 22 is connected to the I / O 21, and one input terminal B of the plurality of input terminals A and B is open. The other input terminal A of the plurality of input terminals A and B is connected to the test circuit 23.

[0017] The test circuit 23 outputs a predetermined value to the MUX 22. The "predetermined value" here is a value used to control the output enable of the I / O 21 in order to perform a multi-chip operation test. The MUX 22 outputs a control signal for controlling the output enable of the I / O 21 in accordance with the predetermined value from the test circuit 23. The I / O 21 outputs "1" to the logic circuit 24 in accordance with the control signal from the MUX 22. Note that although "1" is output from the I / O 21 in the example of FIG. 1, "0" may also be output.

[0018] On the other hand, the second semiconductor chip 30 has a plurality (N) of I / Os 31. The I / Os 31 are IO ports for DtoW. Note that, like the first semiconductor chip 20, the second semiconductor chip 30 may also be provided with a semiconductor integrated circuit, a multiplexing unit, and a test circuit.

[0019] 1, the configuration is such that the output enable of I / O 21 can be controlled from test circuit 23. In other words, even if first semiconductor chip 20 is not connected to second semiconductor chip 30, by controlling the output enable of I / O 21 from test circuit 23, I / O 21 of first semiconductor chip 20 can output "1" to logic circuit 24, and an operation test of first semiconductor chip 20 can be performed with all "1" as the expected value.

[0020] Next, the operation of the semiconductor device 10 according to the first embodiment will be described with reference to FIG.

[0021] FIG. 2 is a flowchart showing an example of the flow of the operation test method for the semiconductor device 10 according to the first embodiment.

[0022] 2, the test circuit 23 outputs a predetermined value to the MUX 22. As described above, this predetermined value is used to control the output enable of the I / O 21 in order to perform a multi-chip operation test.

[0023] In step S102, the MUX 22 outputs a control signal for controlling the output enable of the I / O 21 in accordance with a predetermined value from the test circuit 23.

[0024] In step S103, the I / O 21 outputs "1" to the logic circuit 24 in response to the control signal from the MUX 22. Although the I / O 21 outputs "1" in the example of FIG. 1, it may instead output "0."

[0025] Also, a circuit combining other cells such as AND and NAND may be used instead of MUX 22. Also, MUX 22 and test circuit 23 may be provided on the second semiconductor chip 30, or MUX 22 and test circuit 23 may be provided on both the first semiconductor chip 20 and the second semiconductor chip 30.

[0026] In the semiconductor device 10 according to this embodiment, the MUX 22 is provided between the I / O 21 and the test circuit 23, so that no delay is added to the operation path from the I / O 21 to the logic circuit 24. Furthermore, even if the MUX 22 fails, the system can operate normally.

[0027] According to this embodiment, in a semiconductor package including multiple semiconductor chips, multi-chip operation tests can be performed on individual semiconductor chips in a wafer state. Furthermore, since abnormal semiconductor chips can be removed in advance before connecting the multiple semiconductor chips, it is not necessary to discard the entire multi-chip.

[0028] [Second embodiment] In the first embodiment, a configuration in which a logic circuit is used as an example of a semiconductor integrated circuit is described, but in the second embodiment, a configuration in which an analog circuit is used as a semiconductor integrated circuit is described.

[0029] FIG. 3 is a block diagram showing an example of the configuration of a semiconductor device 10A according to the second embodiment.

[0030] As shown in FIG. 3, the semiconductor device 10A according to this embodiment includes a first semiconductor chip 20 and a second semiconductor chip 30. As described above, the first semiconductor chip 20 and the second semiconductor chip 30 are not connected to each other. The first semiconductor chip 20 includes a plurality of I / Os 21, a plurality of MUXes 22, a test circuit 23, and an analog circuit 25. The analog circuit 25 is an example of a semiconductor integrated circuit. In the semiconductor device 10A shown in FIG. 3, the components other than the analog circuit 25 are the same as those of the semiconductor device 10 shown in FIG. 1, and therefore repeated description thereof will be omitted.

[0031] The second semiconductor chip 30 includes, for example, a memory element for trimming the analog circuit 25. Even in a configuration in which the analog circuit 25 of the first semiconductor chip 20 is trimmed by a memory element for trimming mounted on the second semiconductor chip 30 after the semiconductor device 10A is assembled, any value can be input from the test circuit 23 to the analog circuit 25 of the first semiconductor chip 20. This makes it possible to, for example, evaluate the trimming of the analog circuit 25 and test the operation path from the I / O 21 to the analog circuit 25.

[0032] In the semiconductor device 10A according to this embodiment, the MUX 22 is also provided between the I / O 21 and the test circuit 23, so that no delay is added to the operation path from the I / O 21 to the analog circuit 25. Furthermore, even if the MUX 22 fails, the system can still operate normally.

[0033] As described above, according to this embodiment, even when applied to an analog circuit, in a semiconductor package including multiple semiconductor chips, a multi-chip operation test can be performed on each semiconductor chip in a wafer state. Furthermore, since abnormal semiconductor chips can be removed in advance before connecting multiple semiconductor chips, it is not necessary to discard the entire multi-chip.

[0034] [Third embodiment] In the third embodiment, a configuration will be described in which a MUX is provided between an I / O and a logic circuit included in a first semiconductor chip.

[0035] FIG. 4 is a block diagram showing an example of the configuration of a semiconductor device 10B according to the third embodiment.

[0036] 4, the semiconductor device 10B according to this embodiment includes a first semiconductor chip 20 and a second semiconductor chip 30. As described above, the first semiconductor chip 20 and the second semiconductor chip 30 are not connected to each other. The first semiconductor chip 20 includes a plurality of I / Os 21, a plurality of MUXes 22, a test circuit 23, and a logic circuit 24. The logic circuit 24 is an example of a semiconductor integrated circuit.

[0037] The MUX 22 has a plurality of input terminals A and B and one output terminal Y. The output terminal Y of the MUX 22 is connected to the logic circuit 24, and one input terminal A of the plurality of input terminals A and B is connected to the I / O 21. The other input terminal B of the plurality of input terminals A and B is connected to the test circuit 23.

[0038] The I / O 21 outputs a first value to the MUX 22. The test circuit 23 outputs a second value to the MUX 22. The second value is a value that is preset in the test circuit 23. Both the first value and the second value are values ​​used in a multi-chip operation test to perform an operation test on a multi-chip (i.e., a plurality of semiconductor chips). The MUX 22 outputs a control signal in which the first value and the second value are multiplexed to the logic circuit 24.

[0039] In other words, even if the first semiconductor chip 20 and the second semiconductor chip 30 are not connected, by presetting the second value required for the multi-chip operation test in the test circuit 23, it is possible to perform the multi-chip operation test using the first semiconductor chip 20 alone.

[0040] Next, the operation of the semiconductor device 10B according to the third embodiment will be described with reference to FIG.

[0041] FIG. 5 is a flowchart showing an example of the flow of a method for testing the operation of the semiconductor device 10B according to the third embodiment.

[0042] In step S111 of FIG. 5, the I / O 21 outputs to the MUX 22 a first value used in a multi-chip operation test.

[0043] In step S112, the test circuit 23 outputs a second value used in a multi-chip operation test to the MUX 22. Note that the order of steps S111 and S112 may be reversed.

[0044] In step S113, the MUX 22 outputs to the logic circuit 24 a control signal obtained by multiplexing the first value and the second value.

[0045] As described above, according to this embodiment, in a semiconductor package including multiple semiconductor chips, a multi-chip operation test can be performed on each semiconductor chip in a wafer state, as in the first and second embodiments. Furthermore, since abnormal semiconductor chips can be removed in advance before connecting multiple semiconductor chips, it is not necessary to discard the entire multi-chip.

[0046] [Fourth embodiment] In the third embodiment, a configuration in which a logic circuit is used as an example of a semiconductor integrated circuit is described, but in the fourth embodiment, a configuration in which an analog circuit is used as a semiconductor integrated circuit is described.

[0047] FIG. 6 is a block diagram showing an example of the configuration of a semiconductor device 10C according to the fourth embodiment.

[0048] As shown in FIG. 6, a semiconductor device 10C according to this embodiment includes a first semiconductor chip 20 and a second semiconductor chip 30. As described above, the first semiconductor chip 20 and the second semiconductor chip 30 are not connected to each other. The first semiconductor chip 20 includes a plurality of I / Os 21, a plurality of MUXes 22, a test circuit 23, and an analog circuit 25. The analog circuit 25 is an example of a semiconductor integrated circuit. In the semiconductor device 10C shown in FIG. 6, the components other than the analog circuit 25 are the same as those of the semiconductor device 10B shown in FIG. 4, and therefore, repeated description thereof will be omitted.

[0049] The second semiconductor chip 30 includes, for example, a memory element for trimming the analog circuit 25. Even in a configuration in which the analog circuit 25 of the first semiconductor chip 20 is trimmed by a memory element for trimming mounted on the second semiconductor chip 30 after the semiconductor device 10C is assembled, any value can be input from the test circuit 23 to the analog circuit 25 of the first semiconductor chip 20. This makes it possible to, for example, evaluate the trimming of the analog circuit 25 and test the operation path from the I / O 21 to the analog circuit 25.

[0050] As described above, according to this embodiment, even when applied to an analog circuit, in a semiconductor package including multiple semiconductor chips, a multi-chip operation test can be performed on each semiconductor chip in a wafer state. Furthermore, since abnormal semiconductor chips can be removed in advance before connecting multiple semiconductor chips, it is not necessary to discard the entire multi-chip.

[0051] As described above, according to each of the above embodiments, in a semiconductor package including a plurality of semiconductor chips, a multi-chip operation test can be performed on each semiconductor chip in a wafer state.

[0052] It should be noted that the configurations of the semiconductor device and the semiconductor device operation test method described in the above embodiments are merely examples, and it goes without saying that the configurations may be changed within the scope of the embodiments without departing from the spirit of the embodiments.

[0053] The following additional notes are provided regarding the above-described embodiments.

[0054] (Appendix 1) A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit connected to the semiconductor integrated circuit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the input / output unit, and one of the plurality of input terminals being open; a test circuit to which the other of the plurality of input terminals is connected; Including, the test circuit outputs a predetermined value used to control output enable of the input / output unit to the multiplexing unit; the multiplexing unit outputs a control signal for controlling an output enable of the input / output unit in accordance with the predetermined value; the input / output unit outputs 0 or 1 to the semiconductor integrated circuit in response to the control signal; Semiconductor device. (Appendix 2) A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the semiconductor integrated circuit, and one of the plurality of input terminals being connected to the input / output unit; a test circuit to which the other of the plurality of input terminals is connected; Including, the input / output unit outputs a first value used in an operation test of the plurality of semiconductor chips to the multiplexing unit; the test circuit outputs a second value used in an operation test on the plurality of semiconductor chips to the multiplexing unit; the multiplexing unit outputs a control signal obtained by multiplexing the first value and the second value to the semiconductor integrated circuit. Semiconductor device. (Appendix 3) the semiconductor integrated circuit is a logic circuit, 10. The semiconductor device according to claim 1 or 2. (Appendix 4) the semiconductor integrated circuit is an analog circuit; 10. The semiconductor device according to claim 1 or 2. (Appendix 5) The plurality of semiconductor chips are not connected to each other. 5. The semiconductor device according to claim 1. (Appendix 6) A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit connected to the semiconductor integrated circuit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the input / output unit, and one of the plurality of input terminals being open; a test circuit to which the other of the plurality of input terminals is connected; Including, A method for testing an operation of a semiconductor device, comprising: the test circuit outputs a predetermined value used to control output enable of the input / output unit to the multiplexing unit; the multiplexing unit outputs a control signal for controlling an output enable of the input / output unit in accordance with the predetermined value; the input / output unit outputs 0 or 1 to the semiconductor integrated circuit in response to the control signal; A method for testing the operation of a semiconductor device. (Appendix 7) A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the semiconductor integrated circuit, and one of the plurality of input terminals being connected to the input / output unit; a test circuit to which the other of the plurality of input terminals is connected; Including, A method for testing an operation of a semiconductor device, comprising: the input / output unit outputs a first value to be used in an operation test on the plurality of semiconductor chips to the multiplexing unit; the test circuit outputs a second value used for an operation test on the plurality of semiconductor chips to the multiplexing unit; the multiplexing unit outputs a control signal obtained by multiplexing the first value and the second value to the semiconductor integrated circuit. A method for testing the operation of a semiconductor device. [Explanation of symbols]

[0055] 10, 10A-10C Semiconductor device 20 First semiconductor chip 30 Second semiconductor chip 21,31 I / O 22 MUX 23 Test Circuit 24 Logic Circuits 25 Analog Circuits

Claims

1. A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit connected to the semiconductor integrated circuit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the input / output unit, and one of the plurality of input terminals being open; a test circuit to which the other of the plurality of input terminals is connected; Including, the test circuit outputs a predetermined value used to control output enable of the input / output unit to the multiplexing unit; the multiplexing unit outputs a control signal for controlling an output enable of the input / output unit in accordance with the predetermined value; the input / output unit outputs 0 or 1 to the semiconductor integrated circuit in response to the control signal; Semiconductor device.

2. A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the semiconductor integrated circuit, and one of the plurality of input terminals being connected to the input / output unit; a test circuit to which the other of the plurality of input terminals is connected; Including, the input / output unit outputs a first value used in an operation test of the plurality of semiconductor chips to the multiplexing unit; the test circuit outputs a second value used in an operation test on the plurality of semiconductor chips to the multiplexing unit; the multiplexing unit outputs a control signal obtained by multiplexing the first value and the second value to the semiconductor integrated circuit. Semiconductor device.

3. the semiconductor integrated circuit is a logic circuit, 3. The semiconductor device according to claim 1.

4. the semiconductor integrated circuit is an analog circuit; 3. The semiconductor device according to claim 1.

5. The plurality of semiconductor chips are not connected to each other.

3. The semiconductor device according to claim 1.

6. A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit connected to the semiconductor integrated circuit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the input / output unit, and one of the plurality of input terminals being open; a test circuit to which the other of the plurality of input terminals is connected; Including, A method for testing an operation of a semiconductor device, comprising: the test circuit outputs a predetermined value used to control output enable of the input / output unit to the multiplexing unit; the multiplexing unit outputs a control signal for controlling an output enable of the input / output unit in accordance with the predetermined value; the input / output unit outputs 0 or 1 to the semiconductor integrated circuit in response to the control signal; A method for testing the operation of a semiconductor device.

7. A plurality of semiconductor chips are provided, At least one of the plurality of semiconductor chips a semiconductor integrated circuit; at least one input / output unit; at least one multiplexing unit having a plurality of input terminals and one output terminal, the output terminal being connected to the semiconductor integrated circuit, and one of the plurality of input terminals being connected to the input / output unit; a test circuit to which the other of the plurality of input terminals is connected; Including, A method for testing an operation of a semiconductor device, comprising: the input / output unit outputs a first value to be used in an operation test on the plurality of semiconductor chips to the multiplexing unit; the test circuit outputs a second value used for an operation test on the plurality of semiconductor chips to the multiplexing unit; the multiplexing unit outputs a control signal obtained by multiplexing the first value and the second value to the semiconductor integrated circuit; A method for testing the operation of a semiconductor device.

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