Method for manufacturing nitride semiconductor laminate, and nitride semiconductor laminate

Abstract

To provide a method for manufacturing a nitride semiconductor laminate having high electrical properties, and the nitride semiconductor laminate.SOLUTION: A method for manufacturing a nitride semiconductor laminate comprises the steps of: forming a ground layer formed of AlxGa(1-x)N (0.5≤x≤1) using an organic metal vapor phase deposition method in the environment of a temperature of 600°C or more and 1000°C or less and a pressure of 50 mbar or more and 500 mbar or less on an Al containing nitride semiconductor substrate; and forming a GaN layer in the environment of a temperature of 600°C or more and 900°C or less on the ground layer. Thereby, a step ST served as a step part and a flat terrace TE are repeated in the miss cut direction of the substrate on the surface of the nitride semiconductor substrate; a terrace end ETE served as the end part of the terrace TE has an amplitude in the miss cut direction of the nitride semiconductor substrate; and a wave-shaped step terrace structure formed to be extended in the direction perpendicular to the miss cut direction of the nitride semiconductor substrate improves electrical properties.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to a method for manufacturing a nitride semiconductor stack and the nitride semiconductor stack. [Background technology]

[0002] In general power devices using nitride semiconductor laminates, an AlGaN barrier layer is provided on a GaN substrate (for example, Patent Document 1). Also, in order to increase the breakdown voltage of power devices, a method has been disclosed in which a nitride semiconductor laminate is grown on an AlN substrate with a wider band gap to create a power device (for example, Non-Patent Document 1). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2009-49121 [Non-patent literature]

[0004] [Non-Patent Document 1] Sumitomo Electric Technical Review No. 180, Page 83 (2012) Summary of the Invention [Problem to be solved by the invention]

[0005] In nitride semiconductor laminates, when the miscut angle of the substrate is large, at 0.1 degrees or more, each layer of the semiconductor laminate formed on the substrate tends to relax, which can sometimes introduce new threading dislocations into the nitride semiconductor laminate. On the other hand, even when the miscut angle of the substrate is small, at less than 0.1 degrees, relaxation of the layers formed on the substrate is less likely to occur, but the problem still arises that the electrical properties of the nitride semiconductor laminate fall short of the required level. An object of the present disclosure is to provide a method for manufacturing a nitride semiconductor stack having excellent electrical properties, and a nitride semiconductor stack. [Means for solving the problem]

[0006] In order to solve the above-described problems, a method for manufacturing a nitride semiconductor laminate according to one embodiment of the present disclosure includes depositing Al on a nitride semiconductor substrate containing Al by metal organic chemical vapor deposition in an environment where the temperature is 600° C. or higher and 1000° C. or lower and the pressure is 50 mbar or higher and 500 mbar or lower. x Ga (1-x) The method includes the steps of forming an underlayer made of N (0.5≦x≦1) and forming a GaN layer on the underlayer in an environment at a temperature of 600° C. or higher and 900° C. or lower.

[0007] A nitride semiconductor laminate according to another aspect of the present disclosure includes a nitride semiconductor substrate containing Al, and an Al x Ga (1-x) The nitride semiconductor laminate includes an underlayer made of N (0.5≦x≦1), and a GaN layer disposed on the underlayer. In the nitride semiconductor laminate, steps and flat terraces are repeated in the miscut direction of the substrate on the surface opposite to the nitride semiconductor laminate substrate of the layer farthest from the nitride semiconductor substrate, and the terrace edges, which are the ends of the terraces, have an amplitude in the miscut direction of the nitride semiconductor substrate and a wave-like shape extending in a direction perpendicular to the miscut direction of the nitride semiconductor substrate. It should be noted that the above summary of the invention does not list all of the features of the invention according to the present disclosure. [Effects of the Invention]

[0008] According to the present disclosure, it is possible to provide a method for manufacturing a nitride semiconductor stack having excellent electrical properties, and a nitride semiconductor stack having excellent electrical properties. [Brief explanation of the drawings]

[0009] [Figure 1] 1 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to an embodiment of the present invention. [Figure 2A]FIG. 2 is a perspective view illustrating a step-terrace structure formed on the surface of the underlayer of the nitride semiconductor stack according to the embodiment. [Figure 2B] 3 is a top view for schematically explaining a step-terrace structure formed on the surface of the underlayer of the nitride semiconductor laminate according to the embodiment. FIG. [Figure 3] 3 is a cross-sectional view schematically illustrating a step-terrace structure formed on the surface of the underlayer of the nitride semiconductor stack according to the embodiment. FIG. [Figure 4A] 1 is an AFM image showing a step-terrace structure on the surface of an underlayer of a nitride semiconductor laminate according to an embodiment of the present invention. [Figure 4B] 1 is an AFM image showing a step-terrace structure on the surface of an underlayer of a conventional nitride semiconductor laminate. [Figure 5A] 1 is an AFM image showing a step-terrace structure on the surface (surface of the GaN layer) of the nitride semiconductor stack according to the present embodiment. [Figure 5B] 1 is an AFM image showing the structure of the surface (GaN layer surface) of a conventional nitride semiconductor laminate. [Figure 6] 1 is a TEM image of a vertical cross section of a nitride semiconductor stack according to an embodiment of the present invention. [Figure 7] 7 is a graph showing the composition ratios of Al and Ga in the vertical cross section of the nitride semiconductor stack according to the embodiment shown in FIG. 6. [Figure 8] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 9] 10 is an AFM image showing a step-terrace structure on the surface (surface of the electron barrier layer) of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 10] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 11] FIG. 10 is a cross-sectional view schematically showing a cross section of a nitride semiconductor stack according to a modified example of the present embodiment. [Figure 12]1 is a cross-sectional view showing an example of the configuration of a high electron mobility transistor (HEMT), which is an example of a power device using the nitride semiconductor stack according to this embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0010] The nitride semiconductor stack according to the present disclosure will be described below through embodiments, but the following embodiments do not limit the scope of the invention according to the claims. Furthermore, not all of the combinations of features described in the embodiments are necessarily essential to the solution of the invention. Furthermore, in the following description, "up" and "down" do not necessarily refer to the vertical direction relative to the ground. In other words, the "up" and "down" directions are not limited to the direction of gravity. "Up" and "down" are merely convenient expressions for specifying the relative positional relationship of surfaces, films, substrates, etc., and do not limit the technical idea of ​​the present disclosure. For example, if the paper is rotated 180 degrees, "up" will of course become "down" and "down" will become "up."

[0011] 1. First embodiment A nitride semiconductor stack according to a first embodiment of the present disclosure will be described with reference to Fig. 1 to Fig. 7. The nitride semiconductor stack according to the first embodiment is used in a power device such as a high electron mobility transistor (HEMT) device. The nitride semiconductor stack according to the first embodiment will be described below.

[0012] (1.1) Structure of nitride semiconductor laminate A nitride semiconductor stack 1 according to this embodiment will be described with reference to Fig. 1. Fig. 1 is a cross-sectional view schematically showing the configuration of a vertical cross section of the nitride semiconductor stack 1 according to this embodiment. The nitride semiconductor laminate 1 includes a nitride semiconductor substrate (hereinafter referred to as a substrate) 11 containing Al, and an Al x Ga (1-x)The nitride semiconductor laminate 1 includes an underlayer 12 made of N (0.5≦x≦1), and a GaN layer 13 disposed on the underlayer 12. The nitride semiconductor laminate 1 has a step-terrace structure on the surface opposite to the substrate 11 of the layer farthest from the substrate 11 (GaN layer 13 in FIG. 1 ), in which steps ST, which are stepped portions in the miscut direction of the substrate 11, and flat terraces TE are repeated in the miscut direction of the substrate 11, and the terrace edges ETE, which are the ends of the terraces TE, have amplitude in the miscut direction of the nitride semiconductor substrate and a wave shape extending in a direction perpendicular to the miscut direction of the substrate 11. Here, the "layer farthest from" the substrate 11 refers to the layer disposed on the outermost surface of the nitride semiconductor laminate 1 among the layers disposed above the substrate 11. The step-terrace structure will be described in detail later. Hereinafter, each layer of the nitride semiconductor laminate 1 (substrate 11, and underlying layer 12 and GaN layer 13, which are semiconductor laminate portions formed thereon) will be described in detail.

[0013] <Nitride semiconductor substrate> Substrate 11 includes an Al-containing nitride semiconductor. The Al-containing nitride semiconductor is, for example, an Al-containing nitride semiconductor such as AlGaN or AlN, and is preferably AlN. When substrate 11 is a nitride semiconductor single crystal substrate such as AlN or AlGaN, the difference in lattice constant with the nitride semiconductor layer formed on the substrate 11 is small, and threading dislocations can be reduced by growing the nitride semiconductor layer in a lattice-matched system, which is preferable, and an aluminum nitride single crystal substrate is more preferable.

[0014] Here, the "comprises" in the expression "substrate 11 comprises a nitride semiconductor" means that the nitride semiconductor is mainly contained in the layer, but this expression also includes cases where other elements are contained. Specifically, this expression also includes cases where the composition of this layer is slightly modified by adding small amounts of other elements (for example, elements such as Ga (when Ga is not the main element), In, As, P, or Sb in a few percent or less). The wording "comprises" has a similar meaning when describing the composition of other layers. Furthermore, the small amounts of elements contained are not limited to those described above.

[0015] The substrate 11 may be doped n-type or p-type with donor impurities or acceptor impurities, and may be a mixed crystal of a nitride semiconductor such as AlN and sapphire (Al2O3), Si, SiC, MgO, Ga2O3, ZnO, GaN, or InN.

[0016] For example, the substrate 11 preferably has a film thickness of 100 μm or more and 600 μm or less. The plane orientation may be c-plane (0001), a-plane (11-20), m-plane (10-10), etc., with the c-plane substrate being more preferred.

[0017] The miscut angle of the substrate 11 is preferably 0.1 to 0.4 degrees. By providing the underlayer 12 described below, it becomes possible to form each layer of the lattice-matched semiconductor laminate on the upper layer of the substrate 11, even when the substrate 11 has a large miscut angle of 0.1 degrees or more. This improves the electrical characteristics of a device formed using the nitride semiconductor laminate 1. The miscut direction of the substrate 11 is preferably the <10-10> direction, which allows a step-terrace structure, in which steps, which are level differences in the <10-10> direction, and flat terraces are repeated, to be exposed on the surface of the uppermost layer of the nitride semiconductor stack 1.

[0018] <Underlayer> The underlayer 12 is Al x Ga (1-x) N (0.5≦x≦1), that is, Al with an Al composition of 50% or more and 100% or less x Ga (1-x) The base layer 12 is a nitride semiconductor layer formed of N. The base layer 12 is formed on the entire surface of the substrate 11. That is, the base layer 12 is provided between the substrate 11 and a GaN layer 13, which will be described later. Here, for example, the word "on" in the expression "underlayer 12 is formed on substrate 11" means that underlayer 12 is formed on one surface of substrate 11. The above expression also includes the case where another layer exists between substrate 11 and underlayer 12. The word "on" has a similar meaning in the relationship between other layers. For example, the case where another layer is formed between substrate 11 and underlayer 12 is also included in the expression "underlayer 12 is formed on substrate 11."

[0019] Underlayer 12 can recover pits and polishing marks formed on the surface of the substrate. Also, the difference in lattice constant and thermal expansion coefficient between underlayer 12 and GaN layer 13 is small, allowing a nitride semiconductor layer with few defects to be grown on underlayer 12. Underlayer 12 also allows GaN layer 13 to be grown under compressive stress, suppressing the occurrence of cracks in GaN layer 13. Therefore, even when substrate 11 is formed of a nitride semiconductor such as AlN or AlGaN, a nitride semiconductor layer with few defects can be grown above substrate 11 via underlayer 12.

[0020] The underlayer 12 is formed by metal-organic vapor phase epitaxy at a temperature between 600°C and 1000°C, both inclusive, and at a pressure between 50 mbar and 500 mbar, both of which are lower than conventional methods. As a result, as shown in Fig. 2A, a step-terrace structure is revealed on the surface of the underlayer 12, in which steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction (<10-10> direction) of the substrate 11, and the terrace edges ETE, which are the ends of the terraces TE, have amplitude in the miscut direction (<10-10> direction) of the substrate 11 and are wavy extending in the direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of the substrate 11.

[0021] The step-terrace structure formed on the underlayer 12 will now be described. Fig. 2A is a perspective view schematically showing the step-terrace structure formed on the surface of the underlayer 12, and Fig. 2B is a top view of the step-terrace structure shown in Fig. 2A. Fig. 3 is a cross-sectional view showing the AA cross section shown in Fig. 2B, which schematically shows a longitudinal cross section of the step-terrace structure in the miscut direction of the substrate 11. Here, in Fig. 3, atoms are schematically shown as circles. A step ST is a step portion of one or more atoms, and a terrace TE is an atomic alignment site. In the step-terrace structure, for example, two terraces TE are connected by a step ST. In this embodiment, a terrace end ETE is a convex end portion formed by the terrace TE and the step ST connected to the terrace TE. The step-terrace structure formed on the surface of the underlayer 12 can be confirmed from an image formed by, for example, an atomic force microscope (AFM) or a scanning probe microscope (SPM) such as a scanning tunneling microscope (STM). Furthermore, the height of the steps ST and the width of the terraces TE of the step-terrace structure can be confirmed from, for example, the cross-sectional profile of the AFM image or the STM image. It should be noted that the step-terrace structures shown in FIGS. 2A and 2B and FIG. 3 are schematic structures, and the step-terrace structures that are actually formed do not necessarily conform to the schematic diagrams.

[0022] Here, FIG. 4A is an AFM (Atomic Force Microscopy) image of the surface of underlayer 12 formed on a substrate with a miscut angle of 0.2 degrees under the temperature and pressure environment of this embodiment. For comparison, the surface structure of the underlayer formed under a conventional high-temperature environment (e.g., 1100°C or higher and 1250°C or lower) will be described with reference to Fig. 4B, which is an AFM image of the surface of the underlayer formed under the conventional high temperature conditions. 4B, a step-terrace structure is revealed on the surface of the base layer formed in a conventional high-temperature environment, in which steps ST, which are step portions, and flat terraces TE are repeated in the miscut direction (<10-10> direction) of the substrate 11. In this case, the terrace edges of the step-terrace structure are nearly linear.

[0023] As described above, the terrace width WTE (the width between steps ST in the miscut direction (<10-10> direction) of substrate 11 in FIGS. 2B and 3) of the step-terrace structure having wavy terrace edges ETE exposed on the surface of underlayer 12 is preferably 50 nm or more and 150 nm or less. This makes it possible to form underlayer 12 and each nitride semiconductor layer formed above underlayer 12 that are pseudo-lattice matched to substrate 11, i.e., have a lattice constant that is approximately equal to that of substrate 11, even when using a substrate 11 with a large miscut angle of 0.1 degree or more.

[0024] Furthermore, the distance W1 between adjacent peaks (for example, P1 and P2 shown in FIG. 2B) of the wavy terrace edge ETE is preferably 300 nm or more and 800 nm or less. Furthermore, it is preferable that the distance W2 of a perpendicular line L3 drawn between a first straight line L1 connecting two peaks (e.g., P1 and P2 shown in FIG. 2B) of the wavy terrace end ETE and a second straight line L2 connecting two valleys (e.g., P3 and P4 shown in FIG. 2B) of the wavy terrace end ETE is not less than 50 nm and not more than 150 nm. Furthermore, it is preferable that the angle θ between one peak (e.g., P2 shown in FIG. 2B) of the wavy terrace edge ETE and two adjacent valleys (e.g., P3 and P4 shown in FIG. 2B) sandwiching this peak be 60 degrees or more and 120 degrees or less. As a result, even if the miscut angle of the substrate 11 is large, at 0.1 degrees or more, it is possible to form the underlayer 12 that is pseudo-lattice matched to the substrate 11, i.e., has a lattice constant that is approximately the same as that of the substrate 11, and each nitride semiconductor layer formed above the underlayer 12, thereby further improving the electrical characteristics.

[0025] The underlying layer 12 may contain impurities such as C, B, O, H, Si, Fe, and Mg. When AlN is used as the material for forming the substrate 11, since the underlying layer 12 and the substrate 11 are formed of the same material, the boundary between the underlying layer 12 and the substrate 11 becomes unclear. When the substrate 11 is formed of AlN, the substrate 11 may be regarded as constituting the substrate 11 and the underlying layer 12.

[0026] The underlying layer 12 has a thickness of, for example, several μm or less. Specifically, the thickness of the underlying layer 12 is preferably greater than 10 nm and less than 1 μm, and more preferably 50 nm or more and 200 nm or less. When the thickness of the underlying layer 12 is greater than 10 nm, the recovery of the substrate surface progresses and the crystallinity of AlN increases. Also, when the thickness of the underlying layer 12 is 50 nm or more, the effect of forming a nitride semiconductor layer having a lattice constant substantially matching the lattice constant of the substrate 11 by the step terrace structure described above becomes higher. Also, from the viewpoint of raw material costs, it is preferable that the thickness of the underlying layer 12 is less than 1 μm, and more preferably 200 nm or less.

[0027] <GaN layer> The GaN layer 13 is formed on the underlying layer 12. The GaN layer 13 is formed in an environment at a temperature of 600°C or higher and lower than 900°C, which is a lower temperature compared to the conventional case (for example, about 1000°C). In the nitride semiconductor laminate 1 of the present embodiment, the GaN layer 13 becomes the uppermost layer and the surface of the nitride semiconductor laminate 1. FIG. 5A shows an AFM image of the surface of the GaN layer 13, which is the surface of the nitride semiconductor laminate 1. As shown in FIG. 5A, a step terrace structure is formed on the surface of the GaN layer 13, similar to the underlying layer, 12. Note that the step terrace structure formed on the surface of the GaN layer 13 and the step terrace structure formed on the surface of the underlying layer 12 may have a non-identical structure.

[0028] The step-terrace structure exposed on the upper surface of GaN layer 13 is formed when GaN layer 13 is formed on underlayer 12 having a step-terrace structure, and the step-terrace structure of underlayer 12 is maintained up to the upper surface of GaN layer 13. That is, the step-terrace structure formed on the surface of GaN layer 13, like underlayer 12, has a repeating pattern of steps ST, which are stepped portions, and flat terraces TE in the miscut direction (<10-10> direction) of substrate 11, and the terrace ends ETE (boundaries between terraces TE and steps ST in top view) which are the ends of terraces TE have amplitude in the miscut direction (<10-10> direction) of substrate 11 and form a wave-like structure extending in the direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of substrate 11. In this way, in the nitride semiconductor stack 1 in which a step-terrace structure of a predetermined structure is exposed on the surface of the GaN layer 13, which is the surface of the nitride semiconductor stack 1, the mobility and carrier concentration are improved, thereby reducing the sheet resistance and resulting in improved electrical characteristics.

[0029] For comparison, the surface structure of a GaN layer formed on a conventional underlayer (the underlayer shown in FIG. 4B) will be described with reference to FIG. 5B, which is an AFM image of the surface of a GaN layer formed on a conventional underlayer. As shown in Figure 5B, the surface of a GaN layer grown on a conventional underlayer does not have the step-terrace structure described in Figure 5A, but has a surface structure formed by island-like crystal growth. Furthermore, as shown in Figure 5B, the GaN layer grown on a conventional underlayer is not pseudomorphic to the underlayer and is relaxed.

[0030] 1, an unintentional diffusion layer may be formed at the interface between the underlayer 12 and the GaN layer 13. The unintentional diffusion layer is a layer that is formed at the interface between the underlayer 12 and the GaN layer 13 as a result of forming the GaN layer 13 on the underlayer 12. x Ga (1-x)The layer contains Al and Ga and is formed by diffusing Al from underlayer 12 made of N (0.5≦x≦1) into GaN layer 13 and diffusing Ga from GaN layer 13 into underlayer 12. Fig. 6 is a TEM (Transmission Electron Microscope) image of a vertical cross section of the nitride semiconductor laminate 1. As shown in Fig. 6, a diffusion layer 16 is formed between the base layer 12 (denoted as "LT-AlN" in Fig. 6) and the GaN layer 13 (denoted as "GaN" in Fig. 6). Fig. 7 is a graph showing the composition ratios of Al and Ga in the cross section shown in Fig. 6. Fig. 7 shows the composition ratios when the underlayer is AlN, with the Al composition indicated by a solid line and the Ga composition indicated by a dotted line. As shown in Fig. 7, a diffusion layer 16 is formed between underlayer 12 and GaN layer 13, in which the Al composition x decreases from 1 to 0 as one moves from underlayer 12 made of AlN toward GaN layer 13, and the Ga composition (1-x) increases from 0 to 1 as one moves from underlayer 12 made of AlN toward GaN layer 13.

[0031] Al constituting the underlayer 12 x Ga (1-x) N (0.5≦x≦1) and the GaN that makes up the GaN layer 13 each have spontaneous polarization, which is polarized in the c-axis direction. When layers with different polarizations are stacked, a charge equal to the difference in polarization is generated at the interface. In addition, piezoelectric polarization occurs due to lattice distortion. This piezoelectric polarization and spontaneous polarization induce carriers in the semiconductor layer, forming a highly concentrated sheet-like two-dimensional carrier layer at the interface.

[0032] AlN (Al composition is 100% x Ga (1-x) When GaN layer 13 is formed on underlayer 12 formed of N, a two-dimensional hole gas (2DHG) which is a two-dimensional carrier gas is formed at the interface between underlayer 12 and GaN layer 13. Two-dimensional carrier gases have high saturated mobility, which allows for high-frequency characteristics. Furthermore, power devices can be obtained that combine low on-resistance due to high mobility with high breakdown voltage characteristics due to a wide band gap. Here, the on-resistance is determined by the mobility and carrier concentration of the two-dimensional carrier gas. Lower sheet resistance, which includes both the mobility and carrier concentration parameters mentioned above, is advantageous for reducing on-resistance. Furthermore, breakdown voltage is determined by the band gap of the nitride semiconductors that make up the HEMT, a device using a nitride semiconductor stack.

[0033] The generation of such two-dimensional carrier gas is affected by polarization, i.e., strain. To form this two-dimensional hole gas (2DHG) with higher concentration and higher mobility, the influence of alloy scattering must be taken into consideration. s Ga (1-s) When an N layer is used, if the Al composition is too high, the mobility will be significantly reduced due to alloy scattering. Furthermore, when the nitride semiconductor laminate 1 is used to form a power device, it is preferable that the layer provided on the underlayer 12 does not contain Al, from the viewpoint of achieving both a high two-dimensional hole gas (2DHG) concentration and high mobility. For this reason, it is preferable to provide a GaN layer 13 on the underlayer 12.

[0034] In order to increase the concentration of the two-dimensional hole gas (2DHG), the abruptness of the interface is important, and from that viewpoint, the thickness of the GaN layer 13 is preferably 0.5 nm or more and 30 nm or less. The relaxation rate of GaN layer 13 is preferably 0% or more and 5% or less.

[0035] From the viewpoint of distorting the GaN layer 13 from its original lattice constant, it is preferable that misfit dislocations exist at the interface between the GaN layer 13 and the substrate 11. Specifically, it is preferable that misfit dislocations exist in the miscut direction (<10-10> direction) of the substrate 11 at the above-mentioned interface. Furthermore, it is preferable that the misfit dislocations in the miscut direction (<10-10> direction) of the substrate 11 exist in the same plane. It is particularly preferable that the misfit dislocations exist within a range of 5 nm above and below the interface between the underlayer 12 and the GaN layer 13. This allows the strain at the interface to be released without generating threading dislocations extending in a direction perpendicular to the substrate 11. As a result, the quality of the two-dimensional hole gas (2DHG) is improved. Here, in the present disclosure, "misfit dislocations are present" means that the dislocation density measured by the method described below is 4.5 / μm or more and 11 / μm or less. This means that The two-dimensional hole gas (2DHG) has high mobility, which allows a power device such as a HEMT using the nitride semiconductor laminate 1 to obtain high frequency characteristics. For this reason, high-quality crystallinity and interface abruptness are desired in the nitride semiconductor laminate 1.

[0036] From the viewpoint of increasing the mobility of the two-dimensional hole gas (2DHG), the coverage of the GaN layer 13 with respect to the layer immediately below is preferably 80% or more and 100% or less. From the viewpoint of high crystal quality, the dislocation density in the GaN layer 13 is 1×10 4 cm -3 It is preferable that: From the viewpoint of interface abruptness, the surface root-square roughness of the surface of GaN layer 13 is preferably 0.9 nm or less. Here, the surface root-square roughness of GaN layer 13 is the surface root-square roughness of the surface of GaN layer 13 opposite to substrate 11. This allows the realization of a high-concentration, high-mobility two-dimensional hole gas (2DHG).

[0037] The GaN layer 13 may contain impurities such as group V elements other than N, such as P, As, and Sb, and C, H, F, O, Be, Mg, Zn, and Si, but the types of impurity elements are not limited to these.

[0038] (1.2) Variations (1.2.1) Variation 1 The nitride semiconductor stack 1A of Modification 1 will be described with reference to Fig. 8 and Fig. 9. Fig. 8 is a cross-sectional schematic diagram showing a cross section of the nitride semiconductor stack 1A, and Fig. 9 is an AFM image showing the shape of the surface of the nitride semiconductor stack 1A.

[0039] 8, the nitride semiconductor stack 1A includes a substrate 11, an underlayer 12, a GaN layer 13, and an electron barrier layer 14 provided on the GaN layer 13. That is, the nitride semiconductor stack 1A differs from the nitride semiconductor stack 1 according to the first embodiment in that the nitride semiconductor stack 1A further includes the electron barrier layer 14 on the GaN layer 13. The following describes in detail the electron barrier layer 14. Note that, in the nitride semiconductor stack 1A, the substrate 11, the underlayer 12, and the GaN layer 13 are the same as the layers constituting the nitride semiconductor stack 1, and therefore descriptions thereof will be omitted.

[0040] <Electron barrier layer> The electron barrier layer 14 is a layer provided for forming a two-dimensional electron gas (2DEG) that serves as a two-dimensional carrier layer at the interface with, for example, the GaN layer 13. In the nitride semiconductor stack 1A of Modification 2, the electron barrier layer 14 is the uppermost layer, which forms the surface of the nitride semiconductor stack 1A. Fig. 9 shows an AFM image of the surface of the electron barrier layer 14, which is the surface of the nitride semiconductor laminate 1A. As shown in Fig. 9, the surface of the electron barrier layer 14, like the underlayer 12, has a stepped portion, that is, a step ST, and a flat terrace TE repeated in the miscut direction (<10-10> direction) of the substrate 11, and the end of the terrace TE, that is, the terrace end ETE (the boundary between the terrace TE and the step ST in the top view), has an amplitude in the miscut direction (<10-10> direction) of the substrate 11 and forms a wave-like step-terrace structure extending in the direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of the substrate 11. The step-terrace structure formed on the surface of the electron barrier layer 14 and the step-terrace structure formed on the surface of the underlayer 12 may not be completely identical to each other.

[0041] The electron barrier layer 14 is a layer of a nitride semiconductor containing Al and Ga or Al. From the viewpoint of increasing the carrier concentration, the electron barrier layer 14 is made of Al. y Ga (1-y) Al formed with N (0.7≦y≦1) y Ga (1-y) Preferably, the electron barrier layer 14 is an N layer. The electron barrier layer 14 may also contain impurities such as Group III atoms other than Al and Ga, such as In, Group V elements other than N, such as P, As, and Sb, and C, H, F, O, Be, Mg, Zn, and Si, but the types of impurity elements are not limited to these.

[0042] On the GaN layer 13, an Al is formed as an electron barrier layer 14. y Ga (1-y) When an N layer (0.7≦y≦1, for example, an AlN layer) is stacked, a two-dimensional electron gas (2DEG) is formed at the interface between the GaN layer 13 and the electron barrier layer 14. From the viewpoint of two-dimensional electron gas (2DEG) formation, it is preferable that the Al composition y in the electron barrier layer 14 is larger than the Al composition x in the GaN layer 13 (y>x). Furthermore, if the difference between the Al composition x in the GaN layer 13 and the Al composition y in the electron barrier layer 14 is smaller than 0.5, cracks may occur in the GaN layer 13 and the electron barrier layer 14. For this reason, it is preferable that the difference between the Al composition x in the GaN layer 13 and the Al composition y in the electron barrier layer 14 is larger than 0.5.

[0043] The thickness of the electron barrier layer 14 is preferably, for example, 2 nm or more and 30 nm or less. When the thickness of the electron barrier layer 14 is 2 nm or more, a sufficient two-dimensional electron gas (2DEG) layer can be formed between the GaN layer 13 and the electron barrier layer 14, further improving the electrical characteristics of the nitride semiconductor stack 1A. When the thickness of the electron barrier layer 14 is 30 nm or more, the resistance of the electron barrier layer 14 is high, making it difficult to make sufficient contact with the two-dimensional electron gas (2DEG).

[0044] The characteristics of nitride semiconductor stack 1A, which uses an aluminum nitride single crystal substrate as substrate 11 and includes underlayer 12 formed of AlN to a thickness of 900 nm under the conditions of this embodiment, GaN layer 13 to a thickness of 15 nm, and electron barrier layer 14 formed of AlN to a thickness of 7.5 nm, are compared with the characteristics of a conventional nitride semiconductor stack in which the underlayer is formed in a conventional high-temperature environment. In the nitride semiconductor stack 1A, the mobility was improved by more than 200%, the carrier concentration was improved by more than 110%, and the sheet resistance was reduced to about 40% compared to the conventional nitride semiconductor stack.

[0045] (1.2.2) Variation 2 A nitride semiconductor stack 1B of Modification 2 will be described with reference to Fig. 10. Fig. 10 is a cross-sectional schematic diagram showing a cross section of the nitride semiconductor stack 1B.

[0046] 10, nitride semiconductor stack 1B includes substrate 11, underlayer 12, GaN layer 13, electron barrier layer 14, and compositionally graded layer 15 provided between underlayer 12 and GaN layer 13. That is, nitride semiconductor stack 1B differs from nitride semiconductor stack 1A of Modification 1 in that it further includes compositionally graded layer 15 provided between underlayer 12 and GaN layer 13. The following describes in detail the composition gradient layer 15. In the nitride semiconductor stack 1B, the substrate 11, the underlayer 12, and the GaN layer 13 are the same as the layers constituting the nitride semiconductor stack 1, and the electron barrier layer 14 is the same as the electron barrier layer 14 constituting the nitride semiconductor stack 1A, so a description thereof will be omitted. The nitride semiconductor stack 1B includes the substrate 11, the underlayer 12, the GaN layer 13, and the compositionally graded layer 15, that is, the electron barrier layer 14 may not be provided.

[0047] <Composition gradient layer> The compositionally graded layer 15 is a buffer layer provided between the underlayer 12 and the GaN layer 13, and serves to further reduce the lattice mismatch between the underlayer 12 and the GaN layer 13. The composition gradient layer 15 is, for example, Al z Ga (1-z) N (0≦z≦1). The Al composition z of the composition gradient layer 15 changes in the direction away from the substrate 11. It is preferable that the Al composition z of the composition gradient layer 15 decreases in the direction away from the substrate 11.

[0048] The profile (gradient) of the Al composition z in the composition gradient layer 15 may change continuously or intermittently. Here, "intermittently changing" means that the composition gradient layer 15 includes a portion where the Al composition z is constant. In other words, the composition gradient layer 15 may include a portion where the Al composition z does not change in the direction away from the substrate 11. However, it is preferable that the profile (gradient) of the Al composition z in the composition gradient layer 15 change linearly.

[0049] Furthermore, misfit dislocations in the miscut direction (<10-10> direction) of substrate 11 are preferably present at the interface between GaN layer 13 and compositionally graded layer 15. Furthermore, misfit dislocations in the miscut direction (<10-10> direction) of substrate 11 are preferably present in the same plane. Here, "misfit dislocations are present in the same plane" means that misfit dislocations are present at the interface between GaN layer 13 and compositionally graded layer 15 so as to extend substantially parallel to the surface of substrate 11. Such misfit dislocations are preferably present within a range of 5 nm above and below the interface between GaN layer 13 and compositionally graded layer 15. This allows strain at the interface to be released without generating threading dislocations extending perpendicular to substrate 11. As a result, the quality of the two-dimensional electron gas (2DEG) is improved. Here, in the present disclosure, "misfit dislocations are present" means that the dislocation density measured by the method described below is 4.5 dislocations / μm or more and 11 dislocations / μm or less.

[0050] The thickness of the compositionally graded layer 15 is preferably, for example, 5 nm or more and 20 nm or less. When the thickness of the compositionally graded layer 15 is 5 nm or more, the lattice mismatch between the GaN layer 13 and the compositionally graded layer 15 is further reduced, and the electrical characteristics of the nitride semiconductor stack 1B are further improved. Furthermore, when the thickness of the compositionally graded layer 15 is 20 nm or less, relaxation in the compositionally graded layer 15 is suppressed, and the above-mentioned two-dimensional hole gas (2DHG) characteristics are improved. From the viewpoint of increasing the concentration of the two-dimensional hole gas (2DHG), it is preferable that a buffer layer such as the above-described compositionally graded layer 15 is not provided at the interface between the underlayer 12 and the GaN layer 13.

[0051] On the surface of the nitride semiconductor laminate 1B provided with such a composition gradient layer 15 (the surface of the electron barrier layer 14), similar to the nitride semiconductor laminate 1A, a step ST which is a stepped portion and a flat terrace TE are repeated in the misorientation direction (<10-10> direction) of the substrate 11, and a terrace end ETE which is an end of the terrace TE (a boundary portion between the terrace TE and the step ST in a top view) has an amplitude in the misorientation direction (<10-10> direction) of the substrate 11, and a step terrace structure in a wave shape extending in a direction (<11-20> direction) perpendicular to the misorientation direction (<10-10> direction) of the substrate 11 appears.

[0052] (1.2.3) Modified Example 3 Referring to FIG. 11, the nitride semiconductor laminate 1C of Modified Example 3 will be described. Here, FIG. 11 is a schematic cross-sectional view showing a cross-section of the nitride semiconductor laminate 1C.

[0053] As shown in FIG. 11, the nitride semiconductor laminate 1C includes a substrate 11, an underlayer 12, a GaN layer 13, and an AlN layer 16 provided between the substrate 11 and the underlayer 12. That is, the nitride semiconductor laminate 1C is different from the nitride semiconductor laminate 1 according to the first embodiment in that it further includes an AlN layer 16. Hereinafter, the AlN layer 16 will be described in detail. Note that since the substrate 11, the underlayer 12, and the GaN layer 13 in the nitride semiconductor laminate 1C are the same as the respective layers constituting the nitride semiconductor laminate 1, the description thereof will be omitted.

[0054] <AlN layer> The AlN layer 16 is preferably formed over the entire surface of the substrate. Similar to the underlayer 12, the AlN layer 16 is a layer for forming a nitride semiconductor layer having a small lattice constant difference and a small coefficient of thermal expansion difference in the upper layer and having few defects. The AlN layer 16 is formed, for example, in an environment at a temperature of 1100°C or higher and 1,250°C or lower. That is, the AlN layer 16 is formed at a higher temperature than the underlayer 12. The AlN layer 16 is preferably a nitride semiconductor layer containing Al, and is formed of a nitride semiconductor such as AlN, AlGaN, etc. The AlN layer 16 may also contain impurities such as C, Si, Fe, Mg, etc.

[0055] The AlN layer 16 has a thickness of, for example, several μm. Specifically, the thickness of the AlN layer 16 is preferably greater than 10 nm and less than 10 μm, for example, 900 nm. When the thickness of the AlN layer 16 is greater than 10 nm, the crystallinity of nitride semiconductors such as AlN is increased. Furthermore, when the thickness of the AlN layer 16 is less than 10 μm, cracks are less likely to occur in the AlN layer 16 formed by crystal growth over the entire wafer surface.

[0056] (1.3) Method for manufacturing nitride semiconductor laminate A method for manufacturing the nitride semiconductor stack 1 of this embodiment will be described. The nitride semiconductor stack 1 is manufactured through the following steps. (A) Al is deposited on a substrate 11, which is a nitride semiconductor substrate containing Al, by metal organic chemical vapor deposition in an environment where the temperature is 600° C. or more and 1000° C. or less and the pressure is 50 mbar or more and 500 mbar or less. x Ga (1-x) Forming the underlayer 12 made of N (0.5≦x≦1) (B) Forming a GaN layer 13 on the underlayer 12 in an environment where the temperature is 600° C. or higher and 900° C. or lower.

[0057] Substrate 11 is formed by a common substrate growth method, such as a vapor phase growth method such as sublimation or hydride vapor phase epitaxy (HVPE), or a liquid phase growth method. The miscut angle of substrate 11 is not particularly limited, but a miscut angle of 0.1 degrees or more and 0.4 degrees or less is preferable because the effect of underlayer 12 is significant. In addition, the miscut direction of substrate 11 is preferably the <10-10> direction.

[0058] The step of forming the underlayer 12 on the substrate 11 can be performed using a metal organic chemical vapor deposition (MOCVD) method in an environment where the temperature is 600°C or higher and 1000°C or lower and the pressure is 50 mbar or higher and 500 mbar or lower. Here, the underlayer 12 formed on the substrate 11 can be formed using, for example, an Al raw material containing trimethylaluminum (TMAl), a Ga raw material containing, for example, trimethylgallium (TMGa) or triethylgallium (TEGa), or an N raw material containing, for example, ammonia (NH3).

[0059] Specifically, the underlayer 12 is formed by placing the substrate 11 at a temperature of 600° C. or higher and lower than 1000° C. in an environment with a pressure of 50 mbar or higher and 500 mbar or lower, and growing Al by metal organic chemical vapor deposition. x Ga (1-x) It is only necessary to form a layer formed of N (0.5≦x≦1), and other conditions are not particularly limited. As a result, on the surface of the underlayer 12, steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction (<10-10> direction) of the substrate 11, and the ends of the terraces TE, which are the terrace ends ETE (the boundary between the terraces TE and the steps ST in a top view), have amplitude in the miscut direction (<10-10> direction) of the substrate 11, resulting in a wave-shaped step-terrace structure extending in a direction (<11-20> direction) perpendicular to the miscut direction (<10-10> direction) of the substrate 11 (see Figure 2A).

[0060] The growth rate of the underlayer 12 is preferably 0.5 μm / hr or more and less than 2 μm / hr. x Ga (1-x) When the growth rate of N is 0.5 μm / hr or more, the aforementioned wavy step-terrace structure is well formed, and better electrical properties can be obtained. Similarly, when the growth rate is less than 2 μm / hr, the aforementioned wavy step-terrace structure is well formed, and better electrical properties can be obtained. The growth rate of the underlayer 12 can be controlled by appropriately adjusting the temperature of the substrate 11, the degree of vacuum in the chamber, and the flow rate of the source gas. From the viewpoint of removing impurities, it may be preferable to anneal the substrate 11 in a hydrogen atmosphere at 1000° C. or higher, preferably 1200° C. or higher.

[0061] (1.4) Method for measuring physical properties of nitride semiconductor laminate The physical properties of the above-described nitride semiconductor stack 1 and the nitride semiconductor stacks 1A and 1B in the modified examples can be measured as follows.

[0062] (GaN layer coverage measurement) The coverage of the GaN layer 13 is measured using, for example, a scanning electron microscope (FE-SEM "SU9000" manufactured by Hitachi High-Technologies Corporation) and image processing software (image analysis software "A-Zo-kun" (registered trademark) manufactured by Asahi Kasei Engineering Co., Ltd.). More specifically, during SEM measurement, the exposed surface of the GaN layer 13 is measured at three arbitrary points within a measurement range of 50 μm × 50 μm. At this time, a backscattered electron image is obtained using a lower detector, resulting in an SEM image with clear contrast due to compositional differences.

[0063] The obtained SEM image is processed using image processing software. Areas with brightness 50% or more lower than the average brightness in the SEM image are defined as areas where the GaN layer 13 is not covering the substrate 11 directly below. The coverage rate is the proportion of the covered area, and the average value of any three points is defined as the coverage rate of the GaN layer 13.

[0064] The surface roughness is measured using an atomic force microscope (AFM) (Seiko Instruments Inc., "SPA400"). The same location as in the coverage measurement is measured using the AFM at three arbitrary points within a measurement range of 4 μm × 4 μm. The scan frequency is 0.2 Hz. The average value of the root mean square roughness at the three points obtained by the measurement is taken as the surface roughness of the GaN layer 13.

[0065] (Method for measuring GaN layer thickness and threading dislocations) The thickness of the GaN layer 13 can be measured by cutting out a predetermined cross section perpendicular to the substrate 11, observing this cross section with a transmission electron microscope (TEM), and using the length measurement function of the TEM. For the TEM measurement, for example, a transmission electron microscope "HD-2300" manufactured by Hitachi High-Technologies Corporation is used. As a measurement method, first, a cross section perpendicular to the major surface of the substrate 11 of the nitride semiconductor laminate is observed using a TEM. As an example, measurement on the a-plane (11-20) is preferred. Specifically, for example, within a TEM image showing a cross section perpendicular to the major surface of the substrate 11 of the nitride semiconductor laminate 1, an observation width of 2 μm or more is set in a direction parallel to the major surface of the substrate 11. Within this observation width, contrast is observed at the interface between two layers with different compositions, so the thickness up to this interface is observed in a continuous observation region 200 nm wide. The film thickness of each layer can be obtained by calculating the average thickness of each layer included in this 200-nm-wide observation region from five locations arbitrarily selected from the above-mentioned observation width of 2 μm or more.

[0066] Similarly, for threading dislocations, the number of threading dislocations per volume is calculated from the number of threading dislocations present in a cross section perpendicular to the main surface of the substrate 11, the field area, and the thickness of the sample. The number of threading dislocations is calculated from five samples, and the average value of these is taken as the number of threading dislocations.

[0067] (Measurement of strain, misfit dislocations, and stacking faults in nitride semiconductor layers) Misfit dislocations formed near the interface can be measured by cutting out a predetermined cross section parallel to the substrate 11 and observing it with a transmission electron microscope (TEM). As an example, a primary sample including an observation area of ​​20 μm square or more, including the GaN layer 13, is prepared from the substrate 11 by a focused ion beam method. Next, a secondary sample is prepared by thinning the primary sample to a thickness of 0.5 μm by polishing or the focused ion beam method. The secondary sample is <0001> Planar TEM images are obtained using a zone-axis incident electron beam. During this process, cross-sectional TEM images can be simultaneously obtained using the primary sample or a sample obtained using a similar method to the primary sample. Misfit dislocations were observed at a magnification of 10k to 20k with an applied voltage of 200kV. <0001> The counting is performed using a planar TEM image with the zone-axis incidence. The direction of the obtained dislocation lines is not perfectly parallel to the <10-10> direction throughout the entire field of view, and the number of lines may increase or decrease as they intersect with other dislocation lines. Therefore, the number of dislocation lines is counted by imagining a sampling line parallel to the <10-10> direction and determining the number of intersections between the sampling line and the dislocation line as the statistical average value over multiple sampling lines. The sampling lines are spaced at intervals of 1 μm or less, and counting is performed 20 times or more within a 20 μm field of view.

[0068] (Method for measuring Al composition and relaxation rate in AlxGa(1-x)N layers) The relaxation rate can be measured, for example, by reciprocal space mapping (RSM) using X-ray diffraction (XRD). For XRD measurements, a PANalytical "X'pert3 MRD" is used. In this case, the tube is set to 45 kV / 40 mA, a collimated radiation source using a double-crystal Ge (220) is used, the incident Soller slit is set to 0.04°, and the detector slit is set to 1 / 16 mm, and the axis is aligned with the (20-24) plane peak of the substrate 11. Then, a 2θ / ω scan is performed, and the ω is changed in 0.05° increments within a range of ±1.5°. From these measurements, the spatial coordinates Qx and Qy are calculated, and the relaxation rate and Al composition for the substrate 11 are calculated.

[0069] (1.5) Effects of this embodiment The nitride semiconductor stack and the method for manufacturing the nitride semiconductor stack according to this embodiment have the following advantages. (1) The method for producing a nitride semiconductor laminate according to this embodiment is to deposit Al on a nitride semiconductor substrate containing Al by metal organic chemical vapor deposition in an environment where the temperature is 600° C. or higher and 1000° C. or lower and the pressure is 50 mbar or higher and 500 mbar or lower. x Ga (1-x) The method includes the steps of forming an underlayer made of N (0.5≦x≦1) and forming a GaN layer on the underlayer in an environment at a temperature of 600° C. or higher and 900° C. or lower. This allows the formation of a step-terrace structure on the surface of the nitride semiconductor laminate, in which steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction of the substrate, and the terrace ends ETE, which are the ends of the terraces TE, have a wave shape that has amplitude in the miscut direction of the nitride semiconductor substrate and extends in a direction perpendicular to the miscut direction of the nitride semiconductor substrate, thereby allowing the production of a nitride semiconductor laminate with excellent electrical properties.

[0070] (2) In the method for manufacturing a nitride semiconductor laminate according to this embodiment, it is preferable to use an aluminum nitride single crystal substrate as the nitride semiconductor substrate. This reduces the difference in lattice constant between the nitride semiconductor substrate and the nitride semiconductor layer formed on the nitride semiconductor substrate, and by growing the nitride semiconductor layer in a lattice-matched system, threading dislocations can be reduced, thereby improving the quality of the nitride semiconductor laminate.

[0071] (3) In the method for manufacturing a nitride semiconductor laminate according to this embodiment, it is preferable to use a nitride semiconductor substrate having a miscut angle of 0.1 degrees or more and 0.4 degrees or less. As a result, by providing the underlayer, it becomes possible to form each layer of the lattice-matched semiconductor laminate on the upper layer of the substrate even when using a substrate 11 with a large miscut angle of 0.1 degrees or more, and the electrical characteristics of the device formed using the nitride semiconductor laminate are improved.

[0072] (4) In the method for manufacturing a nitride semiconductor laminate according to this embodiment, it is preferable to use a nitride semiconductor substrate whose miscut direction is the <10-10> direction. This allows a step-terrace structure, in which steps, which are level portions in the <10-10> direction, and flat terraces are repeated, to be exposed on the surface of the uppermost layer of the nitride semiconductor laminate.

[0073] (5) The nitride semiconductor laminate according to this embodiment includes a nitride semiconductor substrate containing Al, and an Al x Ga (1-x) The nitride semiconductor laminate includes an underlayer made of N (0.5≦x≦1), and a GaN layer disposed on the underlayer. The surface of the layer furthest from the nitride semiconductor substrate in the nitride semiconductor laminate opposite to the nitride semiconductor substrate has a step-terrace structure in which steps ST, which are stepped portions, and flat terraces TE are repeated in the miscut direction of the substrate, and the terrace edges ETE, which are the ends of the terraces TE, have a wave shape that has amplitude in the miscut direction of the nitride semiconductor substrate and extends in a direction perpendicular to the miscut direction of the nitride semiconductor substrate. This makes it possible to obtain a nitride semiconductor stack with excellent electrical properties.

[0074] (6) In the nitride semiconductor stack according to this embodiment, the distance between adjacent peaks at the edge of the wavy terrace is preferably 300 nm or more and 800 nm or less. In addition, in the nitride semiconductor stack according to this embodiment, the distance between a first straight line connecting two peaks at the wavy terrace edge and a perpendicular line connecting two valleys at the terrace edge is preferably 50 nm or more and 150 nm or less. Furthermore, in the nitride semiconductor stack according to this embodiment, the angle θ formed between one peak at the edge of the wavy terrace and two adjacent valleys sandwiching the peak is preferably 60 degrees or more and 120 degrees or less. This makes it possible to form an underlayer and each nitride semiconductor layer formed above the underlayer that are pseudo-lattice matched to the substrate, i.e., have a lattice constant that is approximately the same as that of the substrate, even when the miscut angle of the substrate is as large as 0.1 degrees or more, thereby achieving further improved electrical properties.

[0075] (7) In the nitride semiconductor laminate according to this embodiment, the nitride semiconductor substrate is preferably an aluminum nitride single crystal substrate. This reduces the difference in lattice constant between the nitride semiconductor substrate and the nitride semiconductor layer formed on the nitride semiconductor substrate, and by growing the nitride semiconductor layer in a lattice-matched system, threading dislocations can be reduced, thereby improving the quality of the nitride semiconductor laminate.

[0076] (8) In the nitride semiconductor stack according to this embodiment, the miscut angle of the nitride semiconductor substrate is preferably 0.1 degrees or more and 0.4 degrees or less. As a result, by providing the underlayer, it becomes possible to form each layer of the lattice-matched semiconductor laminate on the upper layer of the substrate even when using a substrate 11 with a large miscut angle of 0.1 degrees or more, and the electrical characteristics of the device formed using the nitride semiconductor laminate are improved.

[0077] (9) In the nitride semiconductor stack according to this embodiment, the miscut direction of the nitride semiconductor substrate is preferably the <10-10> direction. This allows a step-terrace structure, in which steps, which are level portions in the <10-10> direction, and flat terraces are repeated, to be exposed on the surface of the uppermost layer of the nitride semiconductor laminate.

[0078] (10) In the nitride semiconductor stack according to this embodiment, the thickness of the underlayer is preferably 50 nm or more and 200 nm or less. This further enhances the effect of depositing a nitride semiconductor layer having a lattice constant that is approximately equal to that of the substrate due to the step-terrace structure described above.

[0079] (11) In the nitride semiconductor laminate according to this embodiment, an Al y Ga (1-y) It is preferable to have an electron barrier layer formed of N (0.7≦y≦1). This allows a two-dimensional electron gas (2DEG) to be formed at the interface between the GaN layer and the electron barrier layer, improving the electrical characteristics of the nitride semiconductor laminate.

[0080] (12) In the nitride semiconductor stack according to this embodiment, the underlayer and the GaN layer formed on the nitride semiconductor substrate preferably have a pseudomorphic lattice match with the nitride semiconductor substrate. This further reduces the lattice mismatch between the nitride semiconductor substrate and each of the upper layers, further improving the electrical characteristics of the nitride semiconductor laminate. This means:

[0081] (13) In the nitride semiconductor laminate according to this embodiment, an Al z Ga (1-z) It is preferable to provide a compositionally graded layer formed of N (0≦z≦1) in which the profile of the Al composition z changes linearly. This further reduces the lattice mismatch between the underlayer 12 and the GaN layer 13, reducing threading dislocations and improving the quality of the nitride semiconductor laminate.

[0082] (14) In the nitride semiconductor stack according to this embodiment, it is preferable that the interface between the GaN layer and the compositionally graded layer has misfit dislocations in the same direction as the miscut direction of the nitride semiconductor substrate. In the nitride semiconductor stack according to this embodiment, misfit dislocations preferably exist in the same plane. This allows the strain at the interface between the underlayer 12 and the GaN layer 13 to be released without generating threading dislocations extending in a direction perpendicular to the substrate 11. As a result, the quality of the two-dimensional hole gas (2DHG) is improved.

[0083] 2. Specific Examples of Embodiments A high electron mobility transistor (HEMT, hereinafter referred to as HEMT), which is a power device using a nitride semiconductor stack according to a first embodiment of the present disclosure, will be described with reference to Fig. 12. Fig. 12 is a cross-sectional view showing an example of the configuration of a HEMT 100. As shown in FIG. 12, the HEMT 100 includes a substrate 11, an underlayer 12, a GaN layer 13, and an electron barrier layer 14, and a gate electrode 101, a source electrode 102, and a drain electrode 103 are provided on the electron barrier layer 14. The substrate 11, the base layer 12, and the GaN layer 13 of the HEMT 100 are the same as the layers constituting the nitride semiconductor stack 1 described in the first embodiment, and the electron barrier layer 14 is the same as the electron barrier layer 14 constituting the nitride semiconductor stack 1A described in the first modification of the first embodiment, so detailed description thereof will be omitted.

[0084] The thicknesses of the underlayer 12, the GaN layer 13, and the electron barrier layer 14 of the HEMT 100 are, for example, 900 nm, 15 nm, and 7.5 nm, respectively. At the interface between the GaN layer 13 and the electron barrier layer 14, a sheet-like two-dimensional electron gas (2DEG) layer with a high concentration of electrons is formed. Such a two-dimensional electron gas (2DEG) layer has high saturated electron mobility, allowing the HEMT 100 to achieve high frequency characteristics. Furthermore, the HEMT 100 is a power device that combines low on-resistance due to high electron mobility with high breakdown voltage characteristics due to a wide band gap. In the MT100, the two-dimensional electron gas (2DEG) layer serves as the channel of the HEMT100. [Example]

[0085] Example 1 The nitride semiconductor stack of the present disclosure will be described below with reference to examples and comparative examples, but the nitride semiconductor stack of the present disclosure is not limited to these examples. The substrate used was a (0001) AlN single crystal substrate with a thickness of 550 μm, a miscut direction in the <10-10> direction, and a miscut angle of 0.2 degrees. Next, an AlN layer, a homoepitaxial layer similar to a conventional underlayer, was formed on the substrate. The AlN layer was formed to a thickness of 900 nm in an environment of 1200°C. At this time, the ratio of the supply rate of the Group III element source gas to the supply rate of the nitrogen source gas (V / III ratio) was set to 50. The growth rate of the AlN layer was 0.5 μm / hr. Trimethylaluminum (TMAl) was used as the Al source, and ammonia (NH3) was used as the N source.

[0086] On this AlN layer, Al with Al composition x=1 was grown to a thickness of 100 nm by metal organic chemical vapor deposition under an environment of 800°C and 200 mbar pressure. x Ga (1-x) The underlayer was formed by depositing N (i.e., AlN) with a V / III ratio of 3000 and a growth rate of 0.5 μm / hr.

[0087] Next, a 15-nm-thick GaN layer was formed on the underlayer by metalorganic vapor phase epitaxy at a temperature of 800°C and a pressure of 150 mbar. The V / III ratio was set to 3650, and the growth rate of the GaN layer was set to 1.0 μm / hr.

[0088] Observation of the nitride semiconductor stack obtained as described above with an atomic force microscope (AFM) revealed that a step-terrace structure was formed on the surface of the GaN layer, which was the layer farthest from the nitride semiconductor substrate. The terrace edges had a wave-like shape with amplitude in the <10-10> direction and extended in the <11-20> direction, perpendicular to the <10-10> direction. The distance W1 between adjacent peaks of this wave-shaped terrace edge was 400 nm. Furthermore, the distance W2 between a perpendicular line L3 drawn between a first line L1 connecting two peaks of the wave-shaped terrace edge ETE and a second line L2 connecting two valleys of the wave-shaped terrace edge ETE was 100 nm. Furthermore, the angle θ between one peak of the wave-shaped terrace edge and two adjacent valleys across this peak was 90 degrees.

[0089] <Example 2> The nitride semiconductor stack of Example 2 was formed in the same manner as in Example 1, except that the temperature for forming the underlayer was 600°C. In the nitride semiconductor stack of Example 2, the distance W1 between the peaks at the terrace edge was 300 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ formed between one peak at the terrace edge and two adjacent valleys across that peak was 70 degrees.

[0090] Example 3 The nitride semiconductor stack of Example 3 was formed in the same manner as in Example 1, except that the temperature for forming the underlayer was 1000°C. In the nitride semiconductor stack of Example 3, the distance W1 between the peaks at the terrace edge was 800 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ formed between one peak at the terrace edge and two adjacent valleys across that peak was 120 degrees.

[0091] Example 4 The nitride semiconductor stack of Example 4 was formed in the same manner as in Example 1, except that the formation pressure of the underlayer was 50 mbar. In the nitride semiconductor stack of Example 4, the distance W1 between the peaks at the terrace edge was 500 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ formed between one peak at the terrace edge and the two valleys adjacent to that peak was 100 degrees.

[0092] <Example 5> The nitride semiconductor stack of Example 5 was formed in the same manner as in Example 1, except that the formation pressure of the underlayer was 500 mbar. In the nitride semiconductor stack of Example 5, the distance W1 between the peaks at the terrace edge was 350 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ between one peak at the terrace edge and the two valleys adjacent to that peak was 80 degrees.

[0093] Example 6 Al that makes up the underlayer x Ga (1-x) The Al composition x of N is set to 0.5 (i.e., Al 0.5 Ga 0.5 The nitride semiconductor stack of Example 6 was formed in the same manner as in Example 1, except that (N) was used. In the nitride semiconductor stack of Example 6, the distance W1 between the peaks at the terrace edge was 400 nm. The distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. The angle θ formed between one peak at the terrace edge and two valleys adjacent to that peak was 90 degrees.

[0094] Example 7 Al that makes up the underlayer x Ga (1-x) The Al composition x of N is set to 0.75 (i.e., Al 0.75 Ga 0.25 The nitride semiconductor stack of Example 7 was formed in the same manner as in Example 1, except that (N) was used. In the nitride semiconductor stack of Example 7, the distance W1 between the peaks at the terrace edge was 400 nm. The distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. The angle θ formed between one peak at the terrace edge and two valleys adjacent to that peak was 90 degrees.

[0095] Example 8 The nitride semiconductor stack of Example 8 was formed in the same manner as in Example 1, except that the GaN layer was formed at a temperature of 600°C. In the nitride semiconductor stack of Example 8, the distance W1 between the peaks at the terrace edge was 430 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ formed between one peak at the terrace edge and the two valleys adjacent to that peak was 95 degrees.

[0096] Example 9 The nitride semiconductor stack of Example 9 was formed in the same manner as in Example 1, except that the GaN layer was formed at a temperature of 900°C. In the nitride semiconductor stack of Example 9, the distance W1 between the peaks at the terrace edge was 710 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ formed between one peak at the terrace edge and the two valleys adjacent to that peak was 110 degrees.

[0097] Example 10 The nitride semiconductor stack of Example 10 was formed in the same manner as in Example 1, except that a substrate with a miscut angle of less than 0.1 degrees was used. In the nitride semiconductor stack of Example 10, the distance W1 between the peaks at the terrace edge was 700 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 200 nm. Furthermore, the angle θ formed between one peak at the terrace edge and the two valleys adjacent to that peak was 80 degrees.

[0098] Example 11 The nitride semiconductor stack of Example 11 was formed in the same manner as in Example 1, except that a substrate with a miscut angle of 0.1 degrees was used. In the nitride semiconductor stack of Example 11, the distance W1 between the peaks at the terrace edge was 550 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 150 nm. Furthermore, the angle θ formed between one peak at the terrace edge and the two valleys adjacent to that peak on either side was 85 degrees.

[0099] Example 12 The nitride semiconductor stack of Example 12 was formed in the same manner as in Example 1, except that a substrate with a miscut angle of 0.4 degrees was used. In the nitride semiconductor stack of Example 12, the distance W1 between the peaks at the terrace edge was 350 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 50 nm. Furthermore, the angle θ between one peak at the terrace edge and the two valleys adjacent to that peak was 120 degrees.

[0100] Example 13 The nitride semiconductor stack of Example 13 was formed in the same manner as in Example 1, except that a substrate with a miscut angle of 0.5 degrees was used. In the nitride semiconductor stack of Example 13, the distance W1 between the peaks at the terrace edge was 250 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 30 nm. Furthermore, the angle θ formed between one peak at the terrace edge and the two valleys adjacent to that peak was 130 degrees.

[0101] <Comparative Example 1> The nitride semiconductor stack of Comparative Example 1 was formed in the same manner as in Example 1, except that the temperature for forming the underlayer was 550°C. In the nitride semiconductor stack of Comparative Example 1, a step-terrace structure was not formed on the surface of the GaN layer, and a surface structure formed by island-like crystal growth was formed. For this reason, the distances W1, W2, and the angle θ described above in the nitride semiconductor stack were indistinguishable.

[0102] <Comparative Example 2> A nitride semiconductor stack of Comparative Example 2 was formed in the same manner as in Example 1, except that the temperature for forming the underlayer was set to 1100°C. In the nitride semiconductor stack of Comparative Example 2, a step-terrace structure with linear terrace edges was formed on the surface of the GaN layer. Therefore, the distance W1, the distance W2, and the angle θ in the nitride semiconductor stack could not be determined.

[0103] <Comparative Example 3> The nitride semiconductor stack of Comparative Example 3 was formed in the same manner as in Example 1, except that the formation pressure of the underlayer was 30 mbar. In the nitride semiconductor stack of Comparative Example 3, the distance W1 between the peaks at the terrace edge was 900 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ between one peak at the terrace edge and the two valleys adjacent to that peak was 135 degrees.

[0104] <Comparative Example 4> The nitride semiconductor stack of Comparative Example 4 was formed in the same manner as in Example 1, except that the formation pressure of the underlayer was 600 mbar. In the nitride semiconductor stack of Comparative Example 4, the distance W1 between the peaks at the terrace edge was 200 nm. Furthermore, the distance W2 of the perpendicular line L3 drawn between a first line L1 connecting the two peaks at the terrace edge and a second line L2 connecting the two valleys was 100 nm. Furthermore, the angle θ between one peak at the terrace edge and the two valleys adjacent to that peak was 50 degrees.

[0105] <Comparative Example 5> A nitride semiconductor stack of Comparative Example 5 was formed in the same manner as in Example 1, except that the underlayer was formed by sputtering. In the nitride semiconductor stack of Comparative Example 5, a step-terrace structure was not formed on the surface of the GaN layer, and a surface structure formed by island-like crystal growth was formed. For this reason, the distances W1, W2, and the angle θ described above in the nitride semiconductor stack were indistinguishable.

[0106] <Comparative Example 6> Al that makes up the underlayer x Ga (1-x) The Al composition x of N is set to 0.4 (i.e., Al 0.4 Ga 0.6 In the nitride semiconductor stack of Comparative Example 6, which was the same as Example 1 except that the step-terrace structure was not formed on the surface of the GaN layer, but rather a surface structure formed by island-like crystal growth was formed. Therefore, the distances W1, W2, and the angle θ described above in the nitride semiconductor stack were indistinguishable.

[0107] <Comparative Example 7> A nitride semiconductor stack of Comparative Example 7 was formed in the same manner as in Example 1, except that the GaN layer was formed at a temperature of 1000°C. In the nitride semiconductor stack of Comparative Example 7, a step-terrace structure was not formed on the surface of the GaN layer, and a surface structure formed by island-like crystal growth was formed. For this reason, the distances W1, W2, and the angle θ described above in the nitride semiconductor stack were indistinguishable.

[0108] [evaluation] The carrier mobility, carrier concentration, and sheet resistance of the above-mentioned nitride semiconductor laminate were measured. For the measurements, electrodes were formed by laminating V, Al, Ni, and Au in this order at the four corners of the GaN layer, which was the outermost layer of the sample, which was cut into 10 mm sections. The electrodes were then formed by electron beam (EB) deposition, and the sample was then heat-treated at 850°C. These samples were measured by the Van der Pauw method using a Hall measurement device manufactured by Toyo Corporation, with a magnetic field of 0.5 gauss applied. The evaluation results are shown in Table 1 below.

[0109] [Table 1]

[0110] As shown in Table 1, Al was grown by metalorganic vapor phase epitaxy under the conditions of temperature between 600°C and 1000°C and pressure between 50 mbar and 500 mbar. x Ga (1-x)The nitride semiconductor stacks of the examples, which had an underlayer formed of N (0.5≦x≦1) and a GaN layer formed on the underlayer in an environment with a temperature of 600°C or higher and 900°C or lower, had improved carrier mobility and carrier concentration and reduced sheet resistance, resulting in improved electrical properties, compared to the nitride semiconductor stacks of the comparative examples formed by methods other than the examples.

[0111] Furthermore, in Examples 1 and 10-13, in which an underlayer and a GaN layer were formed under specified conditions, the evaluation results were better and the electrical properties were improved compared to Comparative Examples 3 and 4, in which an underlayer and a GaN layer were not formed under specified conditions, regardless of the substrate miscut angle. In particular, as can be seen from Examples 1, 11, and 12, the electrical properties were particularly improved when the substrate miscut angle was 0.1 or more and 0.4 or less. Furthermore, from each example, it was found that the electrical characteristics were significantly improved when the distance W1 between the peaks at the terrace edge was 300 nm or more and 800 nm or less, the distance W2 of the perpendicular line L3 drawn between the first line L1 connecting the two peaks at the terrace edge and the second line L2 connecting the two valleys was 50 nm or more and 150 nm or less, and the angle θ between one peak at the terrace edge and the two valleys adjacent to it on either side was 60 degrees or more and 120 degrees or less.

[0112] Although the embodiments of the present disclosure have been described above, the above embodiments are merely examples of devices and methods for embodying the technical ideas of the present disclosure, and the technical ideas of the present disclosure do not specify the materials, shapes, structures, arrangements, etc. of the components. The technical ideas of the present disclosure can be modified in various ways within the technical scope defined by the claims. [Explanation of symbols]

[0113] 1, 1A, 1B Nitride semiconductor laminate 11 Nitride semiconductor substrate (substrate) 12 Base layer 13 GaN layer 14 Electron barrier layer 15 Compositionally graded layer 16 AlN layer 101 gate electrode 102 Source electrode 103 Drain electrode

Claims

1. Al is deposited on a nitride semiconductor substrate containing Al by metal organic chemical vapor deposition under an environment of a temperature of 600°C to 1000°C and a pressure of 50 mbar to 500 mbar. ｘ Ga （１－ｘ） forming an underlayer made of N (0.5≦x≦1); forming a GaN layer on the underlayer in an environment at a temperature of 600°C or higher and 900°C or lower; A method for manufacturing a nitride semiconductor stack comprising:

2. An aluminum nitride single crystal substrate is used as the nitride semiconductor substrate. The method for producing the nitride semiconductor laminate according to claim 1 .

3. The nitride semiconductor substrate has a miscut angle of 0.1 degrees or more and 0.4 degrees or less. The method for producing the nitride semiconductor laminate according to claim 1 or 2.

4. The nitride semiconductor substrate has a miscut direction in the <10-10> direction. The method for producing the nitride semiconductor laminate according to claim 1 or 2.

5. a nitride semiconductor substrate containing Al; an Al nitride semiconductor substrate; ｘ Ga （１－ｘ） an underlayer formed of N (0.5≦x≦1); a GaN layer disposed on the underlayer; Equipped with The surface of the layer farthest from the nitride semiconductor substrate opposite to the nitride semiconductor substrate has a step-terrace structure in which steps, which are stepped portions, and flat terraces are repeated in the miscut direction of the nitride semiconductor substrate, and the terrace edges, which are the ends of the terraces, have a wave shape that has amplitude in the miscut direction of the nitride semiconductor substrate and extends in a direction perpendicular to the miscut direction of the nitride semiconductor substrate. Nitride semiconductor stack.

6. The distance between adjacent peaks of the wavy terrace edge is 300 nm or more and 800 nm or less. The nitride semiconductor stack according to claim 5 .

7. a distance between a first straight line connecting two peaks of the wavy terrace edge and a second straight line connecting two valleys of the wavy terrace edge is 50 nm or more and 150 nm or less; The nitride semiconductor stack according to claim 5 .

8. an angle θ formed between one peak at the terrace edge of the wave-shaped shape and two adjacent valleys sandwiching the peak is equal to or greater than 60 degrees and equal to or less than 120 degrees; The nitride semiconductor stack according to claim 5 .

9. A diffusion layer containing Al and Ga is provided at the interface between the underlayer and the GaN layer, the diffusion layer being formed by diffusing Al from the underlayer into the GaN layer and diffusing Ga from the GaN layer into the underlayer. The nitride semiconductor stack according to claim 5 .

10. The nitride semiconductor substrate is an aluminum nitride single crystal substrate. The nitride semiconductor stack according to claim 5 .

11. The miscut angle of the nitride semiconductor substrate is 0.1 degrees or more and 0.4 degrees or less. The nitride semiconductor stack according to claim 5 or 10.

12. The miscut direction of the nitride semiconductor substrate is the <10-10> direction. The nitride semiconductor stack according to claim 5 or 10.

13. The thickness of the underlayer is 50 nm or more and 200 nm or less. The nitride semiconductor stack according to claim 5 or 10.

14. an Al layer disposed on the GaN layer; ｙ Ga （１－ｙ） An electron barrier layer formed of N (0.7≦y≦1) The nitride semiconductor stack according to claim 5 .

15. The underlayer and the GaN layer formed on the nitride semiconductor substrate are pseudomorphic to the nitride semiconductor substrate. The nitride semiconductor stack according to claim 5 .

16. an Al layer provided between the underlayer and the GaN layer; ｚ Ga （１－ｚ） The composition gradient layer is formed of N (0≦z≦1) and has a linear change in the profile of the Al composition z. The nitride semiconductor stack according to claim 5 .

17. The interface between the GaN layer and the composition gradient layer has misfit dislocations in the same direction as the miscut direction of the nitride semiconductor substrate. The nitride semiconductor stack according to claim 16.

18. The misfit dislocations are in the same plane. The nitride semiconductor stack according to claim 17.

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