Multilayer ceramic electronic component, and method of manufacturing multilayer ceramic electronic component

Abstract

To provide a multilayer ceramic electronic component which has sufficient bias characteristics while having high lifetime characteristics, and a manufacturing method thereof.SOLUTION: A multilayer ceramic capacitor 100 comprises an element assembly 10 including: a plurality of dielectric layers 11 laminated along a first axis; a plurality of internal electrode layers 12a and 12b each disposed between the dielectric layers which are adjacent along the first axis; and an intermediate region 40 disposed between the dielectric layer and the internal electrode layer. The dielectric layer contains a compound, which is expressed by a general formula: ABO3-α (0≤α≤1), and has a perovskite structure, and additive elements. The internal electrode layer contains a base metal element and copper as a main component, and an intermediate region contains the additive elements and copper. The additive elements include one or more selected from among holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium and ytterbium.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a multilayer ceramic electronic component and a method for manufacturing a multilayer ceramic electronic component. [Background technology]

[0002] Multilayer ceramic electronic components have a structure in which dielectric layers and internal electrode layers are alternately stacked, and examples of multilayer ceramic electronic components include multilayer ceramic capacitors (MLCCs).

[0003] With the increasing multi-function and high performance of electronic devices such as mobile phones, there is a demand for multilayer ceramic electronic components such as multilayer ceramic capacitors to be more compact, have higher capacitance, and offer improved reliability. To meet these demands, attempts have been made to add various elements and compounds to the dielectric layers, for example.

[0004] For example, Patent Document 1 discloses a compound having the composition formula Ba as the main component. (1-x) Ca x A dielectric ceramic composition is disclosed that contains barium calcium titanate represented by TiO3 (x is 0.05 or more and 0.1 or less) and contains an oxide of Y and an oxide of Yb as accessory components.

[0005] The dielectric ceramic composition disclosed in Patent Document 1 is said to have high insulation resistance and satisfy the EIA standard X9R characteristics for the temperature characteristics of capacitance (capacitance-temperature characteristics), i.e., the characteristic that the rate of change in capacitance from -55°C to 175°C is within ±15%. [Prior art documents] [Patent documents]

[0006] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-114751 Summary of the Invention [Problem to be solved by the invention]

[0007] However, thinner dielectric layers are required for multilayer ceramic electronic components to achieve smaller sizes and higher capacities, which increases the electric field strength applied to the dielectric layers. Therefore, thinner dielectric layers tend to be more susceptible to damage when a voltage is applied to the dielectric layers, shortening the life of the multilayer ceramic electronic components.

[0008] In order to ensure the life of multilayer ceramic electronic components, the addition of additive elements to the dielectric layer material has been investigated. However, there is a problem in that the bias characteristics deteriorate when additive elements are added to the dielectric layer material and the amount of additive element added is large.

[0009] An object of the present disclosure is to provide a multilayer ceramic electronic component that has a long lifespan and sufficient bias characteristics. [Means for solving the problem]

[0010] The multilayer ceramic electronic component of the present disclosure includes a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is a compound of the general formula ABO 3-α (0≦α≦1), containing a compound having a perovskite structure and an additive element, the internal electrode layers contain a base metal element and copper as main components, the intermediate region contains the additional element and copper, The additional element includes one or more selected from the group consisting of holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, and ytterbium. [Effects of the Invention]

[0011] According to the present disclosure, it is possible to provide a multilayer ceramic electronic component that has a long lifespan and sufficient bias characteristics. [Brief explanation of the drawings]

[0012] [Figure 1] FIG. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 2] FIG. 2 is a cross-sectional view illustrating a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 3] FIG. 3 is a cross-sectional view illustrating a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 4] FIG. 4 is a cross-sectional view illustrating details of an element body according to one embodiment of the present disclosure. [Figure 5] FIG. 5 is an explanatory diagram of a method for determining whether or not there is an intermediate region. [Figure 6] FIG. 6 is a flowchart of a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 7] FIG. 7 is a diagram illustrating a method for manufacturing a multilayer ceramic capacitor according to one embodiment of the present disclosure. [Figure 8] Figure 8 shows an example of the measurement results of three-dimensional atom probe analysis. DETAILED DESCRIPTION OF THE INVENTION

[0013] Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. In this specification and the drawings, components having substantially the same functional configurations may be designated by the same reference numerals to avoid redundant description. The drawings also show, where appropriate, mutually orthogonal X-, Y-, and Z-axes. The X-, Y-, and Z-axes define a fixed coordinate system fixed to a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component. When the multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component, has an approximately rectangular parallelepiped outer shape, the X-, Y-, and Z-axes may correspond to the length, width, and height of the capacitor. Hereinafter, a multilayer ceramic electronic component of this embodiment will be described using a multilayer ceramic capacitor, which is an example of a multilayer ceramic electronic component.

[0014] [Multilayer ceramic electronic components] (1) Structure of multilayer ceramic electronic components FIG. 1 is a partial cross-sectional perspective view illustrating a multilayer ceramic capacitor 100. FIGS. 2 and 3 are cross-sectional views illustrating the multilayer ceramic capacitor. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes an element body 10 having a substantially rectangular parallelepiped shape. Two opposing surfaces of the element body 10 are referred to as the top and bottom surfaces, and four surfaces connecting the top and bottom surfaces are referred to as side surfaces. Typically, the surface facing the circuit board when the multilayer ceramic capacitor is mounted on the circuit board is referred to as the bottom surface, but this is not limited to this. In the example illustrated in FIGS. 1 to 3, a first external electrode 20a and a second external electrode 20b are provided on two opposing side surfaces of the element body 10, namely, a first side surface 10a and a second side surface 10b (see FIG. 2). The first external electrode 20a extends from the first side surface 10a to the four adjacent surfaces. The second external electrode 20b extends from the second side surface 10b to four adjacent surfaces. However, the first external electrode 20a and the second external electrode 20b are spaced apart from each other. The external electrodes may be provided on any surface of the element body 10, not limited to the two opposing side surfaces.

[0015] The stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked is the first axis, and in Figures 1 to 3, the first axis, which is the stacking direction in which the dielectric layers 11 and the internal electrode layers 12 are stacked, is the Z axis, which is the direction in which the internal electrode layers face each other.

[0016] The axis perpendicular to the first axis, which is the stacking direction, is the second axis. In Figures 1 to 3, the second axis perpendicular to the first axis, which is the stacking direction, is the X-axis. The second axis is along the length direction of the element body 10, and is the axis along the direction in which the first side surface 10a and the second side surface 10b of the element body 10 face each other, and the direction in which the first external electrode 20a and the second external electrode 20b face each other.

[0017] The third axis is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis. The third axis is an axis along the width of the internal electrode layer 12. In Figures 1 to 3, the third axis, which is an axis perpendicular to the first axis, which is the stacking direction, and perpendicular to the second axis, is the Y axis, which is an axis along the direction in which the third side surface 10c and the fourth side surface 10d, which are the two side surfaces other than the first side surface 10a and the second side surface 10b, of the four side surfaces of the element body 10, face each other (see Figure 3). The X axis, Y axis, and Z axis are orthogonal to each other.

[0018] The stacking direction is not limited to the Z direction and can be any direction. Therefore, for example, the first axis, which is the stacking direction, may be the X axis in the X direction or the Y axis in the Y direction.

[0019] In this specification, for the purpose of explaining a general embodiment, figures illustrating a specific embodiment may be used, and the content described using the coordinate axis system used in the embodiment is applied to the general embodiment by replacing it with a general coordinate system in which the stacking direction is the first axis. For example, what is described as the X-axis, Y-axis, and Z-axis used in Figures 1 to 3 in a specific embodiment, where the stacking direction coincides with the Z-axis, can be replaced with the second axis, third axis, and first axis in the general embodiment.

[0020] The element body 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The internal electrode layers 12 include a plurality of first internal electrode layers 12a and a plurality of second internal electrode layers 12b. The first internal electrode layers 12a and the second internal electrode layers 12b are alternately stacked. The edges of the first internal electrode layers 12a extend to the surface of the element body 10 on which the first external electrode 20a is provided, that is, the first side surface 10a in the examples of FIGS. 1 to 3. The edges of the second internal electrode layers 12b extend to the surface of the element body 10 on which the second external electrode 20b is provided, that is, the second side surface 10b in the examples of FIGS. 1 to 3. As a result, the first internal electrode layers 12a and the second internal electrode layers 12b are alternately electrically connected to the first external electrode 20a and the second external electrode 20b. Therefore, the multilayer ceramic capacitor 100 has a configuration in which capacitor units are stacked. In addition, in a laminate of dielectric layers 11 and internal electrode layers 12, the internal electrode layers 12 are arranged as the outermost layers in the lamination direction, and the outer surfaces of the laminate in the lamination direction, i.e., the upper and lower surfaces in the examples of FIGS. 1 to 3, are covered with cover layers 13. The cover layers 13 are mainly composed of a ceramic material. For example, the composition of the cover layers 13 may be the same as or different from that of the dielectric layers 11. Note that the configuration is not limited to that shown in FIGS. 1 to 3 as long as the first internal electrode layers 12a and the second internal electrode layers 12b are exposed in different regions on the surface of the laminate and are conductive to different external electrodes. The different regions on the surface of the laminate may be respective surface regions on opposing surfaces of the laminate, respective surface regions on adjacent surfaces of the laminate, or different surface regions on the same surface of the laminate. As long as the different external electrodes are spaced apart from each other, the first internal electrode layers 12a and the second internal electrode layers 12b may extend from the surfaces exposed in the surface region of the laminate to other surfaces.

[0021] As will be described in detail later, the element body 10 has a plurality of intermediate regions 40 (see FIG. 4) between the dielectric layers 11 and the internal electrode layers 12. The intermediate regions 40 are not shown in FIGS. 1 to 3.

[0022] The size of the multilayer ceramic capacitor 100 is not particularly limited, and may be, for example, 0.25 mm long, 0.125 mm wide, and 0.125 mm high; 0.4 mm long, 0.2 mm wide, and 0.2 mm high; 0.6 mm long, 0.3 mm wide, and 0.3 mm high; 1.0 mm long, 0.5 mm wide, and 0.5 mm high; 3.2 mm long, 1.6 mm wide, and 1.6 mm high; or 4.5 mm long, 3.2 mm wide, and 2.5 mm high. However, the above-listed sizes of the multilayer ceramic capacitor 100 are merely examples, and the multilayer ceramic capacitor is not limited to these sizes. The size of the multilayer ceramic capacitor 100 may be, for example, length > width ≥ height; width > length ≥ height; height > length ≥ width; or height > width ≥ length. Note that, for example, length represents the size in the X-axis direction, width represents the size in the Y-axis direction, and height represents the size in the Z-axis direction.

[0023] As described above, the multilayer ceramic capacitor 100 of this embodiment has a plurality of dielectric layers 11 stacked along the Z-axis, which is a first axis, and a plurality of internal electrode layers 12 arranged between adjacent dielectric layers 11 along the first axis. Furthermore, the multilayer ceramic capacitor 100 of this embodiment has an intermediate region 40 arranged between the dielectric layers 11 and the internal electrode layers 12. The dielectric layers 11, the internal electrode layers 12, and the intermediate region 40 will be described below. (2) Dielectric layer The dielectric layer 11 is a compound represented by the general formula ABO 3-α (0≦α≦1) and contains a compound having a perovskite structure and an additive element. (2-1) Components contained in the dielectric layer (Compounds with perovskite structure) When a compound having a perovskite structure has a stoichiometric composition, α, which indicates the amount of deviation from the stoichiometric composition, is 0 and is represented by the general formula ABO3. In the compound having a perovskite structure represented by the above general formula, α may be greater than 0 and equal to or less than 1. In other words, the compound having a perovskite structure represented by the above general formula may have more oxygen deficiencies than the stoichiometric composition.

[0024] Compounds with a perovskite structure include barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), and BaTiO3, which forms a perovskite structure. 1-x-y Ca x Sr y Ti 1-z Zr z One or more types selected from O3 (0≦x≦1, 0≦y≦1, 0≦z≦1) and the like can be used.

[0025] Ba 1-x-y Ca x Sr y Ti 1-z Zr z O3 includes barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, and barium calcium titanate zirconate. Note that any compound having a perovskite structure may contain oxygen vacancies.

[0026] The dielectric layer 11 preferably contains barium titanate as a compound having a perovskite structure, as this has particularly excellent dielectric properties. The dielectric layer 11 may contain barium titanate as a main component, or may be composed solely of barium titanate. Barium titanate has excellent dielectric properties, such as an extremely high dielectric constant and low dielectric loss. Therefore, when the dielectric layer 11 contains barium titanate as a compound having a perovskite structure, the capacitance of the multilayer ceramic capacitor 100 can be increased. In this specification, the term "main component" refers to the component that is contained in the largest amount by substance ratio among the components contained.

[0027] Furthermore, the compound having a perovskite structure may be contained as a main component in the dielectric layer 11. For example, the dielectric layer 11 may contain 50 mol % or more, or 90 mol % or more of the compound having a perovskite structure. (Additional element) The dielectric layer 11 may further contain an additive element. The additive element may be contained in a simple state, or may form a compound with other elements.

[0028] The dielectric layers 11 containing an additive element can extend the life of the multilayer ceramic capacitor 100. That is, the dielectric layers 11 containing an additive element can improve the life characteristics of the multilayer ceramic capacitor.

[0029] It has been confirmed that the life characteristics of the multilayer ceramic capacitor can be improved by increasing the amount of additive element added to the dielectric layers 11, and the same tendency is observed even when the dielectric layers 11 are made thinner. However, it is preferable to select the amount of additive element added depending on the firing conditions when manufacturing the multilayer ceramic capacitor and the required life characteristics, etc., so that the additive element is not unevenly distributed within the dielectric layers 11.

[0030] The proportion of the additive element contained in the dielectric layer 11 is not particularly limited, and can be added and contained to the extent that an intermediate region, which will be described later, is formed depending on the life characteristics required of the multilayer ceramic capacitor.

[0031] The type of additive element contained in the dielectric layer 11 is not particularly limited, but the additive element may be one or more selected from holmium (Ho), yttrium (Y), samarium (Sm), dysprosium (Dy), europium (Eu), gadolinium (Gd), terbium (Tb), erbium (Er), thulium (Tm), ytterbium (Yb), etc. (Additives) The dielectric layer 11 may contain an additive as an optional component.

[0032] The additives that can be contained in the dielectric layer 11 are not particularly limited, but examples thereof include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements (scandium (Sc), cerium (Ce), and neodymium (Nd)); oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); and glasses containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon. (2-2) Thickness of the dielectric layer The thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase the capacitance, it is preferably 1.0 μm or less, and more preferably 0.8 μm or less.

[0033] The lower limit of the thickness of the dielectric layer 11 is not particularly limited, but from the viewpoint of improving productivity and yield, it can be set to, for example, 0.2 μm or more.

[0034] The thickness of the dielectric layer 11 is evaluated in a cross section including a first axis parallel to the stacking direction. For example, it is preferable to evaluate the thickness in either a cross section including a second axis perpendicular to the stacking direction or a cross section including a third axis perpendicular to the stacking direction and perpendicular to the second axis, because of ease of polishing and measurement. The multilayer ceramic capacitor 100 is polished in the third axis direction for the former, and in the second axis direction for the latter. Ten layers are selected from the center, top, and bottom of the exposed dielectric layers 11 in the first axis direction. The thickness of the center of each selected dielectric layer is then measured, and the measured thickness is defined as the thickness of each dielectric layer 11. Furthermore, the average thickness of all the selected and evaluated dielectric layers 11 can be defined as the thickness of the dielectric layers 11 in the multilayer ceramic capacitor 100.

[0035] In the example shown in Figures 1 and 2, the first axis, which is the lamination direction, is the Z-axis direction, so this is an example in which the multilayer ceramic capacitor 100 is polished along the Y-axis, which is the third axis, to expose the XZ plane on which the dielectric layers 11 and the internal electrode layers 12 are laminated.

[0036] In this case, of the exposed XZ plane, ten dielectric layers 11 located in the center along the Z axis, which is the first axis, and ten dielectric layers 11 located at the top and bottom along the Z axis, which is the first axis, are selected. At this time, the selected dielectric layers 11 are selected from within the capacitive section 14.

[0037] Then, for the selected dielectric layer 11, the thickness is measured at the center along the X-axis, which is the second axis, and this is defined as the thickness of the dielectric layer 11. Using the same procedure, the thicknesses of all the selected dielectric layers 11 are measured, and the average value of the thicknesses of all the measured dielectric layers 11 can be used as the thickness of the dielectric layer 11 in the evaluated multilayer ceramic capacitor 100.

[0038] The thickness of the dielectric layer 11 described above and the thickness of the internal electrode layer 12 described later are measured from a cross-sectional observation image or the like of the multilayer ceramic capacitor 100. Since the intermediate region 40 does not appear clearly on the outside, the thickness of the dielectric layer 11 described above and the thickness of the internal electrode layer 12 described above are measured based on the boundary between the dielectric layer 11 and the internal electrode layer 12, which can be visually confirmed. Therefore, the thickness of the dielectric layer 11 described above and the thickness of the internal electrode layer 12 described later also include the intermediate region 40. (3) Internal electrode layers (3-1) Components contained in the internal electrode layer First, each part of the multilayer ceramic capacitor 100 related to the internal electrode layers 12 will be described.

[0039] 2, the region where the first internal electrode layer 12a connected to the first external electrode 20a and the second internal electrode layer 12b connected to the second external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, the region where capacitance is generated is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers connected to different external electrodes face each other.

[0040] The region where the first internal electrode layers 12a connected to the first external electrode 20a face each other in the stacking direction without the second internal electrode layer 12b connected to the second external electrode 20b intervening therebetween is referred to as the first end margin 15a. The region where the second internal electrode layers 12b connected to the second external electrode 20b face each other in the stacking direction without the first internal electrode layer 12a connected to the first external electrode 20a intervening therebetween is referred to as the second end margin 15b. Each end margin is a region where internal electrode layers connected to the same external electrode face each other in the stacking direction without the internal electrode layer connected to a different external electrode intervening therebetween. The first end margin 15a and the second end margin 15b are regions that do not generate capacitance.

[0041] The side margin 16 is a region provided outside the capacitive section 14 in a direction along the Y-axis in the example of Fig. 3, which is a third axis perpendicular to the stacking direction and perpendicular to the second axis. In other words, the side margin 16 is an outer region adjacent to the capacitive section 14 when viewed from the stacking direction, and is an outer region adjacent to the capacitive section 14 on the side where the internal electrode layer 12 is not drawn out. The side margin 16 is also a region that does not generate electrical capacitance.

[0042] Normally, the sintering temperature of the material of the dielectric layers 11, which mainly contains ceramic, is higher than the sintering temperature of the material of the internal electrode layers 12, which mainly contains metal. For this reason, when a laminate in which the dielectric green sheets that will become the dielectric layers 11 and the metal conductive pastes that will become the internal electrode layers 12 are alternately arranged to form a predetermined shape is fired at a temperature determined based on the sintering temperature of the dielectric layers 11, over-sintering of the internal electrode layers 12 may occur. If over-sintering of the internal electrode layers 12 occurs, some or all of the internal electrode layers 12 will become discontinuous spheres or the like, and the desired film shape cannot be achieved due to a decrease in continuity, which may also cause problems such as a decrease in capacitance.

[0043] Therefore, a method can be considered in which the firing conditions when firing the laminate are selected to prevent over-sintering of the internal electrode layers 12. However, there is a risk that the additive element, which is one or more selected from holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, ytterbium, etc., added to the dielectric layers 11, may not be sufficiently diffused within the dielectric layers 11 and may be unevenly distributed within the dielectric layers 11, resulting in a deterioration in bias characteristics, etc. However, if the amount of the additive element added to the dielectric layers 11 is reduced in order to prevent the uneven distribution of the additive element within the dielectric layers 11, there is a risk that the life characteristics of the multilayer ceramic capacitor 100 may not be sufficiently improved.

[0044] Therefore, the inventors of the present invention conducted studies and confirmed that when the internal electrode layers 12 contain copper, an intermediate region containing the additive element originating from the dielectric layer 11 and the copper originating from the internal electrode layer 12 is formed between the internal electrode layer 12 and the dielectric layer 11, which was not formed when the conventional internal electrode layer 12 did not contain copper. According to the studies of the inventors of the present invention, the presence of such an intermediate region in the multilayer ceramic capacitor increases the amount of the additive element in the dielectric layer 11, and prevents uneven distribution of the additive element in the dielectric layer 11 even when the laminate is fired under conditions that do not cause over-sintering of the internal electrode layers 12. At the same time, the effect of copper allows excess additive element to be collected in the intermediate region. Therefore, the multilayer ceramic capacitor 100 can have a long life characteristic and sufficient bias characteristic.

[0045] Therefore, the internal electrode layer 12 can contain a base metal element and copper as the main component. The proportion of copper contained in the internal electrode layer 12 is not particularly limited, and can be added and contained to the extent that the above-mentioned intermediate region is formed. Details of the intermediate region will be described later.

[0046] The internal electrode layers 12 may contain, in addition to copper, components used in the internal electrode layers of multilayer ceramic capacitors. The internal electrode layers 12 may contain, as the main component, in particular, a base metal such as nickel (Ni) or tin (Sn) or an alloy containing one or more selected from the group of base metals, in other words, the largest component in terms of substance amount.

[0047] The internal electrode layers 12 preferably contain nickel, as this provides excellent electrical properties and allows costs to be reduced, and may contain nickel as a main component.

[0048] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main component of both the first internal electrode layer 12a and the second internal electrode layer 12b may be nickel. (3-2) Thickness of the internal electrode layer The thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of miniaturizing the multilayer ceramic capacitor 100 while increasing the number of layers to increase the capacitance, it is preferably 0.8 μm or less, and more preferably 0.6 μm or less.

[0049] The lower limit of the thickness of the internal electrode layer 12 is not particularly limited, but from the viewpoint of increasing productivity and yield, it can be 0.4 μm or more when forming by printing a metal conductive paste, which is a slurry for the internal electrode layer, by a printing method such as screen printing or gravure printing. For example, when forming by a thin film process such as sputtering or vapor deposition, it can be 0.1 μm or more, which is thinner than the thickness by the printing method.

[0050] The thickness of the internal electrode layer 12 is evaluated in a cross section including a first axis equal to the lamination direction, similar to the evaluation of the thickness of the dielectric layer 11. For example, it is preferable to evaluate in either a cross section that further includes a second axis set perpendicular to the lamination direction, or a cross section that further includes a third axis set perpendicular to the lamination direction and also perpendicular to the second axis, in terms of ease of polishing and measurement.

[0051] The multilayer ceramic capacitor 100 is polished so that the cross section can be seen, and 10 layers are selected from the central portion, the upper end portion, and the lower end portion in the first axial direction of the exposed internal electrode layers 12. Then, the thickness of the central portion of each selected internal electrode layer 12 is measured, and the measured thickness is defined as the thickness of each internal electrode layer 12. Furthermore, the average value of the thicknesses of all the selected and evaluated internal electrode layers 12 can be defined as the thickness of the internal electrode layers 12 in the multilayer ceramic capacitor 100.

[0052] 1 and 2, a sample is prepared by polishing a multilayer ceramic capacitor 100 along the Y axis to expose an XZ plane where dielectric layers 11 and internal electrode layers 12 are laminated. Then, from the XZ plane exposed by polishing, ten internal electrode layers 12 located in the center along the Z axis, which is the first axis, and ten internal electrode layers 12 located at the top and bottom along the Z axis, which is the first axis, are selected. The selected internal electrode layers 12 are selected from within the capacitive section 14.

[0053] Then, for the selected internal electrode layer 12, the thickness is measured at the center along the X-axis, which is the second axis, and this is defined as the thickness of the internal electrode layer 12. Using the same procedure, the thicknesses of all the selected internal electrode layers 12 are measured, and the average value of the thicknesses of all the measured internal electrode layers 12 can be used as the thickness of the internal electrode layer 12 in the evaluated multilayer ceramic capacitor 100. (4) Intermediate Area 4 shows an enlarged view of a portion of the dielectric layer 11 and the internal electrode layer 12 of the element body 10. FIG. 4 is an enlarged view of, for example, region C in FIG.

[0054] The multilayer ceramic capacitor 100 has an intermediate region 40 containing an additive element and copper between the internal electrode layers 12 and the dielectric layers 11. Because Fig. 4 is a schematic diagram, the intermediate region 40 is shown as a continuous layer with a constant thickness, but this is not limited to this form. The intermediate region 40 may be discontinuous, for example, and the thickness may vary depending on the location.

[0055] As shown in FIG. 4, the intermediate region 40 can be arranged so as to include, for example, the surface of the internal electrode layer 12 as its boundary.

[0056] The presence or absence of the intermediate region 40 can be confirmed by elemental mapping using energy dispersive X-ray spectroscopy (EDX) analysis with a transmission electron microscope (TEM) or a scanning transmission electron microscope (STEM). The evaluation is performed on a cross section including a first axis parallel to the stacking direction. For example, it is preferable to evaluate either a cross section including a second axis perpendicular to the stacking direction or a cross section including a third axis perpendicular to the stacking direction and perpendicular to the second axis, because this facilitates polishing and measurement. In the example shown in FIGS. 1 and 2 , the first axis, which is the stacking direction, is the Z-axis. Therefore, the multilayer ceramic capacitor 100 is polished along the Y-axis, which is the third axis, to expose the XZ plane where the dielectric layers 11 and the internal electrode layers 12 are stacked. The sample is then sliced ​​to a thickness of approximately 0.1 μm, and the presence or absence of the intermediate region 40 can be confirmed by TEM / STEM-EDX analysis of the sample.

[0057] For example, from the element mapping results obtained, the presence or absence of the intermediate region 40 can be determined by observing the portion where the dielectric layer 11 and the internal electrode layer 12 are laminated.

[0058] When the above sample was subjected to TEM / STEM-EDX analysis, it was possible to confirm the distribution regions of elements contained in the dielectric material contained in the dielectric layer 11, as shown in Fig. 5(A). Fig. 5(A) shows a titanium distribution region 51 in the case where the dielectric layer 11 contains barium titanate as a dielectric material.

[0059] Furthermore, when the above sample is subjected to TEM / STEM-EDX analysis, it is possible to confirm the distribution region of the base metal element contained as the main component in the internal electrode layer 12, as shown in Fig. 5(B). Fig. 5(B) shows a nickel distribution region 52 in the case where the internal electrode layer 12 contains nickel as the base metal, as an example.

[0060] 5(C), in the element mapping result for copper, a copper distribution region 53 exists beyond a nickel distribution region 52, which is a distribution region of a base metal element contained as a main component in the internal electrode layer 12. In this case, it is observed that the copper distribution region 53 extends to a titanium distribution region 51, which is a distribution region of an element contained in the dielectric contained in the dielectric layer 11.

[0061] 5(D), in the element mapping results for the additive element, the distribution region 54 of the additive element exists beyond the distribution region 51 of titanium, which is the distribution region of the element contained in the dielectric contained in the dielectric layer 11. In this case, it is observed that the distribution region 54 of the additive element extends to the distribution region 52 of nickel, which is the distribution region of the base metal element contained as a main component in the internal electrode layer 12.

[0062] That is, when element mapping of copper and the additive element is performed, it can be determined that an intermediate region 40 is formed when a region where a copper distribution region 53 and an additive element distribution region 54 overlap is generated near the boundary where the dielectric layer 11 and the internal electrode layer 12 are laminated. With regard to the additive element, a bias in the element distribution may be observed in the additive element distribution region 54, and the additive element concentration may be higher in a region 541 corresponding to the intermediate region 40 shown in FIG. 5(C) than in the dielectric layer 11 portion.

[0063] The intermediate region 40 only needs to contain the additive element and copper, and the state of the additive element and copper in the intermediate region 40 is not particularly limited. In the intermediate region 40, the additive element and copper may form a compound, or the additive element and copper may each form a compound with another element, etc. Furthermore, in the intermediate region 40, at least one of the additive element and copper may exist in an elemental state without forming a compound.

[0064] When the dielectric layer 11 contains an additive element, the life characteristics of the multilayer ceramic capacitor 100 can be improved.

[0065] However, if firing conditions are selected to avoid over-sintering of the internal electrode layers 12, the additive elements may not be sufficiently diffused within the dielectric layers 11 and may be unevenly distributed, resulting in a deterioration in bias characteristics. Furthermore, if the content of the additive elements in the dielectric layers 11 is reduced in order to prevent uneven distribution of the additive elements within the dielectric layers 11, there is a risk that the lifespan of the multilayer ceramic capacitor 100 may not be sufficiently reduced.

[0066] In contrast, by adding copper to the internal electrode layers 12, it is believed that the copper traps the additive elements that would conventionally be unevenly distributed in the dielectric layers 11 after firing, thereby forming the intermediate region 40. By forming the intermediate region 40, it is possible to suppress uneven distribution of the additive elements without reducing the amount of additive element added in the dielectric layers 11. Therefore, by forming the intermediate region 40, it is possible to improve the life characteristics of the multilayer ceramic capacitor 100 while suppressing a decrease in the bias characteristics. Therefore, it is possible to provide a multilayer ceramic capacitor 100 that has both high life characteristics and sufficient bias characteristics. (Composition of the intermediate region) The intermediate region 40 is not particularly limited in composition as long as it contains the additive element and copper. From the viewpoint of particularly improving the life characteristics and bias characteristics of the internal electrode layer 12, it is preferable that the average atomic percentage of the additive element content in the intermediate region 40 is 0.13 at% or more and 0.67 at% or less, and the average atomic percentage of the copper content is 0.32 at% or more and 3.15 at% or less, when three-dimensional atom probe analysis is performed.

[0067] When three-dimensional atom probe analysis is performed, the average atomic ratio of the copper content in the intermediate region 40 may be, for example, 0.5 to 3.0 times the average atomic ratio of the copper content in the central portion along the Z axis, which is the first axis of the adjacent internal electrode layer 12.

[0068] If the average atomic percentage of the content of elements contained in the intermediate region 40 is analyzed and quantified by energy dispersive X-ray (EDX) analysis using a transmission electron microscope (TEM) or scanning transmission electron microscope (STEM), the average atomic percentage of the content of elements in portions of the sample other than the intermediate region 40 may also be included, which may result in reduced analytical accuracy. This is because, when preparing a sample for TEM / STEM observation, the sample is thinned, and there is a possibility that the intermediate region 40 may not be accurately evaluated if portions other than the intermediate region 40 are included on the back side of the sample, etc. For this reason, when analyzing the content of elements contained in the intermediate region 40, three-dimensional atom probe (3DAP) analysis is used to quantify the concentration.

[0069] The average atomic percentage of the added element and copper content in the intermediate region 40 can be evaluated by the procedure described in the examples, and therefore the description thereof will be omitted here.

[0070] The average value of the atomic number ratio of the copper content in the center along the Z-axis, which is the first axis, of the internal electrode layer 12 adjacent to the intermediate region 40 can also be evaluated using the 3D atom probe. The evaluation can be performed at the center along the X-axis and Y-axis, which are the second and third axes, of the multilayer ceramic capacitor 100, and at the center along the Z-axis, which is the first axis, of the internal electrode layer 12 to be evaluated.

[0071] [Manufacturing method for multilayer ceramic capacitors] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. Fig. 6 is a flowchart 60 illustrating an example of the method for manufacturing the multilayer ceramic capacitor 100. Fig. 7 is a diagram illustrating an example of the method for manufacturing the multilayer ceramic capacitor 100.

[0072] The method for manufacturing the multilayer ceramic capacitor of this embodiment can include a dielectric green sheet forming step, an internal electrode layer forming step, and a firing step. The method for manufacturing the multilayer ceramic capacitor of this embodiment will be described below, including any steps other than the above steps. (1) Raw material powder preparation process (S1) In the raw material powder preparation step, first, a dielectric material is prepared for forming the dielectric layer 11. The A-site elements and B-site elements contained in the dielectric layer 11 are usually ABO 3-α The dielectric layer 11 contains a sintered body of particles with a (0≦α≦1) structure. For example, barium titanate is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. Barium titanate can generally be obtained by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate. Various methods have been known for synthesizing the ceramic that is the main component of the dielectric layer 11, including the solid-phase method, the sol-gel method, and the hydrothermal method. Any of these methods can be used in this embodiment.

[0073] In the raw material powder preparation process, additives such as simple additive elements or compounds containing additive elements can be added to the obtained ceramic raw material powder. Depending on the purpose, specific additive compounds can also be added to the obtained ceramic raw material powder. Examples of additive compounds include oxides containing one or more elements selected from zirconium (Zr), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), and rare earth elements (scandium (Sc), cerium (Ce), and neodymium (Nd)); oxides containing one or more elements selected from cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), and silicon (Si); and glasses containing one or more elements selected from cobalt, nickel, lithium, boron, sodium, potassium, and silicon.

[0074] For example, a ceramic material can be prepared by wet-mixing a ceramic raw material powder with an additive containing an additive element or an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. By the above steps, a raw material powder that is a dielectric material is obtained. (2) Dielectric green sheet forming process (S2) Next, in the dielectric green sheet forming step, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer can be added to the obtained raw material powder and wet-mixed. Note that in the raw material powder preparation step (S1), a binder or the like may be added when mixing the ceramic raw material powder and the like, and then wet-mixed. Other necessary additives can also be added to the raw material powder and the slurry for forming the dielectric green sheet.

[0075] In the dielectric green sheet forming step, the obtained slurry is used to apply it to a substrate by, for example, a die coater method or a doctor blade method, and then dried to form a dielectric green sheet 71. The substrate is, for example, a polyethylene terephthalate (PET) film. Figures illustrating the dielectric green sheet forming step are omitted.

[0076] Therefore, the dielectric green sheet forming step (S2) is carried out by forming a dielectric green sheet using a compound represented by the general formula ABO 3-α (0≦α≦1), a dielectric green sheet containing a compound having a perovskite structure and an additive element can be formed.

[0077] As already explained, the additional element can include one or more selected from holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, and ytterbium. (3) Internal electrode layer formation process (S3) As described above, the first internal electrode layer 12a and the second internal electrode layer 12b can be mainly composed of base metal elements such as nickel (Ni) and tin (Sn) or alloys containing these. The internal electrode layer 12 contains copper in addition to the above main components.

[0078] The main component of the first internal electrode layer 12a and the main component of the second internal electrode layer 12b may be the same or different. For example, the main component of both the first internal electrode layer 12a and the second internal electrode layer 12b may be nickel.

[0079] The metal conductive paste for forming the precursors of the first internal electrode layer 12a and the second internal electrode layer 12b can be prepared by kneading the main component selected from the above, copper, an organic binder, and a solvent. Copper may be added in a simple form or in a compound form. Furthermore, as the base metal element or copper, an alloy containing the base metal element as the main component and copper may be used, or the surface of the base metal element as the main component or a compound containing the base metal element may be coated with copper or a copper compound before addition. The internal electrode paste may also contain various additives such as dispersants in required amounts, as needed.

[0080] In the internal electrode layer forming process, as illustrated in FIG. 7(A), a metal conductive paste for forming an internal electrode layer containing an organic binder can be printed on the surface of a dielectric green sheet 71 by screen printing, gravure printing, or the like. As a result, a first internal electrode layer pattern 72a for the first internal electrode layer 12a or a second internal electrode layer pattern 72b for the second internal electrode layer 12b is arranged on the surface of the dielectric green sheet 71. Ceramic particles can also be added as a co-material to the metal conductive paste. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. When ceramic particles are added as a co-material, they can be added when kneading the metal conductive paste. The method for forming the internal electrode layer is not limited to printing, and plating, vacuum deposition, sputtering, or CVD may also be used.

[0081] Therefore, in the internal electrode layer forming step (S3), an internal electrode layer pattern containing a base metal element and copper as main components is formed on the surface of the dielectric green sheet formed in the dielectric green sheet forming step, thereby producing a ceramic green sheet.

[0082] Alternatively, a dielectric pattern paste for the reverse pattern layer can be obtained by adding a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder to the raw material powder, which is the dielectric material obtained in the raw material powder preparation step, and kneading the mixture in a roll mill. As shown in Fig. 7(A), a dielectric pattern paste can be printed on a peripheral area of ​​a dielectric green sheet 71 where the internal electrode layer pattern is not printed, thereby arranging a dielectric pattern 73 and filling in any steps with the internal electrode layer pattern. The dielectric green sheet 71 on which the internal electrode layer pattern and the dielectric pattern 73 are printed is referred to as a lamination unit. (4) Lamination process (S4) In the lamination step (S4), as illustrated in Fig. 7(B), the lamination units can be laminated so that the internal electrode layers and the dielectric layers alternate, and so that the edges of the internal electrode layers are alternately exposed at both end faces in the length direction of the dielectric layers and alternately drawn out to a pair of external electrodes. Specifically, a dielectric green sheet 71 on which a first internal electrode layer pattern 72a and a dielectric pattern 73 are printed and a dielectric green sheet 71 on which a second internal electrode layer pattern 72b and a dielectric pattern 73 are printed are laminated in this order. For example, the number of layers in the lamination unit can be set to 100 to 500. (5) Crimping process (S5) In the compression bonding step, a predetermined number of cover sheets, for example, 2 to 10 layers, can be laminated on the top and bottom of the laminate in which the lamination units are stacked, and then thermally compressed. (6) Singulation process (S6) In the singulation step, the compressed body can be singulated. As a singulation method, an existing method such as dicing with a dicer or laser cutting can be used as appropriate. (7) Firing process (S7) In the firing step, the singulated laminate, i.e., the laminate formed by stacking ceramic green sheets, can be fired. The firing conditions are not particularly limited, but it is preferable to raise the temperature from 600°C to the firing temperature at a rate of 30,000°C / h or more and to hold the temperature at the firing temperature for 10 seconds or less.

[0083] By setting the temperature rising rate to 30,000° C. / h or more and the holding time at the firing temperature to 10 seconds or less, it is possible to prevent the internal electrode layers 12 from being over-sintered.

[0084] The upper limit of the temperature rise rate is not particularly limited, but is preferably 50,000° C. / h or less. The lower limit of the holding time at the firing temperature is also not particularly limited, but if the temperature rise zone and temperature drop zone of the firing furnace are adjacent to each other, they will interfere with each other and the firing temperature (maximum temperature) will become unstable. To avoid this, the holding time is preferably 2 seconds or more, and more preferably 5 seconds or more.

[0085] The firing temperature is not particularly limited, but is preferably 1000° C. or higher and 1400° C. or lower. By firing at the above firing temperature, the internal electrode layers 12 can be prevented from being over-sintered, and the diffusion of the additive elements in the dielectric layers 11 can be sufficiently promoted.

[0086] The firing atmosphere in the firing step is not particularly limited. For example, the oxygen partial pressure is 10 -10 atm over 10 -8 The reducing atmosphere can be set to a value of atm or less. (8) External electrode formation process (S8) In the external electrode forming step, the first external electrode 20a and the second external electrode 20b can be formed by plating etc. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0087] The above steps are merely an example, and the method for manufacturing the multilayer ceramic capacitor of this embodiment is not limited to the above-described embodiment.

[0088] [Other embodiments] Although the embodiments have been described in detail above, the present disclosure is not limited to the specific embodiments, and various modifications and changes are possible within the scope of the claims.

[0089] For example, the above embodiment is applied to a multilayer ceramic capacitor having two terminal electrodes as external electrodes, but may be applied to a multilayer ceramic capacitor having three or more terminals.

[0090] Although the above embodiment describes a multilayer ceramic capacitor as an example of a multilayer ceramic electronic component, the present disclosure is applicable to multilayer ceramic electronic components in general, such as chip varistors and chip thermistors. [Example]

[0091] The present invention will be explained below by giving specific examples, but the present invention is not limited to these examples. (1) Evaluation method (1-1) Presence or absence of intermediate areas The presence or absence of the intermediate region 40 was confirmed by element mapping using energy dispersive X-ray (EDX) analysis with a transmission electron microscope (TEM) or a scanning transmission electron microscope (STEM). For the evaluation, since the first axis, which is the stacking direction in Figures 1 and 2, is the Z-axis direction, the multilayer ceramic capacitor 100 was polished along the Y-axis, which is the third axis, as shown in Figures 1 and 2, to prepare a sample in which the XZ plane where the dielectric layers 11 and the internal electrode layers 12 were stacked was exposed. The sample was then sliced ​​to a thickness of about 0.1 µm, and the presence or absence of the intermediate region 40 was confirmed by TEM / STEM-EDX analysis.

[0092] Specifically, from the obtained element mapping results, the locations where the dielectric layers 11 and the internal electrode layers 12 were stacked were observed.

[0093] When the intermediate region 40 is formed, as shown in FIG. 5(C), in the mapping result for copper, a copper distribution region 53 exists beyond a nickel distribution region 52, which is a distribution region of base metal elements contained as a main component in the internal electrode layer 12. In this case, it is observed that the copper distribution region 53 extends to a titanium distribution region 51, which is a distribution region of elements contained in the dielectric contained in the dielectric layer 11. Furthermore, as shown in FIG. 5(D), in the mapping result for the additional element, a distribution region 54 of the additional element exists beyond a titanium distribution region 51, which is a distribution region of elements contained in the dielectric contained in the dielectric layer 11. In this case, it is observed that the additional element distribution region 54 extends to a nickel distribution region 52, which is a distribution region of base metal elements contained as a main component in the internal electrode layer 12.

[0094] That is, when elemental mapping of copper and the added element is performed, if a region where the copper distribution region 53 and the added element distribution region 54 overlap is found near the boundary where the dielectric layer 11 and the internal electrode layer 12 are stacked, it is determined that an intermediate region 40 is formed.

[0095] In contrast, if at least one of the copper distribution region 53 and the additive element distribution region 54 could not be confirmed, or if there was no overlapping region between the copper distribution region 53 and the additive element distribution region 54, it was determined that an intermediate region had not been formed.

[0096] For the evaluation, the multilayer ceramic capacitor 100 was polished, and two internal electrode layers 12 located at the center along the Z axis (the first axis) and two internal electrode layers 12 located at the top and bottom along the Z axis (the first axis) were selected from the exposed XZ surface. The above-mentioned observation of the vicinity of the interface between the selected internal electrode layers 12 and the dielectric layer 11 was then carried out over the entire outer periphery of the internal electrode layers 12. When selecting the internal electrode layers 12 from the top, center, and bottom along the Z axis (the first axis), the selection was made so that the number of first internal electrode layers 12a and second internal electrode layers 12b was the same. The selected internal electrode layers 12 were selected from within the capacitance section 14.

[0097] In Table 1, in the "Intermediate Region" column, if the intermediate region 40 was confirmed at any of the locations evaluated, it is marked "Present," and if the intermediate region was not confirmed at any of the locations evaluated on the sample, it is marked "Absent." (1-2) Average atomic percentage of added elements and copper content in the intermediate region The composition of the intermediate region 40 was analyzed using a three-dimensional atom probe (LEAP5000XS manufactured by AMETEK Corporation) along the Z-axis, which is the first axis, from the dielectric layer 11 to the internal electrode layer 12. The three-dimensional atom probe is a method for measuring three-dimensional atomic distribution by applying a high voltage to the sample, detecting ions that are field evaporated from the surface of the sample with a mass spectrometer, detecting each detected ion continuously in the depth direction, and arranging the ions in the order in which they were detected.

[0098] For the measurement, as shown in Figures 1 and 2, the multilayer ceramic capacitor 100 was polished along the Y axis to prepare a sample with the XZ plane where the dielectric layers 11 and the internal electrode layers 12 were laminated exposed, and the exposed XZ plane was evaluated.

[0099] An example of the measurement results is shown in Fig. 8. As shown in Fig. 8, by performing three-dimensional atom probe analysis, the content ratio of each element contained in the dielectric layer 11 and the internal electrode layer 12 can be measured and calculated.

[0100] Among the measurement results, an intersection 81 between a graph of the content ratio of oxygen resulting from compounds having a perovskite structure contained in the dielectric layer 11 and a graph of elements resulting from the metal contained as a main component in the internal electrode layer 12 can be used as a reference. In the graph shown in FIG. 8, the element resulting from the metal contained as a main component in the internal electrode layer 12 is nickel. A line L81 is a line 3 nm away from the line L80 passing through the intersection 81 and within the region of the dielectric layer 11, and a line L82 is a line 4 nm away from the region of the dielectric layer 11 than the line L81. The region sandwiched between the lines L81 and L82 is defined as an intermediate region 40.

[0101] In Comparative Examples 1 to 9, no intermediate region was formed, but the intermediate region was defined in the same manner and evaluation was performed.

[0102] The average atomic percentages of the added elements and copper contained in the intermediate region 40 were then calculated. For the evaluation, the multilayer ceramic capacitor 100 was polished, and one dielectric layer located in the center along the Z axis (the first axis) of the exposed XZ surface was selected, along with one dielectric layer located at the top and one dielectric layer located at the bottom along the Z axis (the first axis). Three-dimensional atom probe analysis was then performed from the selected dielectric layer 11 to the internal electrode layer 12 located above along the first axis, and the average atomic percentages of the holmium and copper contained in all elements detected in the intermediate region 40 were calculated. The selected dielectric layer 11 was selected from within the capacitive section 14.

[0103] The average atomic percentages of the holmium and copper contents within all the evaluated intermediate regions 40 are shown in Table 1 in the "Ho" and "Cu" columns under "Average atomic percentages of element contents in intermediate regions." (1-3) Accelerated life test, accelerated life judgment From each experimental example, 100 samples were selected and each of the selected samples underwent an accelerated life test (HALT). In the accelerated life test, a voltage of 6 V was applied to each of the 100 samples manufactured under the same conditions at 125°C, and the time to failure was measured.

[0104] The insulation resistance was measured every hour, and if the insulation resistance value fell below 10 MΩ, it was determined to be a failure.

[0105] The time until failure of the sample of Comparative Example 1 is set to 100, and the values ​​are normalized.

[0106] When the accelerated life result was 100 or more, the accelerated life judgment was evaluated as ◯. When the accelerated life result was 95 or more but less than 100, the accelerated life judgment was evaluated as △. When the accelerated life result was less than 95, the accelerated life judgment was evaluated as ×.

[0107] The accelerated life evaluation is graded as ◯, △, and × in descending order, and when the accelerated life evaluation is ◯ or △, it can be said that the multilayer ceramic capacitor has excellent life characteristics. (1-4) DC bias characteristics, DC bias characteristics determination The capacitance change rate was calculated from the measured no-load capacitance C0 and the capacitance C3V when DC 3V was applied according to the following formula (1).

[0108] Capacitance change rate = (C3V - C0) / C0 × 100 (1) In measuring the DC bias characteristics, ten multilayer ceramic capacitors manufactured under the same conditions were evaluated for each experimental example, and the average value of the DC bias characteristics of the ten multilayer ceramic capacitors was used as the DC bias characteristic of the multilayer ceramic capacitor for that experimental example.

[0109] In the "DC bias characteristics" column of Table 1, the capacitance change rate in Comparative Example 1 is shown as a normalized value, with the rate being 100.

[0110] When the result of the DC bias characteristic was 100 or more, the DC bias characteristic was evaluated as ◯. When the result of the DC bias characteristic was 85 or more but less than 100, the DC bias characteristic was evaluated as △. When the result of the DC bias characteristic was less than 85, the DC bias characteristic was evaluated as ×.

[0111] The DC bias characteristics are evaluated in the order of ◯, △, and ×, and when the DC bias characteristics are evaluated as ◯ or △, the multilayer ceramic capacitor can be said to have sufficient bias characteristics. (1-5) Overall Judgment In the overall evaluation, if the accelerated life evaluation is ◯ and the DC bias characteristic evaluation is ◯, it is marked as ◯, and if either or both of the accelerated life evaluation and the DC bias characteristic evaluation are △ but do not include ×, it is marked as △. In addition, in the overall evaluation, if at least one of the accelerated life evaluation or the DC bias characteristic evaluation is ×, it is marked as ×. [Example 1] A multilayer ceramic capacitor was manufactured according to the flow chart 60 shown in FIG.

[0112] Specifically, first, barium titanate powder, polyvinyl butyral (PVB) resin, solvent, plasticizer, glass powder containing SiO2 as a sintering aid, and holmium oxide (Ho2O3) were wet mixed to obtain a slurry (raw material powder preparation process).

[0113] The obtained slurry was applied onto a base film, and the slurry applied onto the base film was dried to obtain a dielectric green sheet (dielectric green sheet forming step).

[0114] Next, a copper-containing organometallic complex solution was added to and mixed with Ni powder, the main component metal element, to prepare a mixed powder. To the prepared mixed powder, binders such as ethyl cellulose (EC) or polyvinyl butyral (PVB) resin, a solvent, and a plasticizer were added and wet-mixed to obtain a metal conductive paste for forming internal electrode layers. The metal conductive paste was then printed on a partial area of ​​the surface of the dielectric green sheets to form internal electrode layer patterns containing nickel and copper, which are base metal elements as main components, on each of the dielectric green sheets, thereby producing ceramic green sheets that become laminate units (internal electrode layer forming process). These ceramic green sheets have dielectric green sheets and internal electrode layer patterns formed on the surfaces of the dielectric green sheets.

[0115] Next, 500 laminate units were laminated to form a laminate (lamination step).

[0116] Then, the laminate was pressure-bonded and then cut into individual pieces to obtain chip-shaped green laminates (pressure-bonding step, cutting step).

[0117] Next, the chip-shaped green laminate was subjected to a degreasing treatment in a nitrogen atmosphere at 500°C.

[0118] After the degreasing treatment, a metal conductive paste containing a metal filler mainly composed of nickel, co-materials, binder, solvent, etc. was applied to the green laminate from both end faces to each side face to form a base layer, and then dried. Thereafter, the green laminate with the base layer of the external electrodes applied was placed in a firing furnace and fired (firing process).

[0119] In the firing process, the temperature was raised from 600°C to 1300°C at the rate shown in Table 1, and held at the firing temperature of 1300°C for 10 seconds. During the temperature rise, the supply amount of the green laminate and the oxygen partial pressure were adjusted to prevent a sudden change in the firing atmosphere due to gas generated from the green laminate and to prevent cracks from occurring in the fired product.

[0120] After firing, the first external electrode 20a and the second external electrode 20b were formed on the laminate by plating (external electrode forming step).

[0121] The obtained multilayer ceramic capacitor had a chip shape of 1.0 mm × 0.5 mm × 0.5 mm, a dielectric layer 11 thickness of 0.8 μm, an internal electrode layer 12 thickness of 0.6 μm, and the number of laminated layers was 500. The thicknesses of the dielectric layer 11 and the internal electrode layer 12 were evaluated by the procedure already described.

[0122] The obtained multilayer ceramic capacitor was evaluated as described above, and the evaluation results are shown in Table 1. [Examples 2 to 15] Multilayer ceramic capacitors were manufactured using the same procedures as in Example 1, except that the amounts of holmium and copper added to the raw materials for the dielectric layers 11 and internal electrode layers 12 were changed so that the holmium and copper contents in the intermediate region would be the values ​​shown in Table 1. The obtained multilayer ceramic capacitors were also evaluated as described above. The evaluation results are shown in Table 1. [Comparative Examples 1 to 8] Multilayer ceramic capacitors were manufactured using the same procedures as in Example 1, except that the amounts of holmium and copper added to the raw materials for the dielectric layers 11 and internal electrode layers 12 were changed so that the holmium and copper contents in the intermediate region would be the values ​​shown in Table 1. The obtained multilayer ceramic capacitors were also evaluated as described above. The evaluation results are shown in Table 1. Comparative Example 9 A multilayer ceramic capacitor was manufactured in the same manner as in Example 1, except that the rate of temperature increase from 600° C. to 1300° C. in the firing step was set to the rate shown in Table 1.

[0123] When the cross section of the obtained multilayer ceramic capacitor was observed, it was confirmed that the internal electrode layers 12 were discontinuous spheres and not in a film shape. In other words, over-sintering had occurred in the internal electrode layers 12. For this reason, it was not possible to accurately evaluate whether or not there was an intermediate region, so in Table 1, the intermediate region is marked as "absent."

[0124] The obtained multilayer ceramic capacitor was evaluated as described above, and the evaluation results are shown in Table 1.

[0125] [Table 1] According to the results shown in Table 1, in Examples 1 to 15 in which an intermediate region is formed, the overall evaluation was ◯ or △, confirming that the samples have high life characteristics and sufficient bias characteristics.

[0126] Aspects of the present disclosure are, for example, as follows.

[0127] <1> a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is a compound of the general formula ABO 3-α(0≦α≦1), containing a compound having a perovskite structure and an additive element, the internal electrode layers contain a base metal element and copper as main components, the intermediate region contains the additional element and copper, The multilayer ceramic electronic component, wherein the additive element includes one or more elements selected from the group consisting of holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, and ytterbium.

[0128] <2> When a three-dimensional atom probe analysis is performed, the average atomic percentage of the content of the additive element in the intermediate region is 0.13 at% or more and 0.67 at% or less, and the average atomic percentage of the content of copper is 0.32 at% or more and 3.15 at% or less. <1> The multilayer ceramic electronic component according to claim 1.

[0129] <3> The internal electrode layers contain nickel. <1> or <2> The multilayer ceramic electronic component according to claim 1.

[0130] <4> the dielectric layer contains barium titanate as the compound having a perovskite structure; <1> from <3> 10. The multilayer ceramic electronic component according to claim 9, wherein

[0131] <5> General formula ABO 3-α a dielectric green sheet forming step of forming a dielectric green sheet containing a compound having a perovskite structure represented by (0≦α≦1) and an additive element; an internal electrode layer forming step of forming an internal electrode layer pattern containing a base metal element and copper as a main component on a surface of the dielectric green sheet to produce a ceramic green sheet; a firing step of firing a laminate obtained by stacking the ceramic green sheets, the additional element includes one or more selected from holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, and ytterbium; In the firing step, the temperature is increased from 600°C to the firing temperature at a rate of 30,000°C / h or more, and the firing temperature is maintained for 10 seconds or less.

[0132] <6> The firing temperature is 1000°C or higher and 1400°C or lower. <5> 10. A method for producing the multilayer ceramic electronic component according to claim 9. [Explanation of symbols]

[0133] 100 Multilayer ceramic capacitors 10 Base 10a First side 10b Second side 11 Dielectric layer 12 Internal electrode layer 12a 1st internal electrode layer 12b Second internal electrode layer 13 Cover Layer 14 Capacity part 15a First End Margin 15b Second End Margin 16 Side Margin 20a 1st external electrode 20b 2nd external electrode C area 40 Intermediate area 51 Titanium distribution area 52 Nickel distribution area 53 Copper distribution area 54 Distribution area of ​​added elements 541 area 60 Flowchart S1 Raw material powder preparation process S2 Dielectric green sheet forming process S3 Internal electrode layer formation process S4 Lamination process S5 Crimping process S6 singulation process S7 Firing process S8 External electrode formation process 71 Dielectric green sheet 72a First internal electrode layer pattern 72b Second internal electrode layer pattern 73 Dielectric Pattern 81 intersection L80 straight line L81 straight line L82 straight line

Claims

1. a plurality of dielectric layers stacked along a first axis; a plurality of internal electrode layers each disposed between adjacent dielectric layers along the first axis; an intermediate region disposed between the dielectric layer and the internal electrode layer, The dielectric layer is formed of a material having the general formula ABO ３－α (0≦α≦1), containing a compound having a perovskite structure and an additive element, the internal electrode layers contain a base metal element and copper as main components, the intermediate region contains the additional element and copper, The additive element includes at least one element selected from the group consisting of holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, and ytterbium.

2. 2. The multilayer ceramic electronic component according to claim 1, wherein, when a three-dimensional atom probe analysis is performed, the average atomic percentage of the content of the additive element in the intermediate region is 0.13 at% or more and 0.67 at% or less, and the average atomic percentage of the content of copper in the intermediate region is 0.32 at% or more and 3.15 at% or less.

3. 3. The multilayer ceramic electronic component according to claim 1, wherein the internal electrode layers contain nickel.

4. 3. The multilayer ceramic electronic component according to claim 1, wherein the dielectric layers contain barium titanate as the compound having a perovskite structure.

5. General formula ABO ３－α a dielectric green sheet forming step of forming a dielectric green sheet containing a compound having a perovskite structure represented by (0≦α≦1) and an additive element; an internal electrode layer forming step of forming an internal electrode layer pattern containing a base metal element and copper as a main component on a surface of the dielectric green sheet to produce a ceramic green sheet; a firing step of firing a laminate obtained by stacking the ceramic green sheets, the additional element includes one or more selected from holmium, yttrium, samarium, dysprosium, europium, gadolinium, terbium, erbium, thulium, and ytterbium; In the firing step, the temperature is increased from 600°C to the firing temperature at a temperature increase rate of 30,000°C / h or more, and the firing temperature is maintained for 10 seconds or less.

6. 6. The method for producing a multilayer ceramic electronic component according to claim 5, wherein the firing temperature is 1000°C or higher and 1400°C or lower.

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