Semiconductor device and regulator device

Abstract

To reduce current consumption and to reliably start up a regulator when the power supply is started.SOLUTION: This semiconductor device includes a regulator unit that generates an operating voltage, and a microcontroller unit that operates by receiving the operating voltage. The regulator unit includes a first regulator that generates a first operating voltage, a second regulator that generates a second operating voltage, a low-voltage detection circuit that detects a rise in the second operating voltage smaller than a rise in the first operating voltage, and a startup circuit that starts up the second regulator in response to a rise in the first operating voltage and starts up the second regulator in response to a detection result of the low-voltage detection circuit.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a regulator device. Regarding. [Background technology]

[0002] A regulator startup circuit is used to start the regulator in a multi-chip package (MCP) that mounts a microprocessor unit (MCU) and a regulator chip in a single package. MCPs can integrate different LSIs into a single package, offering many advantages, such as reducing the number of components, lowering costs, and allowing the use of processes with different voltage resistances. In automotive products, by incorporating into the MCP a regulator that generates voltages such as 5V / 3V for the MCU from a 12V battery voltage, it becomes possible to connect the battery directly to the MCU power supply.

[0003] Conventionally, in order to reduce power consumption, MCPs have been known in which a control circuit and a timer are mounted on a regulator chip, and the regulator chip is equipped with a first regulator that supplies a first power supply voltage to the control circuit and the timer, and a second regulator that supplies a second power supply voltage for the MCU. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2002-91794 Summary of the Invention [Problem to be solved by the invention]

[0005] However, in the conventional MCPs described above, there is a problem that the second regulator does not start due to malfunction of the regulator control circuit (for example, an indeterminate signal at the time of startup of the regulator control circuit, a failure of the power-on reset circuit, etc.), and as a result, there is a risk of falling into a so-called deadlock state in which the MCU cannot be started. The present invention provides a semiconductor device that can reduce current consumption and can reliably start the regulator when the power is started. [Means for solving the problem]

[0006] A semiconductor device according to the present invention includes a regulator unit that generates an operating voltage and a microcontroller unit that operates by receiving the operating voltage. The regulator unit includes a first regulator that generates a first operating voltage, a second regulator that generates a second operating voltage, a low-voltage detection circuit that detects when a rise in the second operating voltage is smaller than a rise in the first operating voltage, and a startup circuit that starts the second regulator in response to a rise in the first operating voltage and also starts the second regulator in response to a detection result of the low-voltage detection circuit. [Brief explanation of the drawings]

[0007] [Figure 1] 1 is a circuit diagram illustrating a multi-chip package (semiconductor device) 300 according to an embodiment of the present invention. [Figure 2] 10 is a timing chart illustrating the operation of the multi-chip package (semiconductor device) 300 according to the embodiment of the present invention. [Figure 3] 10 is a timing chart illustrating the operation of the multi-chip package (semiconductor device) 300 according to the embodiment of the present invention. [Figure 4] The configuration of a multi-chip package 300 of the first comparative example will be described. [Figure 5] The configuration of a multi-chip package 300 of the second comparative example will be described. [Figure 6]10 is a timing chart illustrating the operation and problems of the multi-chip package 300 of the second comparative example. [Figure 7] 10 is a timing chart illustrating the operation and problems of the multi-chip package 300 of the second comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0008] Hereinafter, the present embodiment will be described with reference to the accompanying drawings. In the accompanying drawings, functionally identical elements may be designated by the same numerals. Note that the accompanying drawings show embodiments and implementation examples according to the principles of the present disclosure, but these are for understanding the present disclosure and are not to be used to interpret the present disclosure in a limiting manner. The descriptions in this specification are merely typical examples and are not intended to limit the scope or application of the present disclosure in any way.

[0009] Although the present embodiment has been described in sufficient detail to enable those skilled in the art to practice the present disclosure, it should be understood that other implementations and forms are possible, and that changes in configuration and structure and substitutions of various elements are possible without departing from the scope and spirit of the technical ideas of the present disclosure. Therefore, the following description should not be interpreted as being limited thereto.

[0010] Before describing the embodiments of the present invention, a multi-chip package according to a comparative example of the present embodiments will be described. First, with reference to FIG. 4, the configuration of a conventional multi-chip package 300 will be described as a first comparative example. This multi-chip package 300 is configured by mounting a regulator chip 100 and an MCU 200 in a single package. The regulator chip 100 includes a voltage generating circuit 11 and a regulator REG. The regulator REG may include, for example, an OP amplifier OP1 and a PMOS transistor M1.

[0011] The OP amplifier OP1 receives the voltage generated by the voltage generating circuit 11 at its non-inverting input terminal, and its inverting input terminal is connected to the drain of the PMOS transistor M1. The PMOS transistor M1 receives the output signal of the OP amplifier OP1 at its gate, receives the power supply voltage VDD at its source, and has its drain connected to the MCU 200. A stabilizing capacitor 400 is connected between the input terminal and ground terminal of the MCU 200.

[0012] 1, when the power supply voltage VDD is turned on, the multi-chip package 300 of the first comparative example is automatically started up and the voltage VDDR2 is supplied to the MCU 200. When the voltage VDDR2 is supplied to the MCU 200, a power-on reset operation is initiated by a power-on reset circuit (not shown), and the MCU 200 then transitions to normal operation. Since the current consumption of the MCU 200 varies depending on the operating state, power consumption can also be reduced by setting the MCU 200 to a sleep state or a halt state.

[0013] However, in the multi-chip package 300 of the first comparative example shown in Fig. 1, even when the MCU 200 is in a sleep state or the like, the regulator chip 100 continues to operate, so current consumption cannot be sufficiently reduced. A conventional example that improves on this point is the multi-chip package 300 of the second comparative example shown in Fig. 5. Fig. 6 is a timing chart illustrating the operation of the multi-chip package 300 of the second comparative example.

[0014] The regulator chip 100 of the multi-chip package 300 of the second comparative example in FIG. 5 includes a first regulator REG1 and a second regulator REG2. Similar to the first comparative example, the second regulator REG2 generates a power supply voltage VDDR2 to be supplied to the MCU 200. The first regulator REG1 may include, for example, an OP amplifier OP1 and a PMOS transistor M1. The regulator REG2 may include, for example, an OP amplifier OP2 and a PMOS transistor M2. Because the first regulator REG1 and the second regulator REG2 output the same reference voltage VREF as voltage followers, the first operating voltage VDDR1 and the second operating voltage VDDR2 are substantially the same voltage.

[0015] The first regulator REG1 supplies a first operating voltage VDDR1 to the timer 14, regulator control circuit 15, input / output control circuit 16, and power-on reset circuit 17 provided in the regulator chip 100. The first regulator REG1 raises the first operating voltage VDDR1 after the power supply voltage VDD rises. When the first operating voltage VDDR1 rises, as shown in Figure 6, the power-on reset circuit 17 raises the power-on reset signal POR, and in response, the regulator control circuit 15 raises the activation signal REG2EN, which causes the second regulator REG2 to start operating and the second operating voltage VDDR2 output by the second regulator REG2 to start rising.

[0016] When the MCU200 does not need to operate, the start signal REG2EN switches to "L" and the second operating voltage VDDR2 also drops. This makes it possible to reduce the current consumed by the MPU200 as close to zero as possible. After the start signal REG2EN switches to "L", the timer 14 is set to a specified value and starts counting. When the count value of the timer 14 determines that the time has come when the MCU200 needs to operate, the start signal REG2N switches to "H" again and the second operating voltage VDDR2 also rises, thereby restarting the operation of the MPU200.

[0017] In the multi-chip package 300 of the second comparative example, in order to power on / off the second regulator REG2, the MCU 200 must always start up at the initial startup, set the timer 14, and set the control terminal of the second regulator REG2 in the power-on direction. This requires a power-on reset circuit that always operates. If this power-on reset operation fails and the control signal REG2EN of the second regulator REG2 remains low, the MCU 200 cannot start up, resulting in a so-called deadlock state (see the timing chart in FIG. 7). Furthermore, this deadlock state can also occur if the start signal REG2N output by the regulator control circuit 15 becomes unstable immediately after the power supply voltage VDD is turned on.

[0018] A multi-chip package (semiconductor device) 300 of this embodiment will be described with reference to Fig. 1. The same components as those in the second comparative example (Fig. 5) are denoted by the same reference numerals in Fig. 1 as those in Fig. 5.

[0019] The multi-chip package 300 of this embodiment is configured by mounting a regulator chip 100 and an MCU 200 in one package. The regulator chip 100 is configured to include a voltage generation circuit 11, a first regulator REG1, a second regulator REG2, a low-voltage detection circuit 600, a timer 14, a regulator control circuit 15, and a startup circuit 700. The timer 14 is the same as that in the second comparative example.

[0020] The low-voltage detection circuit 600 detects whether the rise in the second operating voltage VDDR2 is lower than the rise in the first operating voltage VDDR1 by a predetermined value or more after the first operating voltage VDDR1 rises. The startup circuit 700 is configured to receive the output signal RESET_N from the low-voltage detection circuit 600 and detect whether the rise in the second operating voltage VDDR2 is lower than the rise in the first operating voltage VDDR1 by a predetermined value or more after the first operating voltage VDDR1 starts to rise. The startup circuit 700 detects whether the rise in the second operating voltage VDDR2 is lower than the rise in the first operating voltage VDDR1 only once after the first operating voltage VDDR1 starts to rise. In other words, the startup circuit 700 is configured to ignore the detection signal from the low-voltage detection circuit 600 after the first operating voltage VDDR1 rises to the predetermined value.

[0021] The first regulator REG1 may include, for example, an operational amplifier OP1 and a PMOS transistor M1. The regulator REG2 may include, for example, an operational amplifier OP2 and a PMOS transistor M2. The operational amplifier OP1 receives a reference voltage VREF generated by the voltage generating circuit 11 at its non-inverting input terminal, and its inverting input terminal is connected to the drain of the PMOS transistor M1. The PMOS transistor M1 receives an output signal from the operational amplifier OP1 at its gate, is supplied with a power supply voltage VDD at its source, and outputs a first operating voltage VDDR1 from its drain. The operational amplifier OP2 receives a reference voltage VREF generated by the voltage generating circuit 11 at its non-inverting input terminal, and its inverting input terminal is connected to the drain of the PMOS transistor M2. The PMOS transistor M2 receives an output signal from the operational amplifier OP2 at its gate, is supplied with a power supply voltage VDD at its source, and outputs a first operating voltage VDDR2 from its drain. A stabilizing capacitor 400 is connected between the input terminal and ground terminal of the MCU 200. A stabilizing capacitor 500 is connected between the output terminal of the first regulator REG1 and the ground terminal.

[0022] The low-voltage detection circuit 600, for example, includes a bias current source CS, NMOS transistors M3 and M5, a PMOS transistor M4, an inverter IN, and a latch circuit LT. The bias current source CS is connected between the drain of the NMOS transistor M3 and the output terminal (first operating voltage VDDR1) of the first regulator REG1, and supplies a constant current to the NMOS transistor M3. The PMOS transistor M4 and the NMOS transistor M5 are connected in series between the output terminal (output terminal of the first operating voltage VDDR1) of the first regulator REG1 and the ground terminal, and the NMOS transistors M3 and M5 are connected in a current mirror configuration. The gate of the NMOS transistor M4 is supplied with the second operating voltage VDDR2, and the source is supplied with the first operating voltage VDDR1. The PMOS transistor M4 is turned on when the second operating voltage VDDR2 is lower than the first operating voltage VDDR1 by its threshold voltage Vt (for example, about 0.5 to 1 V). When the PMOS transistor M4 becomes conductive, the output signal RN of the inverter IN switches from "H" to "L".

[0023] The start-up circuit 700 includes, for example, an inverter 31, an RC filter 32, an inverter 33, an EXOR gate 34, an inverter 35, a D flip-flop circuit 36, and an inverter 37.

[0024] The inverter 31 receives the first start signal REG2_PD from the regulator control circuit 15 and outputs an inverted signal. The first start signal REG_PD is a signal that powers down the second regulator REG2 when it goes high. An RC filter 32, an inverter 33, and an EXOR gate 34 are connected to the output terminal of the inverter 31, in that order. The EXOR gate 34 receives the output signal of the inverter 33 and the first start signal REG2_PD, which is the output signal from the regulator control circuit 15. The inverter 31, the RC filter 32, the inverter 33, and the EXOR gate 34 form a one-shot pulse circuit that generates a one-shot pulse when the first start signal REG2_PD switches from high to low or from low to high. The output signal of the EXOR gate 34 is inverted by an inverter 35 to become a signal REG2_PD'.

[0025] The D flip-flop circuit 36 ​​receives the first start-up signal REG2_PD at its input terminal and receives the signal REG2_PD' at its clock terminal. The output signal of the D flip-flop circuit 36 ​​is inverted by an inverter 37 to become the second start-up signal REG2EN. The second start-up signal REG2EN is output to the second regulator REG2 to start the second regulator REG2 and generate the second operating voltage VDDR2.

[0026] Next, the operation of the multi-chip package 300 of this embodiment will be described with reference to the timing charts of FIGS. 2 and 3. The first regulator REG1 raises the first operating voltage VDDR1 after the power supply voltage VDD rises from 0 V. When the first operating voltage VDDR1 rises, the regulator control circuit 15 correspondingly raises the first start-up signal REG2_PD, which is input to the start-up circuit 700. In response to the rise of the first start-up signal REG2_PD, the start-up circuit 700 outputs the second start-up signal REG2EN and supplies it to the second regulator REG2. This causes the second regulator REG2 to start operating, and the second operating voltage VDDR2 output by the second regulator REG2 begins to rise.

[0027] The second start-up signal REG2EN, which is based on the output signal of the D flip-flop circuit 36 ​​powered by the first operating voltage VDDR1, is in an undefined state (a state in which it is not determined whether it is "H" or "L") when the first operating voltage VDDR1 rises. Therefore, the following will explain the cases where the second start-up signal REG2EN is "H" (Case 1: FIG. 2) and "L" (Case 2: FIG. 3) separately. In either case, this embodiment can properly complete operation without a power-on reset signal.

[0028] (Case 1) First, we will explain the case where the second activation signal REG2EN is "L" when the first operating voltage VDDR1 rises. In this case, the second regulator REG2 is in a power-down state, the second operating voltage VDDR2 remains at 0V, and the first operating voltage VDDR1 rises as the power supply voltage VDD starts to rise from time t0 (FIG. 2). At this time, the PMOS transistor M4 of the low-voltage detection circuit 600 is in a conductive state (ON) because the second operating voltage VDDR2 supplied to its gate is 0V. Then, due to this conductive state of the PMOS transistor M4, the output signal RN of the inverter IN also becomes "L" (time tx in FIG. 2).

[0029] The output signal RESET_N of the latch circuit LT becomes "L" because both the signal RN and the second operating voltage VDDR2 are "L." This output signal RESET_N is input to the reset terminal of the D flip-flop circuit 36, and the output signal of the D flip-flop circuit 36 ​​also becomes "L." As a result, the second start-up signal REG2EN becomes "H" after time tx, and the second regulator REG2 is started (powered on).

[0030] When the second regulator REG2 is started, the second operating voltage VDDR2 rises and the signal RN switches to "H." At this point, the D flip-flop circuit 36 ​​is released from reset, completing the startup sequence of the second regulator REG2. When the second operating voltage VDDR2 rises, the MCU 200 starts up and updates the value of the first startup signal REG2_PD (time t2). At this time, because the initial value of REG2_PD is also indefinite, there are two possible patterns: either it changes from "H" to "L" or it remains at "L" (see symbol P2 in Figure 2).

[0031] The circuit consisting of the RC filter 32, inverter 33, and EXOR gate 34 constitutes a one-shot pulse generating circuit that generates a one-shot pulse only when its input signal switches from "H" to "L" or from "L" to "H," and updates the output signal (signal REG2_PD' falls) only when the initial value of the first start-up signal REG2_PD is "H." In this way, start-up is always performed even when the initial value of the first start-up signal REG2_PD is "H" (which is normally the power-down state).

[0032] After the power supply voltage VDD and the first operating voltage VDDR1 rise, if it is desired to power down the second regulator REG2 in order to switch the MCU 200 to a non-activated state, the first start-up signal REG2_PD is switched to "H" (time t3). When the second regulator REG2 powers down and the second power supply voltage VDDR2 drops, the low-voltage detection circuit 600 detects this, but because the latch circuit LT connected downstream is enabled, the output is not transmitted to the downstream (the signal RESET_N does not switch), and the detection result of the drop in the second power supply voltage VDDR2 is, so to speak, ignored. In this way, when the initial value of the second start-up signal REG2EN is "L," the second operating voltage VDDR2 does not rise by default, but the low-voltage detection circuit 600 resets the D flip-flop circuit 36, causing the second operating voltage VDDR2 to rise. The reset operation of the D flip-flop circuit 56 (activation of the start-up circuit 700) based on the result of detection of a drop in the second operating voltage VDDR2 by the low-voltage detection circuit 600 is performed only once after the first operating voltage VDDR1 starts to rise. After the first operating voltage VDDR1 rises, if the second operating voltage VDDR2 is intentionally lowered, the voltage drop is ignored and does not affect the operation of the start-up circuit 700.

[0033] (Case 2) Next, we will explain the case where the second start-up signal REG2EN is "H" when the first operating voltage VDDR1 rises. In this case, since the second operating voltage VDDR2 is enabled, the second regulator REG2 is also started up as the first operating voltage VDDR1 starts to rise, and the second operating voltage VDDR2 starts to rise. After that, the started-up MCU 200 sets the first start-up signal REG2_PD and transitions to normal operation.

[0034] The latch circuit LT is directly latched by the voltage of the second operating voltage VDDR2, and if the second regulator REG2 is subsequently arbitrarily powered down, even if a drop in the second operating voltage VDDR2 is detected by the low-voltage detection circuit 600, this does not affect the operation of the startup circuit 700, as in Case 1. In this way, when the initial value of the second startup signal REG2EN is "H," the second operating voltage VDDR2 is started by default, and the low-voltage detection circuit 600 does not reset the second startup signal REG2EN, and the second regulator REG2 starts up as is. Because the output of the low-voltage detection circuit 600 is latched by the second operating voltage VDDR2, subsequent power-down / power-on can be controlled by the timer 14 and regulator control circuit 15.

[0035] As described above, according to this embodiment, the second regulator REG2 can be reliably started when the first operating voltage VDDR1 is started, regardless of the state of the second start-up signal REG2EN. In conventional examples such as the second comparative example, if the initial value of the second start-up signal REG2EN is “L” and the power-on reset signal from the power-on reset circuit is not generated, the MCU 200 may not start and may become deadlocked. However, in the above embodiment, the second regulator REG2 can be reliably started when the power is started, regardless of the initial value of the second start-up signal REG2EN. In other words, in this embodiment, the low-voltage detection circuit 600 functions as a power-on reset circuit for the second start-up signal REG2EN, ensuring that the second operating voltage VDDR2 is started regardless of whether Case 1 or 2 is satisfied. After the second regulator REG2 is started, the second regulator REG2 can be powered down at will, for example, by a command from the MCU 200. This reduces current consumption by powering down the second regulator when the MCU 200 is not required to operate.

[0036] The present invention is not limited to the above-described embodiments and includes various modifications. For example, the above-described embodiments have been described in detail to clearly explain the present invention, and the present invention is not necessarily limited to those including all of the described configurations. Furthermore, it is possible to replace part of the configuration of one embodiment with the configuration of another embodiment, or to add the configuration of another embodiment to the configuration of one embodiment. Furthermore, it is possible to add, delete, or replace part of the configuration of each embodiment with other configurations. [Explanation of symbols]

[0037] 11...Voltage generation circuit 14...Timer 15...Regulator control circuit 16...Input / output control circuit 17...Power-on reset circuit 31, 33, 35, 37...Inverter 32...RC filter 34...EXOR Gate 36...D flip-flop circuit 100...Regulator chip 200...MCU 300...Multi-chip package 400, 500…Stabilization capacity 600...Low voltage detection circuit 700...Starting circuit CS...Bias current source IN...Inverter LT...Latch circuit M1 to M5: Transistors OP1, OP2...op amps

Claims

1. a regulator unit for generating an operating voltage; a microcontroller unit that operates by receiving the operating voltage; In a semiconductor device comprising: The regulator unit includes: a first regulator that generates a first operating voltage; a second regulator for generating a second operating voltage; a low voltage detection circuit that detects that an increase in the second operating voltage is smaller than an increase in the first operating voltage; a start-up circuit that starts the second regulator in response to a rise of the first operating voltage and starts the second regulator in response to a detection result of the low-voltage detection circuit; A semiconductor device comprising:

2. the startup circuit receives a first startup signal instructing startup of the second regulator and outputs a second startup signal to the second regulator; 2. The semiconductor device according to claim 1, configured to output the second activation signal to the second regulator based on a detection signal from the low-voltage detection circuit.

3. 3. The semiconductor device according to claim 2, wherein the start-up of said second regulator by said start-up circuit based on said detection result of said low-voltage detection circuit is executed only once after said first operating voltage starts to rise.

4. 3. The semiconductor device according to claim 2, wherein the startup circuit comprises a flip-flop circuit having an input terminal to which the first startup signal is input, a clock terminal to which a pulse signal generated in response to the first startup signal is input, and a reset terminal to which the detection signal of the low-voltage detection circuit is input.

5. The low voltage detection circuit a bias current source that generates a bias current; a current mirror circuit that mirrors the bias current to generate a mirror current; a PMOS transistor supplied with the mirror current and having the second operating voltage supplied to its gate; The semiconductor device according to claim 1 , comprising:

6. A regulator device configured to be connectable to a microcontroller and generating an operating voltage for the microcontroller, a first regulator that generates a first operating voltage; a second regulator for generating a second operating voltage; a low voltage detection circuit that detects that an increase in the second operating voltage is smaller than an increase in the first operating voltage; a start-up circuit that starts the second regulator in response to a rise of the first operating voltage and starts the second regulator in response to a detection result of the low-voltage detection circuit; A regulator device comprising:

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