Electrostatic protective element

Abstract

To improve ESD resistance by mitigating electric field concentration when an ESD surge is applied in an electrostatic protective element of the transistor structure.SOLUTION: An electrostatic protective element has a source region and a drain region provided in a semiconductor substrate, and a first gate provided on the surface of the semiconductor substrate between the source region and the drain region. The drain region includes a low-concentration region made of a semiconductor with a relatively low impurity concentration, a high-concentration region contained within the low-concentration region and made of a semiconductor with a relatively high impurity concentration, and a medium-concentration region contained within the low-concentration region and containing the high-concentration region, made of a semiconductor with an impurity concentration higher than that of the low-concentration region but lower than that of the high-concentration region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The disclosed technology relates to an electrostatic protection element. [Background technology]

[0002] The following techniques are known as techniques related to semiconductor devices. For example, Patent Document 1 describes a semiconductor device in which a drain region includes a drift region into which impurities are implanted, and the drain region is entirely encompassed by the drift region, and includes a high-concentration region in which the concentration of impurities of the second polarity is higher than that of the drift region, and a medium-concentration region in which the concentration of impurities of the second polarity is higher than that of the drift region and lower than that of the high-concentration region.

[0003] Patent Document 2 describes a configuration in which an SiO2 film and a polycrystalline Si layer are provided on the surface of a drain region that is configured by a low-concentration impurity region and a high-concentration impurity region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. 2012 / 120899 [Patent Document 2] Japanese Patent Application Publication No. 2-142191 Summary of the Invention [Problem to be solved by the invention]

[0005] Integrated circuits such as driver ICs (Integrated Circuits) use transistor-structured electrostatic protection elements to protect internal circuits from excessive input voltages and currents caused by electrostatic discharge (ESD). When an ESD surge is applied to a transistor-structured electrostatic protection element, an electric field concentration occurs in accordance with the impurity concentration gradient in the drain region, causing the lattice temperature to rise. If the lattice temperature becomes excessive, the electrostatic protection element will be destroyed.

[0006] The disclosed technology aims to improve the ESD resistance of an electrostatic protection element having a transistor structure by alleviating electric field concentration when an ESD surge is applied. [Means for solving the problem]

[0007] The electrostatic protection element according to the disclosed technology has a source region and a drain region provided in a semiconductor substrate, and a first gate provided on the surface of the semiconductor substrate between the source region and the drain region, and the drain region includes a low-concentration region made of a semiconductor with a relatively low impurity concentration, a high-concentration region contained within the low-concentration region and made of a semiconductor with a relatively high impurity concentration, and a medium-concentration region contained within the low-concentration region and containing the high-concentration region, made of a semiconductor with an impurity concentration higher than that of the low-concentration region but lower than that of the high-concentration region.

[0008] Another electrostatic protection element according to the disclosed technology is an electrostatic protection element having a source region and a drain region provided in a semiconductor substrate, and a first gate provided on the surface of the semiconductor substrate between the source region and the drain region, wherein the drain region includes a low-concentration region made of a semiconductor having a relatively low impurity concentration, and a high-concentration region contained inside the low-concentration region and made of a semiconductor having a relatively high impurity concentration, and has a second gate provided on the surface of the low-concentration region at a position separated from the high-concentration region and near the high-concentration region via an insulating film, and electrically connected to the high-concentration region.

[0009] Another electrostatic protection element according to the disclosed technology is an electrostatic protection element having a source region and a drain region provided in a semiconductor substrate, and a first gate provided on the surface of the semiconductor substrate between the source region and the drain region, wherein the drain region includes a low-concentration region made of a semiconductor with a relatively low impurity concentration, and a high-concentration region contained inside the low-concentration region and made of a semiconductor with a relatively high impurity concentration, and has a second gate provided via an insulating film on the surface of the semiconductor substrate at a position straddling the boundary between the low-concentration region and the high-concentration region, and set to a floating potential. [Effects of the Invention]

[0010] According to the disclosed technology, in an electrostatic protection element having a transistor structure, it is possible to improve the ESD resistance by alleviating electric field concentration when an ESD surge is applied. [Brief explanation of the drawings]

[0011] [Figure 1] 1 is a cross-sectional view showing an example of the configuration of an electrostatic protection element according to an embodiment of the disclosed technique; [Figure 2] FIG. 10 is a cross-sectional view showing an example of the configuration of an electrostatic protection element according to a comparative example. [Figure 3] FIG. 10 is a diagram showing a potential distribution when the Kirk effect occurs in the electrostatic protection element according to the comparative example. [Figure 4] 10 shows simulation results of TLP characteristics of an electrostatic protection element according to an embodiment of the disclosed technique and an electrostatic protection element according to a comparative example. [Figure 5] FIG. 10 is a cross-sectional view showing an example of the configuration of an electrostatic protection element according to another embodiment of the disclosed technique. [Figure 6] FIG. 10 is a cross-sectional view showing an example of the configuration of an electrostatic protection element according to another embodiment of the disclosed technique. [Figure 7] FIG. 10 is a cross-sectional view showing an example of the configuration of an electrostatic protection element according to another embodiment of the disclosed technique. DETAILED DESCRIPTION OF THE INVENTION

[0012] Hereinafter, embodiments of the disclosed technology will be described with reference to the drawings. In each drawing, substantially the same or equivalent components or parts are denoted by the same reference numerals.

[0013] [First embodiment] 1 is a cross-sectional view showing an example of the configuration of an electrostatic protection element 10 according to a first embodiment of the disclosed technology. The electrostatic protection element 10 is an ESD protection element having a transistor structure, and is connected to the power supply line of a driver IC, for example, and has the function of protecting the internal circuit from ESD surges that enter the power supply line.

[0014] The electrostatic protection element 10 has an N-channel MOSFET (Metal Oxide Semiconductor) structure including a source region 1, a drain region 2, and a gate 20, which is provided on a P-type semiconductor substrate 11. The semiconductor substrate 11 can be, for example, a silicon substrate.

[0015] The source region 1 has an N-type low-concentration region 14 with a relatively low impurity concentration, and an N-type high-concentration region 15 with a relatively high impurity concentration. The low-concentration region 14 and the high-concentration region 15 are provided in the surface layer portion of the semiconductor substrate 11. The bottom surface of the low-concentration region 14 reaches deeper into the semiconductor substrate 11 than the bottom surface of the high-concentration region 15, and the bottom and side surfaces of the high-concentration region 15 are in contact with the low-concentration region 14. In other words, the high-concentration region 15 is contained inside the low-concentration region 14.

[0016] The drain region 2 is provided in a surface layer portion of the semiconductor substrate 11 at a position separated from the source region 1. The drain region 2 has an N-type low concentration region 16 having a relatively low impurity concentration, and an N-type high concentration region 17 having a relatively high impurity concentration. The drain region 2 further has an N-type intermediate concentration region 18 having an impurity concentration higher than that of the low concentration region 16 but lower than that of the high concentration region 17.

[0017] The bottom surface of the low concentration region 16 reaches deeper into the semiconductor substrate 11 than the bottom surface of the medium concentration region 18, and the bottom surface and side surfaces of the medium concentration region 18 are in contact with the low concentration region 16. In other words, the medium concentration region 18 is contained inside the low concentration region 16.

[0018] The bottom surface of the medium concentration region 18 reaches deeper into the semiconductor substrate 11 than the bottom surface of the high concentration region 17, and the bottom surface and side surfaces of the high concentration region 17 are in contact with the medium concentration region 18. In other words, the high concentration region 17 is contained inside the medium concentration region 18, and there is no boundary between the low concentration region 16 and the high concentration region 17.

[0019] The distance between the boundary between the low concentration region 16 and the medium concentration region 18 and the boundary between the medium concentration region 18 and the high concentration region 17 is preferably 0.1 μm or less.

[0020] The gate 20 is provided on the surface of the semiconductor substrate 11 between the source region 1 and the drain region 2 via an insulating film 19. One end of the gate 20 and the insulating film 19 extends over the source region 1, and the other end extends over the drain region 2. The source-side edges of the gate 20 and the insulating film 19 are aligned with the boundary between the low-concentration region 14 and the high-concentration region 15. That is, the source-side high-concentration region 15 is formed using the gate 20 as a mask. Meanwhile, the drain-side high-concentration region 17 is positioned away from the gate 20, and the low-concentration region 16 and the medium-concentration region 18 extend between the gate 20 and the high-concentration region 17. This configuration improves the surge current resistance of the electrostatic protection element 10. The gate 20 is made of, for example, polysilicon, and the insulating film 19 is made of, for example, SiO2. The gate 20 is an example of a "first gate" in the disclosed technology.

[0021] The electrostatic protection element 10 has a P-type substrate contact region 13 in a surface layer portion of a semiconductor substrate 11. The substrate contact region 13 has a higher impurity concentration than the semiconductor substrate 11. The substrate contact region 13 and the transistor structure are insulated from each other by an element isolation region 12 made of an insulator. The bottom surface of the element isolation region 12 reaches deeper into the semiconductor substrate 11 than the bottom surfaces of the low concentration regions 14 and 16. The element isolation region 12 has, for example, an STI (Shallow Trench Isolation) structure.

[0022] Contact electrodes 21, 22, 23, and 24 are provided on the surfaces of the substrate contact region 13, the high concentration region 15, the gate 20, and the high concentration region 17, respectively. The substrate contact region 13, the high concentration region 15, and the gate 20 are connected to a ground line via the contact electrodes 21, 22, and 23, respectively, and the high concentration region 17 is connected to a power supply line via the contact electrode 24.

[0023] The protection function of the electrostatic protection element 10 is exerted by the operation of a parasitic NPN transistor formed inside the electrostatic protection element 10. The electrostatic protection element 10 operates as follows against an ESD surge applied to the power supply line.

[0024] When an ESD surge is applied to the power supply line, the potential of the low-concentration region 16 of the drain region 2 connected to the power supply line rises. When the potential difference between the low-concentration region 16 and the semiconductor substrate 11 exceeds the reverse breakdown voltage of the PN junction (diode) formed by these regions, current flows from the low-concentration region 16 to the semiconductor substrate 11, raising the potential of the semiconductor substrate 11. This causes current to flow from the semiconductor substrate 11 to the source region 1 connected to the ground line. This current becomes the base current of the parasitic NPN transistor. This turns the parasitic NPN transistor on, and the surge current flows from the collector (drain region 2) to the emitter (source region) and out to the ground line.

[0025] 2 is a cross-sectional view showing an example of the configuration of an electrostatic protection element 10X according to a comparative example. The electrostatic protection element 10X according to the comparative example differs from the electrostatic protection element 10 (see FIG. 1) according to the embodiment of the disclosed technique in that the drain region 2 does not have a medium concentration region 18.

[0026] FIG. 3 shows the potential distribution when the Kirk effect occurs in the electrostatic protection element 10X according to the comparative example. When the current flowing into the drain increases, an electric field concentrates near the edge of the high-concentration region 17. At the electric field concentration point, holes are generated by impact ionization. These holes flow into the low-concentration region 16, causing the Kirk effect. When the Kirk effect occurs, the lattice temperature rises at the electric field concentration point, exciting carriers, reducing resistance and causing current concentration. Current concentration further increases the lattice temperature, resulting in thermal runaway, which destroys the electrostatic protection element 10X. In the electrostatic protection element 10X according to the comparative example, the difference in impurity concentration between the low-concentration region 16 and the high-concentration region 17 in the drain region 2 is large. A steep concentration gradient at the boundary between these regions generates a high electric field, making the electric field prone to concentration.

[0027] On the other hand, according to the electrostatic protection element 10 of the embodiment of the disclosed technique, the presence of the medium concentration region 18 between the low concentration region 16 and the high concentration region 17 reduces the impurity concentration gradient in the drain region 2. This reduces electric field concentration and increases the voltage at which the Kirk effect occurs, thereby suppressing the rise in lattice temperature when an ESD surge is applied. In other words, according to the electrostatic protection element 10 of the embodiment of the disclosed technique, it is possible to improve the ESD resistance.

[0028] FIG. 4 shows simulation results of the TLP (Transmission Line Pulse) characteristics of the electrostatic protection element 10 according to the embodiment of the disclosed technology (see FIG. 1) and the electrostatic protection element 10X according to the comparative example (see FIG. 2). In FIG. 4, the solid line corresponds to the electrostatic protection element 10 according to the embodiment of the disclosed technology, and the dotted line corresponds to the electrostatic protection element 10X according to the comparative example. It was confirmed that the voltage at which the Kirk effect occurs is higher in the electrostatic protection element 10 according to the embodiment of the disclosed technology than in the electrostatic protection element 10X according to the comparative example. In other words, it can be said that the ESD tolerance of the electrostatic protection element 10 according to the embodiment of the disclosed technology is higher than that of the electrostatic protection element 10X according to the comparative example.

[0029] Furthermore, in the electrostatic protection element 10 according to the embodiment of the disclosed technique, the high-concentration region 17 is contained within the medium-concentration region 18, and there is no boundary between the low-concentration region 16 and the high-concentration region 17. That is, there is no region with a steep concentration gradient, which promotes the effect of improving ESD resistance. Furthermore, by setting the distance between the boundary between the low-concentration region 16 and the medium-concentration region 18 and the boundary between the medium-concentration region 18 and the high-concentration region 17 to 0.1 μm or less, it is possible to sufficiently mitigate the electric field concentration.

[0030] [Second embodiment] 5 is a cross-sectional view showing an example of the configuration of an electrostatic protection element 10A according to a second embodiment of the disclosed technology. The electrostatic protection element 10A differs from the electrostatic protection element 10 according to the first embodiment (see FIG. 1) in that it has a gate 31 with sidewalls 60 formed on its side surfaces.

[0031] The gate 31 is provided on the surface of the low-concentration region 16 at a position separated from the high-concentration region 17 and near the high-concentration region 17 via an insulating film 30. A sidewall 60 covers the side surface of the gate 31. In the electrostatic protection element 10A, the gate 31 has no electrical function and is at a floating potential. The gate 31 is made of, for example, polysilicon, and the insulating film 30 and the sidewall 60 are made of, for example, SiO2. The gate 31 is an example of a "second gate" in the disclosed technology.

[0032] After the gate 31 is formed, ion implantation is performed to form the medium concentration region 18 using the gate 31 as a mask, and after the medium concentration region 18 is formed, the sidewall 60 is formed, and after the sidewall 60 is formed, ion implantation is performed to form the high concentration region 17 using the gate 31 and the sidewall 60 as a mask. As a result, a structure is obtained in which the position of the edge of the gate 31 is aligned with the position of the boundary between the low concentration region 16 and the medium concentration region 18, and the position of the edge of the sidewall 60 is aligned with the position of the boundary between the medium concentration region 18 and the high concentration region 17.

[0033] The process for forming the drain region 2 using the insulating film 30, the gate 31, and the sidewall 60 can be made common to the process for forming an LDD (Lightly Doped Drain) region of the integrated circuit that is the protection target of the electrostatic protection element 10A. That is, by forming the drain region 2 using the insulating film 30, the gate 31, and the sidewall 60, it is possible to form the drain region 2 including the low concentration region 16, the high concentration region 17, and the medium concentration region 18 without adding any additional steps.

[0034] In the source region 1, similarly to the drain region 2, a moderately doped region 70 may be formed between the low-doped region 14 and the high-doped region 15 by using the gate 20 and the sidewall 61. Also, an N-type well 71 may be provided under the low-doped region 16 of the drain region 2. In this case, the electric field relaxation effect of the moderately doped region 18 and the effect of the well 71 do not compete with each other.

[0035] [Third embodiment] 6 is a cross-sectional view showing an example of the configuration of an electrostatic protection element 10B according to a third embodiment of the disclosed technology. The electrostatic protection element 10B differs from the electrostatic protection element 10 according to the first embodiment (see FIG. 1) in that it does not have a medium concentration region 18 and has a gate 41.

[0036] The gate 41 is provided on the surface of the low-concentration region 16 at a position separated from the high-concentration region 17 and near the high-concentration region 17 via an insulating film 40. The distance between the edge of the high-concentration region 17 and the edge of the gate 41 on the high-concentration region 17 side is preferably 0.1 μm or less. The gate 41 is made of, for example, polysilicon, and the insulating film 40 is made of, for example, SiO2. The gate 41 is an example of a "second gate" in the disclosed technology.

[0037] A contact electrode 25 is provided on the gate 41. The contact electrode 25 is electrically connected to a contact electrode 24 connected to the high concentration region 17. That is, the gate 41 is electrically connected to the high concentration region 17. The gate 41 and the high concentration region 17 are connected to a power supply line via the contact electrodes 25 and 24, respectively.

[0038] The protection function of the electrostatic protection element 10B according to this embodiment is exerted by the operation of a parasitic NPN transistor formed inside the electrostatic protection element 10B, similar to the electrostatic protection element 10 according to the first embodiment described above.

[0039] The electrostatic protection element 10B according to this embodiment differs from the electrostatic protection element 10 according to the first embodiment in the mechanism for mitigating the electric field concentration occurring near the edge of the high-concentration region 17 during ESD surge application. According to the electrostatic protection element 10B according to this embodiment, a gate 41 having the same potential as the high-concentration region 17 is provided near the high-concentration region 17 on the surface of the low-concentration region 16 via an insulating film 40. This allows the potential of the high-concentration region 17 to be coupled to the boundary between the low-concentration region 16 and the high-concentration region 17 via the insulating film 40. This averages the potential gradient near the boundary between the low-concentration region 16 and the high-concentration region 17, thereby mitigating the electric field concentration occurring near the edge of the high-concentration region 17. This increases the voltage at which the Kirk effect occurs, thereby suppressing the rise in lattice temperature during ESD surge application. In other words, the electrostatic protection element 10B according to this embodiment can improve ESD resistance. By setting the distance between the edge of the high concentration region 17 and the edge of the gate 41 on the high concentration region 17 side to 0.1 μm or less, it is possible to achieve a sufficient effect of reducing the electric field concentration.

[0040] Furthermore, since the gate 41 has a structure adjacent to the high concentration region 17, it is possible to perform ion implantation for forming the high concentration region 17 using the gate 41 as a mask.

[0041] As in the electrostatic protection element according to the second embodiment (see FIG. 5), an N-type well may be provided below the low concentration region 16 of the drain region 2.

[0042] [Fourth embodiment] 7 is a cross-sectional view showing an example of the configuration of an electrostatic protection element 10C according to a fourth embodiment of the disclosed technology. The electrostatic protection element 10C differs from the electrostatic protection element 10 according to the first embodiment (see FIG. 1) in that it does not have a medium concentration region 18 and has a gate 51.

[0043] The gate 51 is provided on the surface of the semiconductor substrate 11 at a position spanning the boundary between the low-concentration region 16 and the high-concentration region 17, with an insulating film 50 interposed therebetween. Preferably, the distance between the edge of the high-concentration region 17 and one edge of the gate 51 (the edge on the low-concentration region 16 side) is 0.1 μm or less, and the distance between the edge of the high-concentration region 17 and the other edge of the gate 51 (the edge on the high-concentration region 17 side) is 0.3 μm or more. Furthermore, it is preferable that the area S1 of the portion of the gate 51 extending over the high-concentration region 17 is larger than the area S2 of the portion of the gate 51 extending over the low-concentration region 16. More specifically, it is preferable that the area S1 is three times or more the area S2. The gate 51 is made of, for example, polysilicon, and the insulating film 50 is made of, for example, SiO2. The gate 51 is an example of a "second gate" in the disclosed technology. The gate 51 is at a floating potential.

[0044] The protection function of the electrostatic protection element 10C according to this embodiment is exerted by the operation of a parasitic NPN transistor formed inside the electrostatic protection element 10C, similar to the electrostatic protection element 10 according to the first embodiment described above.

[0045] The electrostatic protection element 10C according to this embodiment differs from the electrostatic protection element 10 according to the first embodiment in the mechanism for mitigating the electric field concentration occurring near the edge of the high-concentration region 17 during ESD surge application. According to the electrostatic protection element 10C according to this embodiment, the gate 51, which is at a floating potential, is provided on the surface of the semiconductor substrate 11 at a position straddling the boundary between the low-concentration region 16 and the high-concentration region 17 via the insulating film 50. This allows the potential of the high-concentration region 17 to be coupled to the boundary between the low-concentration region 16 and the high-concentration region 17 via the insulating film 50. This averages the potential gradient near the boundary between the low-concentration region 16 and the high-concentration region 17, thereby mitigating the electric field concentration occurring near the edge of the high-concentration region 17. This increases the voltage at which the Kirk effect occurs, thereby suppressing the rise in lattice temperature during ESD surge application. In other words, the electrostatic protection element 10C according to this embodiment can improve ESD resistance.

[0046] The effect of alleviating electric field concentration can be made sufficient by setting the distance between the edge of high concentration region 17 and one edge of gate 51 (the edge on the low concentration region 16 side) to 0.1 μm or less and the distance between the edge of high concentration region 17 and the other edge of gate 51 (the edge on the high concentration region 17 side) to 0.3 μm or more. In addition, the effect of alleviating electric field concentration can also be made sufficient by making the area S1 of the portion of gate 51 extending over high concentration region 17 larger than the area S2 of the portion of gate 51 extending over low concentration region 16.

[0047] As in the electrostatic protection element according to the second embodiment (see FIG. 5), an N-type well may be provided below the low concentration region 16 of the drain region 2.

[0048] In the above first to fourth embodiments, an electrostatic protection element having an N-channel MOSFET structure formed on a P-type semiconductor substrate has been exemplified, but the disclosed technology is not limited to this embodiment. The electrostatic protection element may have a P-channel MOSFET structure formed on an N-type semiconductor substrate. Furthermore, the electrostatic protection element may have an N-channel MOSFET structure formed on a P-type well. Furthermore, the electrostatic protection element may have a P-channel MOSFET structure formed on an N-type well. [Explanation of symbols]

[0049] 1 Source Area 2. Drain region 10, 10A, 10B, 10C, 10X electrostatic protection element 11 Semiconductor substrate 12 Element isolation region 13 Substrate contact area 14, 16 Low concentration area 15, 17 High concentration area 18, 70 medium concentration area 19, 30, 40, 50 insulating film Gates 20, 31, 41, and 51 60, 61 sidewall 71 wells

Claims

1. An electrostatic protection element having a source region and a drain region provided in a semiconductor substrate, and a first gate provided on a surface of the semiconductor substrate between the source region and the drain region, The drain region is a low concentration region made of a semiconductor having a relatively low impurity concentration; a high-concentration region that is contained within the low-concentration region and is made of a semiconductor having a relatively high impurity concentration; a medium concentration region that is contained within the low concentration region and that contains the high concentration region, the medium concentration region being made of a semiconductor and having an impurity concentration higher than that of the low concentration region and lower than that of the high concentration region; Contains Electrostatic protection element.

2. The distance between the boundary between the low concentration region and the medium concentration region and the boundary between the medium concentration region and the high concentration region is 0.1 μm or less. The electrostatic protection element according to claim 1 .

3. a second gate provided on the surface of the low concentration region at a position spaced apart from the high concentration region and in the vicinity of the high concentration region via an insulating film; a sidewall covering a side surface of the second gate; and an edge of the second gate is aligned with a boundary between the low concentration region and the medium concentration region; The edge position of the sidewall is aligned with the boundary position between the medium concentration region and the high concentration region. The electrostatic protection element according to claim 1 or 2.

4. An electrostatic protection element having a source region and a drain region provided in a semiconductor substrate, and a first gate provided on a surface of the semiconductor substrate between the source region and the drain region, The drain region is a low concentration region made of a semiconductor having a relatively low impurity concentration; a high-concentration region that is contained within the low-concentration region and is made of a semiconductor having a relatively high impurity concentration; Including, a second gate provided on the surface of the low concentration region at a position separated from the high concentration region and in the vicinity of the high concentration region via an insulating film, the second gate being electrically connected to the high concentration region; Electrostatic protection element.

5. The distance between the edge of the high concentration region and the edge of the second gate is 0.1 μm or less. The electrostatic protection element according to claim 4 .

6. An electrostatic protection element having a source region and a drain region provided in a semiconductor substrate, and a first gate provided on a surface of the semiconductor substrate between the source region and the drain region, The drain region is a low concentration region made of a semiconductor having a relatively low impurity concentration; a high-concentration region that is contained within the low-concentration region and is made of a semiconductor having a relatively high impurity concentration; Including, a second gate provided on the surface of the semiconductor substrate via an insulating film at a position spanning the boundary between the low concentration region and the high concentration region, the second gate being set to a floating potential; Electrostatic protection element.

7. a distance between an edge of the high concentration region and one edge of the second gate is 0.1 μm or less; The distance between the edge of the high concentration region and the other edge of the second gate is 0.3 μm or more. The electrostatic protection element according to claim 6 .

8. The area of ​​the second gate extending over the high concentration region is larger than the area of ​​the second gate extending over the low concentration region. The electrostatic protection element according to claim 6 or 7.

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