Wake-up timer circuit, wireless ic, and control method for wake-up timer circuit

Abstract

To reduce power consumption without lowering the accuracy of checking received radio waves, even when the reception frequency varies depending on the time of day.SOLUTION: A wake-up timer circuit 103 is provided with a reception frequency recording circuit 50 for recording a reception frequency, which is a frequency of detecting received radio waves per unit time, an addition value selection circuit 60 for changing an addition value signal according to the reception frequency per unit time, a timer counter 30 for incrementing a count value according to an addition value signal, and a comparator 40 for comparing the count value with a predetermined full count value and outputting a start signal when the count value reaches or exceeds the full count value.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a wake-up timer circuit, a wireless IC, and a control method for a wake-up timer circuit. [Background technology]

[0002] Some wireless integrated circuits (ICs) are equipped with a wake-up timer circuit to reduce power consumption (see, for example, Patent Document 1). This wake-up timer circuit outputs an interrupt signal to a microcomputer (hereinafter referred to as "mc") in a sleep state and intermittently checks for the presence or absence of received radio waves, thereby reducing power consumption. A wireless IC in a stopped state enters a state in which it is ready to transmit and receive signals at the time set in the wake-up timer circuit, and after performing a pre-set process, it enters a stopped state again. If the wireless IC is set in advance to enter a state in which it is ready to receive radio waves after waking up, it will enter a state in which it is ready to receive radio waves after waking up, and will issue an interrupt notification to the mc when a received radio wave is present.

[0003] 9 is a block diagram showing the configuration of a conventional wireless communication device. The wireless communication device shown in FIG. 9 includes a wireless IC 500 and a microcomputer 600.

[0004] The wireless IC 500 includes an antenna 501, a reception detection circuit 502, a wake-up timer circuit 503, and an SPI (Serial Peripheral Interface) circuit 504. The reception detection circuit 502 and the wake-up timer circuit 503 are each connected to the microcomputer 600 via the SPI circuit 504. The reception detection circuit 502 outputs a reception detection signal to the wake-up timer circuit 503, and the wake-up timer circuit 503 outputs an activation signal to the reception detection circuit 502. The microcomputer 600 is normally in a sleep state to reduce power consumption, and is activated by a microcomputer activation interrupt signal from the reception detection circuit 502.

[0005] 10 is a block diagram showing the configuration of a conventional wake-up timer circuit 503. The wake-up timer circuit 503 shown in FIG. 10 includes a count expiration value register 701, a count enable register 702, a timer counter 703, and a comparator 704.

[0006] The operation of the wake-up timer circuit 503 will now be described. Register control is performed by the microcomputer 600 via the SPI circuit 504. First, a count expiration value for waking up is set in the count expiration value register 701. Next, when the count enable register 702 is set, a count enable signal is output to the timer counter 703, and the timer counter 703 begins incrementing while the count enable signal is set. The count value is appropriately compared with the count expiration value in the count expiration value register 701 by the comparator 704, and when the count value becomes equal to or greater than the count expiration value, the comparator 704 outputs a start signal and simultaneously outputs a count clear signal to the timer counter 703. The count clear signal returns the count value of the timer counter 703 to 0. When the count value of the timer counter 703 becomes 0, the start signal from the comparator 704 becomes invalid. [Prior art documents] [Patent documents]

[0007] [Patent Document 1] Patent Publication No. 2021-106377 Summary of the Invention [Problem to be solved by the invention]

[0008] In the conventional circuit configuration described above, the reception frequency is unknown at an initial stage, so the wake-up cycle is set short, and then it is necessary to set the wake-up cycle according to the reception frequency later. However, because the reception frequency varies throughout the day, it is sometimes necessary to use a method in which the microcontroller sets a short wake-up cycle during periods of high reception frequency and a long wake-up cycle during periods of low reception frequency. In this case, the microcontroller must constantly check the time and set the wake-up cycle, which ultimately increases the operating time of the microcontroller. For this reason, further reductions in power consumption are desired.

[0009] The present invention has been made in consideration of the above-mentioned circumstances, and aims to provide a wake-up timer circuit, a wireless IC, and a control method for a wake-up timer circuit that can reduce power consumption without reducing the accuracy of checking received radio waves, even when the reception frequency varies depending on the time of day. [Means for solving the problem]

[0010] In order to solve the above problem, the wake-up timer circuit of the present invention comprises a reception frequency recording circuit that records a reception frequency, which is the frequency at which received radio waves are detected per unit time, an addition value selection circuit that changes an addition value signal according to the reception frequency per unit time, a timer counter that increments a count value according to the addition value signal, and a comparator that compares the count value with a predetermined count expiration value and outputs a start signal when the count value becomes equal to or greater than the count expiration value.

[0011] The wireless IC of the present invention includes the above-mentioned wake-up timer circuit, a reception detection circuit that outputs a reception detection signal indicating that a received radio wave has been detected to the wake-up timer circuit, and a unit time elapse notification circuit that outputs a unit time elapse notification signal that notifies the wake-up timer circuit that a unit time has elapsed.

[0012] In a control method for a wake-up timer circuit according to the present invention, the wake-up timer circuit records a reception frequency, which is the frequency at which received radio waves are detected per unit time, changes an addition value signal according to the reception frequency per unit time, increments a count value according to the addition value signal, compares the count value with a predetermined count expiration value, and outputs a start signal when the count value becomes equal to or greater than the count expiration value. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a block diagram showing an example of a configuration of a wireless communication device according to a first embodiment. [Figure 2] 1 is a block diagram showing an example of the configuration of a wake-up timer circuit according to a first embodiment. [Figure 3] 1 is a block diagram showing an example of the configuration of a reception frequency recording circuit according to a first embodiment. [Figure 4] 2 is a block diagram showing an example of the configuration of an addend selection circuit according to the first embodiment. FIG. [Figure 5] 4A and 4B are diagrams illustrating an example of the operation of the wake-up timer circuit according to the first embodiment. [Figure 6] 4 is a flowchart showing an example of the flow of a control method for the wake-up timer circuit according to the first embodiment. [Figure 7] FIG. 10 is a block diagram showing an example of the configuration of an addend selection circuit according to a second embodiment. [Figure 8] 10A and 10B are diagrams illustrating an example of the operation of the wake-up timer circuit according to the second embodiment. [Figure 9] FIG. 1 is a block diagram showing a configuration of a conventional wireless communication device. [Figure 10] FIG. 1 is a block diagram showing a configuration of a conventional wake-up timer circuit. DETAILED DESCRIPTION OF THE INVENTION

[0014] An example of an embodiment of the technology of the present invention will be described in detail below with reference to the drawings. Note that components and processes that perform similar operations, actions, and functions are given the same reference numerals throughout the drawings, and duplicated descriptions may be omitted as appropriate. Each drawing is merely a schematic illustration to allow a sufficient understanding of the technology of the present invention. Therefore, the technology of the present invention is not limited to the illustrated examples. Furthermore, in this embodiment, descriptions of configurations that are not directly related to the present invention or well-known configurations may be omitted.

[0015] [First embodiment] 1 is a block diagram showing an example of the configuration of a wireless communication device according to the first embodiment. The wireless communication device shown in FIG.

[0016] As shown in FIG. 1, a wireless IC 100 according to this embodiment includes an antenna 101, a reception detection circuit 102, a wake-up timer circuit 103, an SPI circuit 104, and a unit time lapse notification circuit 105.

[0017] The antenna 101 is an antenna for transmitting and receiving radio waves. The reception detection circuit 102 is connected to the antenna 101, detects received radio waves, and outputs a reception detection signal to the wake-up timer circuit 103. The reception detection signal is a signal indicating that received radio waves have been detected. The wake-up timer circuit 103 inputs the reception detection signal from the reception detection circuit 102 and outputs an activation signal to the reception detection circuit 102. The activation signal is a signal for activating the microcomputer 200 via the reception detection circuit 102.

[0018] The unit time lapse notification circuit 105 outputs a unit time lapse notification signal to the wake-up timer circuit 103. The unit time lapse notification signal is a signal that notifies the passage of a unit time. The "unit time" here is, for example, one hour, but is not particularly limited and may be set to an appropriate time depending on the application of the wireless communication device, etc. The reception detection circuit 102 and the wake-up timer circuit 103 are each connected to the microcomputer 200 via the SPI circuit 104. The microcomputer 200 is normally in a sleep state to reduce power consumption, and is woken up by a microcomputer wake-up interrupt signal from the reception detection circuit 102.

[0019] The wake-up timer circuit 103 puts the wireless IC 100 into a state where it can transmit and receive data in response to the unit time elapse notification signal input from the unit time elapse notification circuit 105. When the reception detection circuit 102 detects a received radio wave, it outputs a reception detection signal to the wake-up timer circuit 103. The wake-up timer circuit 103 outputs a start-up signal to the reception detection circuit 102, and the reception detection circuit 102 outputs a microcomputer start-up interrupt signal to the microcomputer 200 in response to the start-up signal, thereby starting up the microcomputer 200.

[0020] FIG. 2 is a block diagram showing an example of the configuration of the wake-up timer circuit 103 according to the first embodiment.

[0021] As shown in FIG. 2, the wake-up timer circuit 103 of this embodiment includes a count expiration value register 10, a count enable register 20, a timer counter 30, a comparator 40, a reception frequency recording circuit 50, an addition value selection circuit 60, and a reception frequency recording enable register 70.

[0022] The reception frequency recording circuit 50 receives a unit time elapse notification signal from the unit time elapse notification circuit 105 and a reception detection signal from the reception detection circuit 102. The reception frequency recording circuit 50 records the reception frequency. The reception frequency is the frequency at which received radio waves are detected per unit time. The addition value selection circuit 60 changes the addition value signal according to the reception frequency per unit time. The timer counter 30 increments the count value according to the addition value signal. The comparator 40 compares the count value input from the timer counter 30 with a count completion value preset in the count completion value register 10, and outputs a start signal when the count value becomes equal to or greater than the count completion value.

[0023] Specifically, register control is performed by the microcomputer 200 via the SPI circuit 104. The reception frequency recording circuit 50 is enabled while the reception frequency recording enable register 70 is set from the microcomputer 200 via the SPI circuit 104. The reception frequency recording circuit 50 counts the number of times a reception detection signal is input, and stores the number of reception detections per unit time in a table within the reception frequency recording circuit 50 each time the unit time elapsed notification signal goes high. The stored data (i.e., the number of reception detections) is input to the addend value selection circuit 60 as a table value read signal, and an addend value signal is output via a decoder circuit within the addend value selection circuit 60.

[0024] On the other hand, when data is stored in the table up to a preset value, the reception frequency recording circuit 50 outputs a table expiration notification signal to the addition value selection circuit 60 and also outputs a recording disable signal to the reception frequency recording enable register 70. When the recording disable signal is input, the reception frequency recording enable register 70 sets the recording enable signal to Low to disable the reception frequency recording circuit 50.

[0025] Next, the operation of the wake-up timer circuit 103 will be described. First, a count completion value for waking up is set in the count completion value register 10. Next, when the count enable register 20 is set, a count enable signal is output to the timer counter 30. While the count enable signal is set, the timer counter 30 begins incrementing its count value each time an addition value signal is input from the addition value selection circuit 60. The count value counted by the timer counter 30 is appropriately compared with the count completion value in the count completion value register 10 by the comparator 40. When the count value becomes equal to or greater than the count completion value, the comparator 40 outputs a start signal and simultaneously outputs a count clear signal to the timer counter 30. The count clear signal resets the count value of the timer counter 30 to 0. When the count value of the timer counter 30 becomes 0, the start signal from the comparator 40 becomes invalid.

[0026] FIG. 3 is a block diagram showing an example of the configuration of the reception frequency recording circuit 50 according to the first embodiment.

[0027] As shown in FIG. 3, the reception frequency recording circuit 50 according to this embodiment includes a reception count recording table 51, a table value counter 52, a reception count counter 53, a table full register 54, and an AND circuit 55.

[0028] When the unit time elapsed notification signal is input, the table value counter 52 outputs a table value counter signal indicating the counted table value. The reception count counter 53 inputs the reception detection signal and the unit time elapsed notification signal, and outputs the number of times radio waves are received per unit time. When the unit time elapsed notification signal is input as a count clear signal, the reception count counter 53 resets the count value to 0. The reception count record table 51 outputs a table value read signal indicating the number of receptions input from the reception count counter 53 in accordance with the table value counter signal input from the table value counter 52. The table full register 54 outputs a table full notification signal when a preset value of data has been stored in the reception count record table 51. The AND circuit 55 inputs the record enable signal and the unit time elapsed notification signal, and outputs a reception count write signal to the reception count record table 51.

[0029] Next, the operation of the reception frequency recording circuit 50 will be described. When the reception frequency record enable register 70 is set and a received radio wave is detected during that time, the reception count counter 53 counts up each time. When a unit time elapsed notification signal is input to the AND circuit 55, table value counter 52, and reception count counter 53, the reception count write signal goes High, and the reception count and table value counter signal (table count value) at that time are written to the reception count recording table 51. Because the unit time elapsed notification signal also serves as a count clear signal for the reception count counter 53 at the same time as generating the write signal, the count value of the reception count counter 53 returns to 0. When data is stored in the table equal to the value set in the table full register 54, a table full notification signal is output and input as a record disable signal to the reception frequency record enable register 70, causing the record enable signal to go Low and disabling the reception frequency recording circuit 50.

[0030] FIG. 4 is a block diagram showing an example of the configuration of the addend selection circuit 60 according to the first embodiment.

[0031] As shown in FIG. 4, the addend selection circuit 60 according to this embodiment includes a decoder circuit 61 and a selector circuit 62.

[0032] The decoder circuit 61 outputs a table value addition signal in response to a table value read signal input from the reception count record table 51. The selector circuit 62 selects the table value addition signal input from the decoder circuit 61 as an addition value signal when the table expiration notification signal input from the table full register 54 is High.

[0033] Next, the operation of the addition value selection circuit 60 will be described. When a table value read signal is input from the reception count record table 51, a table value addition signal is generated through the decoder circuit 61. If the table expiration notification signal is High at that time, the table value addition signal is selected as the addition value signal by the selector circuit 62. The output addition value signal is input to the timer counter 30 and used as the increment value for the timer counter 30.

[0034] Fig. 5 is a diagram showing an example of the operation of the wake-up timer circuit 103 according to the first embodiment. In Fig. 5, as an example, it is assumed that the reception frequency is sampled 24 times every hour and the number of receptions for one day is stored as a table.

[0035] First, the count expiration value register 10 is set to 0xFFFF, the record enable signal of the reception frequency record enable register 70 is set to High, and the value of the table full register 54 in the reception frequency recording circuit 50 is set to 0x17. From the point at which the value of the table full register 54 is set, the reception count counter 53 counts the number of receptions and stores the data every hour in the reception count record table 51 in the reception frequency recording circuit 50. Then, when the count value of the table value counter 52 reaches the value set in the table full register 54, the reception frequency recording circuit 50 outputs a table expiration notification signal. This table expiration notification signal becomes a record disable signal for the reception frequency record enable register 70, and the value in the reception count record table 51 is not updated thereafter.

[0036] When the table expiration notification signal goes high, the selector circuit 62 in the addend selection circuit 60 operates. The addend signal, which had previously been output at a fixed value of 1, is decoded and output as a value corresponding to the table value read signal. When the table expiration notification signal goes high, the table value read signal changes according to the table value counter signal in the reception frequency recording circuit 50. In the example of Figure 5, the value output as the addend signal is 0x100 if the number of receptions is 0 or more but less than 50, 0x1000 if the number of receptions is 50 or more but less than 100, and 0x10000 if the number of receptions is 100 or more.

[0037] Next, the operation of the wake-up timer circuit 103 according to the first embodiment will be described with reference to FIG.

[0038] FIG. 6 is a flowchart showing an example of the flow of a control method for the wake-up timer circuit 103 according to the first embodiment.

[0039] In step S101 of FIG. 6, the reception frequency recording circuit 50 receives an input of a unit time lapse notification signal from the unit time lapse notification circuit 105, as shown in FIG. 2 above, for example.

[0040] In step S102, the reception frequency recording circuit 50 records the reception frequency, which is the frequency at which received radio waves are detected per unit time, in response to the unit time elapse notification signal, as shown in FIG. 2 above, for example.

[0041] In step S103, the addition value selection circuit 60 changes and outputs the addition value signal according to the reception frequency per unit time, which is represented as a table value read signal input from the reception frequency recording circuit 50, as shown in Figure 2 above, as an example.

[0042] In step S104, the timer counter 30 increments the count value in response to the additional value signal input from the additional value selection circuit 60, as shown in FIG. 2 above, for example.

[0043] In step S105, the comparator 40 determines whether the count value input from the timer counter 30 is equal to or greater than the count expiration value preset in the count expiration value register 10. If the count value is equal to or greater than the count expiration value (if the determination is affirmative), the process proceeds to step S106, and if the count value is less than the count expiration value (if the determination is negative), the process returns to step S101 and repeats.

[0044] In step S106, the comparator 40 outputs an activation signal to the reception detection circuit 102, as shown in FIG. 2 above, for example.

[0045] In step S107, the reception frequency recording circuit 50 determines whether the end timing has arrived. If it is determined that the end timing has not arrived (in the case of a negative determination), the process returns to step S101 and is repeated, and if it is determined that the end timing has arrived (in the case of a positive determination), the series of processes ends.

[0046] In this embodiment, the unit time elapsed notification circuit 105 is provided to generate the unit time elapsed notification signal, but the unit time elapsed notification signal may also be generated by, for example, dividing a 32 kHz clock. As an example, since the 32 kHz clock has a period of 31,250 ns, if a pulse is to be generated every hour, this can be achieved by dividing the period by 115,200,000. Furthermore, in addition to recording the reception frequency every hour, the unit time to be recorded may be changed as appropriate, such as in units of one day or one minute.

[0047] According to this embodiment, even if the reception frequency varies depending on the time period, the reception frequency recording circuit 50 and the addition value selection circuit 60 can change the addition value signal to the timer counter 30. Therefore, it is possible to reduce the unnecessary waiting state for reception of radio waves while maintaining the accuracy of checking the reception of radio waves.

[0048] Furthermore, because startup control is completed within the wake-up timer circuit 103, the microcomputer 200 does not need to constantly check the time and set the wake-up period. As a result, the operating time of the microcomputer 200 is reduced, and low power consumption can be achieved while maintaining the accuracy of checking received radio waves.

[0049] [Second embodiment] In the second embodiment, a clock dividing function that can lengthen the wake-up period by dividing the clock will be described. Note that the wake-up timer circuit of the second embodiment differs from the wake-up timer circuit of the first embodiment only in the configuration of the additional value selection circuit, and the other circuit configurations are the same, so repeated explanations will be omitted here.

[0050] FIG. 7 is a block diagram showing an example of the configuration of an addend selection circuit 60A according to the second embodiment.

[0051] As shown in FIG. 7, the addend selection circuit 60A of this embodiment includes a decoder circuit 61, a first selector circuit 62, a comparator 63, a frequency division threshold register 64, a flip-flop circuit 65, and a second selector circuit 66.

[0052] The decoder circuit 61 outputs a table value addition signal in response to a table value read signal input from the reception count record table 51. A threshold value for comparison with the reception count is set in the frequency division threshold register 64. The comparator 63 compares the reception count of the table value read signal input from the reception count record table 51 with the threshold value set in the frequency division threshold register 64, and outputs a comparison signal if the reception count is less than the threshold value. The first selector circuit 62 selects the table value addition signal input from the decoder circuit 61 as an addition value signal when the comparison signal input from the comparator 63 is High. The flip-flop circuit 65 inputs a timer counter clock and outputs a divided timer clock obtained by dividing the timer clock indicated by the timer counter clock. The second selector circuit 66 selects the divided timer clock input from the flip-flop circuit 65 when the comparison signal input from the comparator 63 is High.

[0053] According to the clock frequency division function, when the number of receptions is less than the threshold set in the frequency division threshold register 64, the wake-up period can be lengthened more flexibly by dividing the clock frequency.

[0054] Next, the operation of the addend selection circuit 60A will be described. When a table value read signal is input to the decoder circuit 61, the comparator 63 compares the number of times the table value read signal is received with the threshold set in the frequency division threshold register 64. If the number of times the signal is received at that time is smaller than the threshold set in the frequency division threshold register 64, the comparison signal goes high, causing the first selector circuit 62 to select 1 as the addend signal, and causing the flip-flop circuit 65 to divide the timer clock by 2.

[0055] Fig. 8 is a diagram showing an example of the operation of the wake-up timer circuit 103 according to the second embodiment. In Fig. 8, as an example, it is assumed that the reception frequency is sampled 24 times every hour and the number of receptions for one day is stored as a table.

[0056] First, the microcomputer 200 sets the frequency division threshold register 64 in advance via the SPI circuit 104. In the example of FIG. 8, it is set to 0x32. The lowest 8 bits of the table value read signal indicate the number of receptions, and if the number of receptions is less than 50, 0x1 is selected as the addition value signal; if the number of receptions is between 50 and 100, 0x100 is selected as the addition value signal; and if the number of receptions is 200 or more, 0x1000 is selected as the addition value signal. Furthermore, if the number of receptions is less than 0x32 set in the frequency division threshold register 64, the timer clock is divided by 2 and output as soon as the addition value signal becomes 0x1, thereby lengthening the wake-up period.

[0057] As described above, by providing the frequency division threshold register 64 and the flip-flop circuit 65 in the addition value selection circuit 60A, it is possible not only to shorten the wake-up period during time periods when the reception frequency is high, but also to lengthen the wake-up period by dividing the timer clock. It is also possible to reduce wake-up events during time periods when the reception frequency is low. Reducing the number of times the circuits in the wireless IC 100 are started also reduces the power consumption of the wireless IC 100. This makes it possible to achieve lower power consumption throughout the entire system, including the wireless IC 100 and the microcomputer 200.

[0058] In this embodiment, the frequency is fixed to 2 when the number of receptions is less than the threshold of the frequency division threshold register 64, but a frequency division circuit that can adjust the clock period may be provided. Also, a register may be provided for the decoder circuit that outputs a fixed addition value according to the number of receptions, so that a variable addition value can be set.

[0059] It should be noted that the configurations of the wake-up timer circuit and wireless device described in the above embodiments are merely examples, and it goes without saying that the configurations may be changed within the scope of the embodiments without departing from the spirit of the embodiments.

[0060] The following additional notes are provided regarding the above-described embodiments.

[0061] (Appendix 1) a reception frequency recording circuit for recording a reception frequency, which is the frequency at which received radio waves are detected per unit time; an additional value selection circuit that changes an additional value signal in accordance with the reception frequency per unit time; a timer counter that increments a count value in response to the additional value signal; a comparator that compares the count value with a predetermined count end value and outputs a start signal when the count value is equal to or greater than the count end value; 1. A wake-up timer circuit comprising: (Appendix 2) The reception frequency recording circuit a table value counter that outputs a table value counter signal indicating a counted table value when a unit time lapse notification signal that notifies the user that a unit time has lapsed is input; a reception count counter that receives a reception detection signal indicating that a received radio wave has been detected and the unit time lapse notification signal, and outputs the number of times the received radio wave has been received per unit time; a reception count recording table that outputs a table value read signal indicating the number of receptions input from the reception count counter in response to the table value counter signal input from the table value counter; a table full register that outputs a table expiration notification signal when a preset amount of data has been stored in the reception count record table; Including, 2. The wake-up timer circuit of claim 1. (Appendix 3) The addition value selection circuit a decoder circuit that outputs a table value addition signal in response to the table value read signal input from the reception count record table; a selector circuit that selects the table value addition signal input from the decoder circuit as an addition value signal when the table expiration notification signal input from the table full register is high; Including, 3. The wake-up timer circuit of claim 2. (Appendix 4) The addition value selection circuit a decoder circuit that outputs a table value addition signal in response to the table value read signal input from the reception count record table; a division threshold register in which a threshold is set; a comparator that compares the number of times the table value read signal is received with a threshold value set in the frequency division threshold register, and outputs a comparison signal if the number of times the table value read signal is received is less than the threshold value; a first selector circuit that selects the table value addition signal input from the decoder circuit as an addition value signal when the comparison signal input from the comparator is High; a flip-flop circuit that receives a timer counter clock and divides a timer clock indicated by the timer counter clock, and outputs a divided timer clock; a second selector circuit that selects the divided timer clock input from the flip-flop circuit when the comparison signal input from the comparator is High; Including, 3. The wake-up timer circuit of claim 2. (Appendix 5) A wake-up timer circuit according to any one of Supplementary Note 1 to Supplementary Note 4; a reception detection circuit that outputs a reception detection signal indicating that a received radio wave has been detected to the wake-up timer circuit; a unit time lapse notification circuit that outputs a unit time lapse notification signal that is a signal that notifies the wake-up timer circuit that a unit time lapse has elapsed; A wireless IC equipped with (Appendix 6) The wake-up timer circuit Record the reception frequency, which is the frequency at which received radio waves are detected per unit time, changing the sum signal in accordance with the reception frequency per unit time; Incrementing a count value in response to the additional value signal; The count value is compared with a predetermined count end value, and when the count value is equal to or greater than the count end value, a start signal is output. A method for controlling a wake-up timer circuit. [Explanation of symbols]

[0062] 10 Count Expiration Value Register 20 Count Enable Register 30 Timer Counter 40 Comparator 50 Reception frequency recording circuit 60 Addition value selection circuit 70 Reception Frequency Record Enable Register 100 Wireless IC 101 Antenna 102 Reception detection circuit 103 Wake-up timer circuit 104 SPI circuit 105 Unit time elapsed notification circuit 200 microcomputers

Claims

1. a reception frequency recording circuit for recording a reception frequency, which is the frequency at which received radio waves are detected per unit time; an additional value selection circuit that changes an additional value signal in accordance with the reception frequency per unit time; a timer counter that increments a count value in response to the additional value signal; a comparator that compares the count value with a predetermined count end value and outputs a start signal when the count value is equal to or greater than the count end value; 1. A wake-up timer circuit comprising:

2. The reception frequency recording circuit a table value counter that outputs a table value counter signal indicating a counted table value when a unit time lapse notification signal that notifies the user that a unit time has lapsed is input; a reception count counter that receives a reception detection signal indicating that a received radio wave has been detected and the unit time lapse notification signal, and outputs the number of times the received radio wave has been received per unit time; a reception count recording table that outputs a table value read signal indicating the number of receptions input from the reception count counter in response to the table value counter signal input from the table value counter; a table full register that outputs a table expiration notification signal when a preset amount of data has been stored in the reception count record table; Including, 2. The wake-up timer circuit according to claim 1.

3. The addition value selection circuit a decoder circuit that outputs a table value addition signal in response to the table value read signal input from the reception count record table; a selector circuit that selects the table value addition signal input from the decoder circuit as an addition value signal when the table expiration notification signal input from the table full register is High; Including, 3. The wake-up timer circuit according to claim 2.

4. The addition value selection circuit a decoder circuit that outputs a table value addition signal in response to the table value read signal input from the reception count record table; a division threshold register in which a threshold is set; a comparator that compares the number of times the table value read signal is received with a threshold value set in the frequency division threshold register, and outputs a comparison signal if the number of times the table value read signal is received is less than the threshold value; a first selector circuit that selects the table value addition signal input from the decoder circuit as an addition value signal when the comparison signal input from the comparator is High; a flip-flop circuit that receives a timer counter clock and divides a timer clock indicated by the timer counter clock, and outputs a divided timer clock; a second selector circuit that selects the divided timer clock input from the flip-flop circuit when the comparison signal input from the comparator is High; Including, 3. The wake-up timer circuit according to claim 2.

5. A wake-up timer circuit according to any one of claims 1 to 4; a reception detection circuit that outputs a reception detection signal indicating that a received radio wave has been detected to the wake-up timer circuit; a unit time lapse notification circuit that outputs a unit time lapse notification signal that is a signal that notifies the wake-up timer circuit that a unit time lapse has elapsed; A wireless IC equipped with the above.

6. The wake-up timer circuit Record the reception frequency, which is the frequency at which received radio waves are detected per unit time, changing the sum signal in accordance with the reception frequency per unit time; Incrementing a count value in response to the additional value signal; The count value is compared with a predetermined count end value, and when the count value is equal to or greater than the count end value, a start signal is output. A method for controlling a wake-up timer circuit.

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