Ceramic electronic component

Abstract

To provide a ceramic electronic component that can increase capacitance in the low voltage and high frequency range.SOLUTION: A ceramic electronic component includes a laminated chip including a laminated portion in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked, and the plurality of internal electrode layers are alternately drawn out to two opposing end faces of the laminated chip, the laminated chip has a side margin outside a capacitive portion which is a region where the plurality of dielectric layers and the plurality of internal electrode layers are opposed in a third direction perpendicular to a first direction in which the plurality of internal electrode layers are opposed to each other and a second direction in which the two end faces are opposed to each other, and the plurality of internal electrode layers are provided in a total of 300 or more layers, and the thickness of the plurality of internal electrode layers is 1.5 times or more the thickness of the plurality of dielectric layers.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] The present invention relates to a ceramic electronic component. [Background technology]

[0002] BACKGROUND ART Ceramic electronic components such as multilayer ceramic capacitors have a structure in which internal electrode layers are laminated with dielectric layers sandwiched therebetween (see, for example, Patent Documents 1 to 3). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Laid-Open No. 2014-204117 [Patent Document 2] U.S. Patent Publication No. 2022 / 0157530 [Patent Document 3] Japanese Patent Publication No. 2022-073955 Summary of the Invention [Problem to be solved by the invention]

[0004] Generally, in a dielectric layer, the larger the grain diameter, the higher the dielectric constant, and the higher the dielectric constant, the higher the capacitance of the entire ceramic electronic component. However, in the low-voltage, high-frequency region, a dielectric with a high dielectric constant may have its capacitance reversed by a dielectric with a low dielectric constant.

[0005] The present invention has been made in view of the above-mentioned problems, and has as its object to provide a ceramic electronic component that can increase the capacitance in the low voltage and high frequency range. [Means for solving the problem]

[0006] The ceramic electronic component according to the present invention comprises a laminated chip including a laminated portion in which a plurality of dielectric layers and a plurality of internal electrode layers are stacked, the plurality of internal electrode layers being alternately drawn out to two opposing end faces of the laminated chip, the laminated chip having a side margin outside a capacitive portion which is a region where the plurality of dielectric layers and the plurality of internal electrode layers are opposed in a third direction perpendicular to a first direction in which the plurality of internal electrode layers are opposed to each other and a second direction in which the two end faces are opposed to each other, the plurality of internal electrode layers being provided in a number of 300 or more, and the thickness of the plurality of internal electrode layers being 1.5 times or more the thickness of the plurality of dielectric layers.

[0007] In the plurality of dielectric layers of the ceramic electronic component, when an outer 10% region of each of the capacitance sections in the third direction is defined as an outer region and the remaining 80% region is defined as an inner region, the D50% grain size of the ceramic grain size distribution in the outer region may be larger than the D50% grain size of the ceramic grain size distribution in the inner region.

[0008] In the plurality of dielectric layers of the ceramic electronic component, when an outer 10% region of each of the capacitance sections in the third direction is defined as an outer region and the remaining 80% region is defined as an inner region, the D50% particle size of the ceramic grain size distribution in the inner region may be 50 nm or more and 200 nm or less.

[0009] In the plurality of dielectric layers of the ceramic electronic component, when an outer region is defined as a 10% region on the outside of each of the dimensions of the capacitive section in the third direction, and an inner region is defined as the remaining 80% region, the D90% particle size of the ceramic grain size distribution in the inner region may be 300 nm or less.

[0010] In the ceramic electronic component, the Si / Ti element ratio in the side margin may be greater than the Si / Ti element ratio in the plurality of dielectric layers in the capacitance section.

[0011] In the ceramic electronic component, the Si / Ti element number ratio in the side margin may be 0.01 or more.

[0012] In the ceramic electronic component, an end margin may be defined as a region outside the capacitive portion of the laminated chip in the second direction, where internal electrode layers drawn to one of the two end faces face each other without an internal electrode layer drawn to the other end face in between, and the Si / Ti element ratio in the end margin may be greater than the Si / Ti element ratio of the plurality of dielectric layers in the capacitive portion.

[0013] In the ceramic electronic component, the Si / Ti element number ratio in the end margin may be 0.01 or more.

[0014] The ceramic electronic component may have a size equal to or larger than the 0603 shape.

[0015] In the ceramic electronic component, the plurality of internal electrode layers may be provided in a number of 500 or more, and the ceramic electronic component may have a size of 1005 or larger.

[0016] In the ceramic electronic component, the Si / Ti element number ratio in the side margin may be 0.03 or more.

[0017] In the ceramic electronic component, the Si / Ti element number ratio in the end margin may be 0.03 or more. [Effects of the Invention]

[0018] According to the present invention, it is possible to provide a ceramic electronic component that can increase capacitance in the low voltage and high frequency range. [Brief explanation of the drawings]

[0019] [Figure 1] FIG. 2 is a partial cross-sectional perspective view of a multilayer ceramic capacitor. [Figure 2] FIG. 2 is a cross-sectional view taken along line AA in FIG. [Figure 3] FIG. 2 is a cross-sectional view taken along line BB in FIG. [Figure 4] FIG. 2 is an enlarged cross-sectional view of the vicinity of an external electrode. [Figure 5] (a) is an enlarged view of the YZ cross section, and (b) is an enlarged view of the XZ cross section. [Figure 6] FIG. 10 is a diagram for explaining grain rearrangement. [Figure 7] FIG. 2 is an enlarged schematic cross-sectional view of the vicinity of a side margin. [Figure 8] 2 is a diagram for explaining each region in a YZ cross section corresponding to the cross section along the line BB in FIG. 1. FIG. [Figure 9] FIG. 2 is a diagram illustrating the relationship between the silicon content and the amount of shrinkage. [Figure 10] 1A to 1C are diagrams illustrating a flow of a method for manufacturing a multilayer ceramic capacitor. [Figure 11] 10(a) and 10(b) are diagrams illustrating an internal electrode forming step. [Figure 12] 10A to 10C are diagrams illustrating a crimping step. [Figure 13] 10A and 10B are diagrams illustrating an example in which a side margin portion is retrofitted. DETAILED DESCRIPTION OF THE INVENTION

[0020] Hereinafter, embodiments will be described with reference to the drawings.

[0021] (Embodiment) FIG. 1 is a partial cross-sectional perspective view of a multilayer ceramic capacitor 100 according to an embodiment. FIG. 2 is a cross-sectional view taken along line AA in FIG. 1. FIG. 3 is a cross-sectional view taken along line BB in FIG. 1. As illustrated in FIGS. 1 to 3, the multilayer ceramic capacitor 100 includes a laminated chip 10 having a substantially rectangular parallelepiped shape and external electrodes 20a, 20b provided on two opposing end faces of the laminated chip 10. Of the four faces of the laminated chip 10 other than the two end faces, the two faces other than the top and bottom faces in the stacking direction are referred to as side faces. The external electrodes 20a, 20b extend on the top, bottom and two side faces of the laminated chip 10 in the stacking direction. However, the external electrodes 20a, 20b are spaced apart from each other.

[0022] 1 to 3, the Z-axis direction (first direction) is the stacking direction, and is the direction in which the internal electrode layers 12 face each other. The X-axis direction (second direction) is the length direction of the laminated chip 10, and is the direction in which the two end faces of the laminated chip 10 face each other, and is the direction in which the external electrodes 20a and 20b face each other. The Y-axis direction (third direction) is the width direction of the internal electrode layers 12, and is the direction in which the two side faces other than the two end faces of the four side faces of the laminated chip 10 face each other. The X-axis direction, Y-axis direction, and Z-axis direction are perpendicular to each other.

[0023] The multilayer chip 10 has a configuration in which dielectric layers 11 containing a ceramic material that functions as a dielectric and internal electrode layers 12 are alternately stacked. The edges of each internal electrode layer 12 are alternately extended to the end face of the multilayer chip 10 where the external electrode 20a is provided and the end face where the external electrode 20b is provided. As a result, each internal electrode layer 12 is alternately electrically connected to the external electrode 20a and the external electrode 20b. As a result, the multilayer ceramic capacitor 100 has a configuration in which multiple dielectric layers 11 are stacked with the internal electrode layers 12 interposed therebetween. In addition, in the stack of the dielectric layers 11 and the internal electrode layers 12, internal electrode layers 12 are arranged on both outermost layers in the stacking direction, and the outermost internal electrode layers 12 are covered by cover layers 13. The cover layers 13 are primarily composed of a ceramic material. For example, the cover layers 13 may have the same or different composition as the dielectric layers 11.

[0024] The size of the multilayer ceramic capacitor 100 is, for example, 0.25 mm in length, 0.125 mm in width, and 0.125 mm in height, or 0.4 mm in length, 0.2 mm in width, and 0.2 mm in height, or 0.6 mm in length, 0.3 mm in width, and 0.3 mm in height, or 1.0 mm in length, 0.5 mm in width, and 0.5 mm in height, or 3.2 mm in length, 1.6 mm in width, and 1.6 mm in height, or 4.5 mm in length, 3.2 mm in width, and 2.5 mm in height, but is not limited to these sizes.

[0025] The internal electrode layers 12 are mainly composed of base metals such as nickel (Ni), copper (Cu), tin (Sn), etc., or alloys thereof. The internal electrode layers 12 may also be mainly composed of precious metals such as platinum (Pt), palladium (Pd), silver (Ag), gold (Au), etc., or alloys containing these metals. The internal electrode layers 12 may also contain ceramic particles as co-materials.

[0026] The dielectric layer 11 has a main phase made of a ceramic material having a perovskite structure represented by the general formula ABO3. 3-α For example, the ceramic material includes barium titanate (BaTiO3), calcium zirconate (CaZrO3), calcium titanate (CaTiO3), strontium titanate (SrTiO3), magnesium titanate (MgTiO3), Ba which forms a perovskite structure, 1-x-y Ca x Sr y Ti 1-z Zr z At least one of the following can be selected and used: O3 (0≦x≦1, 0≦y≦1, 0≦z≦1). 1-x-y Ca x Sr y Ti 1-z Zr zO3 is barium strontium titanate, barium calcium titanate, barium zirconate, barium titanate zirconate, calcium titanate zirconate, barium calcium titanate zirconate, etc. For example, the dielectric layer 11 contains 90 at % or more of the main component ceramic.

[0027] An additive may be added to the dielectric layer 11. Examples of additives to the dielectric layer 11 include oxides of zirconium (Zr), hafnium (Hf), magnesium (Mg), manganese (Mn), molybdenum (Mo), vanadium (V), chromium (Cr), rare earth elements (yttrium (Y), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), and ytterbium (Yb)), oxides containing cobalt (Co), nickel (Ni), lithium (Li), boron (B), sodium (Na), potassium (K), or silicon (Si), or glasses containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0028] 2, the region where the internal electrode layer 12 connected to the external electrode 20a and the internal electrode layer 12 connected to the external electrode 20b face each other is a region where capacitance is generated in the multilayer ceramic capacitor 100. Therefore, this region where capacitance is generated is referred to as a capacitance portion 14. In other words, the capacitance portion 14 is a region where adjacent internal electrode layers 12 connected to different external electrodes face each other.

[0029] The region where the internal electrode layers 12 connected to the external electrode 20a face each other without an internal electrode layer 12 connected to the external electrode 20b interposed therebetween is called the end margin 15. The region where the internal electrode layers 12 connected to the external electrode 20b face each other without an internal electrode layer 12 connected to the external electrode 20a interposed therebetween is also the end margin 15. In other words, the end margin 15 is the region where the internal electrode layers 12 connected to the same external electrode face each other without an internal electrode layer 12 connected to a different external electrode interposed therebetween. The end margin 15 is a region where no capacitance is generated.

[0030] 3, in the laminated chip 10, the side margins 16 are regions provided to cover the ends (ends in the Y-axis direction) of two side surfaces of the dielectric layers 11 and the internal electrode layers 12. In other words, the side margins 16 are regions provided outside the capacitive section 14 in the Y-axis direction. The side margins 16 are also regions that do not generate electrical capacitance.

[0031] FIG. 4 is an enlarged cross-sectional view of the vicinity of the external electrode 20a. Hatching is omitted in FIG. 4. As illustrated in FIG. 4, a plating layer 22 may be provided on the outer surface of the external electrode 20a, with the external electrode 20a serving as a base layer. The external electrode 20a is primarily composed of Cu. The external electrode 20a may also contain a glass component. The plating layer 22 is primarily composed of a metal such as Cu, Ni, aluminum (Al), zinc (Zn), or Sn, or an alloy of two or more of these metals. The plating layer 22 may be a plating layer of a single metal component, or may be a plurality of plating layers of different metal components. For example, the plating layer 22 has a structure in which a first plating layer 23, a second plating layer 24, and a third plating layer 25 are formed in this order from the external electrode 20a side. The first plating layer 23 is, for example, a Cu plating layer. The second plating layer 24 is, for example, a Ni plating layer. The third plating layer 25 is, for example, a Sn plating layer. Although FIG. 4 illustrates the external electrode 20a as an example, the plating layer 22 may also be provided on the outer surface of the external electrode 20b in the same manner.

[0032] Fig. 5(a) is an enlarged view of the YZ cross section. As illustrated in Fig. 5(a), the dielectric layer 11 has a structure in which a plurality of ceramic grains 41 are sintered. The side margin 16 has a structure in which a plurality of ceramic grains 42 are sintered. Fig. 5(b) is an enlarged view of the XZ cross section. As illustrated in Fig. 5(b), the ceramic portion in the end margin 15 has a structure in which a plurality of ceramic grains 43 are sintered.

[0033] In such multilayer ceramic capacitors, the larger the grain diameter in the dielectric layers, the higher the dielectric constant, and the higher the dielectric constant, the higher the capacitance of the entire multilayer ceramic capacitor. However, in the low-voltage, high-frequency range, a high-dielectric-constant dielectric may have its capacitance reversed by a low-dielectric-constant dielectric.

[0034] Recently, there has been an increasing demand for multilayer ceramic capacitors to exhibit high capacitance in the low voltage and high frequency range, which has led to the need for new dielectrics and structural designs that are different from those used in the past.

[0035] It is known that increasing the capacitance in the low-voltage, high-frequency range is effective by increasing the number of layers while keeping the grain diameter in the dielectric layer uniform and small, and by increasing the area of ​​the internal electrode layer inside the ceramic electronic component. Possible methods for increasing the number of layers include reducing the thickness of each layer or slightly expanding the case size in the height direction. To reduce the grain diameter, the particle size of the dielectric material powder must be reduced.

[0036] However, when small-diameter dielectric powder is used, grain rearrangement during sintering becomes easier, facilitating sintering. As sintering progresses, the grain size gradually increases. This tendency is particularly pronounced near the side and end margins, where the continuity of the electrodes is interrupted and grain rearrangement is more likely to occur.

[0037] FIG. 6 is a diagram for explaining grain rearrangement. FIG. 6 schematically illustrates a cross section near a side margin 201. As illustrated in FIG. 6, when the dielectric layer 202 and the internal electrode layer 203 have similar thicknesses, the region in the Z-axis direction of the internal electrode layer 203, where sintering tends to proceed first during firing, becomes narrower, and the amount of shrinkage in the Z-axis direction in the side margin 201 is therefore smaller. This makes it relatively easy for the ceramic grains 204 to be rearranged in the region of the dielectric layer 202. The amount of shrinkage is also small in the end margin, so that it is relatively easy for the ceramic grains 204 to be rearranged in the region of the dielectric layer 202.

[0038] Furthermore, the greater the number of laminated dielectric layers 202 and internal electrode layers 203, the more the restraining force from the side margins 201 is dispersed, which also makes it easier for rearrangement of the ceramic grains 204 to occur in the dielectric layers 202, and promotes sintering. Therefore, when a smaller-diameter dielectric material is used and the number of laminated layers is increased, it is difficult to obtain the desired uniform distribution of small-diameter grains.

[0039] Therefore, the multilayer ceramic capacitor 100 according to this embodiment has a configuration capable of suppressing rearrangement of the ceramic grains 41 in the dielectric layers 11. First, the number of stacked internal electrode layers 12 is set to 300 or more. This increases the capacitance. Next, the thickness of the internal electrode layers 12 in the Z-axis direction is increased. FIG. 7 is a schematic cross-sectional view enlarging the vicinity of the side margin 16. As illustrated in FIG. 7, the thickness of the internal electrode layers 12 in the Z-axis direction is set to 1.5 times or more the thickness of each dielectric layer 11 in the Z-axis direction. In this configuration, the region in the Z-axis direction of the internal electrode layer 203, where sintering tends to proceed first during firing, becomes wider, and the amount of shrinkage in the Z-axis direction in the side margin 16 increases. As a result, compressive stress in the Z-axis direction is applied to the region of the dielectric layer 11, suppressing rearrangement of the ceramic grains 41. This suppresses the enlargement of the grain diameter in the dielectric layer 11, enabling the ceramic grains 41 to be reduced in diameter and to have a uniform grain diameter. As a result, the capacitance can be increased in the low voltage and high frequency range.

[0040] The thickness of each of the internal electrode layers 12 in the Z-axis direction can be measured by observing a cross section of the multilayer ceramic capacitor 100 including the Z-axis direction with an SEM (scanning electron microscope), measuring the thickness at 10 points for each of 10 different internal electrode layers 12, and deriving the average value of all the measurement points. The thickness of each of the dielectric layers 11 in the Z-axis direction can be measured by observing a cross section of the multilayer ceramic capacitor 100 including the Z-axis direction with an SEM, measuring the thickness at 10 points for each of 10 different dielectric layers 11, and deriving the average value of all the measurement points.

[0041] In order to increase the amount of shrinkage in the Z-axis direction in the side margins 16, it is preferable to further thicken the internal electrode layers 12. In this embodiment, the thickness of the internal electrode layers 12 in the Z-axis direction is preferably 1.75 times or more, and more preferably 2 times or more, the thickness of each dielectric layer 11 in the Z-axis direction.

[0042] The thickness of each of the internal electrode layers 12 in the Z-axis direction is, for example, 0.20 μm to 0.90 μm, or 0.30 μm to 0.80 μm, or 0.40 μm to 0.70 μm. The thickness of each of the dielectric layers 11 in the Z-axis direction is, for example, 0.1 μm to 0.7 μm, or 0.2 μm to 0.6 μm, or 0.3 μm to 0.5 μm.

[0043] Furthermore, in the multilayer ceramic capacitor 100 according to this embodiment, the number of laminations of the internal electrode layers 12 may be 400 or more, or may be 500 or more. When the number of laminations of the internal electrode layers 12 is 300 or more, the multilayer ceramic capacitor 100 preferably has a size equal to or larger than a 0603 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). As an example, when the total thickness of the dielectric layers 11 and the internal electrode layers 12 is 1 μm or more, a height of approximately 300 μm is required. When the number of laminations of the internal electrode layers 12 is 500 or more, the multilayer ceramic capacitor 100 preferably has a size equal to or larger than a 1005 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm).

[0044] 8 is a diagram for explaining each region in a YZ cross section corresponding to the cross section taken along line BB in FIG. 1. As illustrated in FIG. 8, in the capacitive section 14, a region within a predetermined range on the inside in the Y-axis direction is defined as an inner region 141. In the capacitive section 14, two regions sandwiching the inner region 141 in the Y-axis direction are defined as outer regions 142. In this embodiment, when the dimension of the capacitive section 14 in the Y-axis direction is defined as 100%, each of the two outer regions 142 is a region within a range of 10%. Therefore, when the dimension of the capacitive section 14 in the Y-axis direction is defined as 100%, the dimension of the inner region 141 in the Y-axis direction is a region within a range of the remaining 80%.

[0045] In this embodiment, since it is preferable that the grain diameter of the ceramic grains 41 in the dielectric layer 11 is small, the D50% particle diameter of the particle size distribution of the ceramic grains 41 in the inner region 141 is preferably 200 nm or less, more preferably 150 nm or less, and even more preferably 120 nm or less. Furthermore, since it is preferable that the grain diameter of the ceramic grains 41 in the dielectric layer 11 is uniform, the D90% particle diameter of the particle size distribution of the ceramic grains 41 in the inner region 141 is preferably 300 nm or less, more preferably 250 nm or less, and even more preferably 200 nm or less.

[0046] If the grain diameter of the ceramic grains 41 in the dielectric layer 11 is too small, the dielectric constant may be too low, resulting in a lack of capacitance. Therefore, it is preferable to set a lower limit for the D50% grain diameter of the ceramic grains 41 in the dielectric layer 11 in the inner region 141. In this embodiment, the D50% grain diameter of the ceramic grains 41 in the dielectric layer 11 in the inner region 141 is preferably 50 nm or more, more preferably 80 nm or more, and even more preferably 100 nm or more.

[0047] It is preferable that the D50% grain size of the ceramic grains 41 of the dielectric layer 11 in the outer region 142 is larger than the D50% grain size of the ceramic grains 41 of the dielectric layer 11 in the inner region 141. This is because if the D50% grain size of the ceramic grains 41 in the outer region 142 is too small, the desired capacitance (0 V) may not be obtained.

[0048] Here, we will explain the method for measuring the particle size distribution of the ceramic grains in the inner region 141, outer region 142, and side margin 16. The multilayer ceramic capacitor 100 is cut at the center in the X-axis direction parallel to the end faces on which the external electrodes are formed, and the cross section is polished. This cross section corresponds to a YZ cross section. The particle size of the ceramic grains is measured based on a cross-sectional photograph of the dielectric layer taken of this cross section using a scanning electron microscope (SEM). Based on the SEM image, the maximum length of the ceramic grains in the lamination direction is defined as the grain diameter, and the particle size distribution is obtained. Once the particle size distribution is obtained, the D50% particle size and D90% particle size can be obtained.

[0049] Furthermore, in order to increase the amount of shrinkage in the Z-axis direction in the side margins 16, it is preferable to make the silicon concentration in the side margins 16 higher than that in the capacitive portion 14. When the main component of the dielectric layer 11 and the side margins 16 is barium titanate, the Si / Ti element ratio can be used as a substitute for the silicon concentration. Therefore, when the main component of the dielectric layer 11 and the side margins 16 is barium titanate, it is preferable that the Si / Ti element ratio be higher in the side margins 16 than in the capacitive portion 14 (the inner region 141 and the outer region).

[0050] Fig. 9 is a diagram illustrating the relationship between the silicon content and the amount of shrinkage. In Fig. 9, the horizontal axis represents temperature, and the vertical axis represents the amount of shrinkage (%). The larger the absolute value of the negative value of the amount of shrinkage, the greater the amount of shrinkage. As illustrated in Fig. 9, it can be seen that the greater the amount of SiO2 content, the greater the amount of shrinkage.

[0051] In the side margin 16, the Si / Ti element number ratio is preferably 0.01 or more, more preferably 0.03 or more, and even more preferably 0.05 or more.

[0052] Furthermore, in order to increase the amount of shrinkage in the Z-axis direction in end margin 15, it is preferable to make the silicon concentration in end margin 15 higher than the silicon concentration in capacitive portion 14. When the main component of dielectric layer 11 and end margin 15 is barium titanate, the Si / Ti element ratio can be used as a substitute for the silicon concentration. Therefore, when the main component of dielectric layer 11 and end margin 15 is barium titanate, it is preferable that the Si / Ti element ratio be higher in end margin 15 than in capacitive portion 14 (inner region 141 and outer region).

[0053] In the end margin 15, the Si / Ti element number ratio is preferably 0.01 or more, more preferably 0.03 or more, and even more preferably 0.05 or more.

[0054] Next, a description will be given of a method for manufacturing the multilayer ceramic capacitor 100. FIG.

[0055] (raw powder production process) First, a dielectric material for forming the dielectric layer 11 is prepared. The A-site elements and B-site elements contained in the dielectric layer 11 are typically contained in the dielectric layer 11 in the form of a sintered body of ABO3 particles. For example, barium titanate is a tetragonal compound with a perovskite structure and exhibits a high dielectric constant. This barium titanate can generally be obtained by synthesizing barium titanate by reacting a titanium raw material such as titanium dioxide with a barium raw material such as barium carbonate.

[0056] To the resulting ceramic powder, a predetermined additive compound is added depending on the purpose, such as an oxide of zirconium, hafnium, magnesium, manganese, molybdenum, vanadium, chromium, or a rare earth element (yttrium, samarium, europium, gadolinium, terbium, dysprosium, holmium, erbium, thulium, or ytterbium), or an oxide containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon, or a glass containing cobalt, nickel, lithium, boron, sodium, potassium, or silicon.

[0057] For example, a ceramic material is prepared by wet-mixing a ceramic raw material powder with a compound containing an additive compound, followed by drying and pulverization. For example, the ceramic material obtained as described above may be pulverized as necessary to adjust the particle size, or may be combined with a classification process to adjust the particle size. A dielectric material is obtained by the above process.

[0058] (Coating process) Next, a binder such as polyvinyl butyral (PVB) resin, an organic solvent such as ethanol or toluene, and a plasticizer are added to the obtained raw material powder and wet mixed. The obtained slurry is used to coat a dielectric green sheet 51 on a substrate by, for example, a die coater method or a doctor blade method, and then dried. The substrate is, for example, a polyethylene terephthalate (PET) film. Figures illustrating the coating process are omitted.

[0059] (Internal electrode formation process) Next, as illustrated in FIG. 11(a), a metal conductive paste for forming an internal electrode containing an organic binder is printed on the surface of the dielectric green sheet 51 by screen printing, gravure printing, or the like, to arrange an internal electrode pattern 52 for the internal electrode layer. In addition to nickel, ceramic particles are added to the metal conductive paste as a co-material. The main component of the ceramic particles is not particularly limited, but is preferably the same as the main component ceramic of the dielectric layer 11. The thickness of the internal electrode pattern 52 is adjusted so that the thickness of the internal electrode layer 12 obtained by firing the metal conductive paste is 1.5 times or more the thickness of the dielectric layer 11 obtained by firing the dielectric green sheet 51.

[0060] Next, a binder such as an ethyl cellulose-based binder and an organic solvent such as a terpineol-based binder are added to the dielectric pattern material obtained in the raw powder preparation step, and the mixture is kneaded in a roll mill to obtain a dielectric pattern paste for the reverse pattern layer. As illustrated in FIG. 11(a), a dielectric pattern paste is printed on a dielectric green sheet 51 in the peripheral area where the internal electrode pattern 52 is not printed, thereby arranging the dielectric pattern 53 and filling in any gaps with the internal electrode pattern 52. The dielectric green sheet 51 on which the internal electrode pattern 52 and the dielectric pattern 53 are printed is referred to as a lamination unit. In this embodiment, it is preferable that the silicon concentration relative to the main component ceramic is higher in the dielectric pattern 53 than in the dielectric green sheet 51.

[0061] 11(b), the laminated units are laminated so that the internal electrode layers 12 and the dielectric layers 11 are alternately arranged, and so that the edges of the internal electrode layers 12 are alternately exposed at both end faces in the length direction of the dielectric layers 11 and are alternately drawn out to a pair of external electrodes 20a, 20b having opposite polarities. In this embodiment, the number of laminated units is 300 or more.

[0062] (Crimping process) 12, a predetermined number (for example, 2 to 10 layers) of cover sheets 54 are laminated on the top and bottom of a laminate in which the lamination units are stacked, and then thermocompression bonded. The cover sheets 54 are also green sheets containing ceramic powder.

[0063] The side margins may be attached or applied to the side surfaces of the laminated portion. Specifically, as illustrated in FIG. 13, the laminated portion is obtained by alternately stacking dielectric green sheets 51 and internal electrode patterns 52 having the same width as the dielectric green sheets 51. Next, sheets formed from a dielectric pattern paste may be attached to the side surfaces of the laminated portion as side margins 55. In this embodiment, it is preferable that the silicon concentration in the main component ceramic is higher in the side margins 55 than in the dielectric green sheets 51.

[0064] (Firing process) The ceramic laminate thus obtained was subjected to binder removal treatment in an N2 atmosphere, and then a metal paste for the external electrodes 20a and 20b was applied by dipping. -12 MPa~10 -9 The mixture is fired in a reducing atmosphere at 1160°C to 1280°C (for example, 1180°C or higher and 1230°C or lower) under MPa for 5 minutes to 10 hours.

[0065] (Reoxidation treatment process) In order to return oxygen to the barium titanate, which is the partially reduced main phase of the dielectric layer 11 fired in a reducing atmosphere, heat treatment may be performed in a mixed gas of N2 and water vapor at about 1000°C or in the air at 500°C to 700°C, to a temperature that does not oxidize the internal electrode layer 12. This process is called a reoxidation treatment process.

[0066] (Plating process) Thereafter, the external electrodes 20a, 20b are plated with a metal coating of copper, nickel, tin, etc. Through the above steps, the multilayer ceramic capacitor 100 is completed.

[0067] In the above embodiments, a multilayer ceramic capacitor has been described as an example of a multilayer ceramic electronic component, but the present invention is not limited to this. For example, other multilayer ceramic electronic components such as a varistor or a thermistor may also be used. [Example]

[0068] The multilayer ceramic capacitor according to the above embodiment was fabricated and its characteristics were examined.

[0069] (Examples 1 to 6 and Comparative Examples 1 to 6) Barium titanate powder was prepared as the ceramic raw material powder. The average diameter of the ceramic raw material powder was set to 100 nm. The ceramic raw material powder was then wet-mixed with an organic solvent. A binder was added, and the resulting slurry was applied to a dielectric green sheet using the doctor blade method and dried. A Ni-containing metal conductive paste was screen-printed in a predetermined pattern onto the dielectric green sheet to form an internal electrode pattern. In addition, to fill the gap between the dielectric green sheet and the internal electrode pattern, a dielectric pattern having a pattern complementary to the internal electrode pattern was screen-printed onto the dielectric green sheet. The resulting laminate units were stacked, pressed, and cut to obtain a molded body.

[0070] The molded sample was debindered at 300°C in a N2 atmosphere. -5 atm~10-8 The material was fired in a reducing atmosphere at 1300 to 1250°C at 1 atm. After cooling, the material was heated to a temperature range of 800 to 1050°C in a N2 atmosphere and maintained at that temperature for reoxidation.

[0071] In all of Examples 1 to 6 and Comparative Examples 1 to 6, the size of the obtained samples was a 0603 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). In Comparative Examples 1 to 3, the number of layers in the lamination unit was 200. In Examples 1 and 2 and Comparative Example 4, the number of layers in the lamination unit was 300. In Examples 3 and 4 and Comparative Example 5, the number of layers in the lamination unit was 400. In Examples 5 and 6 and Comparative Example 6, the number of layers in the lamination unit was 500.

[0072] In all of Examples 1 to 6 and Comparative Examples 1 to 6, the thickness of each dielectric layer in the fired sample was 0.40 μm. In Comparative Example 1 and Examples 1, 3, and 5, the thickness of each internal electrode layer was 0.70 μm. In Comparative Example 2 and Examples 2, 4, and 6, the thickness of each internal electrode layer was 0.60 μm. In Comparative Examples 3 to 6, the thickness of each internal electrode layer was 0.50 μm.

[0073] The D50% particle size of the ceramic grains in the inner region 141 described in FIG. 8 was 149 nm in Comparative Example 1, 152 nm in Comparative Example 2, 161 nm in Comparative Example 3, 148 nm in Example 1, 157 nm in Example 2, 164 nm in Comparative Example 4, 152 nm in Example 3, 161 nm in Example 4, 171 nm in Comparative Example 5, 155 nm in Example 5, 163 nm in Example 6, and 174 nm in Comparative Example 6.

[0074] The D50% particle size of the ceramic grains in the outer region 142 described in FIG. 8 was 171 nm in Comparative Example 1, 183 nm in Comparative Example 2, 198 nm in Comparative Example 3, 182 nm in Example 1, 191 nm in Example 2, 209 nm in Comparative Example 4, 187 nm in Example 3, 193 nm in Example 4, 217 nm in Comparative Example 5, 191 nm in Example 5, 197 nm in Example 6, and 223 nm in Comparative Example 6.

[0075] The Si / Ti element ratio in the inner region 141 described in FIG. 8 was 0.007 in Comparative Example 1, 0.007 in Comparative Example 2, 0.007 in Comparative Example 3, 0.008 in Example 1, 0.007 in Example 2, 0.007 in Comparative Example 4, 0.007 in Example 3, 0.008 in Example 4, 0.007 in Comparative Example 5, 0.007 in Example 5, 0.007 in Example 6, and 0.007 in Comparative Example 6.

[0076] The Si / Ti element ratio in the outer region 142 described in FIG. 8 was 0.007 in Comparative Example 1, 0.007 in Comparative Example 2, 0.007 in Comparative Example 3, 0.007 in Example 1, 0.007 in Example 2, 0.008 in Comparative Example 4, 0.007 in Example 3, 0.007 in Example 4, 0.007 in Comparative Example 5, 0.008 in Example 5, 0.007 in Example 6, and 0.007 in Comparative Example 6.

[0077] The Si / Ti element ratio in the side margin 16 was 0.035 in Comparative Example 1, 0.036 in Comparative Example 2, 0.034 in Comparative Example 3, 0.036 in Example 1, 0.035 in Example 2, 0.035 in Comparative Example 4, 0.034 in Example 3, 0.035 in Example 4, 0.035 in Comparative Example 5, 0.034 in Example 5, 0.036 in Example 6, and 0.035 in Comparative Example 6.

[0078] The Si / Ti element ratio in the end margin 15 was 0.007 in Comparative Example 1, 0.007 in Comparative Example 2, 0.007 in Comparative Example 3, 0.008 in Example 1, 0.007 in Example 2, 0.007 in Comparative Example 4, 0.007 in Example 3, 0.008 in Example 4, 0.008 in Comparative Example 5, 0.007 in Example 5, 0.007 in Example 6, and 0.007 in Comparative Example 6.

[0079] The results are shown in Table 1. SM indicates the side margin, and EM indicates the end margin. [Table 1]

[0080] The capacitance of each sample in Examples 1 to 6 and Comparative Examples 1 to 6 was measured. An LCR meter 4284A was used for the measurements. Each sample was pretreated by heating at 150°C for 1 hour and then left for 24 hours. In Table 1, the capacitance @10mVrms (μF) is the capacitance when a 100kHz AC voltage of 0.01V is applied. In Table 1, the capacitance @10mVrms-1VBias is the capacitance when a bias voltage of DC 1V is applied and a 100kHz AC voltage of 0.01V is applied. The capacitance change rate @1VBias indicates the rate of decrease from the capacitance @10mVrms to the capacitance @10mVrms-1VBias.

[0081] As shown in Table 1, the capacitance @10 mVrms was not sufficiently high in Comparative Examples 1 to 3. This is thought to be due to the small number of layers in the lamination unit. Next, for Examples 1 and 2 and Comparative Example 4, which had 300 lamination layers, the capacitance change rate @1 VBias was improved in Examples 1 and 2 compared to Comparative Example 4. This is thought to be because the thickness of the internal electrode layers was 1.5 times or more the thickness of the dielectric layers in Examples 1 and 2. Next, for Examples 3 and 4 and Comparative Example 5, which had 400 lamination layers, the capacitance change rate @1 VBias was improved in Examples 3 and 4 compared to Comparative Example 5. This is thought to be because the thickness of the internal electrode layers was 1.5 times or more the thickness of the dielectric layers in Examples 3 and 4. Next, for Examples 5 and 6 and Comparative Example 6, which had 500 lamination layers, the capacitance change rate @1 VBias was improved in Examples 5 and 6 compared to Comparative Example 6. This is thought to be because the thickness of the internal electrode layers was 1.5 times or more the thickness of the dielectric layers in Examples 5 and 6.

[0082] Examples 7 to 13 In Examples 7 to 13, samples were prepared in the same manner as in Example 1. In all of Examples 7 to 14, the size of the obtained sample was 0603 shape (length 0.6 mm, width 0.3 mm, height 0.3 mm). The number of layers in the lamination unit was 400. The thickness of each dielectric layer in the fired sample was 0.40 μm. The thickness of each internal electrode layer in the fired sample was 0.60 μm.

[0083] The D50% particle size of the ceramic grains in the inner region 141 described in FIG. 8 was 161 nm in Example 7, 163 nm in Example 8, 162 nm in Example 9, 161 nm in Example 10, 161 nm in Example 11, 161 nm in Example 12, and 161 nm in Example 13.

[0084] The D50% particle size of the ceramic grains in the outer region 142 described in FIG. 8 was 193 nm in Example 7, 194 nm in Example 8, 198 nm in Example 9, 192 nm in Example 10, 194 nm in Example 11, 191 nm in Example 12, and 193 nm in Example 13.

[0085] The Si / Ti element ratio in the inner region 141 described in FIG. 8 was 0.008 in Example 7, 0.008 in Example 8, 0.007 in Example 9, 0.008 in Example 10, 0.008 in Example 11, 0.008 in Example 12, and 0.008 in Example 13.

[0086] The Si / Ti element ratio in the outer region 142 described in FIG. 8 was 0.007 in Example 7, 0.007 in Example 8, 0.007 in Example 9, 0.007 in Example 10, 0.007 in Example 11, 0.007 in Example 12, and 0.007 in Example 13.

[0087] The Si / Ti element ratio in the side margin was 0.035 in Example 7, 0.025 in Example 8, 0.015 in Example 9, 0.035 in Example 10, 0.035 in Example 11, 0.035 in Example 12, and 0.035 in Example 13.

[0088] The Si / Ti element ratio in the end margin was 0.008 in Example 7, 0.008 in Example 8, 0.007 in Example 9, 0.035 in Example 10, 0.026 in Example 11, 0.014 in Example 12, and 0.008 in Example 13.

[0089] The results are shown in Table 2. SM indicates the side margin, and EM indicates the end margin. [Table 2]

[0090] The capacitance of each sample in Examples 7 to 13 was measured in the same manner as in Example 1. As shown in Table 2, it was confirmed that a good capacitance change rate @1VBias could be obtained by increasing the Si / Ti element ratio in at least one of the side margin and end margin compared to the inner region and outer region.

[0091] (Examples 14 to 19 and Comparative Examples 7 to 9) Samples were prepared in the same manner as in Example 1. In all of Examples 14 to 19 and Comparative Examples 7 to 9, the size of the obtained samples was 1005 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). In Examples 14 and 15 and Comparative Example 7, the number of layers in the lamination unit was 300. In Examples 16 and 17 and Comparative Example 8, the number of layers in the lamination unit was 400. In Examples 18 and 19 and Comparative Example 9, the number of layers in the lamination unit was 500.

[0092] In all of Examples 14 to 19 and Comparative Examples 7 to 9, the thickness of each dielectric layer in the fired sample was 0.40 μm. In Examples 14, 16, and 18, the thickness of each internal electrode layer was 0.70 μm. In Examples 15, 17, and 19, the thickness of each internal electrode layer was 0.60 μm. In Comparative Examples 7 to 9, the thickness of each internal electrode layer was 0.50 μm.

[0093] The D50% particle size of the ceramic grains in the inner region 141 described in FIG. 8 was 146 nm in Example 14, 148 nm in Example 15, 161 nm in Comparative Example 7, 150 nm in Example 16, 155 nm in Example 17, 168 nm in Comparative Example 8, 145 nm in Example 18, 151 nm in Example 19, and 172 nm in Comparative Example 9.

[0094] The D50% particle size of the ceramic grains in the outer region 142 described in FIG. 8 was 157 nm in Example 14, 162 nm in Example 15, 185 nm in Comparative Example 7, 161 nm in Example 16, 175 nm in Example 17, 193 nm in Comparative Example 8, 156 nm in Example 18, 169 nm in Example 19, and 198 nm in Comparative Example 9.

[0095] The Si / Ti element ratio in the inner region 141 described in FIG. 8 was 0.007 in Example 14, 0.008 in Example 15, 0.007 in Comparative Example 7, 0.008 in Example 16, 0.007 in Example 17, 0.008 in Comparative Example 8, 0.007 in Example 18, 0.008 in Example 19, and 0.007 in Comparative Example 9.

[0096] The Si / Ti element ratio in the outer region 142 described in FIG. 8 was 0.007 in Example 14, 0.007 in Example 15, 0.008 in Comparative Example 7, 0.007 in Example 16, 0.007 in Example 17, 0.007 in Comparative Example 8, 0.007 in Example 18, 0.008 in Example 19, and 0.008 in Comparative Example 9.

[0097] The Si / Ti element ratio in the side margin 16 was 0.036 in Example 14, 0.034 in Example 15, 0.036 in Comparative Example 7, 0.036 in Example 16, 0.035 in Example 17, 0.036 in Comparative Example 8, 0.036 in Example 18, 0.036 in Example 19, and 0.034 in Comparative Example 9.

[0098] The Si / Ti element ratio in the end margin 15 was 0.008 in Example 14, 0.007 in Example 15, 0.007 in Comparative Example 7, 0.007 in Example 16, 0.007 in Example 17, 0.008 in Comparative Example 8, 0.007 in Example 18, 0.007 in Example 19, and 0.007 in Comparative Example 9.

[0099] The results are shown in Table 3. SM indicates the side margin, and EM indicates the end margin. [Table 3]

[0100] For Examples 14 and 15 and Comparative Example 7, which had 300 stacked layers, the capacitance change rate @1VBias was improved in Examples 14 and 15 compared to Comparative Example 7. This is thought to be because the thickness of the internal electrode layers in Examples 14 and 15 was 1.5 times or more the thickness of the dielectric layers. Next, for Examples 16 and 17 and Comparative Example 8, which had 400 stacked layers, the capacitance change rate @1VBias was improved in Examples 16 and 17 compared to Comparative Example 8. This is thought to be because the thickness of the internal electrode layers in Examples 16 and 17 was 1.5 times or more the thickness of the dielectric layers. Next, for Examples 18 and 19 and Comparative Example 9, which had 500 stacked layers, the capacitance change rate @1VBias was improved in Examples 18 and 19 compared to Comparative Example 9. This is thought to be because the thickness of the internal electrode layers in Examples 18 and 19 was 1.5 times or more the thickness of the dielectric layers.

[0101] Examples 20 to 29 In Examples 20 to 29, samples were prepared in the same manner as in Example 1. In all of Examples 20 to 29, the size of the obtained sample was 1005 shape (length 1.0 mm, width 0.5 mm, height 0.5 mm). The number of layers in the lamination unit was 600. The thickness of each dielectric layer in the fired sample was 0.40 μm. The thickness of each internal electrode layer in the fired sample was 0.60 μm.

[0102] The D50% particle size of the ceramic grains in the inner region 141 described in FIG. 8 was 151 nm in Example 20, 152 nm in Example 21, 156 nm in Example 22, 146 nm in Example 23, 148 nm in Example 24, 149 nm in Example 25, 151 nm in Example 26, 149 nm in Example 27, 146 nm in Example 28, and 161 nm in Example 29.

[0103] The D50% particle size of the ceramic grains in the outer region 142 described in FIG. 8 was 169 nm in Example 20, 170 nm in Example 21, 176 nm in Example 22, 155 nm in Example 23, 159 nm in Example 24, 158 nm in Example 25, 169 nm in Example 26, 161 nm in Example 27, 151 nm in Example 28, and 177 nm in Example 29.

[0104] The Si / Ti element ratio in the inner region 141 described in Figure 8 was 0.008 in Example 20, 0.008 in Example 21, 0.007 in Example 22, 0.008 in Example 23, 0.008 in Example 24, 0.008 in Example 25, 0.008 in Example 26, 0.015 in Example 27, 0.025 in Example 28, and 0.003 in Example 29.

[0105] The Si / Ti element ratio in the outer region 142 described in FIG. 8 was 0.008 in Example 20, 0.007 in Example 21, 0.007 in Example 22, 0.007 in Example 23, 0.007 in Example 24, 0.007 in Example 25, 0.007 in Example 26, 0.015 in Example 27, 0.025 in Example 28, and 0.003 in Example 29.

[0106] The Si / Ti element ratio in the side margin was 0.035 in Example 20, 0.025 in Example 21, 0.015 in Example 22, 0.035 in Example 23, 0.035 in Example 24, 0.035 in Example 25, 0.035 in Example 26, 0.035 in Example 27, 0.035 in Example 28, and 0.0035 in Example 29.

[0107] The Si / Ti element ratio in the end margin was 0.007 in Example 20, 0.008 in Example 21, 0.007 in Example 22, 0.035 in Example 23, 0.026 in Example 24, 0.014 in Example 25, 0.007 in Example 26, 0.007 in Example 27, 0.007 in Example 28, and 0.007 in Example 29.

[0108] The results are shown in Table 4. SM indicates the side margin, and EM indicates the end margin. [Table 4]

[0109] The capacitance of each sample in Examples 20 to 29 was measured in the same manner as in Example 1. As shown in Table 4, it was confirmed that a good capacitance change rate @1VBias could be obtained by increasing the Si / Ti element ratio in at least one of the side margin and end margin compared to the inner region and outer region.

[0110] Although the embodiments of the present invention have been described in detail above, the present invention is not limited to such specific embodiments, and various modifications and variations are possible within the scope of the gist of the present invention as defined in the claims. [Explanation of symbols]

[0111] 10 stacked chips 11 Dielectric layer 12 Internal electrode layer 13 Cover Layer 14 Capacity part 15 End Margin 16 Side Margin 20a,20b external electrode 22 plating layer 23 First plating layer 24 Second plating layer 25 Third plating layer 51 Dielectric green sheet 52 Internal electrode pattern 53 Dielectric Pattern 54 Cover Sheet 55 Side margin 100 Multilayer ceramic capacitors

Claims

1. a laminated chip including a laminated portion in which a plurality of dielectric layers and a plurality of internal electrode layers are laminated; the plurality of internal electrode layers are alternately drawn out to two opposing end surfaces of the laminated chip, the laminated chip has a side margin outside a capacitance section, which is a region where the plurality of dielectric layers and the plurality of internal electrode layers face each other, in a third direction orthogonal to a first direction in which the plurality of internal electrode layers face each other and a second direction in which the two end faces face each other; The plurality of internal electrode layers are provided in a number of 300 layers or more, A ceramic electronic component, wherein the thickness of the plurality of internal electrode layers is 1.5 times or more the thickness of the plurality of dielectric layers.

2. 2. The ceramic electronic component according to claim 1, wherein, in the plurality of dielectric layers, an outer 10% region of each of the capacitance sections in the third direction is defined as an outer region, and the remaining 80% region is defined as an inner region, and the D50% particle size of the ceramic grain size distribution in the outer region is larger than the D50% particle size of the ceramic grain size distribution in the inner region.

3. 2. The ceramic electronic component according to claim 1, wherein, in the plurality of dielectric layers, when an outer 10% region of each of the capacitance sections in the third direction is defined as an outer region and the remaining 80% region is defined as an inner region, a D50% particle size of a ceramic grain size distribution in the inner region is 50 nm or more and 200 nm or less.

4. 2. The ceramic electronic component according to claim 1, wherein, in the plurality of dielectric layers, when an outer 10% region of each of the capacitance sections in the third direction is defined as an outer region and the remaining 80% region is defined as an inner region, a D90% particle size of a ceramic grain size distribution in the inner region is 300 nm or less.

5. 2. The ceramic electronic component according to claim 1, wherein the Si / Ti element ratio in the side margin is greater than the Si / Ti element ratio in the plurality of dielectric layers in the capacitance section.

6. 6. The ceramic electronic component according to claim 5, wherein the Si / Ti element number ratio in the side margin is 0.01 or more.

7. an end margin is a region that is located outside the capacitive portion of the laminated chip in the second direction, and where internal electrode layers drawn to one of the two end faces face each other without being sandwiched between internal electrode layers drawn to the other end face; 2. The ceramic electronic component according to claim 1, wherein the Si / Ti element ratio in the end margins is greater than the Si / Ti element ratio in the plurality of dielectric layers in the capacitance section.

8. 8. The ceramic electronic component according to claim 7, wherein the Si / Ti element number ratio in the end margin is 0.01 or more.

9. The ceramic electronic component according to claim 1 , wherein the ceramic electronic component has a size equal to or larger than an 0603 shape.

10. The plurality of internal electrode layers are provided in a number of 500 layers or more, The ceramic electronic component according to claim 1 , wherein the ceramic electronic component has a size equal to or larger than a 1005 shape.

11. 6. The ceramic electronic component according to claim 5, wherein the Si / Ti element number ratio in the side margin is 0.03 or more.

12. 8. The ceramic electronic component according to claim 7, wherein the Si / Ti element number ratio in the end margin is 0.03 or more.

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