Switching control device

Abstract

To provide a technique capable of suppressing the degradation of the switching slew rate due to variations in switching element characteristics.SOLUTION: A monitor unit 54 monitors output signals from a switching unit 2 that has one or more switching elements 21, 22. A reference generation unit 53 generates a reference signal based on waveform data that represents a design value of the slew rate to be achieved by the output signal. A slew rate adjustment unit 32 adjusts the rate at which the gate voltage of switching elements 21 and 22 changes according to an instruction signal S. A comparison unit 55 generates an instruction signal S according to a comparison signal that represents the comparison result between the output signal detected by the monitor unit 54 and the reference signal generated by the reference generation unit 53 so that the waveform of the output signal matches the waveform of the reference signal.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present disclosure relates to techniques for improving the accuracy of switching slew rates. [Background technology]

[0002] In switching power supply circuits, the switching slew rate is related to the generation of emission noise and heat. The switching slew rate is an index that shows how well the output waveform follows changes in the input waveform. Switching power supply circuits are designed, verified, and adopted in actual circuits so that the switching slew rate satisfies the requirements for output voltage accuracy, emission noise, and heat.

[0003] Patent Document 1 describes a technology that, in order to reduce the turn-off loss of a switching element, changes the control speed of the gate voltage of the switching element when the peak of the output voltage of the switching element is detected, thereby changing the switching slew rate. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2020-565607 Summary of the Invention [Problem to be solved by the invention]

[0005] As switching power supply circuits continue to handle larger currents, the need to suppress emission noise and heat generation is becoming more apparent. Furthermore, MOS transistors used as switching elements have large variations in parasitic capacitance, which causes the switching slew rate to deviate from the designed value. To accommodate this variation, conventional technology requires designs with a margin for emission noise and heat, which necessitates the addition of components to counter emission noise and an increase in ECU size.

[0006] One aspect of the present disclosure provides a technique for suppressing degradation of switching slew rate due to variations in characteristics of switching elements. [Means for solving the problem]

[0007] One aspect of the present disclosure is a switching control device comprising a monitor unit (54), a reference generation unit (531), a slew rate adjustment unit (32), and a comparison unit (55). The monitor unit is configured to monitor an output signal of a switching unit (2) having one or more switching elements. The reference generation unit is configured to generate a reference signal based on waveform data indicating a design value of the slew rate realized by the output signal. The slew rate adjustment unit is configured to adjust the rate at which the gate voltage of the switching element changes in accordance with an instruction signal. The comparison unit generates an instruction signal in accordance with a comparison signal indicating a comparison result between the output signal detected by the monitor unit and the reference signal generated by the reference generation unit so that the waveform of the output signal approaches the waveform of the reference signal.

[0008] With this configuration, even if there is variation in the characteristics of the switching elements, the waveform of the output signal can be made closer to the waveform of the reference signal that indicates the design value of the slew rate, thereby suppressing deterioration of the slew rate. [Brief explanation of the drawings]

[0009] [Figure 1]1 is a circuit diagram including a block diagram showing the configuration of a switching power supply circuit. [Figure 2] 10 is a flowchart showing processing contents in a reference generation unit. [Figure 3] 10 is a flowchart of a waveform correction process. [Figure 4] 3A and 3B are explanatory diagrams showing signal waveforms of various parts of the switching power supply circuit; DETAILED DESCRIPTION OF THE INVENTION

[0010] Hereinafter, embodiments of the present disclosure will be described with reference to the drawings. [1. Configuration] 1 is used for, for example, driving a motor or supplying power, and includes a switching unit 2, a switching control unit 3, and a PWM signal generation unit 4.

[0011] The switching unit 2 includes a first switching element 21 and a second switching element 22. Hereinafter, unless there is a need to distinguish between them, they will be referred to as switching elements 21 and 22. Both switching elements 21 and 22 are N-channel metal-oxide semiconductor field-effect transistors (hereinafter referred to as MOSFETs). That is, the switching elements 21 and 22 are turned on when their gates are at a high level and turned off when their gates are at a low level. The switching elements 21 and 22 are not limited to MOSFETs, and other semiconductor elements may be used. The switching elements 21 and 22 include freewheeling diodes 23 and 24 connected in antiparallel, respectively.

[0012] The drain of the first switching element 21 is connected to the positive power supply line LP, and the source of the second switching element 22 is connected to the negative power supply line LM. The source of the first switching element 21 and the drain of the second switching element 22 are connected together, and this connection point is referred to as an output point P. The output point P is connected to an output terminal TO via a current detection resistor 25. An inductive load LD, for example, may be connected to the output terminal TO.

[0013] The negative power supply line LM is connected to a reference potential (for example, ground potential). A DC voltage of, for example, 600 to 800 V is applied between the positive power supply line LP and the negative power supply line LM. 4, the PWM signal generating unit 4 generates PWM signals D1 and D2 synchronized with the clock signal CLK based on the clock signal CLK and the PWM control signal generated by the device incorporating the switching power supply circuit 1. PWM stands for Pulse Width Modulation. "Synchronization" here means that the clock signal CLK and the PWM signals D1 and D2 coincide in timing at the boundaries of one cycle.

[0014] The PWM signals D1 and D2 are set to have a duty ratio corresponding to the magnitude of the power supplied to the load connected to the output terminal TO, for example. The PWM signal D1 is used to drive the first switching element 21, and the PWM signal D2 is used to drive the second switching element 22. The PWM signal D2 is a signal obtained by inverting the signal level of the PWM signal D1. In other words, the PWM signals D1 and D2 are set to complementarily drive the switching elements 21 and 22 on and off.

[0015] The switching control unit 3 controls the gate voltages of the switching elements 21 and 22 based on the PWM signals D1 and D2 input from the PWM signal generating unit 4, the monitor signal Vm based on the output signal VP indicating the voltage at the output point P, and the voltage VL across the current detection resistor 25, etc.

[0016] The switching control unit 3 includes a gate drive unit 31, a slew rate adjustment unit 32, and a slew rate control unit 33 as components for controlling the first switching element 21. The switching control unit 3 includes a gate drive unit 34, a slew rate adjustment unit 35, and a slew rate control unit 36 ​​as components for controlling the second switching element 22.

[0017] The gate driver 31 is configured by a complementary metal oxide semiconductor (hereinafter referred to as CMOS). The gate driver 31 supplies a signal obtained by inverting the PWM signal D1 to the gate of the first switching element 21 via the slew rate adjuster 32. In other words, the first switching element 21 is turned off when the PWM signal D1 is at a high level, and turned on when the PWM signal D1 is at a low level.

[0018] The slew rate adjustment unit 32 is provided in a signal path from the output of the gate drive unit 31 to the gate of the first switching element 21. The slew rate adjustment unit 32 is a variable resistor whose resistance value changes in accordance with an instruction signal S from the slew rate control unit 33. When the signal level of the PWM signal D1 changes, the rate at which the signal level of the output signal VP changes depends on the rate at which the gate voltages of the switching elements 21 and 22 change. The rate at which the gate voltage of the first switching element 21 changes is determined by a time constant determined by the parasitic capacitance of the first switching element 21 and the resistance value of the slew rate adjustment unit 32. In other words, as the resistance value of the slew rate adjustment unit 32 increases, the rate at which the signal level of the first switching element 21 changes (i.e., the slew rate) slows down, and as the resistance value decreases, the slew rate increases.

[0019] The slew rate control unit 33 includes a current detection unit 51 , a temperature detection unit 52 , a reference generation unit 53 , a monitor unit 54 , and a comparison unit 55 . As shown in FIG. 4, the current detection unit 51 smoothes the voltage VL across the current detection resistor 25, and detects the magnitude of the load current I flowing through the switching unit 2 based on the smoothed voltage VL across the resistor 25.

[0020] The temperature detection unit 52 detects the temperature using a semiconductor integrated circuit in which the slew rate control unit 33 is built, or a temperature sensor attached to the heat sink of the first switching element 21 or the like. The reference generation unit 53 includes a signal storage unit 531 configured using a nonvolatile storage device. The signal storage unit 531 stores waveform data used to generate the reference signal Vref. The waveform of the reference signal Vref (hereinafter referred to as the reference waveform) indicates an ideal switching slew rate in the first switching element 21. The reference waveform is designed so that the accuracy of the output voltage, emission noise, and heat generation in the switching unit 2 meet required specifications, assuming that the switching elements 21 and 22 have standard characteristics (i.e., there is no variation in parasitic capacitance).

[0021] The reference generating unit 53 reads the waveform data stored in the signal storage unit 531 into a working memory, and generates an analog voltage signal (i.e., a reference signal) Vref having a reference waveform using the waveform data read into the working memory. The reference generating unit 53 generates the reference signal Vref and supplies it to the comparing unit 55 so that the signal level of the reference signal Vref also starts to change at the edge timing at which the signal level of the PWM signal D1 changes.

[0022] Furthermore, the reference generating unit 53 also executes a process of correcting waveform data used to generate the reference signal Vref in accordance with the detection results of the current detecting unit 51 and the temperature detecting unit 52. The waveform data may be a value representing the slope of the reference waveform when the signal level changes (i.e., the rate of change of the signal level over time), or may be the value of a circuit element (e.g., a resistor or a capacitor) used to generate the reference signal that realizes that rate of change over time.

[0023] The monitor unit 54 includes a low-pass filter. The monitor unit 54 receives the output signal VP from the output point P, passes the signal through the low-pass filter, and supplies the signal from which high-frequency noise has been removed to the comparator 55 as a monitor signal Vm.

[0024] The comparison unit 55 generates an instruction signal S for changing the resistance value of the slew rate adjustment unit 32 based on a comparison signal ΔV which is the comparison result between the reference signal Vref and the monitor signal Vm. The comparison signal ΔV in the present embodiment is a signal representing the difference between the reference signal Vref and the monitor signal Vm. As shown in FIG. 4, when Vref = Vm, the comparison signal ΔV becomes a reference value (for example, 2.5V); when Vref < Vm, the comparison signal ΔV becomes a positive value with respect to the reference value; and when Vref > Vm, the comparison signal ΔV becomes a negative value with respect to the reference value.

[0025] Hereinafter, when the switching slew rate indicated by the monitor signal Vm (that is, the output signal VP) is lower than the ideal switching slew rate indicated by the reference signal Vref, it is referred to as a low slew rate. Also, when the switching slew rate indicated by the monitor signal Vm is higher than the ideal switching slew rate indicated by the reference signal Vref, it is referred to as a high slew rate.

[0026] At the falling edge of the PWM signal D1, when the monitor signal Vm has a low slew rate, the comparison signal ΔV becomes a positive value with respect to the reference value; when the monitor signal Vm has a high slew rate, the comparison signal ΔV becomes a negative value with respect to the reference value.

[0027] At the rising edge of the PWM signal D1, contrary to the falling edge, when the monitor signal Vm has a low slew rate, the comparison signal ΔV becomes a negative value with respect to the reference value; when the monitor signal Vm has a high slew rate, the comparison signal ΔV becomes a positive value with respect to the reference value.

[0028] At the falling edge of the PWM signal D1, the comparison unit 55 outputs a signal proportional to the comparison signal ΔV as the instruction signal S, and at the rising edge of the PWM signal D1, it outputs a signal proportional to the comparison signal ΔV inverted with respect to the reference value as the instruction signal S.

[0029] The slew rate adjustment unit 32 adjusts the resistance value of the variable resistor so that the larger the value of the instruction signal S, i.e., the greater the degree to which the monitor signal Vm has a low slew rate, the smaller the resistance value of the variable resistor becomes. Also, the slew rate adjustment unit 32 adjusts the resistance value of the variable resistor so that the smaller the value of the instruction signal S, i.e., the greater the degree to which the monitor signal Vm has a high slew rate, the larger the resistance value of the variable resistor becomes.

[0030] The switching control unit 3 includes a gate driving unit 34, a slew rate adjustment unit 35, and a slew rate control unit 36 ​​as components for controlling the second switching element 22. The gate driving unit 34, the slew rate adjustment unit 35, and the slew rate control unit 36 ​​have the same configurations and operate in the same manner as the gate driving unit 31, the slew rate adjustment unit 32, and the slew rate control unit 33, respectively, and therefore detailed description thereof will be omitted.

[0031] The second switching element 22 is driven by a PWM signal D2 obtained by inverting the PWM signal D1. Therefore, the switching elements 21 and 22 operate in a complementary manner such that when the first switching element 21 is on, the second switching element 22 is off, and when the first switching element 21 is off, the second switching element 22 is on.

[0032] [2. Processing] Next, the processing executed by reference generating unit 53 of slew rate control unit 33 will be described with reference to the flowchart of Fig. 2. Note that while the reference generating unit 53 of slew rate control unit 33 related to the drive of first switching element 21 will be described here, the reference generating unit 53 of slew rate control unit 36 ​​related to the drive of second switching element 22 operates similarly. This processing starts when power is applied to switching power supply circuit 1.

[0033] The processing of the reference generating unit 53 may be realized by hardware, or a part or all of it may be realized by software. As shown in FIG. 2, in S110, the reference generating unit 53 reads out the waveform data stored in the signal storage unit 531 into a working memory.

[0034] In S120, the reference generation unit 53 monitors the PWM signal D1 and determines whether it is an edge timing at which the signal level of the PWM signal D1 changes. If the reference generation unit 53 determines that it is an edge timing, it proceeds to S130. If it determines that it is not an edge timing, it waits by repeating the same step. Hereinafter, the period from one edge timing to the next edge timing is referred to as a processing cycle. Therefore, during one cycle of the clock signal CLK, there are two processing cycles with different periods depending on the duty ratios of the PWM signals D1 and D2.

[0035] In S130, the reference generating unit 53 starts outputting the reference signal Vref generated based on the waveform data in the working memory, that is, generates the reference signal Vref having the gradient indicated by the waveform data.

[0036] S140 is processing by the comparison unit 55 to which the reference signal Vref and the monitor signal Vm are input. The comparison unit 55 generates a comparison signal ΔV indicating the difference between the reference signal Vref and the monitor signal Vm. If the edge timing is a falling edge, the comparison unit 55 outputs an instruction signal S proportional to the comparison signal ΔV, and if the edge timing is a rising edge, the comparison unit 55 outputs an instruction signal S proportional to the comparison signal ΔV inverted by a reference value. The resistance value of the slew rate adjustment unit 32 changes in accordance with this instruction signal S. The change in the resistance value changes the slew rate of the first switching element 21, and the waveform of the monitor signal Vm changes to approach the waveform of the reference signal Vref.

[0037] In S150, the reference generating unit 53 determines whether it is correction timing or not, and if it is correction timing, the process proceeds to S150, and if it is not correction timing, the reference generating unit 53 waits by repeating the same step.

[0038] The correction timing may be the timing when the first switching element 21 is reliably turned off and the second switching element 22 is reliably turned on after the falling edge of the PWM signal D1. Alternatively, the correction timing may be the timing when the first switching element 21 is reliably turned on and the second switching element 22 is reliably turned off after the rising edge of the PWM signal D1. In other words, the correction timing is the timing when the current flowing through the current detection resistor 25 stabilizes to a certain extent. Specifically, for example, as shown in FIG. 4, the correction timing may be the timing when a predetermined time Tw has elapsed after the reference signal Vref generated based on waveform data reaches a low level or a high level.

[0039] In S160, the reference generating unit 53 executes waveform correction processing, which will be described in detail later. In S170, the reference generating unit 53 stores in the signal storage unit 531 the waveform data corrected in the waveform correction process in S150.

[0040] In S180, the reference generating unit 53 determines whether the switching power supply circuit 1 or the device incorporating the switching power supply circuit 1 is in operation, and if it is in operation, returns the processing to S120, and if it is not in operation, ends the processing.

[0041] Next, the waveform correction process executed in S160 will be described with reference to the flowchart of FIG. As shown in FIG. 3, in S210, the reference generating unit 53 acquires the temperature T(t) in the current processing cycle from the temperature detecting unit 52.

[0042] In S220, the reference generating unit 53 determines whether the temperature difference ΔT between the temperature T(t) acquired in S210 and the temperature T(t-1) acquired in the previous processing cycle is greater than the temperature threshold value Tth. If the reference generating unit 53 determines that ΔT > Tth, it proceeds to S240, and if it determines that ΔT ≦ Tth, it proceeds to S230.

[0043] In S230, the reference generation unit 53 determines whether ΔT < Tth. If it is determined that ΔT < Tth, the process proceeds to S250. If it is determined that ΔT ≧ Tth, the process proceeds to S260.

[0044] In S240, in order to indicate that the slew rate of the reference signal Vref needs to be increased, the reference generation unit 53 sets the evaluation value S to 1 and advances the process to S270. In S250, in order to indicate that the slew rate of the reference signal Vref needs to be decreased, the reference generation unit 53 sets the evaluation value S to -1 and advances the process to S270.

[0045] In S260, in order to indicate that the slew rate of the reference signal Vref should be maintained as it is, the reference generation unit 53 sets the evaluation value S to 0 and advances the process to S270. That is, when the current temperature value T(t) is higher than the previous value T(t - 1) and the temperature is increasing, it indicates that the switching losses in the switching elements 21 and 22 tend to increase. Therefore, in this case, in order to reduce the switching losses, the slew rate of the reference signal Vref may be increased.

[0046] When the current temperature value T(t) is lower than the previous value T(t - 1) and the temperature is decreasing, it indicates that the switching losses in the switching elements 21 and 22 tend to decrease and there is a thermal margin. Therefore, in this case, in order to enable the use of the thermal margin for improving the performance of the emission noise, the slew rate of the reference signal Vref may be decreased.

[0047] When the current temperature value T(t) is equal to the previous value T(t - 1), it indicates that the switching losses in the switching elements 21 and 22 are appropriate. Therefore, in this case, the rate of changing the signal level may be maintained as it is.

[0048] In S270, the reference generation unit 53 updates the temperature T(t - 1) based on the temperature T(t). In S280, the reference generation unit 53 acquires the load current I(t) in the current processing cycle from the current detection unit 51.

[0049] In S290, the reference generation unit 53 determines whether the difference ΔI between the load current I(t) acquired in S280 and the load current I(t - 1) acquired in the previous processing cycle is greater than the current threshold Ith. When the reference generation unit 53 determines that ΔI > Ith, the process proceeds to S310; when it determines that ΔT ≦ Tth, the process proceeds to S300.

[0050] In S300, the reference generation unit 53 determines whether ΔI < Ith. When it determines that ΔI < Ith, the process proceeds to S320; when it determines that ΔI ≧ Ith, the process proceeds to S330.

[0051] In S310, in order to indicate that the slew rate of the reference signal Vref needs to be increased, the reference generation unit 53 adds 1 to the evaluation value S and advances the process to S340. In S320, in order to indicate that the slew rate of the reference signal Vref needs to be decreased, the reference generation unit 53 subtracts 1 from the evaluation value S and advances the process to S340.

[0052] In S330, in order to indicate that the slew rate of the reference signal Vref should be maintained as it is, the reference generation unit 53 maintains the evaluation value S as it is and advances the process to S340. That is, when the current value I(t) of the load current is greater than the previous value I(t - 1) and the load current tends to increase, it indicates that the emission noise also tends to increase. Therefore, in this case, in order to reduce the emission noise, the slew rate of the reference signal Vref may be increased.

[0053] If the current load current I(t) is smaller than the previous load current I(t-1) and the load current is tending to decrease, the emission noise also tends to decrease, indicating that there is a margin in the noise tolerance. Therefore, in this case, the slew rate of the reference signal Vref may be slowed down so that the margin in the noise tolerance can be used to reduce switching loss.

[0054] If the current load current I(t) is equal to the previous load current I(t-1), it indicates that the emission noise generation situation is appropriate. Therefore, in this case, the slew rate of the reference signal Vref may be maintained as it is.

[0055] In S340, the reference generating unit 53 updates the load current I(t-1) based on the load current I(t). In S350, the criterion generating unit 53 determines whether the evaluation value S is greater than 0, and if S>0, the process proceeds to S370, and if S>0 is not satisfied, the process proceeds to S360.

[0056] In S360, the criterion generating unit 53 determines whether the evaluation value S is smaller than 0. If S<0, the process proceeds to S380, and if S<0, the process proceeds to S390. In S370, the reference generating unit 53 corrects the waveform data so that the slew rate of the reference signal Vref becomes one step faster, and then ends the process.

[0057] In S380, the reference generating unit 53 corrects the waveform data so that the slew rate of the reference signal Vref becomes slower by one step, and then ends the process. In S390, the reference generating unit 53 ends the process without correcting the waveform data so that the slew rate of the reference signal Vref remains the same.

[0058] The waveform data corrected in this way is used to generate the reference signal Vref in the next processing cycle.

[0059] [3. Terminology] The switching control unit 3 of this embodiment corresponds to the switching control device in this disclosure. The PWM signals D1 and D2 of this embodiment correspond to the drive signals for driving the gates in this disclosure.

[0060] [4. Effects] According to the embodiment described above in detail, the following effects are achieved. (4a) In the switching power supply circuit 1, the rate at which the gate voltages of the switching elements 21 and 22 change is adjusted based on the comparison signal ΔV that indicates the difference between the reference signal Vref and the monitor signal Vm, thereby controlling the waveform of the output signal VP to approach the waveform of the reference signal Vref. Therefore, regardless of variations in the characteristics of the switching elements 21 and 22, the slew rate of the output signal VP can be made to approach the ideal slew rate indicated by the reference signal Vref.

[0061] (4b) In the switching power supply circuit 1, the waveform data used to generate the reference signal Vref is corrected for each processing cycle so that the switching loss and the amount of emission noise generated are appropriate according to the design. Therefore, the slew rate of the output signal VP can be adjusted using an appropriate reference signal Vref according to the operating status of the switching power supply circuit 1.

[0062] (4c) In the switching power supply circuit 1, the corrected waveform data is stored in the signal storage unit 531, which is configured as a nonvolatile storage device. Therefore, when the switching power supply circuit 1 is temporarily stopped and then restored, processing can be resumed using the waveform data stored immediately before the stoppage.

[0063] (4d) In the switching power supply circuit 1, the timing at which the signal level of the reference signal Vref changes is synchronized with the edge timing of the PWM signals D1 and D2. This allows the reference signal Vref to be synchronized with the waveform of the output signal VP, thereby preventing deterioration in control accuracy due to a shift in the timing at which the signal level of the waveform starts to change.

[0064] 5. Other Embodiments Although the embodiments of the present disclosure have been described above, the present disclosure is not limited to the above-described embodiments and can be implemented in various modified forms.

[0065] (5a) In the above embodiment, waveform data corrected in a certain processing cycle is used in the next processing cycle without distinguishing between falling edges and rising edges. However, the correction result in the even-numbered (2N-1)th processing cycle may be used in the (2M+1)th processing cycle, and the correction result in the 2Nth processing cycle may be used in the (2N+2)th processing cycle, thereby distinguishing between falling edges and rising edges and correcting the waveform data.

[0066] (5b) In the above embodiment, when the switching power supply circuit 1 is temporarily stopped and then restarted, processing is resumed using the waveform data saved immediately before the stoppage. However, overwriting of waveform data in the signal storage unit 531 may be prohibited, and processing may be performed using the initial values ​​of the waveform data saved in the signal storage unit 531 (i.e., design values ​​under ideal conditions) every time the switching power supply circuit 1 is started.

[0067] (5c) In the above embodiment, some or all of the slew rate control units 33 and 36 may be configured to process digital signals. In this case, for example, the monitor unit 54 may sample the output signal VP or the monitor signal Vm. Furthermore, the current detection unit 51 may sample the voltage VL across the current detection resistor 25 or the load current I output by the current detection unit 51. Furthermore, the temperature T detected by the temperature detection unit 52 may be sampled.

[0068] (5d) Multiple functions possessed by one component in the above embodiments may be realized by multiple components, or one function possessed by one component may be realized by multiple components. Also, multiple functions possessed by multiple components may be realized by one component, or one function realized by multiple components may be realized by one component. Also, part of the configuration of the above embodiments may be omitted. Also, at least part of the configuration of the above embodiments may be added to or substituted for the configuration of another of the above embodiments.

[0069] (5e) In addition to the switching control unit 3 as the switching control device described above, the present disclosure can also be realized in various forms, such as a system including the switching control device as a component, a program for causing a computer to function as the switching control unit, a non-transient physical recording medium such as a semiconductor memory on which this program is recorded, and a method for controlling the switching through rate.

[0070] [6. Technical Ideas Disclosed in the Present Specification] [Item 1] a monitor unit (54) configured to monitor an output signal of a switching unit (2) having one or more switching elements; a reference generating unit (531) configured to generate a reference signal based on waveform data indicating a design value of a slew rate realized by the output signal; a slew rate adjusting unit (32) configured to adjust the rate at which the gate voltage of the switching element changes in accordance with an instruction signal; a comparison unit (55) that generates the instruction signal in accordance with a comparison signal representing a comparison result between the output signal detected by the monitor unit and the reference signal generated by the reference generation unit so that the waveform of the output signal approaches the waveform of the reference signal; A switching control device comprising:

[0071] [Item 2] The switching control device according to item 1, the switching unit includes two switching elements that are complementarily driven on and off, The slew rate adjustment unit is configured to adjust the rate at which the gate voltage changes for each of the switching elements. Switching control device.

[0072] [Item 3] The switching control device according to item 1 or 2, the comparison unit uses a difference between the output signal and the reference signal as the comparison signal. Switching control device.

[0073] [Item 4] The switching control device according to any one of items 1 to 3, the reference generating unit is configured to correct the waveform data in accordance with at least one of a temperature of the switching unit and a magnitude of a load current flowing through the switching unit. Switching control device.

[0074] [Item 5] Item 4. The switching control device according to item 4, the reference generating unit is configured to correct the waveform data so that the slew rate becomes faster when the temperature of the switching unit tends to rise, and the slew rate becomes slower when the temperature of the switching unit tends to fall. Switching control device.

[0075] [Item 6] The switching control device according to item 4 or 5, the reference generating unit is configured to correct the waveform data so that the slew rate becomes faster when the load current tends to increase, and the slew rate becomes slower when the load current tends to decrease. Switching control device.

[0076] [Item 7] The switching control device according to any one of items 4 to 6, the reference generating unit includes a non-volatile storage device that stores the corrected waveform data. Switching control device.

[0077] [Item 8] The switching control device according to any one of items 1 to 7, the reference generating unit is configured to generate the reference signal in accordance with an edge timing at which a signal level of a drive signal that drives a gate of the switching element changes. Switching control device.

[0078] [Item 9] The switching control device according to any one of items 1 to 8, The monitor unit includes a low pass filter configured to remove high frequency noise from the output signal. Switching control device.

[0079] [Item 10] The switching control device according to any one of items 1 to 9, The slew rate adjustment unit includes a variable resistor that is provided on a line to which the gate voltage is applied and whose resistance value changes in accordance with the instruction signal. Switching control device.

[0080] [Item 11] The switching control device according to any one of items 1 to 10, The switching element is a MOSFET. Switching control device. [Explanation of symbols]

[0081] 1...switching power supply circuit, 2...switching unit, 3...switching control unit, 4...PWM signal generation unit, 21...first switching element, 22...second switching element, 23, 24...freewheeling diode, 25...current detection resistor, 31, 34...gate drive unit, 32, 35...slew rate adjustment unit, 33, 36...slew rate control unit, 51...current detection unit, 52...temperature detection unit, 53...reference generation unit, 54...monitor unit, 55...comparison unit, 531...signal memory unit.

Claims

1. a monitor unit (54) configured to monitor an output signal of a switching unit (2) having one or more switching elements; a reference generating unit (531) configured to generate a reference signal based on waveform data indicating a design value of a slew rate realized by the output signal; a slew rate adjusting unit (32) configured to adjust the rate at which the gate voltage of the switching element changes in accordance with an instruction signal; a comparison unit (55) that generates the instruction signal in accordance with a comparison signal representing a comparison result between the output signal detected by the monitor unit and the reference signal generated by the reference generation unit so that the waveform of the output signal approaches the waveform of the reference signal; A switching control device comprising:

2. 2. The switching control device according to claim 1, the switching unit includes two switching elements that are complementarily driven on and off, The slew rate adjustment unit is configured to adjust the rate at which the gate voltage changes for each of the switching elements. Switching control device.

3. 2. The switching control device according to claim 1, the comparison unit uses a difference between the output signal and the reference signal as the comparison signal. Switching control device.

4. 2. The switching control device according to claim 1, the reference generating unit is configured to correct the waveform data in accordance with at least one of a temperature of the switching unit and a magnitude of a load current flowing through the switching unit. Switching control device.

5. 5. The switching control device according to claim 4, the reference generating unit is configured to correct the waveform data so that the slew rate becomes faster when the temperature of the switching unit tends to rise, and the slew rate becomes slower when the temperature of the switching unit tends to fall. Switching control device.

6. 5. The switching control device according to claim 4, the reference generating unit is configured to correct the waveform data so that the slew rate becomes faster when the load current tends to increase, and the slew rate becomes slower when the load current tends to decrease. Switching control device.

7. 5. The switching control device according to claim 4, the reference generating unit includes a non-volatile storage device that stores the corrected waveform data. Switching control device.

8. 2. The switching control device according to claim 1, the reference generating unit is configured to generate the reference signal in accordance with an edge timing at which a signal level of a drive signal that drives a gate of the switching element changes. Switching control device.

9. 2. The switching control device according to claim 1, The monitor unit includes a low pass filter configured to remove high frequency noise from the output signal. Switching control device.

10. 2. The switching control device according to claim 1, The slew rate adjustment unit includes a variable resistor that is provided on a line to which the gate voltage is applied and whose resistance value changes in accordance with the instruction signal. Switching control device.

11. 2. The switching control device according to claim 1, The switching element is a MOSFET. Switching control device.

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