Wiring circuit board, and method of manufacturing wiring circuit board

Abstract

To provide a wiring circuit board which secures a satisfactory electrical connection of an inter-layer connection part without thickening the wiring circuit board, a method of manufacturing a wiring circuit board, a semiconductor package including a wiring circuit board and an electronic apparatus.SOLUTION: A wiring circuit board comprises: a metal core layer 1 including a through hole; a first insulation layer 2 on one face of the metal core layer; a second insulation layer 5 on the other face; a first wiring layer 3 disposed on the first insulation layer; a second wiring layer 6 disposed on the second insulation layer; and an inter-layer connection part 23 which penetrates the through hole of the metal core layer, electrically connects the first wiring layer and the second wiring layer and is not electrically with the metal core layer. The inter-layer connection part includes a first inter-layer connection part 21 and a second inter-layer connection part 22 which are disposed in parallel in a thickness direction of the metal core layer. The first inter-layer connection part includes a bottom face 21a which is positioned in a layer region including the insulation layer, a top face 21b which is positioned in a region including the first wiring layer and includes an opening, and a side face 21c connecting an outer peripheral part of the bottom face with an inner peripheral part of the top face.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The present invention relates to a printed circuit board, a method for manufacturing a printed circuit board, a semiconductor package including the printed circuit board, and an electronic device. [Background technology]

[0002] A printed circuit board is manufactured by laminating conductors such as wiring and various insulating layers on a substrate, and the conductors and insulating layers are patterned by, for example, photolithography.

[0003] A multilayer printed wiring board has been proposed as a wiring circuit board, in which insulating layers and conductor layers are alternately stacked and the conductor layers are electrically connected to each other through via holes provided in the insulating layers, the multilayer printed wiring board having a first via group consisting of via holes provided in one of the two outermost insulating layers and at least one insulating layer stacked inward from the insulating layer, and a second via group consisting of via holes provided in the other of the two outermost insulating layers and at least one insulating layer stacked inward from the insulating layer, wherein the first via group and the second via group have a tapered shape in which the diameter of each via hole decreases as it moves inward in the thickness direction of the insulating layer, and the first via group and the second via group include stacked vias that are shifted relative to each other in a direction approximately perpendicular to the thickness direction of the insulating layer and are positioned so that they overlap at least partially in the thickness direction of the insulating layer (see Patent Document 1). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-156525 Summary of the Invention [Problem to be solved by the invention]

[0005] An example of a wired circuit board using a metal core layer is shown in Fig. 5. The wired circuit board shown in Fig. 5 includes a metal core layer 51 having a through hole, a first insulating layer 52 disposed on one surface of the metal core layer 51, a second insulating layer 55 disposed on the other surface of the metal core layer 51, a first wiring layer 53 disposed on the first insulating layer 52, a second wiring layer 56 disposed on the second insulating layer 55, a third insulating layer 54 covering the first wiring layer 53, a fourth insulating layer 57 covering the second wiring layer 56, and an interlayer connection portion 73 that passes through the through hole in the metal core layer 51 and electrically connects the first wiring layer 53 and the second wiring layer 56 but is not electrically connected to the metal core layer 51. The interlayer connection portion 73 includes a first interlayer connection portion 71 and a second interlayer connection portion 72 that are aligned in the thickness direction of the metal core layer 51. Here, the first interlayer connection portion 71 has a larger diameter than the second interlayer connection portion 72 so that the first interlayer connection portion 71 and the second interlayer connection portion 72 are reliably electrically connected even if the positions of the first interlayer connection portion 71 and the second interlayer connection portion 72 are slightly shifted from the designed positions. The manufacturing process of the wired circuit board shown in FIG. 5 includes, for example, the following steps. First, a metal core layer 51 is prepared (FIG. 6A). Next, a first insulating layer 52 is formed on one surface of the metal core layer 51 (FIG. 6B). Next, through holes 52a are formed in the first insulating layer 52 (FIG. 6C). Next, plating is performed. This plating serves both to form the first wiring layer 53 and to perform via-fill plating to fill the through holes 52a. By doing so, a first interlayer connection 71 is formed, and the first wiring layer 53 is formed on the first insulating layer 52 (FIG. 6D). Next, a third insulating layer 54 is formed so as to cover the first wiring layer 53 and the interlayer connection 71 (FIG. 6E). Next, through holes 51a are formed in the metal core layer 51 so that the first interlayer connection 71 is exposed (FIG. 6F). Next, a second insulating layer 55 is formed on the surface of the metal core layer 51 opposite the first insulating layer 52 side, and further, a through hole 55a is formed in the second insulating layer 55 within the through hole of the metal core layer 51 so that a portion of the first interlayer connection 71 is exposed (FIG. 6G). Next, plating is performed. This plating serves both to form the second wiring layer 56 and to perform via-fill plating to fill the through hole 55a. By doing so, the second interlayer connection 72 is formed, and the second wiring layer 56 is formed on the second insulating layer 55 (FIG. 6H). Next, a fourth insulating layer 57 is formed so as to cover the second wiring layer 56 and the second interlayer connection 72 (FIG. 6I). As a result of the above, the wired circuit board shown in FIG. 5 is obtained. Here, when via-fill plating is performed, the larger the opening of the hole to be filled, the thicker the plating thickness must be. Therefore, when attempting to form a first interlayer connection 71 with a large diameter by via-fill plating, the thickness of the first wiring layer 53 formed at the same time also becomes thicker. As a result, the thickness of the wired circuit board becomes thicker.

[0006] The present invention aims to provide a wiring circuit board that can ensure good electrical connection at interlayer connections without increasing the thickness of the wiring circuit board, a method for manufacturing the wiring circuit board, and a semiconductor package and electronic device that include the wiring circuit board. [Means for solving the problem]

[0007] The present inventors have conducted extensive research to solve the above problems, and as a result have found that the above problems can be solved, and have completed the present invention having the following gist.

[0008] That is, the present invention includes the following. [1] A metal core layer having through holes; a first insulating layer disposed on one surface of the metal core layer; a second insulating layer disposed on the other surface of the metal core layer; a first wiring layer disposed on the first insulating layer; a second wiring layer disposed on the second insulating layer; an interlayer connection portion that penetrates the through hole of the metal core layer, electrically connects the first wiring layer and the second wiring layer, and is not electrically connected to the metal core layer; and the interlayer connection portion has a first interlayer connection portion and a second interlayer connection portion aligned in a thickness direction of the metal core layer, the inter-layer connection portion has a bottom surface portion located in a layer region including the first insulating layer, a top surface portion located in a layer region including the first wiring layer and having an opening, and a side surface portion connecting an outer periphery of the bottom surface portion and an inner periphery of the top surface portion, the second interlayer connection portion passes through the through hole of the metal core layer; Wiring circuit board. [2] The wired circuit board according to [1], wherein the area of ​​the surface of the bottom surface of the first interlayer connection portion facing the second interlayer connection portion is larger than the area of ​​the surface of the second interlayer connection portion facing the first interlayer connection portion. [3] The wired circuit board according to [1] or [2], wherein the first interlayer connection portion and the second interlayer connection portion are in contact with each other at their bottom surfaces. [4] The wired circuit board according to any one of [1] to [3], wherein the thickness of the second interlayer connection portion is 100% to 140% of the thickness of the metal core layer. [5] The wired circuit board according to any one of [1] to [4], wherein the thickness of the second interlayer connection portion is greater than the thickness of the first interlayer connection portion. [6] The wired circuit board according to any one of [1] to [5], wherein the thickness of the bottom surface portion of the inter-layer connection portion is thinner than the total thickness of the first wiring layer and the first insulating layer. [7] The wired circuit board according to any one of [1] to [6], wherein the cross-sectional shape of the second interlayer connection portion in the thickness direction of the metal core layer is an inverted trapezoid in which the length of the side on the second insulating layer side is longer than the length of the side on the first insulating layer side. [8] A semiconductor package comprising the printed circuit board according to any one of [1] to [7]. [9] An electronic device including the semiconductor package described in [8].

[10] A method for manufacturing a wired circuit board according to any one of [1] to [7], forming a through hole in the first insulating layer of a laminate of a metal core layer and a first insulating layer; a step of applying conformal plating to the first insulating layer in which the through holes are formed to form a first wiring layer and a first interlayer connection portion; forming a through hole in the metal core layer so that a surface of a bottom surface of the inter-layer connection portion facing the metal core layer is exposed; forming a second insulating layer on a surface of the metal core layer, the second insulating layer having an opening through which a portion of the bottom surface of the inter-layer connection portion is exposed; forming a second wiring layer on the second insulating layer and forming a second interlayer connection portion so as to contact the bottom surface portion of the interlayer connection portion; A method for manufacturing a wired circuit board, comprising: [Effects of the Invention]

[0009] According to the present invention, it is possible to provide a wiring circuit board that can ensure good electrical connection at interlayer connections without increasing the thickness of the wiring circuit board, a method for manufacturing the wiring circuit board, and a semiconductor package and electronic device that include the wiring circuit board. [Brief explanation of the drawings]

[0010] [Figure 1A]FIG. 1A is a schematic diagram of one embodiment of a printed circuit board. [Figure 1B] FIG. 1B is a schematic diagram of one embodiment of a printed circuit board. [Figure 2A] FIG. 2A is a schematic diagram (part 1) for explaining one embodiment of the method for producing a wired circuit board. [Figure 2B] FIG. 2B is a schematic diagram (part 2) for explaining one embodiment of the method for producing a wired circuit board. [Figure 2C] FIG. 2C is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (part 3). [Figure 2D] FIG. 2D is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (part 4). [Figure 2E] FIG. 2E is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (part 5). [Figure 2F] FIG. 2F is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (part 6). [Figure 2G] FIG. 2G is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (part 7). [Figure 2H] FIG. 2H is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (part 8). [Figure 2I] FIG. 2I is a schematic diagram for explaining one embodiment of the method for producing a wired circuit board (No. 9). [Figure 3A] FIG. 3A is a schematic diagram of another embodiment of a printed circuit board. [Figure 3B] FIG. 3B is a schematic diagram of another embodiment of the printed circuit board. [Figure 4A] FIG. 4A is a schematic view (part 1) for explaining another embodiment of the method for producing a wired circuit board. [Figure 4B] FIG. 4B is a schematic view (part 2) for explaining another embodiment of the method for producing a wired circuit board. [Figure 4C]FIG. 4C is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (part 3). [Figure 4D] FIG. 4D is a schematic view for explaining another embodiment of the method for producing a wired circuit board (part 4). [Figure 4E] FIG. 4E is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (part 5). [Figure 4F] FIG. 4F is a schematic view for explaining another embodiment of the method for producing a wired circuit board (No. 6). [Figure 4G] FIG. 4G is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (No. 7). [Figure 4H] FIG. 4H is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (part 8). [Figure 4I] FIG. 4I is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (No. 9). [Figure 4J] FIG. 4J is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (part 10). [Figure 4K] FIG. 4K is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (No. 11). [Figure 4L] FIG. 4L is a schematic diagram for explaining another embodiment of the method for producing a wired circuit board (part 12). [Figure 5] FIG. 5 is a schematic diagram of a conventional example of a printed circuit board. [Figure 6A] FIG. 6A is a schematic view (part 1) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6B] FIG. 6B is a schematic view (part 2) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6C] FIG. 6C is a schematic view (part 3) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6D]FIG. 6D is a schematic view (part 4) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6E] FIG. 6E is a schematic view for explaining one example of a method for manufacturing the wired circuit board shown in FIG. 5 (part 5). [Figure 6F] FIG. 6F is a schematic view (part 6) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6G] FIG. 6G is a schematic view (part 7) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6H] FIG. 6H is a schematic view (part 8) for explaining one example of a method for manufacturing the wired circuit board shown in FIG. [Figure 6I] FIG. 6I is a schematic diagram for explaining one example of a method for manufacturing the wired circuit board shown in FIG. 5 (No. 9). DETAILED DESCRIPTION OF THE INVENTION

[0011] (Wired circuit board and method for manufacturing the wired circuit board) The wired circuit board of the present invention has at least a metal core layer, a first insulating layer, a second insulating layer, a first wiring layer, a second wiring layer, and an interlayer connection portion, and may further have other components as necessary. The metal core layer has a through hole. A first insulating layer is disposed on one side of the metal core layer. A second insulating layer is disposed on the other side of the metal core layer. The first wiring layer is disposed on the first insulating layer. The second wiring layer is disposed on the second insulating layer. The interlayer connection portion passes through the through hole, electrically connects the first wiring layer and the second wiring layer, and is not electrically connected to the metal core layer. Furthermore, the interlayer connection portion has a first interlayer connection portion and a second interlayer connection portion aligned in the thickness direction of the metal core layer. The first inter-layer connection portion has a bottom surface portion, a top surface portion, and a side surface portion. The bottom surface portion is located in a layer region including the first insulating layer. The top surface portion is located in a layer region including the first wiring layer and has an opening. The side surface portion connects the outer periphery of the bottom surface portion and the inner periphery of the top surface portion. The second interlayer connection portion passes through the through hole of the metal core layer.

[0012] The first interlayer connection can be preferably formed by conformal plating. Unlike via-fill plating, conformal plating does not fill the through-hole with plating (precipitate). In conformal plating, a plating (precipitate) film is formed along the outer peripheral surface of the through-hole. Therefore, when the first interlayer connection is formed by conformal plating, the through-hole of the first insulating layer is not filled, and the bottom, top, and side surfaces of the first interlayer connection are formed along the outer peripheral surface of the through-hole. Furthermore, unlike via-fill plating, conformal plating does not increase the thickness of the first wiring layer formed at the same time, even if the area of ​​the hole (through-hole) to be plated is increased. As a result, a wired circuit board can be manufactured without increasing the thickness of the wired circuit board.

[0013] Furthermore, by increasing the area of ​​the bottom surface of the first interlayer connection, good electrical connection between the first interlayer connection and the second interlayer connection can be ensured even if the positions of the first interlayer connection and the second interlayer connection are slightly deviated from their designed positions. This eliminates the need to form pads to ensure electrical connection between the first interlayer connection and the second interlayer connection, thereby shortening the manufacturing process of the wired circuit board. Therefore, in the present invention, the area of ​​the surface of the bottom surface of the first interlayer connection facing the second interlayer connection is preferably larger than the area of ​​the surface of the second interlayer connection facing the first interlayer connection. More preferably, the area of ​​the surface of the bottom surface of the first interlayer connection facing the second interlayer connection is 150% to 300% of the area of ​​the surface of the second interlayer connection facing the first interlayer connection. Furthermore, since the first interlayer connection portion has a recessed structure rather than a structure that fills the through hole in the first insulating layer, the effect of suppressing warpage can be expected even when stress is applied to the interlayer connection portion due to its shape. If the area of ​​the surface of the bottom surface of the first interlayer connection portion facing the second interlayer connection portion is larger than the area of ​​the surface of the second interlayer connection portion facing the first interlayer connection portion, this effect can be expected to be even greater, and connection reliability will be improved.

[0014] The thickness of the second interlayer connection is not particularly limited, but is preferably 100% to 140% of the thickness of the metal core layer. When the second interlayer connection has a thickness equal to or greater than the thickness of the metal core layer, it can work together with the metal core layer to ensure the rigidity of the wiring circuit board and suppress warpage. Here, the thickness of the second interlayer connection portion refers to the length of the second interlayer connection portion in the thickness direction of the metal core layer.

[0015] The first interlayer connection portion and the second interlayer connection portion are preferably in contact with each other at their bottom surfaces, which increases the linearity of electrical signals passing through the interlayer connection portions and reduces transmission loss.

[0016] The thickness of the second interlayer connection portion is preferably greater than the thickness of the first interlayer connection portion.

[0017] The cross-sectional shape of the second interlayer connection portion in the thickness direction of the metal core layer is preferably an inverted trapezoid in which the side on the second insulating layer side is longer than the side on the first insulating layer side. This increases the degree of freedom in the shape of the second interlayer connection portion. As a result, the degree of freedom in the design of the wiring connected to the second interlayer connection portion also increases.

[0018] An example of the wired circuit board of the present invention will be described below with reference to Figures 1A and 1B. In Figure 1B, the regions sandwiched between the dashed lines are layer region 24 including first insulating layer 2 and layer region 25 including first wiring layer 3, respectively. Except for this, Figure 1B is the same as Figure 1A. 1A and 1B has a metal core layer 1, a first insulating layer 2, a second insulating layer 5, a first wiring layer 3, a second wiring layer 6, and an interlayer connection portion 23. The wired circuit board further has a third insulating layer 4 and a fourth insulating layer 7. The interlayer connection portion 23 has a first interlayer connection portion 21 and a second interlayer connection portion 22 arranged in the thickness direction of the metal core layer 1 . The metal core layer 1 has through holes. The first insulating layer 2 is disposed on one surface of the metal core layer 1 . The second insulating layer 5 is disposed on the other surface of the metal core layer 1 . The first wiring layer 3 is disposed on the first insulating layer 2 . The second wiring layer 6 is disposed on the second insulating layer 5 . The third insulating layer 4 covers the first wiring layer 3 and the inter-layer connection portion 21. The fourth insulating layer 7 covers the second wiring layer 6 and the second interlayer connection portion 22. The interlayer connection portion 23 passes through the through hole of the metal core layer 1. The interlayer connection portion 23 electrically connects the first wiring layer 3 and the second wiring layer 6. The interlayer connection portion 23 is not electrically connected to the metal core layer 1. Furthermore, the first interlayer connection portion 21 has a bottom surface portion 21a located in a layer region 24 including the first insulating layer 2, a top surface portion 21b located in a layer region 25 including the first wiring layer 3 and having an opening, and a side surface portion 21c connecting the outer periphery of the bottom surface portion 21a and the inner periphery of the top surface portion 21b. The second interlayer connection portion 22 passes through the through hole of the metal core layer 1 .

[0019] Layer region 25 refers to a region that has the same thickness as first wiring layer 3 and includes first wiring layer 3. Layer region 24 refers to a region adjacent to layer region 25 and sandwiched between metal core layer 1 and layer region 25.

[0020] 1A and 1B, first interlayer connection 21 and second interlayer connection 22 are connected on the same plane as the surface of metal core layer 1 facing first insulating layer 2. The area of ​​bottom surface 21a of first interlayer connection 21 on that plane is larger than the area of ​​the surface of second interlayer connection 22. In other words, the area of ​​the surface of bottom surface 21a of first interlayer connection 21 facing second interlayer connection 22 is larger than the area of ​​the surface of second interlayer connection 22 facing first interlayer connection 21.

[0021] 1A and 1B, first interlayer connection portion 21 and second interlayer connection portion 22 are in contact with each other at their bottom surfaces. The bottom surface refers to one of the surfaces of first interlayer connection portion 21 and second interlayer connection portion 22 in the thickness direction of the wired circuit board.

[0022] 1A and 1B, the thickness of second interlayer connection portion 22 is greater than the thickness of first interlayer connection portion 21. Here, the thickness of second interlayer connection portion 22 refers to the length of the second interlayer connection portion in the thickness direction of the metal core layer. The thickness of first interlayer connection portion 21 refers to the length of the first interlayer connection portion in the thickness direction of the metal core layer. More specifically, the length of the first interlayer connection portion refers to the length from the surface of bottom surface portion 21a facing the metal core layer 1 to the surface of top surface portion 21b opposite the metal core layer 1 side in the thickness direction of the metal core layer.

[0023] 1A and 1B, the cross-sectional shape of the second interlayer connection portion 22 in the thickness direction of the metal core layer 1 is an inverted trapezoid in which the length of the side on the second insulating layer 5 side is longer than the length of the side on the first insulating layer 2 side.

[0024] 1A and 1B, the thickness of the bottom surface portion 21a of the first interlayer connection portion 21 is thinner than the total thickness of the first wiring layer 3 and the first insulating layer 2. In FIG.

[0025] The metal core layer is, for example, an element for ensuring the rigidity of the printed circuit board. The material of the metal core layer is not particularly limited, and examples thereof include Cu, Cu alloys, Al, stainless steel, FeNi alloys such as alloy 42, and combinations thereof. Among these, from the viewpoints of thermal conductivity and electrical conductivity, Cu, Cu alloys, and stainless steel are preferred. The thickness of the metal core layer is not particularly limited, and is, for example, 10 μm or more, preferably 15 μm or more, and is, for example, 500 μm or less, preferably 300 μm or less. In the present invention, the term "thickness" refers to the length of the metal core layer in the thickness direction thereof. The thickness direction of the metal core layer refers to the direction perpendicular to the surface direction of the metal core layer.

[0026] The material for the insulating layers (e.g., first insulating layer, second insulating layer, third insulating layer, fourth insulating layer, fifth insulating layer) in the wired circuit board is not particularly limited, and examples thereof include synthetic resins. Examples of synthetic resins include polyimide, epoxy resin, polyethernitrile, polyethersulfone, polyethylene terephthalate, polyethylene naphthalate, polyvinyl chloride, etc. Polyimide and epoxy resin are preferred because of their excellent heat resistance, low linear expansion coefficient, and dielectric strength. For example, the insulating layer is formed using photosensitive polyimide or photosensitive epoxy resin. The insulating layer may or may not contain a filler, but if it does not contain a filler, it will have excellent insulating properties and excellent electrical leakage suppression. Examples of fillers include inorganic fillers and organic fillers. Examples of inorganic fillers include silicon oxide, silicon nitride, aluminum oxide, aluminum nitride, aluminum hydroxide, boron nitride, crystalline silica, barium sulfate, magnesium carbonate, calcium carbonate, etc. Examples of organic fillers include polyphenylene ether, rubber, etc. The insulating layer may or may not contain glass fiber. An insulating layer containing glass fiber is formed by impregnating a glass fiber cloth with a synthetic resin, such as a glass epoxy resin represented by FR4 (Flame Retardant Type 4). The thickness of the insulating layer is not particularly limited, and is, for example, 1 μm or more, preferably 3 μm or more, and for example, 35 μm or less, preferably 20 μm or less.

[0027] Examples of materials for the wiring layers (e.g., first wiring layer, second wiring layer, third wiring layer) in the printed circuit board include metal materials, such as copper, nickel, gold, solder, and alloys thereof. The thickness of the wiring layer is not particularly limited, and is, for example, 3 μm or more, preferably 5 μm or more, and for example, 50 μm or less, preferably 30 μm or less.

[0028] The main component of the interlayer connection is not particularly limited, and examples thereof include metal materials such as copper, nickel, gold, solder, and alloys thereof. The interconnects may be made of one material or different materials, and by one material it does not mean that they are made of one metal or one compound, but rather that the material composition is the same throughout the interconnect. In one embodiment, the first interlayer connection and the second interlayer connection are different materials. Here, different materials include, for example, materials having different types of main components, materials having the same type of main component but different types of subcomponents or contents of the subcomponents, and the like. The first interlayer connection portion and the second interlayer connection portion may, for example, contain the same metal as the main component, but differ in at least one of the type of subcomponent and the content of the subcomponent. For example, if the first interlayer connection portion and the second interlayer connection portion are mainly composed of Cu and contain Cl and S as subcomponents, and the Cl and S contents are different, the first interlayer connection portion and the second interlayer connection portion are made of different materials.

[0029] A typical example in which the first interlayer connection portion and the second interlayer connection portion are made of different materials is when the first interlayer connection portion and the second interlayer connection portion are formed using different plating solutions.

[0030] The shape of the through-holes in the metal core layer is not particularly limited. The through-hole in the metal core layer preferably has a tapered shape, which allows greater freedom in designing the through-hole. In the present invention, a tapered shape refers to a shape in which one opening of a through hole is larger than the other opening, and therefore, when the through hole has a tapered shape, the shape of the side surface of the through hole is, for example, trapezoidal in a cross section parallel to the thickness direction of the metal core layer.

[0031] The shape of the side surface of the through hole in the metal core layer is not particularly limited. The shape of the side surface of the through hole in the metal core layer may be arc-shaped or linear in a cross section parallel to the thickness direction of the metal core layer. The term "arc-shaped" here refers to a shape that is recessed from the through-hole side toward the metal core layer side.

[0032] The shape of the second interlayer connection portion is not particularly limited. The cross-sectional shape of the second interlayer connection portion is not particularly limited, and may be, for example, rectangular or trapezoidal in a cross section parallel to the thickness direction of the metal core layer.

[0033] The printed circuit board may have a seed layer (not shown), which is used as a conductive layer for electrolytic plating. Examples of materials for the seed layer include copper, chromium, nickel, and alloys thereof.

[0034] The method for producing a wired circuit board of the present invention includes the following steps. A step of forming a through hole in the first insulating layer of a laminate of the metal core layer and the first insulating layer. A step of forming a first wiring layer and a first interlayer connection portion by performing conformal plating on the first insulating layer in which the through holes are formed. A step of forming a through hole in the metal core layer so that the surface of the bottom surface of the first interlayer connection portion on the metal core layer side is exposed A step of forming a second insulating layer on the surface of the metal core layer, the second insulating layer having an opening through which a part of the bottom surface of the first interlayer connection portion is exposed. A step of forming a second wiring layer on the second insulating layer and forming a second interlayer connection portion so as to contact the bottom surface of the first interlayer connection portion. The method for producing the wired circuit board of the present invention is a method for producing the wired circuit board of the present invention.

[0035] An embodiment of a method for manufacturing the wired circuit board shown in FIGS. 1A and 1B will be described with reference to FIGS. 2A to 2H. First, a metal core layer 1 is prepared (FIG. 2A).

[0036] Next, a first insulating layer 2 is formed on one surface of the metal core layer 1 (FIG. 2B). The first insulating layer 2 can be formed, for example, by applying and drying a photosensitive resin composition containing a photosensitive polyimide.

[0037] Next, the first insulating layer 2 is processed into a pattern so as to have through holes 2a (FIG. 2C). The processing into a pattern can be performed, for example, by selectively exposing and developing the formed photosensitive polyimide film.

[0038] Next, a patterned first wiring layer 3 is formed on the first insulating layer 2, and a first interlayer connection 21 is formed in the through hole 2a (FIG. 2D). The formed first interlayer connection 21 has a bottom surface 21a located in a layer region 24 including the first insulating layer 2, a top surface 21b having an opening located in a layer region 25 including the first wiring layer 3, and a side surface 21c connecting the outer periphery of the bottom surface 21a and the inner periphery of the top surface 21b. The first interlayer connection 21 does not fill the through hole 2a but has a recessed structure. The first wiring layer 3 and the interlayer connection 21 can be formed, for example, as follows. Formation of a seed layer (not shown) on the first insulating layer 2 Formation of a photoresist film (not shown) on the seed layer · Formation of resist patterns by selective exposure and development of photoresist film (partial exposure of seed layer) Conformal plating on exposed seed layer Removal of photoresist film and unnecessary seed layer This completes the formation of the patterned first wiring layer 3. Furthermore, first inter-layer connection portions 21 having a recessed structure along the outer peripheral surface of the through holes 2a of the first insulating layer 2 are formed integrally with the patterned first wiring layer 3 by conformal plating.

[0039] Next, a third insulating layer 4 is formed so as to cover the patterned first wiring layer 3 and the interlayer connections 21 (FIG. 2E). The third insulating layer 4 can be formed, for example, by applying and drying a photosensitive resin composition containing a photosensitive polyimide.

[0040] Next, a through hole 1a is formed in the metal core layer 1 so as to expose the entire surface of the bottom surface 21a of the first interlayer connection portion 21 on the side of the metal core layer 1 (FIG. 2F). The through hole 1a can be formed, for example, as follows. Formation of a photoresist film (not shown) on the metal core layer 1 Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the metal core layer 1) Wet etching of the exposed metal core layer 1 (e.g., wet etching using ferric chloride) Photoresist film removal In this way, the through-hole 1a is formed.

[0041] Next, a second insulating layer 5 is formed on the surface of the metal core layer 1 opposite to the first insulating layer 2 side, and further, a through hole 5a is formed in the second insulating layer 5 within the through hole 1a of the metal core layer 1 so as to expose a part of the first interlayer connection 21 (FIG. 2G). The second insulating layer 5 having the through hole 5a can be formed, for example, as follows. Formation of a photosensitive polyimide film by applying and drying a photosensitive resin composition containing a photosensitive polyimide Selective exposure of the photosensitive polyimide film and formation of through-holes 5a by development

[0042] Next, plating is performed selectively on the second insulating layer 5 so as to fill the through holes 5a (FIG. 2H). This plating serves both to form the second wiring layer 6 and to perform via-fill plating to fill the through holes 5a. Plating can be performed, for example, as follows. Formation of a seed layer (not shown) on the second insulating layer 5 Formation of a photoresist film (not shown) on the seed layer · Formation of resist patterns by selective exposure and development of photoresist film (partial exposure of seed layer) Electroplating on exposed seed layer Removal of photoresist film and unnecessary seed layer By doing so, the second interlayer connection portion 22 is formed, and the second wiring layer 6 is formed on the second insulating layer 5 (FIG. 2H). That is, the second wiring layer 6 and the second interlayer connection portion 22 are formed integrally.

[0043] Next, a fourth insulating layer 7 is formed so as to cover the patterned second wiring layer 6 and the second interlayer connection portion 22 (FIG. 2I). The fourth insulating layer 7 can be formed, for example, by applying and drying a photosensitive resin composition containing a photosensitive polyimide. As a result of the above, the printed circuit board shown in FIG. 2I (FIGS. 1A and 1B) is obtained.

[0044] The wired circuit board may be further processed to provide, for example, a terminal connection portion for electrically connecting an external terminal and the interlayer connection portion on the wired circuit board.

[0045] 3A and 3B are schematic diagrams of another embodiment of the wired circuit board. In Fig. 3B, the regions sandwiched between the dashed lines are a layer region 24 including the first insulating layer 2 and a layer region 25 including the first wiring layer 3, respectively. Other than that, Fig. 3B is the same as Fig. 3A. 3A and 3B has a metal core layer 1, a first insulating layer 2, a second insulating layer 5, a first wiring layer 3, a second wiring layer 6, and an interlayer connection portion 23. The wired circuit board further has a third insulating layer 4, a fourth insulating layer 7, a third wiring layer 8, a fifth insulating layer 9, and a connection portion 10 for connecting terminals. The interlayer connection portion 23 has a first interlayer connection portion 21 and a second interlayer connection portion 22 arranged in the thickness direction of the metal core layer 1 . The metal core layer 1 has through holes. The first insulating layer 2 is disposed on one surface of the metal core layer 1 . The second insulating layer 5 is disposed on the other surface of the metal core layer 1 . The first wiring layer 3 is disposed on the first insulating layer 2 . The second wiring layer 6 is disposed on the second insulating layer 5 . The third insulating layer 4 is disposed on the first wiring layer 3 and the inter-layer connection portion 21. The fourth insulating layer 7 is disposed on the second wiring layer 6 and the second interlayer connection portion 22 . The third wiring layer 8 is disposed on the third insulating layer 4. The fifth insulating layer 9 covers the third wiring layer 8. The terminal connection connecting portion 10 is disposed on the second interlayer connecting portion 22 and on the second wiring layer 6. The terminal connection connecting portion 10 is a connecting portion for electrically connecting to an external terminal. The interlayer connection portion 23 passes through the through hole of the metal core layer 1. The interlayer connection portion 23 electrically connects the first wiring layer 3 and the second wiring layer 6. The interlayer connection portion 23 is not electrically connected to the metal core layer 1. Furthermore, the first interlayer connection portion 21 has a bottom surface portion 21a located in a layer region 24 including the first insulating layer 2, a top surface portion 21b located in a layer region 25 including the first wiring layer 3 and having an opening, and a side surface portion 21c connecting the outer periphery of the bottom surface portion 21a and the inner periphery of the top surface portion 21b. The second interlayer connection portion 22 passes through the through hole of the metal core layer 1 .

[0046] An embodiment of a method for manufacturing the wired circuit board shown in FIGS. 3A and 3B will be described with reference to FIGS. 4A to 4L. First, a metal core layer 1 is prepared (FIG. 4A).

[0047] Next, a first insulating layer 2 having through holes 2a is formed on one surface of the metal core layer 1 (FIG. 4B). The first insulating layer 2 having through holes 2a can be formed, for example, as follows. Coating and drying of photosensitive resin compositions containing photosensitive polyimides Selective exposure and development of the formed photosensitive polyimide film

[0048] Next, a patterned first wiring layer 3 is formed on the first insulating layer 2, and a first interlayer connection 21 is formed in the through hole 2a (FIG. 4C). The formed first interlayer connection 21 has a bottom surface 21a located in a layer region 24 including the first insulating layer 2, a top surface 21b having an opening located in a layer region 25 including the first wiring layer 3, and a side surface 21c connecting the outer periphery of the bottom surface 21a and the inner periphery of the top surface 21b. The first interlayer connection 21 does not fill the through hole 2a but has a recessed structure. The first wiring layer 3 and the interlayer connection 21 can be formed, for example, as follows. Formation of a seed layer (not shown) on the first insulating layer 2 Formation of a photoresist film (not shown) on the seed layer · Formation of resist patterns by selective exposure and development of photoresist film (partial exposure of seed layer) Conformal plating on exposed seed layer Removal of photoresist film and unnecessary seed layer This completes the formation of the patterned first wiring layer 3. Furthermore, first inter-layer connection portions 21 having a recessed structure along the outer peripheral surface of the through holes 2a of the first insulating layer 2 are formed integrally with the patterned first wiring layer 3 by conformal plating.

[0049] Next, a third insulating layer 4 is formed on the first wiring layer 3 (FIG. 4D). In the wired circuit board shown in FIGS. 3A and 3B, the third insulating layer 4 is formed in a pattern so that the first interlayer connections 21 and a portion of the first wiring layer 3 are exposed. The patterned third insulating layer 4 can be formed, for example, by applying and drying a photosensitive resin composition containing a photosensitive polyimide, and selectively exposing and developing the formed photosensitive polyimide film.

[0050] Next, the third wiring layer 8 is formed on the patterned third insulating layer 4 (FIG. 4E). The third wiring layer 8 can be formed, for example, as follows. Formation of a seed layer (not shown) on the third insulating layer 4 Formation of a photoresist film (not shown) on the seed layer · Formation of resist patterns by selective exposure and development of photoresist film (partial exposure of seed layer) Electroplating on exposed seed layer Removal of photoresist film and unnecessary seed layer The patterned electrolytic plating layer thus formed becomes the third wiring layer 8. In this way, the patterned third wiring layer 8 is formed.

[0051] Next, a patterned fifth insulating layer 9 is formed on the third wiring layer 8 (FIG. 4F). The patterned fifth insulating layer 9 can be formed, for example, by applying and drying a photosensitive resin composition containing a photosensitive polyimide, and selectively exposing and developing the formed photosensitive polyimide film. In the wired circuit board shown in FIGS. 3A and 3B, the fifth insulating layer 9 is formed in a pattern so that the first interlayer connection 21 and a portion of the first wiring layer 3 are exposed.

[0052] Next, a through hole 1a is formed in the metal core layer 1 so as to expose the entire surface of the bottom surface 21a of the first interlayer connection portion 21 on the metal core layer 1 side (FIG. 4G). The through hole 1a can be formed, for example, as follows. Formation of a photoresist film (not shown) on the metal core layer 1 Formation of a resist pattern by selective exposure and development of a photoresist film (partial exposure of the metal core layer 1) Wet etching of the exposed metal core layer 1 (e.g., wet etching using ferric chloride) Photoresist film removal In this way, the through-hole 1a is formed.

[0053] Next, a second insulating layer 5 is formed on the surface of the metal core layer 1 opposite to the first insulating layer 2 side so as to fill the through-holes 1a (FIG. 4H). The second insulating layer 5 can be formed, for example, by applying and drying a photosensitive resin composition containing a photosensitive polyimide.

[0054] Next, a through hole 5a is formed in the second insulating layer 5 within the through hole 1a of the metal core layer 1 so as to expose a portion of the first interlayer connection portion 21 (FIG. 4I). The through hole 5a can be formed, for example, by selectively exposing the formed photosensitive polyimide film to light and developing it.

[0055] Next, plating is performed selectively on the second insulating layer 5 so as to fill the through holes 5a (FIG. 4J). This plating serves both to form the second wiring layer 6 and to perform via-fill plating to fill the through holes 5a. Plating can be performed, for example, as follows. Formation of a seed layer (not shown) on the second insulating layer 5 Formation of a photoresist film (not shown) on the seed layer · Formation of resist patterns by selective exposure and development of photoresist film (partial exposure of seed layer) Electroplating on exposed seed layer Removal of photoresist film and unnecessary seed layer By doing so, the second interlayer connection portion 22 is formed, and the second wiring layer 6 is formed on the second insulating layer 5 (FIG. 4J). That is, the second wiring layer 6 and the second interlayer connection portion 22 are formed integrally.

[0056] Next, the connecting portion 10 for connecting terminals is formed on the second interlayer connecting portion 22 and on a part of the second wiring layer 6 (FIG. 4K). The connecting portion 10 for connecting terminals can be formed, for example, as follows. Formation of a photoresist film (not shown) on the second insulating layer 5, the second wiring layer 6, and the second interlayer connection portion 22 Formation of a resist pattern by selective exposure and development of a photoresist film (exposure of the second interlayer connection portion 22 and a part of the second wiring layer 6) Plating on the exposed second interlayer connection portion 22 and the second wiring layer 6 Photoresist film removal In this way, the terminal connection part 10 is formed.

[0057] Next, a fourth insulating layer 7 having an opening that exposes the terminal connection connection portion 10 is formed on the second insulating layer 5, the second wiring layer 6, the second interlayer connection portion 22, and the terminal connection connection portion 10 (FIG. 4L). The fourth insulating layer 7 having an opening can be formed, for example, as follows. Formation of the fourth insulating layer 7 by applying and drying a photosensitive resin composition containing a photosensitive polyimide. · Formation of openings by selective exposure and development of the formed photosensitive polyimide film

[0058] As a result of the above, the printed circuit board shown in FIG. 4L (FIGS. 3A and 3B) is obtained.

[0059] (Semiconductor package) The semiconductor package of the present invention includes the wired circuit board of the present invention. The semiconductor package includes, for example, a semiconductor chip connected to a printed circuit board. The semiconductor package includes, for example, a sealing resin that seals the semiconductor chip. Examples of semiconductor packages include FC-CSP (Flip Chip-Chip Scale Package), MIS-BGA (Molded Interconnect Substrate-Ball Grid Array) package, ETS-BGA (Embedded Trace Substrate-Ball Grid Array) package, Fan-out WLP (Wafer Level Package), Fan-in WLP, Fan-out PLP (Panel Level Package), Fan-in PLP, FC-BGA (Flip Chip-Chip, -Ball Grid Array), and high-end 2.5D and 3D packages.

[0060] (electronic equipment) An electronic device of the present invention includes the semiconductor package of the present invention. Examples of electronic devices include, but are not limited to, ICT infrastructure devices such as servers, routers, supercomputers, mainframes, and workstations; antennas such as GPS antennas, antennas for wireless base stations, millimeter-wave antennas, and RFID antennas; communication devices such as mobile phones, smartphones, PHS, PDAs, and tablet terminals; digital devices such as personal computers, televisions, digital cameras, digital video cameras, POS terminals, wearable terminals, and digital media players; in-vehicle electronic devices such as electronic control system devices, in-vehicle communication devices, car navigation devices, millimeter-wave radars, and in-vehicle camera modules; semiconductor testing devices, high-frequency measuring devices, and the like. [Explanation of symbols]

[0061] 1 Metal core layer 1a Through hole 2. First insulating layer 2a Through hole 3 First wiring layer 4. Third insulating layer 5 Second insulating layer 5a through hole 6 Second wiring layer 7 Fourth insulating layer 8 Third wiring layer 9 Fifth insulating layer 10 Terminal connection part 21 First layer inter-connection 21a Bottom part 21b Top part 21c Side part 22 Second interlayer connection 23 Interlayer connection 24 layer area 25 layer area 51 Metal core layer 51a Through hole 52 First insulating layer 52a through hole 53 First wiring layer 54 Third insulating layer 55 Second insulating layer 55a through hole 56 Second wiring layer 57 Fourth insulating layer 71 First layer connection 72 Second interlayer connection 73 Interlayer connection

Claims

1. a metal core layer having a through hole; a first insulating layer disposed on one surface of the metal core layer; a second insulating layer disposed on the other surface of the metal core layer; a first wiring layer disposed on the first insulating layer; a second wiring layer disposed on the second insulating layer; an interlayer connection portion that penetrates the through hole of the metal core layer, electrically connects the first wiring layer and the second wiring layer, and is not electrically connected to the metal core layer; and the interlayer connection portion has a first interlayer connection portion and a second interlayer connection portion aligned in a thickness direction of the metal core layer, the inter-layer connection portion has a bottom surface portion located in a layer region including the first insulating layer, a top surface portion located in a layer region including the first wiring layer and having an opening, and a side surface portion connecting an outer periphery of the bottom surface portion and an inner periphery of the top surface portion, the second interlayer connection portion passes through the through hole of the metal core layer; Wiring circuit board.

2. 2. The wired circuit board according to claim 1, wherein an area of ​​the surface of the bottom surface portion of the first interlayer connection portion facing the second interlayer connection portion is larger than an area of ​​the surface of the second interlayer connection portion facing the first interlayer connection portion.

3. The printed circuit board according to claim 1 , wherein the first interlayer connection portion and the second interlayer connection portion are in contact with each other at their bottom surfaces.

4. 2. The wired circuit board according to claim 1, wherein the thickness of the second interlayer connection portion is 100% to 140% of the thickness of the metal core layer.

5. The printed circuit board according to claim 1 , wherein the second interlayer connection portion has a thickness greater than a thickness of the first interlayer connection portion.

6. The wired circuit board according to claim 1 , wherein the thickness of the bottom surface portion of the inter-layer connection portion is thinner than the total thickness of the first wiring layer and the first insulating layer.

7. 2. The wired circuit board according to claim 1, wherein the cross-sectional shape of the second interlayer connection portion in the thickness direction of the metal core layer is an inverted trapezoid in which the length of the side on the second insulating layer side is longer than the length of the side on the first insulating layer side.

8. A semiconductor package comprising the printed circuit board according to any one of claims 1 to 7.

9. An electronic device comprising the semiconductor package according to claim 8.

10. A method for manufacturing a wired circuit board, which manufactures the wired circuit board according to any one of claims 1 to 7, comprising the steps of: forming a through hole in the first insulating layer of a laminate of a metal core layer and a first insulating layer; a step of applying conformal plating to the first insulating layer in which the through holes are formed to form a first wiring layer and a first interlayer connection portion; forming a through hole in the metal core layer so that a surface of a bottom surface of the inter-layer connection portion facing the metal core layer is exposed; forming a second insulating layer on a surface of the metal core layer, the second insulating layer having an opening through which a portion of the bottom surface of the inter-layer connection portion is exposed; forming a second wiring layer on the second insulating layer and forming a second interlayer connection portion so as to contact the bottom surface portion of the interlayer connection portion; A method for manufacturing a wired circuit board, comprising:

Images