Driving method of semiconductor device

Abstract

To read data from a memory cell having a ferroelectric capacitor without destroying the data.SOLUTION: During a read operation of a memory cell having a ferroelectric capacitor, the read operation is performed by gradually increasing the voltage on the opposite electrode side of the ferroelectric capacitor so as not to destroy the polarization of the ferroelectric capacitor. A first read operation of data from the memory cell is performed by applying a first voltage to the capacitor that does not invert the polarization of the ferroelectric layer, and a second read operation of data from the memory cell is performed by applying a second voltage to the capacitor that does not invert the polarization of the ferroelectric layer, and the second voltage is greater than the first voltage.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a method for driving a semiconductor device, a semiconductor device, or the like.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, imaging devices, display devices, light-emitting devices, power storage devices, memory devices, display systems, electronic devices, lighting devices, input devices, input / output devices, and driving methods thereof or manufacturing methods thereof. Note that a semiconductor device generally refers to a device that utilizes semiconductor characteristics, and a memory device is a semiconductor device. [Background technology]

[0003] In recent years, the development of semiconductor devices has progressed, and LSIs, CPUs, memories, etc. are mainly used in semiconductor devices. A CPU is an assembly of semiconductor elements that have semiconductor integrated circuits (at least transistors and memories) processed from semiconductor wafers and formed into chips, and on which electrodes serving as connection terminals are formed.

[0004] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards, such as printed wiring boards, and are used as components in a variety of electronic devices.

[0005] Furthermore, a technology for constructing transistors using semiconductor thin films formed on substrates with insulating surfaces has attracted attention. Such transistors are widely used in electronic devices such as integrated circuits (ICs) and image display devices (also simply referred to as display devices). Silicon-based semiconductor materials and oxide semiconductors are known as semiconductor thin films applicable to transistors.

[0006] Furthermore, as shown in Non-Patent Document 1, research and development of memory cells using ferroelectrics is being actively conducted. Furthermore, for the next generation of ferroelectric memories, research on hafnium oxide is also being actively conducted, including research on ferroelectric HfO2-based materials (Non-Patent Document 2), research on the ferroelectricity of hafnium oxide thin films (Non-Patent Document 3), and research on the ferroelectricity of HfO2 thin films (Non-Patent Document 4). [Prior art documents] [Non-patent literature]

[0007] [Non-Patent Document 1] TSBoescke,et al,“Ferroelectricity in hafnium oxide thin films”,APL99,2011 [Non-patent document 2] Zhen Fan,et al,“Ferroelectric HfO2-based materials for next-generation ferroelectric memories”,JOURNAL OF ADVANCED DIELECTRICS,Vol.6,No.2,2016 [Non-patent document 3] Jun Okuno,et al,“SoC compatible 1T1C FeRAM memory array based on ferroelectric Hf0.5Zr0.5O2”,VLSI 2020 [Non-patent document 4] Akira Toriumi, "Ferroelectricity of HfO2 Thin Films," The Japan Society of Applied Physics, Vol. 88, No. 9, 2019 Summary of the Invention [Problem to be solved by the invention]

[0008] In a memory cell using a ferroelectric, data is read using the presence or absence of polarization reversal of the ferroelectric. In this case, the data stored in the memory cell is reversed during the data read operation. In other words, a memory cell using a ferroelectric is a destructive read. A memory cell using a ferroelectric, which is a destructive read, requires a data rewrite operation every time data is read. The data rewrite operation requires the application of a high voltage to the ferroelectric, which may result in increased power consumption, etc.

[0009] An object of one embodiment of the present invention is to provide a semiconductor device from which data can be read without destroying the data and a driving method thereof.An object of one embodiment of the present invention is to provide a semiconductor device with low power consumption and a driving method thereof.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and a driving method thereof.An object of one embodiment of the present invention is to provide a novel semiconductor device and a driving method thereof.

[0010] The problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. The other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention solves at least one of the problems listed above and / or other problems. [Means for solving the problem]

[0011] One aspect of the present invention is a method for driving a semiconductor device, which includes a memory cell having a capacitor with a ferroelectric layer between a first electrode and a second electrode, a first read operation of data from the memory cell being performed by applying a first voltage to the capacitor that does not cause polarization reversal of the ferroelectric layer, and a second read operation of data from the memory cell being performed by applying a second voltage to the capacitor that does not cause polarization reversal of the ferroelectric layer, the second voltage being greater than the first voltage.

[0012] One aspect of the present invention is a method for driving a semiconductor device, which includes a memory cell having a capacitor with a ferroelectric layer between a first electrode and a second electrode, a first read operation of data from the memory cell being performed by applying a first voltage to the capacitor that does not invert the polarization of the ferroelectric layer, and a second read operation of data from the memory cell being performed by applying a second voltage to the capacitor that does not invert the polarization of the ferroelectric layer, the second voltage being greater than the first voltage, and the first voltage being greater than a voltage that reduces the polarization of the ferroelectric layer to zero.

[0013] In one aspect of the present invention, a method for driving a semiconductor device is preferred, in which the memory cell has a transistor, a first read voltage read onto a bit line via the transistor by a first read operation is compared with a first reference voltage, and a second read voltage read onto the bit line via the transistor by a second read operation is compared with a second reference voltage, and the second reference voltage is greater than the first reference voltage.

[0014] In one aspect of the present invention, a method for driving a semiconductor device having a reference memory cell is preferred, in which a first read voltage read onto a bit line by a first read operation and a second read voltage read onto a bit line by a second read operation are compared with the read voltage read from the reference memory cell.

[0015] In one embodiment of the present invention, the method for driving a semiconductor device preferably includes the step of: forming a first insulating film on a first insulating film;

[0016] In one aspect of the present invention, the ferroelectric layer preferably comprises hafnium zirconium oxide or a nitride of a metal of Groups 13 to 15. In the method for driving the semiconductor device,

[0017] Other aspects of the present invention will be described in the following embodiments and in the drawings. [Effects of the Invention]

[0018] One embodiment of the present invention can provide a semiconductor device from which data can be read without destroying the data and a driving method thereof. Another embodiment of the present invention can provide a semiconductor device with low power consumption and a driving method thereof. Another embodiment of the present invention can provide a highly reliable semiconductor device and a driving method thereof. Another embodiment of the present invention can provide a novel semiconductor device and a driving method thereof.

[0019] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and / or other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 2] 2A, 2B, and 2C are diagrams showing configuration examples of a semiconductor device. [Figure 3] 3A and 3B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 4] FIG. 4 is a diagram illustrating a configuration example of a semiconductor device. [Figure 5] 5A and 5B are diagrams illustrating an example of the configuration of a semiconductor device. [Figure 6] FIG. 6 is a diagram illustrating a configuration example of a semiconductor device. [Figure 7] FIG. 7 is a diagram illustrating a configuration example of a semiconductor device. [Figure 8] FIG. 8 is a diagram illustrating a configuration example of a semiconductor device. [Figure 9] FIG. 9 is a diagram illustrating a configuration example of a semiconductor device. [Figure 10] FIG. 10 is a diagram illustrating a configuration example of a semiconductor device. [Figure 11] FIG. 11 is a diagram illustrating a configuration example of a semiconductor device. [Figure 12] 12A and 12B are diagrams showing configuration examples of a semiconductor device. [Figure 13] 13A and 13B are diagrams showing configuration examples of a semiconductor device. [Figure 14] FIG. 14 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 15] 15A to 15C are cross-sectional views showing examples of the structure of a transistor. [Figure 16] FIG. 16 is a schematic cross-sectional view showing a configuration example of a semiconductor device. [Figure 17] 17A and 17B are cross-sectional views showing examples of the structure of a transistor. [Figure 18] FIG. 18 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 19] FIG. 19 is a schematic cross-sectional view showing a configuration example of a transistor. [Figure 20] 20A and 20B are cross-sectional views showing examples of the structure of a transistor. [Figure 21] FIG. 21A is a diagram illustrating the classification of IGZO crystal structures, FIG. 21B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 21C is a diagram illustrating the electron microbeam diffraction pattern of crystalline IGZO. [Figure 22] Fig. 22A is a perspective view showing an example of a semiconductor wafer, Fig. 22B is a perspective view showing an example of a chip, Fig. 22C and Fig. 22D are perspective views showing an example of an electronic component. [Figure 23] 23A to 23J are diagrams illustrating an example of an electronic device. [Figure 24] 24A to 24E are diagrams illustrating an example of an electronic device. [Figure 25] 25A to 25C are diagrams illustrating an example of an electronic device. [Figure 26]26A to 26D are diagrams illustrating the measurement data. [Figure 27] 27A and 27B are graphs showing configuration examples of semiconductor devices. [Figure 28] FIG. 28 is a graph showing an example of the configuration of a semiconductor device. DETAILED DESCRIPTION OF THE INVENTION

[0021] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0022] In this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be referred to as "second" in another embodiment or in the claims. For example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0023] In the drawings, the same elements or elements having similar functions, elements made of the same material, or elements formed at the same time may be given the same reference numerals, and repeated explanations thereof may be omitted.

[0024] In this specification and the like, the term "metal oxide" refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as "oxide semiconductors" or simply as "OSs"). For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. That is, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, when the term "OS FET" or "OS transistor" is used, it can be rephrased as a transistor having a metal oxide or an oxide semiconductor.

[0025] (Embodiment 1) In this embodiment, a semiconductor device of one embodiment of the present invention and a driving method thereof will be described.

[0026] One aspect of the present invention relates to a semiconductor device having memory cells. A semiconductor device having memory cells can be called a memory device. The memory cells have a function of retaining data. Specifically, the memory cells have a capacitor (capacitance). The capacitor has a configuration having a ferroelectric layer between a first electrode and a second electrode. A capacitor having a ferroelectric layer is sometimes called a ferroelectric capacitor (ferroelectric capacitance).

[0027] When a voltage (electric or electric field) is applied between the electrodes of a ferroelectric capacitor, the direction and amount of polarization of the ferroelectric layer changes depending on the direction and amount of the applied voltage. A memory cell equipped with a ferroelectric capacitor stores (writes) signals (data) by utilizing the change in the polarization state of the ferroelectric layer. In a ferroelectric capacitor, polarization remains in the ferroelectric layer (residual polarization) even when the voltage between the electrodes is reduced to zero. To rewrite the polarization, a voltage (polarization reversal voltage) is applied to reverse the polarization (polarization reversal).

[0028] When reading data from a memory cell, if a voltage exceeding the polarization inversion voltage is applied to a ferroelectric capacitor, the polarization state of the ferroelectric layer (the polarization direction of the remanent polarization) changes, and an operation to restore the polarization state is required. In other words, when a voltage exceeding the polarization inversion voltage is applied to a ferroelectric capacitor to read data from the ferroelectric capacitor, data refresh is required. In other words, when a voltage exceeding the polarization inversion voltage is applied to a ferroelectric capacitor to read data, the operation of reading data from a memory cell is a destructive read.

[0029] One aspect of the present invention provides a method for driving a semiconductor device that can read data from a memory cell having a ferroelectric capacitor without performing destructive reading.

[0030] Specifically, during a read operation of a memory cell having a ferroelectric capacitor, the read operation is performed by gradually increasing the voltage on the opposite electrode of the ferroelectric capacitor so as not to destroy the polarization of the ferroelectric capacitor. The data read operation from the memory cell is performed by applying a voltage to the ferroelectric capacitor that does not cause polarization reversal of the ferroelectric layer. The next data read operation from the memory cell is performed using a driving method in which a voltage that does not cause polarization reversal of the ferroelectric layer is applied to the ferroelectric capacitor that is higher than the voltage applied in the previous read operation.

[0031] In one aspect of the present invention, a voltage not exceeding the polarization inversion voltage is applied to the ferroelectric capacitor during a data read operation, thereby maintaining the polarization direction of the remanent polarization of the ferroelectric layer before and after data read. Therefore, the semiconductor device of one aspect of the present invention can retain data for a long period of time. This reduces the frequency of refresh (rewriting data to a memory cell), thereby reducing the power consumption of the semiconductor device of one aspect of the present invention. Furthermore, a ferroelectric capacitor having a ferroelectric layer between electrodes can retain data for a long period of time without employing a structure for increasing capacitance, such as a trench structure. This allows for a semiconductor device with an easy-to-manufacture structure.

[0032] 1A is a circuit diagram of a memory cell MC having a ferroelectric capacitor. The memory cell MC is also called a cell. The memory cell MC has a transistor M1 and a ferroelectric capacitor C1.

[0033] The ferroelectric capacitor C1 is illustrated schematically as a capacitor having a ferroelectric layer FE between electrodes UE and LE. For example, a read operation of the memory cell MC involves setting the wiring BL (also called a bit line) connected to the transistor M1 at a predetermined potential and electrically floating, and then controlling the wiring WL (also called a word line) to turn on the transistor M1, thereby changing the voltage of the wiring PL (also called a plate line) on the electrode UE side. This changes the potential of the wiring BL due to capacitive coupling of the ferroelectric capacitor. This change in the potential of the wiring BL depends on the polarization state of the ferroelectric layer in the ferroelectric capacitor, so a potential corresponding to the written data can be read out to the wiring BL.

[0034] FIG. 1B is a graph showing the magnitude of polarization (amount of polarization) depending on the electric field applied to the ferroelectric layer FE. In FIG. 1B, the change in polarization with respect to the electric field of the ferroelectric layer FE is shown as a straight line for ease of understanding, but the actual measured data is expressed as a curve. In FIG. 1B, the horizontal axis represents the electric field E applied to the ferroelectric layer, and the vertical axis represents the polarization P of the ferroelectric layer. The difference between the positive and negative polarizations when the electric field is 0 is expressed as 2P R is illustrated as

[0035] As the electric field applied to the ferroelectric layer FE increases, the polarization of the ferroelectric layer increases. H After applying an electric field E to the ferroelectric layer, if the electric field applied to the ferroelectric layer is reduced, the positive charges will be biased to one electrode side of the capacitance and the negative charges will be biased to the other electrode side of the capacitance, so that when the electric field becomes 0, the positive polarization will remain. If the electric field applied to the ferroelectric layer FE is reduced, the polarization of the ferroelectric layer will become smaller. If the electric field E L After applying an electric field E to the ferroelectric layer, if the electric field applied to the ferroelectric layer is increased, the positive charges will be biased to the other electrode side of the capacitance C1 and the negative charges will be biased to one electrode side of the capacitance, so that when the electric field becomes 0, a negative polarization will remain. H and electric field E L The voltage for applying this polarity inversion voltage can be called a polarization inversion voltage. By applying the polarization inversion voltage to the ferroelectric capacitor C1, data can be written to the memory cell MC.

[0036] When reading data from a memory cell MC, if a voltage exceeding the polarization inversion voltage is applied to the capacitor C1, the polarization state (polarization direction of the remanent polarization) of the ferroelectric layer FE changes, and an operation to restore the polarization state is required. In other words, when reading data from a memory cell MC by applying a voltage exceeding the polarization inversion voltage to the capacitor C1, the data needs to be refreshed.

[0037] In one aspect of the present invention, when data is read from a memory cell MC, a voltage not exceeding the polarization inversion voltage is applied to the ferroelectric capacitor C1, and the ferroelectric capacitor C1 is operated so as to maintain the polarization direction of the remanent polarization of the ferroelectric layer FE. Specifically, when data is read from the memory cell MC, the electric field is increased stepwise so as to maintain the polarization direction of the remanent polarization of the ferroelectric layer FE. Specifically, the electric field E shown in FIG. H Electric fields E1 to E4 not exceeding 100 V are sequentially applied for each read operation. The voltages for applying the electric fields E1 to E4 to the ferroelectric layer FE can be said to be voltages that do not cause polarization inversion. In one embodiment of the present invention, data can be read from the memory cell MC without performing so-called destructive read.

[0038] When the polarization direction of the remanent polarization of the ferroelectric layer FE is reversed by repeated read operations from the ferroelectric capacitor, it is preferable to perform a data refresh operation, which is an operation of writing data again.

[0039] In the read operation of one embodiment of the present invention described above, it is preferable that the magnitude of polarization (amount of polarization) varies when different electric fields are applied in the graph shown in FIG. 1B, which shows the magnitude of polarization (amount of polarization) depending on the electric field to the ferroelectric layer FE. In addition, in the read operation of one embodiment of the present invention, it is preferable that the magnitude of polarization varies when different electric fields are applied in the graph shown in FIG. 1B, which shows the magnitude of polarization (amount of polarization) depending on the electric field to the ferroelectric layer FE, which shows the magnitude of polarization when different electric fields are applied, so that data can be read out. For example, as shown in FIG. 2A, in the shape of the graph showing the magnitude of polarization (amount of polarization) depending on the electric field to the ferroelectric layer FE, the degree of change T of polarization with respect to the change in electric field is VS In order to make the degree of change in polarization with respect to the change in the electric field a positive slope, it is preferable that the voltage for reading data from the memory cell MC during a read operation be greater than the voltage that sets the polarization of the ferroelectric layer FE to zero.

[0040] In addition, it is preferable that the change in polarization with respect to the change in electric field is not large. By adopting this configuration, it is possible to reduce the degree of change in the remanent polarization for each read operation when the polarization direction of the ferroelectric layer FE is not completely reversed but is partially reversed.

[0041] In actuality, the electric field and polarization in the ferroelectric layer change in a curved manner as shown in FIG. 2B. VS The slope can be expressed as the slope of the tangent line. This is also valid for the graph shape shown in Figure 2C.

[0042] On the other hand, in the read operation of one embodiment of the present invention described above, it is not preferable if the degree of change (slope) of polarization with respect to the change in electric field is positive, and the change in polarization with respect to the change in electric field is large and steep, as shown in the graph shape of Figure 3A. In this case, the degree of change in polarization with respect to the change in electric field becomes large, making it difficult to operate to partially reverse the polarization direction of the remanent polarization of the ferroelectric layer FE. As shown in Figure 3B, the same can be said for the shape of the graph as in Figure 3A.

[0043] Ferroelectric materials that can be used for the ferroelectric layer FE include hafnium oxide, zirconium oxide, and cerium oxide. Ferroelectric materials include hafnium oxide to which an element J1 (here, element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added, and zirconium oxide to which element J2 (here, element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) is added. For example, hafnium zirconium oxide (HfZrO) is added with zirconium. X :X is a real number greater than 0) is preferred.

[0044] Furthermore, as a material that can have ferroelectricity, piezoelectric ceramics having a perovskite structure, such as lead titanate, barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may be used. Furthermore, as a material that can have ferroelectricity, for example, a plurality of materials selected from the materials listed above, or a laminate structure consisting of a plurality of materials selected from the materials listed above, may be used. Incidentally, hafnium oxide, zirconium oxide, HfZrO X and materials in which the element J1 is added to hafnium oxide, the crystal structure (characteristics) of which may change not only depending on the film formation conditions but also on various processes, etc., and therefore in this specification and the like, materials that exhibit ferroelectricity are not only called ferroelectrics, but are also called materials that can have ferroelectricity or materials that can be made to have ferroelectricity.

[0045] Furthermore, materials that can have ferroelectricity include aluminum scandium nitride (Al 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value close to 1.) Examples of materials that can exhibit ferroelectricity include metal nitrides containing elements M1, M2, and nitrogen. Here, element M1 is one or more elements selected from aluminum (Al), gallium (Ga), indium (In), etc., and element M2 is one or more elements selected from boron (B), scandium (Sc), yttrium (Y), lanthanum (La), cerium (Ce), neodymium (Nd), europium (Eu), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set appropriately. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectricity even without element M2. Ferroelectric materials include the above-mentioned metal nitrides to which element M3 is added. Element M3 is one or more elements selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. The ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be appropriately set. Because the above-mentioned metal nitrides contain at least a Group 13 element and nitrogen, a Group 15 element, these metal nitrides are sometimes referred to as Group 13-Group 15 ferroelectrics or Group 13 nitride ferroelectrics.

[0046] Among these, HfZrO is used as a material for the ferroelectric layer. X is preferable because it can retain ferroelectricity even when processed into a thin film of a few nm. Here, the film thickness of the ferroelectric layer can be 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less (typically 2 nm to 9 nm). By using a ferroelectric layer that can be thinned, it can be made into a semiconductor device combined with a miniaturized transistor.

[0047] In addition, HfZrO is a material that can have ferroelectric properties. X When using a ferroelectric material, it is preferable to form the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when using thermal ALD to form a film of a material that can have ferroelectricity, it is preferable to use a material that does not contain hydrocarbons (also called hydrocarbon, HC) as a precursor. If the material that can have ferroelectricity contains either or both of hydrogen and carbon, this may inhibit the crystallization of the material that can have ferroelectricity. Therefore, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the material that can have ferroelectricity. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Furthermore, as a material that can have ferroelectricity, a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0048] When a film is formed using a material that can have ferroelectricity, impurities in the film, in this case at least one of hydrogen, hydrocarbon, and carbon, are thoroughly removed, thereby forming a film having high-purity intrinsic ferroelectricity. The film having high-purity intrinsic ferroelectricity and the high-purity intrinsic oxide semiconductor shown in the embodiment described later have very high compatibility in manufacturing processes. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0049] In addition, HfZrO is a material that can have ferroelectric properties. X When using hafnium oxide and zirconium oxide, it is preferable to use a thermal ALD method to alternately form films of hafnium oxide and zirconium oxide in a 1:1 ratio.

[0050] Furthermore, when a film of a material that may have ferroelectricity is formed using a thermal ALD method, the oxidizing agent may be H2O or O3. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0051] Furthermore, the crystal structure of the material capable of exhibiting ferroelectricity is not particularly limited. For example, the crystal structure of the material capable of exhibiting ferroelectricity may be one or more selected from the group consisting of cubic, tetragonal, orthorhombic, and monoclinic. In particular, the material capable of exhibiting ferroelectricity preferably has an orthorhombic crystal structure, since ferroelectricity is exhibited. Alternatively, the material capable of exhibiting ferroelectricity may have a composite structure having an amorphous structure and a crystalline structure.

[0052] <Configuration example of semiconductor device> 4 is a block diagram showing a configuration example of a semiconductor device 10 which is a semiconductor device of one embodiment of the present invention. The semiconductor device 10 can be, for example, a memory device.

[0053] The semiconductor device 10 is provided with a memory cell array MCA in which memory cells MC are arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 1). The semiconductor device 10 also has a word line drive circuit WD, a plate line drive circuit PD, a potential generation circuit SD, and a bit line drive circuit BD.

[0054] The word line driving circuit WD is electrically connected to the memory cells MC via wiring WL, and is also electrically connected to the memory cells MC via wiring RWL. The plate line driving circuit PD is electrically connected to the memory cells MC via wiring PL. The bit line driving circuit BD is electrically connected to the memory cells MC via wiring BL.

[0055] Here, memory cells MC in the same row can be electrically connected to the word line driving circuit WD via the same wiring WL, and can be electrically connected to the plate line driving circuit PD via the same wiring PL. Also, memory cells MC in the same column can be electrically connected to the bit line driving circuit BD via the same wiring BL.

[0056] In this specification etc., for example, the memory cell MC at the first row and first column is described and shown as memory cell MC[1,1], and the memory cell MC at the m-th row and n-th column is described and shown as memory cell MC[m,n]. Also, for example, the wirings WL and PL electrically connected to the memory cells MC in the first row are described and shown as wiring WL[1] and wiring PL[1] respectively, and the wirings WL and PL electrically connected to the memory cells MC in the m-th row are described and shown as wiring WL[m] and wiring PL[m] respectively. Further, for example, the wiring BL electrically connected to the memory cells MC in the first column is described and shown as wiring BL[1], and the wiring BL electrically connected to the memory cells MC in the n-th column is described and shown as wiring BL[n]. Note that the same description may be made for other elements.

[0057] The word line driving circuit WD has a function of controlling the potential of the wiring WL. Specifically, the word line driving circuit WD has a function of selecting the memory cell MC for writing data by controlling the potential of the wiring WL.

[0058] The plate line driving circuit PD has a function of controlling the potential of the wiring PL.

[0059] The bit line driving circuit BD has a function of generating data to be written into the memory cell MC and supplying it to the memory cells MC in a predetermined column. Also, the bit line driving circuit BD has a function of reading out and outputting the data written into the memory cell MC.

[0060] The bit line driver circuit BD will be described in detail. The bit line driver circuit BD includes sense amplifier circuits SA[1] to SA[n]. The sense amplifier circuits SA are electrically connected to the wirings BL, REF, EL, and PRE. The sense amplifier circuits SA[1] to SA[n] are also electrically connected to the wirings OUT[1] to OUT[n].

[0061] The sense amplifier circuit SA has the function of amplifying the difference between the potential of the wiring BL and the potential of the wiring REF. For example, when the potential of the wiring BL is higher than the potential of the wiring REF, the sense amplifier circuit SA can output a high potential. On the other hand, when the potential of the wiring BL is lower than the potential of the wiring REF, the sense amplifier circuit SA can output a low potential. This allows the bit line driver circuit BD to write binary data, specifically binary digital data, to the memory cell MC and to read the binary data written to the memory cell MC. For example, when the potential of the wiring BL is higher than the potential of the wiring REF, it can be assumed that a "0" is written to the memory cell MC or a "0" is read from the memory cell MC. On the other hand, when the potential of the wiring BL is lower than the potential of the wiring REF, it can be assumed that a "1" is written to the memory cell MC or a "1" is read from the memory cell MC.

[0062] An enable signal that controls whether the sense amplifier circuit SA is activated can be supplied to the wiring EL. The enable signal can be, for example, a binary digital signal. For example, when the potential of the wiring EL is high, the sense amplifier circuit SA can be activated, and the difference between the potential of the wiring BL and the potential of the wiring REF is amplified. On the other hand, when the potential of the wiring EL is low, the sense amplifier circuit SA can be deactivated, and the above amplification is not performed.

[0063] A precharge signal that controls whether the potentials of the wiring BL and the wiring REF are precharged can be supplied to the wiring PRE. The precharge signal can be, for example, a binary digital signal. For example, when the potential of the wiring PRE is high, the wiring BL can be precharged to a high potential. Furthermore, the potential of the wiring REF can be set to a potential between the potential of the wiring BL when data with a value of "0" is read from the memory cell MC and the potential of the wiring BL when data with a value of "1" is read from the memory cell MC.

[0064] Note that the potential supplied to the wirings EL[1] to EL[n] may be common to each other. In this case, the wirings EL[1] to EL[n] may be electrically connected to each other. Furthermore, the potential supplied to the wirings PRE[1] to PRE[n] may be common to each other. In this case, the wirings PRE[1] to PRE[n] may be electrically connected to each other.

[0065] Data output from the sense amplifier circuit SA is output from the wiring OUT. Data from the sense amplifier circuit SA[1] can be output from the wiring OUT[1]. Data from the sense amplifier circuit SA[n] can be output from the wiring OUT[n].

[0066] <Memory cell configuration example 1> FIG. 5A shows a circuit diagram of a memory cell applicable to the memory cell MC1 of FIG. 4. The memory cell MC1 has a transistor M1 and a ferroelectric capacitor C1. In the memory cell MC1, each element of the transistor M1 and the ferroelectric capacitor C1 is connected to a wiring BL, a wiring PL, and / or a wiring WL as shown in FIG. 5A. In FIG. 5A, the wiring electrically connecting the transistor M1 and the ferroelectric capacitor C1 is shown as a node N1.

[0067] FIG. 5B is a diagram illustrating the electrical connection between each component of the memory cell MC1, such as the transistor M1 and ferroelectric capacitor C1, and the sense amplifier circuit SA. The sense amplifier circuit SA is connected to the wiring BL, the wiring REF, and the wiring OUT as shown in FIG. 5B. The sense amplifier circuit SA amplifies the difference between the potential of the wiring BL and the potential of the wiring REF. The potential or voltage of the wiring REF is also referred to as the reference potential or reference voltage. The wiring BL and the wiring REF are provided with loads CBL and CREF, which are parasitic capacitances, respectively. The loads CBL and CREF are provided as equivalent loads. The configuration shown in FIG. 5B is the same as that described in FIG. 5A.

[0068] Data is written to the memory cell MC1 by applying a voltage to the ferroelectric capacitor C1. By controlling the signals supplied to the wiring WL and the wiring BL so as to apply an H level potential to the node N1 and an L level potential to the wiring PL, the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "1." By applying an L level potential to the node N1 and an H level potential to the wiring PL, the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "0." The voltages applied to the node N1 and the wiring PL can be set to 0V for the L level and 2.5V or 3.3V for the H level.

[0069] 6 and 7 show timing charts for the case where a read operation according to one embodiment of the present invention is applied to the memory cell MC1 shown in Fig. 5A and Fig. 5B. Fig. 6 is a timing chart for the data read operation when the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "0", and Fig. 7 is a timing chart for the data read operation when the ferroelectric substance in the ferroelectric capacitor C1 is polarized to the state "1".

[0070] 6 and 7, at time T0, the line WL is set to H level, turning on the transistor M1. At time T1, the line PL is set to voltage Va, and the voltage of the line BL is boosted by capacitive coupling via the ferroelectric capacitor C1. At this time, the reference voltage of the line REF is set to voltage Va' corresponding to voltage Va. Here, in FIG. 6, the ferroelectric capacitor C1 is polarized to state "0," so the voltage of the line BL after boosting is smaller than the voltage of the line REF. On the other hand, in FIG. 7, the ferroelectric capacitor C1 is polarized to state "1," so the voltage of the line BL after boosting is larger than the voltage of the line REF.

[0071] At time T2, the line EL is set to H level. An enable signal for the sense amplifier circuit SA is given to the line EL, and setting this enable signal to H level activates the sense amplifier circuit SA. By setting the line EL to H level, the sense amplifier circuit SA amplifies the potential difference between the line REF and the line BL. A signal corresponding to this potential difference is output to the line OUT.

[0072] Compared to destructive reads of data from the ferroelectric capacitor C1, the voltage required to read data in one embodiment of the present invention does not exceed the polarization inversion voltage. Therefore, the polarization direction of the ferroelectric layer is maintained before and after the read operation. This eliminates the need to apply a high voltage to write back data.

[0073] At time T3, the lines PL and EL are set to the L level, the sense amplifier circuit SA is deactivated, and at time T4, the line WL is set to the L level, turning off the transistor M1 and completing the read operation.

[0074] Subsequently, a second read operation is performed after time T5.

[0075] At time T5, the line WL is set to H level, turning on the transistor M1. At time T6, the line PL is set to voltage Vb (> voltage Va), and the voltage of the line BL is boosted by capacitive coupling via the ferroelectric capacitor C1. At this time, the reference voltage of the line REF is set to voltage Vb' (> voltage Va') corresponding to voltage Vb. Here, in FIG. 7, the ferroelectric capacitor C1 is polarized to state "0," so the voltage of the line BL after boosting is smaller than the voltage of the line REF. On the other hand, in FIG. 7, the ferroelectric capacitor C1 is polarized to state "1," so the voltage of the line BL after boosting is larger than the voltage of the line REF.

[0076] At time T7, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines REF and BL. A signal corresponding to this potential difference is output to the line OUT.

[0077] At time T8, the lines PL and EL are set to L level, and the sense amplifier circuit SA is deactivated. At time T9, the line WL is set to L level, turning off the transistor M1 and completing the read operation.

[0078] Subsequently, a third read operation is performed after time T10.

[0079] At time T10, the line WL is set to H level, turning on the transistor M1. At time T11, the line PL is set to voltage Vc (> voltage Vb), and the voltage of the line BL is boosted by capacitive coupling via the ferroelectric capacitor C1. At this time, the reference voltage of the line REF is set to voltage Vc' (> voltage Vb') corresponding to voltage Vc. Here, in FIG. 7, the ferroelectric capacitor C1 is polarized to state "0," so the voltage of the line BL after boosting is smaller than the voltage of the line REF. On the other hand, in FIG. 7, the ferroelectric capacitor C1 is polarized to state "1," so the voltage of the line BL after boosting is larger than the voltage of the line REF.

[0080] At time T12, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines REF and BL. A signal corresponding to this potential difference is output to the line OUT.

[0081] At time T13, the lines PL and EL are set to L level, and the sense amplifier circuit SA is deactivated. At time T14, the line WL is set to L level, turning off the transistor M1 and completing the read operation.

[0082] As described above, by gradually increasing the drive voltage of the line PL and the reference voltage of the line REF each time a read operation is performed, multiple read operations can be realized without performing a write-back operation to the ferroelectric capacitor C1.

[0083] It is preferable to perform a data refresh operation when the voltage of the wiring PL is increased by a certain voltage or more (for example, 3.3 V). In this case, a high voltage is applied to the ferroelectric capacitor C1 to perform the data refresh operation.

[0084] It is effective to use a transistor having an oxide semiconductor in the channel formation region (OS transistor) as the transistor M1 in FIGS. 5A and 5B. Because OS transistors have excellent breakdown voltage, their use in combination with a ferroelectric capacitor with a high drive voltage allows for miniaturization of each element in a memory cell. Furthermore, OS transistors feature extremely low off-state current, enabling them to maintain the voltage at node N1 for a long period of time. Although there is concern that the voltage at node N1 may drop due to leakage current through the ferroelectric capacitor C1, this leakage current can be suppressed if the electric field applied to the ferroelectric capacitor C1 is small.

[0085] 1A, it is possible to read data using the charge stored in node N1. Specifically, the charge stored in node N1 can be distributed to wiring BL, and the change in potential can be amplified by a sense amplifier to read data. Furthermore, if the charge stored in node N1 disappears, wiring PL can be set to 3.0 V or higher to replenish the charge in node N1 via ferroelectric capacitor C1.

[0086] <Memory cell configuration example 2> FIG. 8 shows an example of a configuration different from that shown in FIG. 5B. FIG. 8 illustrates the electrical connections between a memory cell MC1, a memory cell MC1B storing inverted data of data written to the memory cell MC1, and a sense amplifier circuit SA. FIG. 8 illustrates the transistor M1B, ferroelectric capacitor C1B, and node N1B of the memory cell MC1B, which is paired with the memory cell MC1. The memory cell MC1B is also referred to as a reference memory cell. Hereinafter, the method of reading data from a memory cell storing paired data is referred to as a twin-cell type. FIG. 6 also illustrates the wiring BLB to which the memory cell MC1B is connected. The sense amplifier circuit SA amplifies the difference between the potentials of the wirings BL and BLB. The wirings BL and BLB are provided with parasitic capacitance loads CBL and CBLB, respectively. The loads CBL and CBLB are provided as equivalent loads.

[0087] 9 and 10 show timing charts for the case where a read operation according to one aspect of the present invention is applied to the memory cells MC1 and MC1B shown in Fig. 8. Fig. 9 is a timing chart for the data read operation when the ferroelectric in the ferroelectric capacitor C1 is polarized to the state "0", and Fig. 10 is a timing chart for the case where the ferroelectric in the ferroelectric capacitor C1 is polarized to the state "1". Note that the ferroelectric in the ferroelectric capacitor C1B is polarized to a state different from that of the ferroelectric capacitor C1.

[0088] The circuit configuration in FIG. 8 is of a twin cell type, and therefore does not have the line REF shown in FIG. 5B. Therefore, there is no need to change the reference voltage of line REF to match the voltage of line PL. During a data read operation, the precharge of lines BL and BLB can be set to, for example, an L-level potential. Because the circuit configuration in FIG. 8 is of a twin cell type, inverted data is written to memory cells MC1 and MC1B.

[0089] 9 and 10, at time T0, the line WL is set to H level, turning on the transistor M1 and the transistor M1B. At time T1, the line PL is set to voltage Va, and the voltages of the lines BL and BLB are boosted by capacitive coupling via the ferroelectric capacitors C1 and C1B. In FIG. 9, the ferroelectric capacitor C1 is polarized to state "0" (the ferroelectric capacitor C1B is polarized to state "1"), so the voltage of the line BL after boosting is smaller than the voltage of the line BLB. On the other hand, in FIG. 10, the ferroelectric capacitor C1 is polarized to state "1" (the ferroelectric capacitor C1B is polarized to state "0"), so the voltage of the line BL after boosting is larger than the voltage of the line BLB.

[0090] At time T2, the line EL is set to H level. The line EL is an enable signal for the sense amplifier circuit SA, and when it goes to H level, the sense amplifier circuit SA is activated. When the line EL goes to H level, the potential difference between the lines BLB and BL is amplified. A signal corresponding to this potential difference is output to the line OUT.

[0091] Compared to destructive reads of data from the ferroelectric capacitor C1, the voltage required to read data in one embodiment of the present invention does not exceed the polarization inversion voltage. Therefore, the polarization direction of the ferroelectric layer is maintained before and after the read operation. This eliminates the need to apply a high voltage to write back data.

[0092] At time T3, the lines PL and EL go to L level, deactivating the sense amplifier circuit SA. At time T4, the line WL goes to L level, turning off the transistors M1 and M1B and completing the read operation.

[0093] Subsequently, a second read operation is performed after time T5.

[0094] At time T5, the line WL is set to the H level, turning on the transistors M1 and M1B. At time T6, the line PL is set to voltage Vb (>voltage Va), and the voltages of the lines BL and BLB are boosted by capacitive coupling via the ferroelectric capacitors C1 and C1B. In FIG. 9, the ferroelectric capacitor C1 is polarized to state "0" (the ferroelectric capacitor C1B is polarized to state "1"), so the voltage of the line BL after boosting is smaller than the voltage of the line BLB. On the other hand, in FIG. 10, the ferroelectric capacitor C1 is polarized to state "1" (the ferroelectric capacitor C1B is polarized to state "0"), so the voltage of the line BL after boosting is larger than the voltage of the line BLB.

[0095] At time T7, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines BLB and BL. A signal corresponding to this potential difference is output to the line OUT.

[0096] At time T8, the lines PL and EL are set to L level, deactivating the sense amplifier circuit SA. At time T9, the line WL is set to L level, turning off the transistors M1 and M1B, and the read operation ends.

[0097] Subsequently, a third read operation is performed after time T10.

[0098] At time T11, the line WL is set to the H level, turning on the transistor M1 and the transistor M1B. At time T12, the line PL is set to voltage Vc (>voltage Vb), and the voltages of the lines BL and BLB are boosted by capacitive coupling via the ferroelectric capacitors C1 and C1B. In FIG. 9, the ferroelectric capacitor C1 is polarized to state "0" (the ferroelectric capacitor C1B is polarized to state "1"), so the voltage of the line BL after boosting is smaller than the voltage of the line BLB. On the other hand, in FIG. 10, the ferroelectric capacitor C1 is polarized to state "1" (the ferroelectric capacitor C1B is polarized to state "0"), so the voltage of the line BL after boosting is larger than the voltage of the line BLB.

[0099] At time T12, the line EL is set to H level, activating the sense amplifier circuit SA. When the line EL becomes H level, the sense amplifier circuit SA amplifies the potential difference between the lines BLB and BL. A signal corresponding to this potential difference is output to the line OUT.

[0100] At time T13, the lines PL and EL are set to L level, deactivating the sense amplifier circuit SA. At time T14, the line WL is set to L level, turning off the transistors M1 and M1B, and the read operation ends.

[0101] As described above, by increasing the drive voltage of the wiring PL stepwise every time a read operation is performed, multiple read operations can be realized without performing a write-back operation to the ferroelectric capacitor C1.

[0102] It is preferable to perform a data refresh operation when the voltage of the wiring PL is increased by a certain voltage or more (for example, 3.3 V). In this case, a high voltage is applied to the ferroelectric capacitor C1 and the ferroelectric capacitor C1B to perform the data refresh operation.

[0103] Note that similarly to the transistor M1 in FIGS. 5A and 5B, it is effective to use a transistor including an oxide semiconductor in a channel formation region (OS transistor) for the transistors M1 and M1B in FIG.

[0104] <Memory cell configuration example 3> FIG. 11 shows a circuit diagram of a memory cell different from the memory cell MC1 described above. The memory cell MC2 in FIG. 11 has transistors M1, M2, M3, and a ferroelectric capacitor C1. In the memory cell MC2, the transistors M1 to M3 and the ferroelectric capacitor C1 are connected to a wiring WBL (also referred to as a write bit line), a wiring RBL (also referred to as a read bit line), a wiring PL, a wiring SL (also referred to as a source line), a wiring WWL (also referred to as a write word line), and / or a wiring RWL (also referred to as a read word line) as shown in FIG. 11. In FIG. 11, the wiring electrically connecting the transistor M1, the transistor M2, and the ferroelectric capacitor C1 is shown as a node SN.

[0105] 11, by changing the voltage of the wiring PL, the potential of the node SN changes due to the capacitive coupling of the ferroelectric capacitor C1. At this time, a difference in the potential of the node SN occurs depending on the difference in polarization of the ferroelectric layer of the ferroelectric capacitor C1, and this difference can be amplified and read out by the transistor M2.

[0106] By configuring the wiring functioning as a bit line to be separated into wiring WBL and wiring RBL, a high voltage (e.g., 3.3 V) can be applied to wiring WBL, and data can be read out from wiring RBL at a low voltage (e.g., 1.2 V or less).

[0107] 11, when the read operation is performed multiple times, it is effective to increase the voltage of the wiring PL in stages. When the voltage of the wiring PL is increased in stages, the voltage of the node SN increases each time the read operation is performed. Therefore, the read circuit connected to the wiring RBL has a function of adjusting the range of the read voltage depending on the number of reads.

[0108] By driving in this way, during normal read operations, only the wiring RBL that can operate at a low voltage is activated, and the wiring WBL that requires a high voltage is deactivated, thereby reducing power consumption.

[0109] 11, it is effective to use transistors having an oxide semiconductor in the channel formation region (OS transistors). OS transistors have an extremely small off-state current, which allows them to maintain the voltage of node SN for a long time. Although there is a concern that the voltage of node SN may drop due to leakage current through ferroelectric capacitor C1, this leakage current can be suppressed when the electric field applied to ferroelectric capacitor C1 is small.

[0110] 1A, it is also possible to read data by utilizing the charge stored in node SN. Specifically, data can be read by utilizing the fact that the amount of current flowing through transistor M2 is determined according to the potential corresponding to the charge stored in node SN. Furthermore, if the charge stored in node SN disappears, the line PL can be set to 3.0 V or higher to replenish the charge in node SN via ferroelectric capacitor C1.

[0111] <Modification of memory cell> 12A is a circuit diagram showing a modification of the memory cell MC1 described above. The memory cell MC1_A shown in FIG. 12A has a back gate voltage V BG12A shows a configuration having a back gate electrode to which a voltage is applied. The configuration of FIG. 12A can increase the amount of current flowing through each transistor.

[0112] 12B is a circuit diagram showing a modification of the memory cell MC2 described above. The memory cell MC2_A shown in FIG. 12B has a back gate voltage V BG 12B shows a configuration having a back gate electrode to which a voltage is applied. By using the configuration of FIG. 12B, the amount of current flowing through each transistor can be increased. Note that the back gate voltage applied to the back gate of each transistor may be the same voltage or different voltages.

[0113] Fig. 13A is a circuit diagram showing a modified example of the memory cell MC2 described above. The memory cell MC2_B shown in Fig. 13A shows a configuration in which the wiring WBL and the wiring RBL in the memory cell MC2 of Fig. 11 are replaced by a common wiring BL. The configuration of Fig. 13A makes it possible to reduce the number of wirings connected to the memory cell.

[0114] 13B is a circuit diagram showing a modification of the memory cell MC2 described above. The memory cell MC2_C shown in FIG. 13B is a circuit diagram in which the transistor M3 in the memory cell MC2 of FIG. 11 is omitted, and the wiring RWL is connected to the back gate of the transistor M2. The selection signal applied to the wiring RWL controls the threshold voltage of the transistor M2, thereby controlling whether or not a current flows between the wiring RWL and the wiring SL. The configuration of FIG. 13B allows the number of transistors in the memory cell to be reduced.

[0115] As described above, in one aspect of the present invention, in the operation of applying an electric field for reading data, the polarization direction of the remanent polarization of the ferroelectric layer FE is not completely reversed, but is instead partially reversed. Since the balance of the polarization direction of the remanent polarization of the ferroelectric layer FE is lost through the read operation, the read operation is performed by gradually increasing the voltage on the opposite electrode side of the ferroelectric capacitor so as not to destroy the polarization of the ferroelectric capacitor. With this configuration, data can be read even if the remanent polarization of the ferroelectric layer FE is reduced by repeated read operations.

[0116] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like.

[0117] (Embodiment 2) In this embodiment, a structural example of a transistor applicable to the semiconductor device described in the above embodiment will be described. As an example, a structure in which transistors having different electrical characteristics are stacked will be described. By using this structure, the degree of freedom in designing a semiconductor device can be increased. In addition, by stacking transistors having different electrical characteristics, the degree of integration of a semiconductor device can be increased.

[0118] <Configuration example of semiconductor device> 14 illustrates, as an example, the semiconductor device described in the above embodiment, which includes a transistor 300, a transistor 500, and a capacitor 600. Fig. 15A illustrates a cross-sectional view of the transistor 500 in the channel length direction, Fig. 15B illustrates a cross-sectional view of the transistor 500 in the channel width direction, and Fig. 15C illustrates a cross-sectional view of the transistor 300 in the channel width direction.

[0119] The transistor 500 is a transistor (OS transistor) having a metal oxide in a channel formation region. The transistor 500 has characteristics of a small off-state current and a field-effect mobility that does not change easily even at high temperatures. By applying the transistor 500 to a semiconductor device, such as the OS transistor described in the above embodiment, a semiconductor device whose operating capability is not easily degraded even at high temperatures can be realized.

[0120] The transistor 500 is provided above the transistor 300, for example, and the capacitor 600 is provided above the transistor 300 and the transistor 500, for example.

[0121] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. The transistor 300 can be applied to, for example, the Si transistor described in the above embodiment. In FIG. 14, as an example, a configuration is shown in which the gate of the transistor 300 is electrically connected to one of the source and drain of the transistor 500 through a pair of electrodes of a capacitor 600.

[0122] The substrate 310 is preferably a semiconductor substrate (for example, a single crystal substrate or a silicon substrate).

[0123] 15C , the upper surface and the side surfaces in the channel width direction of the semiconductor region 313 of the transistor 300 are covered with a conductor 316 via an insulator 315. By forming the transistor 300 as a fin type in this way, the effective channel width is increased, thereby improving the on-state characteristics of the transistor 300. Furthermore, the contribution of the electric field of the gate electrode can be increased, thereby improving the off-state characteristics of the transistor 300.

[0124] The transistor 300 may be either a p-channel type or an n-channel type.

[0125] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0126] The low resistance region 314a and the low resistance region 314b contain, in addition to the semiconductor material applied to the semiconductor region 313, an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0127] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0128] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0129] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed by using, for example, a LOCOS (LOCal Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, a mesa isolation method, or the like.

[0130] The transistor 300 illustrated in FIG. 14 is just an example, and the structure is not limited thereto. An appropriate transistor may be used depending on the circuit configuration, driving method, and the like. For example, the transistor 300 may have a planar structure instead of the FIN structure illustrated in FIG. 15C. For example, when the semiconductor device is a unipolar circuit including only OS transistors, the structure of the transistor 300 may be the same as that of the transistor 500 including an oxide semiconductor, as illustrated in FIG. 16. The details of the transistor 500 will be described later. In this specification and the like, a unipolar circuit refers to a circuit including transistors of only one polarity, that is, an n-channel transistor or a p-channel transistor.

[0131] In FIG. 16, the transistor 300 is provided on a substrate 310A. However, in this case, the substrate 310A may be a semiconductor substrate similar to the substrate 310 of the semiconductor device in FIG. 14. The substrate 310A may be, for example, an SOI substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate having stainless steel foil, a tungsten substrate, a substrate having tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic. Examples of the material include polypropylene, polyester, polyvinyl fluoride, and polyvinyl chloride, as well as polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, and paper.

[0132] In the transistor 300 shown in FIG. 14, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0133] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0134] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0135] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0136] The insulator 324 is preferably a film having a barrier property that prevents hydrogen, impurities, and the like from diffusing from the substrate 310 or the transistor 300 to a region where the transistor 500 is provided.

[0137] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0138] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15atoms / cm 2 The following is fine.

[0139] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0140] Conductors 328 and 330, which connect to the capacitor 600 or the transistor 500, are embedded in the insulators 320, 322, 324, and 326. The conductors 328 and 330 function as plugs or wirings. A plurality of conductors that function as plugs or wirings may be collectively denoted by the same reference numeral. In this specification and the like, a wiring and a plug connected to the wiring may be integral. That is, a part of a conductor may function as a wiring, and a part of a conductor may function as a plug.

[0141] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0142] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 14 , the insulator 350, the insulator 352, and the insulator 354 are stacked in this order over the insulator 326 and the conductor 330. The conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0143] Note that, for example, the insulator 350 is preferably an insulator having barrier properties against impurities such as hydrogen and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The conductor 356 preferably includes a conductor having barrier properties against impurities such as hydrogen and water. In particular, a conductor having barrier properties against hydrogen is formed in the opening of the insulator 350 having barrier properties against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0144] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0145] Furthermore, on the insulator 354 and the conductor 356, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order.

[0146] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0147] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0148] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0149] An insulator 510, an insulator 512, an insulator 514, and an insulator 516 are stacked in this order over the insulator 364 and the conductor 366. Any of the insulator 510, the insulator 512, the insulator 514, and the insulator 516 is preferably made using a substance that has a barrier property against oxygen and hydrogen.

[0150] For example, the insulator 510 and the insulator 514 are preferably formed using a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 310 or the region where the transistor 300 is provided to the region where the transistor 500 is provided. Therefore, a material similar to that of the insulator 324 can be used.

[0151] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0152] As a film having a barrier property against hydrogen, for example, the insulators 510 and 514 are preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0153] In particular, aluminum oxide has a high blocking effect of preventing the permeation of both oxygen and impurities such as hydrogen and moisture, which can cause fluctuations in the electrical characteristics of a transistor. Therefore, aluminum oxide can prevent impurities such as hydrogen and moisture from entering the transistor 500 during and after the transistor manufacturing process. Furthermore, aluminum oxide can suppress the release of oxygen from the oxide that constitutes the transistor 500. Therefore, aluminum oxide is suitable for use as a protective film for the transistor 500.

[0154] For example, the insulator 512 and the insulator 516 can be formed using a material similar to that of the insulator 320. By using a material with a relatively low dielectric constant for these insulators, parasitic capacitance between wirings can be reduced. For example, the insulators 512 and 516 can be formed using a silicon oxide film, a silicon oxynitride film, or the like.

[0155] A conductor 518, a conductor constituting the transistor 500 (for example, the conductor 503 shown in FIGS. 15A and 15B), and the like are embedded in the insulators 510, 512, 514, and 516. The conductor 518 functions as a plug or a wiring connected to the capacitor 600 or the transistor 300. The conductor 518 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0156] In particular, the conductor 518 in the region in contact with the insulator 510 and the insulator 514 is preferably a conductor that has a barrier property against oxygen, hydrogen, and water. With this structure, the transistor 300 and the transistor 500 can be separated by a layer that has a barrier property against oxygen, hydrogen, and water, and diffusion of hydrogen from the transistor 300 to the transistor 500 can be suppressed.

[0157] Above the insulator 516 is the transistor 500 .

[0158] As shown in FIGS. 15A and 15B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) disposed so as to be embedded in the insulator 514 or the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 572a on the oxide 572b. The oxide 530b includes a conductor 542b on the oxide 530b, an insulator 571b on the conductor 542b, an insulator 552 on the oxide 530b, an insulator 550 on the insulator 552, an insulator 554 on the insulator 550, a conductor 560 (conductor 560a and conductor 560b) located on the insulator 554 and overlapping with part of the oxide 530b, and an insulator 544 located on the insulator 522, the insulator 524, the oxide 530a, the oxide 530b, the conductor 542a, the conductor 542b, the insulator 571a, and the insulator 571b. Note that in this specification and the like, the conductor 542a and the conductor 542b are collectively referred to as the conductor 542, and the insulators 571a and 571b are collectively referred to as the insulator 571. 15A and 15B, insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. The upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulator 554, insulator 550, insulator 552, and insulator 580. Insulator 574 contacts at least a portion of the upper surface of conductor 560, insulator 552, insulator 550, insulator 554, and insulator 580.

[0159] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0160] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0161] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0162] The conductor 560 functions as a first gate (also referred to as a top gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back gate) electrode. The insulators 552, 550, and 554 function as a first gate insulator, and the insulators 522 and 524 function as a second gate insulator. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0163] FIG. 17A shows an enlarged view of the vicinity of the channel formation region in FIG. 15A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 17A, the oxide 530b includes a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in the region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0164] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0165] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible.

[0166] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0167] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0168] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0169] 17A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0170] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0171] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0172] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0173] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0174] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0175] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0176] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0177] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0178] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O In particular, the CAAC-OS can be made to have a dense structure with higher crystallinity by heat-treating the formed metal oxide at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0179] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0180] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen in the vicinity of the oxygen vacancy is converted into a defect where hydrogen enters the oxygen vacancy (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0181] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0182] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0183] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0184] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. O H→H+V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0185] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0186] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0187] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0188] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be suppressed, thereby maintaining conductivity. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0189] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0190] 15B, in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end portions of the side surface and the top surface may be curved (hereinafter also referred to as rounded).

[0191] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0192] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0193] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0194] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0195] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0196] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0197] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0198] 15A and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly in the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0199] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0200] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0201] In this specification, a barrier insulating film refers to an insulating film having barrier properties. In this specification, the barrier properties refer to a function of suppressing the diffusion of a corresponding substance (also referred to as low permeability) or a function of capturing and fixing a corresponding substance (also referred to as gettering).

[0202] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of impurities such as water and hydrogen and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, for example, it is preferable to use aluminum oxide or magnesium oxide, which has the function of capturing and fixing hydrogen, for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 and the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 and the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0203] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO y It is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0204] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0205] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may also be used as appropriate.

[0206] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 during treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0207] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0208] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0209] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0210] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0211] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0212] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0213] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0214] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0215] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed from the oxide 530 as much as possible, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0216] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0217] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 15B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0218] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0219] By configuring the transistor 500 as a normally-off transistor and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the entire bulk can be used as a carrier path, making it a so-called bulk-flow type. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0220] 15B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0221] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0222] Insulator 522 and insulator 524 function as gate insulators.

[0223] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0224] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0225] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0226] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0227] The insulator 524 in contact with the oxide 530 can be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0228] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0229] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0230] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0231] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0232] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0233] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0234] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0235] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0236] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0237] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0238] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0239] As shown in FIG. 15B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0240] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0241] 15A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0242] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0243] To form the insulator 552 into a thin film as described above, it is preferable to form the film by the ALD method. The ALD method includes a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, and a plasma-enhanced ALD method in which a plasma-excited reactant is used. The PEALD method may be preferable because it uses plasma, allowing film formation at a lower temperature.

[0244] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of an opening formed in the insulator 580 or the like and with the thin film thickness described above.

[0245] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0246] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0247] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 is preferably 1 nm or more, or 0.5 nm or more, and preferably 15 nm or less, or 20 nm or less. Note that the above-mentioned lower and upper limits can be combined. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0248] 15A and 15B show a configuration in which the insulator 550 is a single layer, but the present invention is not limited to this and the insulator 550 may have a laminated structure of two or more layers. For example, as shown in Fig. 17B, the insulator 550 may have a two-layer laminated structure of an insulator 550a and an insulator 550b on the insulator 550a.

[0249] As shown in FIG. 17B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the oxygen contained in the insulator 550a from diffusing into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0250] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a layered structure of the insulators 550a and 550b, a layered structure that is thermally stable and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0251] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0252] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0253] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0254] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 15A and 15B, the height of the top of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 15A and 15B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers, other than the two-layer structure.

[0255] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0256] Furthermore, since conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0257] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above conductive material.

[0258] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0259] 15B, in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0260] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0261] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0262] The insulator 580 preferably has a low concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0263] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0264] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0265] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a functioning as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that in this specification and the like, the conductors 540a and 540b are collectively referred to as conductors 540.

[0266] For example, the conductor 540a is provided in a region overlapping with the conductor 542a. Specifically, in the region overlapping with the conductor 542a, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 15A and insulators 582 and 586 shown in FIG. 14, and the conductor 540a is provided inside the openings. For example, the conductor 540b is provided in a region overlapping with the conductor 542b. Specifically, in the region overlapping with the conductor 542b, openings are formed in the insulators 571, 544, 580, 574, 576, and 581 shown in Fig. 15A and insulators 582 and 586 shown in Fig. 14, and the conductor 540b is provided inside the openings. Note that the insulators 582 and 586 will be described later.

[0267] 15A, an insulator 541a may be provided as an insulator having a barrier property against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having a barrier property against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0268] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0269] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0270] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544, etc. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0271] When insulators 541a and 541b are formed into a layered structure as shown in FIG. 15A, it is preferable that the first insulator in contact with the inner wall of an opening such as insulator 580 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0272] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0273] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0274] 14, conductors 610 and 612, which function as wiring and are in contact with the upper portions of conductors 540a and 540b, may be disposed. Conductor 610 and conductor 612 are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors may also have a layered structure. Specifically, for example, the conductors may be a layered structure of titanium or titanium nitride and the above conductive material. The conductors may be formed so as to be embedded in openings provided in an insulator.

[0275] The structure of the transistors included in the group of semiconductor devices of the present invention is not limited to the transistor 500 shown in Figures 14, 15A, 15B, and 16. The structure of the transistors included in the group of semiconductor devices of the present invention may be changed depending on the situation.

[0276] For example, the transistor 500 illustrated in FIGS. 14, 15A, 15B, and 16 may have the structure illustrated in FIG. 18. The transistor in FIG. 18 differs from the transistor 500 illustrated in FIGS. 14, 15A, 15B, and 16 in that it includes an oxide 543a and an oxide 543b. Note that in this specification and the like, the oxide 543a and the oxide 543b are collectively referred to as the oxide 543. The cross-sectional structure of the transistor in FIG. 18 in the channel width direction can be similar to that of the cross-section of the transistor 500 illustrated in FIG. 15B.

[0277] The oxide 543a is provided between the oxide 530b and the conductor 542a, and the oxide 543b is provided between the oxide 530b and the conductor 542b. Here, the oxide 543a is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542a. The oxide 543b is preferably in contact with the upper surface of the oxide 530b and the lower surface of the conductor 542b.

[0278] The oxide 543 preferably has a function of suppressing oxygen permeation. Placing the oxide 543, which has a function of suppressing oxygen permeation, between the conductor 542 functioning as a source electrode or a drain electrode and the oxide 530b is preferable because the electrical resistance between the conductor 542 and the oxide 530b can be reduced. Such a structure can improve the electrical characteristics, field-effect mobility, and reliability of the transistor 500 in some cases.

[0279] Alternatively, a metal oxide containing element M may be used as oxide 543. In particular, element M may be aluminum, gallium, yttrium, or tin. Preferably, oxide 543 has a higher concentration of element M than oxide 530b. Alternatively, oxide 543 may be gallium oxide. Alternatively, oxide 543 may be a metal oxide such as In-M-Zn oxide. Specifically, the atomic ratio of element M to In in the metal oxide used for oxide 530b is preferably greater than the atomic ratio of element M to In in the metal oxide used for oxide 530b. Furthermore, the film thickness of oxide 543 is preferably 0.5 nm or more or 1 nm or more, and is preferably 2 nm or less, 3 nm or less, or 5 nm or less. The above-mentioned lower and upper limits may be combined. Preferably, oxide 543 is crystalline. When oxide 543 is crystalline, oxygen release from oxide 530 can be effectively suppressed. For example, if the oxide 543 has a crystal structure such as a hexagonal crystal structure, the release of oxygen from the oxide 530 may be suppressed.

[0280] An insulator 582 is provided on the insulator 581, and an insulator 586 is provided on the insulator 582.

[0281] The insulator 582 is preferably made of a substance that has a barrier property against oxygen and hydrogen. Therefore, the insulator 582 can be made of a material similar to that of the insulator 514. For example, the insulator 582 is preferably made of a metal oxide such as aluminum oxide, hafnium oxide, or tantalum oxide.

[0282] The insulator 586 can be made of a material similar to that of the insulator 320. The use of a material with a relatively low dielectric constant for these insulators can reduce parasitic capacitance between wirings. For example, the insulator 586 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0283] Next, a description will be given of a capacitor 600 and its peripheral wiring or plugs included in the semiconductor device shown in Fig. 14 and Fig. 16. Note that the capacitor 600, wiring, and / or plugs are provided above the transistor 500 shown in Fig. 14 and Fig. 16.

[0284] The capacitor 600 includes, for example, a conductor 610 , a conductor 620 , and an insulator 630 .

[0285] A conductor 610 is provided over one of the conductors 540a and 540b, the conductor 546, and the insulator 586. The conductor 610 functions as one of a pair of electrodes of the capacitor 600.

[0286] A conductor 612 is provided over the other of the conductor 540a and the conductor 540b and over the insulator 586. The conductor 612 functions as a plug, a wiring, a terminal, or the like that electrically connects the transistor 500 to a circuit element, a wiring, or the like arranged above it.

[0287] The conductor 612 and the conductor 610 may be formed at the same time.

[0288] A metal film containing an element selected from molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, and scandium, or a metal nitride film containing any of the above elements (tantalum nitride film, titanium nitride film, molybdenum nitride film, tungsten nitride film), or the like can be used for the conductor 612 and the conductor 610. Alternatively, a conductive material such as indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can also be used.

[0289] 14, the conductor 612 and the conductor 610 are shown to have a single-layer structure, but are not limited to this structure and may have a stacked structure of two or more layers. For example, a conductor having barrier properties and a conductor having high adhesion to the conductor having high conductivity may be formed between a conductor having barrier properties and a conductor having high conductivity.

[0290] An insulator 630 is provided over the insulator 586 and the conductor 610. The insulator 630 functions as a dielectric sandwiched between a pair of electrodes of the capacitor 600.

[0291] The insulator 630 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, hafnium oxide, hafnium oxynitride, hafnium nitride oxide, hafnium nitride, zirconium oxide, or the like. The insulator 630 can be formed as a stacked layer or a single layer using any of the above-mentioned materials.

[0292] Furthermore, for example, the insulator 630 may have a laminated structure of a high dielectric strength material, such as silicon oxynitride, and a high dielectric constant (high-k) material. With this configuration, the capacitor 600 can ensure sufficient capacitance by having an insulator with a high dielectric constant (high-k), and the capacitor 600 can have improved dielectric strength by having an insulator with a high dielectric strength, thereby preventing electrostatic breakdown of the capacitor 600.

[0293] Examples of high-dielectric-constant (high-k) materials (materials with a high relative dielectric constant) insulators include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, and nitrides containing silicon and hafnium.

[0294] Alternatively, the insulator 630 may be a single layer or a multilayer insulator containing a high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO), or (Ba,Sr)TiO (BST). The insulator 630 may also be a compound containing hafnium and zirconium. As semiconductor devices become increasingly miniaturized and highly integrated, thinning of the gate insulator and dielectrics used in capacitors can cause problems such as leakage current in transistors and capacitors. Using a high-k material for the insulators that function as the gate insulator and dielectrics used in capacitors can reduce the gate potential during transistor operation and ensure the capacitance of capacitors while maintaining the physical film thickness.

[0295] The conductor 620 is provided to overlap with the conductor 610 with the insulator 630 placed therebetween. The conductor 610 functions as one of a pair of electrodes of the capacitor 600.

[0296] The conductor 620 can be made of a conductive material such as a metal material, an alloy material, or a metal oxide material. It is preferable to use a high-melting-point material such as tungsten or molybdenum, which has both heat resistance and conductivity, and tungsten is particularly preferable. When the conductor 620 is formed simultaneously with other structures such as a conductor, a low-resistance metal material such as Cu (copper) or Al (aluminum) can be used. For example, the conductor 620 can be made of a material that can be used for the conductor 610. The conductor 620 may have a laminated structure of two or more layers instead of a single layer structure.

[0297] An insulator 640 is provided over the conductor 620 and the insulator 630. For the insulator 640, for example, a film having a barrier property that prevents diffusion of hydrogen, impurities, and the like into a region where the transistor 500 is provided is preferably used. Therefore, a material similar to that of the insulator 324 can be used.

[0298] An insulator 650 is provided over the insulator 640. The insulator 650 can be provided using a material similar to that of the insulator 320. The insulator 650 may also function as a planarizing film that covers the uneven shape below it. Therefore, the insulator 650 can be made of, for example, a material that can be used for the insulator 324.

[0299] 14 and 16 is a planar type, the shape of the capacitive element is not limited to this. The capacitive element 600 may be, for example, a cylindrical type instead of the planar type.

[0300] 14, an insulator 411, an insulator 412, an insulator 413, and an insulator 414 are provided in this order above an insulator 650. A conductor 416 functioning as a plug or a wiring is provided in the insulators 411, 412, and 413. For example, the conductor 416 can be provided in a region overlapping with a conductor 660 described later.

[0301] Furthermore, openings are provided in the insulators 630, 640, and 650 in regions overlapping with the conductor 612, and the conductor 660 is provided to fill the openings. The conductor 660 functions as a plug or wiring electrically connected to the conductor 416 included in the above-described wiring layer.

[0302] The insulators 411 and 414 are preferably made of an insulator that has barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulators 411 and 414 can be made of a material that can be used for the insulator 324, for example.

[0303] For the insulators 412 and 413, similar to the insulator 326, it is preferable to use an insulator with a relatively low dielectric constant in order to reduce parasitic capacitance between wirings.

[0304] Furthermore, the conductor 612 and the conductor 416 can be formed using, for example, the same material as the conductor 328 and the conductor 330 .

[0305] <Example of a configuration of a transistor and a ferroelectric capacitor> Next, a configuration will be described in which a ferroelectric capacitor is provided around a transistor 500 in which a metal oxide is included in a channel formation region.

[0306] FIG. 19 shows an example of a transistor configuration in which a dielectric that may have ferroelectric properties is provided in the configuration of transistor 500 such as that of FIG. 14 or FIG. 15A.

[0307] 19, an insulator 602 is provided in an opening that overlaps with the conductor 542b and is provided in the insulators 544, 571b, 580, 574, 576, and 581. Specifically, in the opening, an insulator 541b is provided on a side surface of the opening, a conductor 540b is provided over the insulator 541b and over the conductor 542b that is at the bottom of the opening, an insulator 602 is provided in a portion of the insulator 581 and over the conductor 540b, and a conductor 613 is provided over the insulator 602 to fill the remaining opening.

[0308] As another specific configuration example, within the opening, an insulator 541b is provided on the side of the opening, a conductor 540b is provided on the insulator 541b, an insulator 602 is provided in a portion of the insulator 581, on the conductor 540b, and on the conductor 542b at the bottom of the opening, and a conductor 613 is provided on the insulator 602 so as to fill the remaining opening.

[0309] As an example, a dielectric material that may have ferroelectricity can be used for the insulator 602. A structure including conductors provided above and below the dielectric material functions as a ferroelectric capacitor.

[0310] Hafnium oxide or a material containing hafnium oxide and zirconium oxide is preferable as a dielectric material that can have ferroelectricity because it can be processed into a thin film of a few nanometers and still have ferroelectricity. Here, the film thickness of the insulator 602 can be 100 nm or less, preferably 50 nm or less, and more preferably 10 nm or less. By thinning the insulator 602, it can be combined with a miniaturized transistor to form a semiconductor device.

[0311] As the insulator 602, a material having hafnium oxide and zirconium oxide (HfZrO x When using the above-mentioned film, it is preferable to form the film by using a thermal ALD method.

[0312] Furthermore, when the insulator 602 is formed by the thermal ALD method, it is preferable to use a material that does not contain hydrocarbons as a precursor. If the insulator 602 contains either or both of hydrogen and carbon, crystallization of the insulator 602 may be hindered. For this reason, as described above, it is preferable to use a precursor that does not contain hydrocarbons to reduce the concentration of either or both of hydrogen and carbon in the insulator 602. For example, a chlorine-based material can be used as a precursor that does not contain hydrocarbons. Note that the insulator 602 may be formed using a material containing hafnium oxide and zirconium oxide (HfZrO x ) is used, HfCl4 and / or ZrCl4 may be used as the precursor.

[0313] Furthermore, when forming the insulator 602 using a thermal ALD method, the oxidizing agent can be H2O or O3. Note that using O3 as the oxidizing agent for the thermal ALD method is more preferable than using H2O because it can reduce the hydrogen concentration in the film. However, the oxidizing agent for the thermal ALD method is not limited to this. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0314] The conductor 613 can be formed using, for example, a material similar to that of the conductors 328 and 330 .

[0315] The conductor 613 can be formed by ALD or CVD. For example, titanium nitride can be formed by thermal ALD. Here, the conductor 613 is preferably formed by a method in which the substrate is heated, as in the thermal ALD method. For example, the substrate temperature can be set to room temperature or higher, preferably 300°C or higher, more preferably 325°C or higher, and even more preferably 350°C or higher. Alternatively, the substrate temperature can be set to 500°C or lower, preferably 450°C or lower. For example, the substrate temperature can be set to about 400°C.

[0316] By forming the conductor 613 within the temperature range described above, it is possible to impart ferroelectricity to the insulator 602 without performing a high-temperature bake treatment (e.g., a bake treatment at a heat treatment temperature of 400°C or higher or 500°C or higher) after forming the conductor 613. Furthermore, by forming the conductor 613 using the ALD method, which causes relatively little damage to the base, as described above, it is possible to prevent the crystal structure of the insulator 602 from being excessively destroyed, thereby enhancing the ferroelectricity of the insulator 602.

[0317] For example, when the conductor 613 is formed by sputtering, there is a possibility that damage may occur in the underlayer, in this case the insulator 602. For example, when the insulator 602 is made of a material containing hafnium oxide and zirconium oxide (HfZrO x When the conductor 613 is formed by sputtering, the HfZrO x Damage occurs to HfZrO x The crystal structure (typically a cubic crystal structure) of HfZrO may be destroyed by heat treatment. x There are also methods to repair the damage to the crystal structure of HfZrO formed by sputtering. x Damage in, e.g., HfZrO x Dangling bonds in (e.g., O * ) and HfZrO x The hydrogen contained in the x In some cases, damage in the crystal structure of the material cannot be repaired.

[0318] Therefore, HfZrO used as the insulator 602 x It is preferable to use a material that does not contain hydrogen or that contains extremely little hydrogen for the insulator 602. By using a material that does not contain hydrogen or that contains extremely little hydrogen for the insulator 602, the crystallinity of the insulator 602 can be improved, resulting in a structure with high ferroelectricity.

[0319] As described above, in one embodiment of the present invention, for example, a ferroelectric material is formed as the insulator 602 by thermal ALD using a hydrocarbon-free precursor (typically a chlorine-based precursor) and an oxidizer (typically O). Then, the conductor 613 is formed by thermal ALD (typically at 400° C. or higher). This allows the crystallinity or ferroelectricity of the insulator 602 to be improved without annealing after the formation of the conductor 613, in other words, by utilizing the temperature during the formation of the conductor 613. Note that improving the crystallinity or ferroelectricity of the insulator 602 by utilizing the temperature during the formation of the conductor 613 without annealing after the formation of the conductor 613 is sometimes referred to as self-annealing.

[0320] With the configuration of the transistor in FIG. 19, a ferroelectric capacitor can be provided between the conductor 540b and the conductor 613 in the opening included in the region overlapping with the conductor 542b.

[0321] Note that the insulator 602 may have a stacked structure of two or more layers.

[0322] Furthermore, the respective configurations of the transistor and ferroelectric capacitor shown in FIG. 19 can be applied to, for example, the transistor M1 and ferroelectric capacitor C1 described in the first embodiment.

[0323] FIG. 20A shows an example of the configuration of a transistor 500 and a capacitor, in which a capacitor including a dielectric material that may have ferroelectricity is provided around the transistor 500.

[0324] 20A , for example, a plurality of openings are formed in the insulators 544, 571b, 580, 574, 576, and 581 in a region overlapping with the conductor 542b. A conductor 540c functioning as a plug is provided inside one of the openings, and an insulator 541c serving as an insulator with a barrier property against impurities is provided between a side surface of the opening and the conductor 540c. A conductor 540d functioning as a plug is provided inside another of the openings, and an insulator 541d serving as an insulator with a barrier property against impurities is provided between a side surface of the opening and the conductor 540d. The conductor 540c and the conductor 540d can be made of, for example, a material that can be used for the conductor 540a and the conductor 540b, and the insulator 541c and the insulator 541d can be made of, for example, a material that can be used for the insulator 541a and the insulator 541b.

[0325] An insulator 601 is provided on the upper part of the conductor 540c and the conductor 540d so as to be in contact with them. As an example, the insulator 601 can be made of a dielectric material that can have ferroelectricity and can be used for the insulator 602 in FIG.

[0326] A conductor 611 is provided to be in contact with an upper portion of the insulator 601. The conductor 611 can be provided using, for example, the same material as the conductors 328 and 330.

[0327] Therefore, with the configuration shown in FIG. 20A, a ferroelectric capacitor can be provided between the conductor 540c and the conductor 540d that function as plugs and the conductor 611.

[0328] The insulator 601 may have a stacked structure of two or more layers.

[0329] 20A shows two plugs (conductor 540c and conductor 540d) in contact with insulator 601, but the number of plugs may be one or three or more. In other words, while Fig. 20A shows an example in which two openings having conductors as plugs are provided in the region overlapping with insulator 601, the number of openings provided in the region overlapping with insulator 601 may be one or three or more.

[0330] FIG. 20B shows an example of a configuration of a transistor 500 and a capacitor, which is different from that of FIG. 20A, in which a capacitor including a dielectric material that may have ferroelectricity is provided around the transistor 500.

[0331] 20B, an insulator 631 is provided on the top surface of the conductor 610 located on the conductor 540b functioning as a plug and on a portion of the top surface of the insulator 581. As an example, the insulator 631 can be a dielectric that can have ferroelectricity and can be used for the insulator 602 in FIG.

[0332] In addition, a conductor 620 is provided on the upper surface of insulator 631, and an insulator 640 and an insulator 650 are provided in order on the upper surfaces of insulator 581, conductor 612, conductor 620, and a partial region of insulator 631.

[0333] Therefore, with the configuration shown in FIG. 20B, a ferroelectric capacitor can be provided between the conductor 610 and the conductor 620.

[0334] Note that the insulator 631 may have a stacked structure of two or more layers.

[0335] Furthermore, the respective configurations of the transistor and ferroelectric capacitor shown in FIGS. 20A and 20B can be applied to, for example, the transistor M1 and ferroelectric capacitor C1 described in the first embodiment.

[0336] By applying the structure described in this embodiment to a semiconductor device including a transistor having an oxide semiconductor, fluctuations in electrical characteristics of the transistor can be suppressed and reliability can be improved. Alternatively, miniaturization or high integration of a semiconductor device including a transistor having an oxide semiconductor can be achieved.

[0337] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0338] (Embodiment 3) In this embodiment, a metal oxide (hereinafter also referred to as an oxide semiconductor) that can be used for the OS transistor described in the above embodiment will be described.

[0339] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. It is also preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0340] <Classification of crystal structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 21A. Fig. 21A is a diagram for explaining classification of crystal structures of oxide semiconductors, typically IGZO (a metal oxide containing In, Ga, and Zn).

[0341] As shown in FIG. 21A, oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." "Amorphous" includes completely amorphous. "Crystalline" includes c-axis-aligned crystalline (CAAC), nanocrystalline (nc), and cloud-aligned composite (CAC) (excluding single crystal and polycrystal). "Crystalline" excludes single crystal, polycrystal, and completely amorphous. "Crystalline" includes single crystal and polycrystal.

[0342] The structure within the bold frame in Figure 21A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be completely different from the energetically unstable "Amorphous" and "Crystal."

[0343] The crystalline structure of a film or substrate can be evaluated using X-ray diffraction (XRD) spectroscopy. Figure 21B shows the XRD spectrum obtained by GIXD (Grazing-Incidence XRD) measurement of a CAAC-IGZO film classified as "Crystalline" (the vertical axis represents intensity in arbitrary units (au)). The GIXD method is also known as the thin-film method or the Seemann-Bohlin method. Hereinafter, the XRD spectrum obtained by GIXD measurement shown in Figure 21B will be simply referred to as the XRD spectrum. The composition of the CAAC-IGZO film shown in Figure 21B is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the CAAC-IGZO film shown in Figure 21B is 500 nm.

[0344] As shown in Figure 21B, a clear peak indicating crystallinity is detected in the XRD spectrum of the CAAC-IGZO film. Specifically, a peak indicating c-axis orientation is detected near 2θ = 31° in the XRD spectrum of the CAAC-IGZO film. As shown in Figure 21B, the peak near 2θ = 31° is asymmetric with respect to the angle at which the peak intensity is detected.

[0345] The crystalline structure of a film or substrate can be evaluated by the diffraction pattern (also called the nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction pattern of the CAAC-IGZO film is shown in Figure 21C. Figure 21C shows a diffraction pattern observed by NBED, in which an electron beam is incident parallel to the substrate. The composition of the CAAC-IGZO film shown in Figure 21C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. In the nanobeam electron diffraction method, electron diffraction is performed using a probe diameter of 1 nm.

[0346] As shown in FIG. 21C, multiple spots indicating c-axis orientation are observed in the diffraction pattern of the CAAC-IGZO film.

[0347] <<Structure of oxide semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 21A when focusing on their crystal structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0348] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0349] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. Note that distortion refers to a location where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0350] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0351] In an In-M-Zn oxide (wherein M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0352] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type and composition of the metallic elements constituting the CAAC-OS.

[0353] Furthermore, for example, in the electron diffraction pattern of the CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0354] When the crystalline region is observed from the specific direction, the lattice arrangement within the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundaries are observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0355] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries act as recombination centers, trapping carriers and potentially causing a decrease in the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in the semiconductor layer of a transistor. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0356] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities or the formation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budget) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0357] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystalline structures. The size of the microcrystalline structures is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystalline structures are also called nanocrystalline structures. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystalline structures. Therefore, the entire film lacks orientation. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystalline structures (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0358] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0359] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0360] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range. Hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or a similar size range, is also referred to as a mosaic or patch state.

[0361] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0362] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0363] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0364] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0365] For example, in the case of CAC-OS in In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region mainly composed of In (first region) and a region mainly composed of Ga (second region) are unevenly distributed and mixed.

[0366] When CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act in a complementary manner, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0367] Oxide semiconductors have a variety of structures, each with different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0368] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0369] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0370] For the transistor, an oxide semiconductor with a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm -3 Less than or equal to 1×10 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0371] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0372] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0373] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0374] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0375] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentrations of silicon and carbon in the oxide semiconductor and those near the interface with the oxide semiconductor (concentrations obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0376] Furthermore, when an oxide semiconductor contains an alkali metal or alkaline earth metal, defect levels may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0377] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than or equal to 1×10 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0378] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, which may form an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in an oxide semiconductor measured by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0379] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0380] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0381] (Fourth embodiment) In this embodiment mode, an example of a semiconductor wafer on which the semiconductor device or the like described in the above embodiment mode is formed and an example of an electronic component in which the semiconductor device is incorporated will be described.

[0382] <Semiconductor wafer> First, an example of a semiconductor wafer on which semiconductor devices and the like are formed will be described with reference to FIG. 22A.

[0383] 22A includes a wafer 4801 and a plurality of circuit portions 4802 provided on the upper surface of the wafer 4801. Note that on the upper surface of the wafer 4801, a portion where the circuit portions 4802 are not present is a spacing 4803, which is a region for dicing.

[0384] The semiconductor wafer 4800 can be manufactured by forming a plurality of circuit portions 4802 on the surface of the wafer 4801 in a previous process. After that, the surface of the wafer 4801 opposite to the surface on which the plurality of circuit portions 4802 are formed may be ground to thin the wafer 4801. This process reduces warping of the wafer 4801 and allows for miniaturization of the component.

[0385] The next step is the dicing process. Dicing is performed along scribe lines SCL1 and SCL2 (sometimes called dicing lines or cutting lines) indicated by dashed lines. To facilitate the dicing process, spacing 4803 is preferably arranged so that multiple scribe lines SCL1 are parallel to each other, multiple scribe lines SCL2 are parallel to each other, and scribe lines SCL1 and SCL2 are perpendicular to each other.

[0386] By performing a dicing process, chips 4800a as shown in FIG. 22B can be cut out from semiconductor wafer 4800. Chip 4800a has wafer 4801a, circuit portion 4802, and spacing 4803a. It is preferable to make spacing 4803a as small as possible. In this case, it is sufficient that the width of spacing 4803 between adjacent circuit portions 4802 is approximately the same length as the cutting margin of scribe line SCL1 or the cutting margin of scribe line SCL2.

[0387] Note that the shape of the element substrate of one embodiment of the present invention is not limited to the shape of the semiconductor wafer 4800 illustrated in Figure 22A. For example, the semiconductor wafer may have a rectangular shape. The shape of the element substrate can be changed as appropriate depending on the manufacturing process and the device for manufacturing the element.

[0388] <Electronic components> 22C is a perspective view of an electronic component 4700 and a substrate (mounting substrate 4704) on which the electronic component 4700 is mounted. The electronic component 4700 shown in FIG. 22C includes a chip 4800a in a mold 4711. A memory device or the like according to one embodiment of the present invention can be used as the chip 4800a.

[0389] 22C omits some parts to show the interior of electronic component 4700. Electronic component 4700 has lands 4712 on the outside of mold 4711. Lands 4712 are electrically connected to electrode pads 4713, and electrode pads 4713 are electrically connected to chip 4800a via wires 4714. Electronic component 4700 is mounted on, for example, a printed circuit board 4702. A plurality of such electronic components are combined and electrically connected on printed circuit board 4702 to complete mounted board 4704.

[0390] 22D shows a perspective view of electronic component 4730. Electronic component 4730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). Electronic component 4730 has an interposer 4731 provided on a package substrate 4732 (printed circuit board), and a semiconductor device 4735 and multiple semiconductor devices 4710 provided on interposer 4731.

[0391] The semiconductor device 4710 may be, for example, a chip 4800a, the semiconductor device described in the above embodiment, a high bandwidth memory (HBM), etc. The semiconductor device 4735 may be an integrated circuit (semiconductor device) such as a CPU, a GPU, an FPGA, or a memory device.

[0392] A ceramic substrate, a plastic substrate, a glass epoxy substrate, or the like can be used for the package substrate 4732. A silicon interposer, a resin interposer, or the like can be used for the interposer 4731.

[0393] The interposer 4731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 4731 also functions to electrically connect the integrated circuits provided on the interposer 4731 to electrodes provided on the package substrate 4732. For these reasons, the interposer is sometimes called a "rewiring substrate" or "intermediate substrate." In some cases, through electrodes are provided in the interposer 4731, and the integrated circuits and the package substrate 4732 are electrically connected using the through electrodes. In addition, in a silicon interposer, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0394] It is preferable to use a silicon interposer as the interposer 4731. Since a silicon interposer does not require an active element, it can be manufactured at a lower cost than an integrated circuit. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring that is difficult to form with a resin interposer.

[0395] HBM requires many interconnects to achieve a wide memory bandwidth. Therefore, the interposer that implements HBM requires fine and high-density interconnects. Therefore, it is preferable to use a silicon interposer for implementing HBM.

[0396] Furthermore, in SiP or MCM using a silicon interposer, a decrease in reliability due to differences in the expansion coefficient between the integrated circuit and the interposer is unlikely to occur. Furthermore, because the silicon interposer has a highly flat surface, poor connection between the integrated circuit mounted on the silicon interposer and the silicon interposer is unlikely to occur. In particular, it is preferable to use a silicon interposer in a 2.5D package (2.5-dimensional mounting) in which multiple integrated circuits are arranged horizontally on the interposer.

[0397] A heat sink (heat sink) may be provided overlapping the electronic component 4730. When a heat sink is provided, it is preferable to align the height of an integrated circuit provided on the interposer 4731. For example, in the electronic component 4730 shown in this embodiment, it is preferable to align the height of the semiconductor device 4710 and the height of the semiconductor device 4735.

[0398] In order to mount electronic component 4730 on another substrate, electrodes 4733 may be provided on the bottom of package substrate 4732. Fig. 22D shows an example in which electrodes 4733 are formed with solder balls. By providing solder balls in a matrix on the bottom of package substrate 4732, BGA (Ball Grid Array) mounting can be achieved. Electrodes 4733 may also be formed with conductive pins. By providing conductive pins in a matrix on the bottom of package substrate 4732, PGA (Pin Grid Array) mounting can be achieved.

[0399] The electronic component 4730 can be mounted on other substrates using various mounting methods, including but not limited to BGA and PGA, such as a staggered pin grid array (SPGA), a land grid array (LGA), a quad flat package (QFP), a quad flat J-leaded package (QFJ), or a quad flat non-leaded package (QFN).

[0400] The structure described in this embodiment mode can be combined as appropriate with structures described in other embodiments.

[0401] (Embodiment 5) In this embodiment, application examples of a semiconductor device according to one embodiment of the present invention will be described.

[0402] The semiconductor device according to one embodiment of the present invention can be applied to, for example, memory devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording / playback devices, navigation systems, game consoles, and the like). It can also be used in image sensors, IoT (Internet of Things) devices, healthcare-related devices, and the like. Note that the term "computer" as used herein refers to a tablet computer, a notebook computer, a desktop computer, and a large-scale computer such as a server system.

[0403] 23A to 23J and 24A to 24E illustrate examples of electronic devices including an electronic component 4700 or an electronic component 4730 including the semiconductor device according to one embodiment of the present invention.

[0404] [mobile phone] 23A is a mobile phone (smartphone), which is one type of information terminal. The information terminal 5500 has a housing 5510 and a display unit 5511. As input interfaces, a touch panel is provided on the display unit 5511 and buttons are provided on the housing 5510.

[0405] By applying the semiconductor device according to one embodiment of the present invention, the information terminal 5500 can hold temporary files (for example, caches when using a web browser) generated when an application is executed.

[0406] [Wearable devices] 23B illustrates an information terminal 5900, which is an example of a wearable terminal. The information terminal 5900 includes a housing 5901, a display portion 5902, operation switches 5903 and 5904, a band 5905, and the like.

[0407] Like the above-described information terminal 5500, the wearable terminal can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0408] [Information terminal] 23C shows a desktop information terminal 5300. The desktop information terminal 5300 includes a main body 5301 of the information terminal, a display unit 5302, and a keyboard 5303.

[0409] Like the above-described information terminal 5500, the desktop information terminal 5300 can hold temporary files generated when an application is executed by applying a semiconductor device according to one embodiment of the present invention.

[0410] 23A to 23C are taken as examples of electronic devices, and are illustrated in Fig. 23A to 23C, but information terminals other than smartphones, wearable terminals, and desktop information terminals can also be applied. Examples of information terminals other than smartphones, wearable terminals, and desktop information terminals include PDAs (Personal Digital Assistants), notebook information terminals, and workstations.

[0411] [electric appliances] 23D also illustrates an electric refrigerator-freezer 5800 as an example of an electrical appliance. Electric refrigerator-freezer 5800 has a housing 5801, a refrigerator compartment door 5802, a freezer compartment door 5803, etc. For example, electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0412] The semiconductor device according to one embodiment of the present invention can be applied to an electric refrigerator-freezer 5800. The electric refrigerator-freezer 5800 can transmit and receive information about food ingredients stored in the electric refrigerator-freezer 5800, such as expiration dates of the food ingredients, to and from an information terminal or the like via the Internet or the like. The electric refrigerator-freezer 5800 can store a temporary file generated when transmitting the information in the semiconductor device.

[0413] In this example, an electric refrigerator-freezer has been described as an electrical appliance, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cookers, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, audio-visual equipment, etc.

[0414] [Game consoles] 23E shows a portable game machine 5200, which is an example of a game machine. The portable game machine 5200 includes a housing 5201, a display portion 5202, buttons 5203, and the like.

[0415] FIG. 23F further illustrates a stationary game console 7500, which is an example of a game console. The stationary game console 7500 includes a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or via a cable. Although not shown in FIG. 23F, the controller 7522 can include a display unit for displaying game images, a touch panel serving as an input interface other than buttons, a stick, a rotary knob, a sliding knob, or the like. The shape of the controller 7522 is not limited to the shape shown in FIG. 23F, and the shape of the controller 7522 may be modified in various ways depending on the genre of the game. For example, in a shooting game such as an FPS (First Person Shooter), a controller shaped like a gun with a trigger as a button can be used. For example, in a music game, a controller shaped like a musical instrument, a musical device, or the like can be used. Furthermore, the stationary game console may not use a controller, but may instead be equipped with a camera, depth sensor, microphone, etc., and be operated by the game player's gestures and / or voice.

[0416] Furthermore, the images of the above-mentioned game machines can be output by display devices such as television devices, personal computer displays, game displays, and head-mounted displays.

[0417] A low-power portable game machine 5200 or a low-power stationary game machine 7500 can be realized by applying the semiconductor device described in the above embodiments to the portable game machine 5200 or the stationary game machine 7500. Furthermore, the low power consumption can reduce heat generation from a circuit, thereby reducing the influence of heat on the circuit itself, peripheral circuits, and modules.

[0418] Furthermore, by applying the semiconductor device described in the above embodiments to the portable game console 5200 or the stationary game console 7500, temporary files and the like necessary for calculations occurring during game execution can be stored.

[0419] As an example of a game machine, a portable game machine is shown in FIG. 23E. Also, a home-use stationary game machine is shown in FIG. 23F. Note that the electronic device of one embodiment of the present invention is not limited to this. Examples of the electronic device of one embodiment of the present invention include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0420] [Moving object] The semiconductor device described in the above embodiment mode can be applied to automobiles, which are moving objects, and to the vicinity of a driver's seat of an automobile.

[0421] FIG. 23G illustrates an automobile 5700 as an example of a moving object.

[0422] An instrument panel that provides various information by displaying a speedometer or tachometer, mileage, fuel gauge, gear status, air conditioning settings, etc. may be provided around the driver's seat of the automobile 5700. A display device that shows this information may also be provided around the driver's seat.

[0423] In particular, the display device can compensate for the field of view obstructed by pillars, blind spots around the driver's seat, and the like, thereby improving safety by displaying an image from an imaging device (not shown) provided on the automobile 5700. That is, by displaying an image from an imaging device provided on the outside of the automobile 5700, blind spots can be compensated for and safety can be improved.

[0424] The semiconductor device described in the above embodiment can temporarily store information. Therefore, the semiconductor device can be used to store necessary temporary information in an automatic driving system for the automobile 5700, a system that provides road guidance, hazard prediction, or the like. The display device may be configured to display temporary information such as road guidance and hazard prediction. Alternatively, the display device may be configured to store video images from a driving recorder installed in the automobile 5700.

[0425] Although an automobile is described above as an example of a moving body, the moving body is not limited to an automobile. For example, moving bodies may include trains, monorails, ships, and flying bodies (helicopters, unmanned aerial vehicles (drones), airplanes, rockets, etc.).

[0426] [camera] The semiconductor device described in the above embodiment can be applied to a camera.

[0427] 23H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, operation switches 6243, a shutter button 6244, etc., and is also equipped with a detachable lens 6246. Note that, although the digital camera 6240 is configured such that the lens 6246 can be detached from the housing 6241 and replaced, the lens 6246 and the housing 6241 may be integrated. The digital camera 6240 may also be configured such that a strobe device, a viewfinder, etc. can be separately attached.

[0428] A low-power digital camera 6240 can be realized by applying the semiconductor device described in the above embodiment modes to the digital camera 6240. Furthermore, low power consumption can reduce heat generation from the circuit, thereby reducing the influence of heat generation on the circuit itself, peripheral circuits, and modules.

[0429] [Video camera] The semiconductor device described in the above embodiment can be applied to a video camera.

[0430] 23I illustrates a video camera 6300, which is an example of an imaging device. The video camera 6300 includes a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, a connection unit 6306, and the like. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. An image on the display unit 6303 may be switched depending on the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0431] When recording video captured by the video camera 6300, it is necessary to encode the video according to the data recording format. By using the semiconductor device described above, the video camera 6300 can store temporary files generated during encoding.

[0432] [ICD] The semiconductor device described in the above embodiment can be applied to an implantable cardioverter defibrillator (ICD).

[0433] 23J is a cross-sectional schematic diagram showing an example of an ICD. ICD main body 5400 has at least battery 5401, electronic components 4700, a regulator, a control circuit, antenna 5404, wire 5402 to the right atrium, and wire 5403 to the right ventricle.

[0434] The ICD body 5400 is surgically placed in the body, and the two wires are passed through the subclavian vein 5405 and superior vena cava 5406 of the human body so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0435] The ICD main unit 5400 functions as a pacemaker and paces the heart when the heart rate falls outside a specified range. If the heart rate does not improve with pacing and rapid ventricular tachycardia or ventricular fibrillation persists, treatment with an electric shock is performed.

[0436] The ICD main body 5400 must constantly monitor the heart rate in order to properly perform pacing and administer electric shocks. Therefore, the ICD main body 5400 has a sensor for detecting the heart rate. The ICD main body 5400 can also store in the electronic component 4700 the heart rate data acquired by the sensor, the number of pacing treatments performed, the duration, etc.

[0437] Furthermore, the antenna 5404 can receive power, which is then charged into the battery 5401. Furthermore, the ICD main body 5400 can improve safety by having multiple batteries. Specifically, even if some of the batteries in the ICD main body 5400 become unusable, the remaining batteries can still function, so the ICD main body 5400 can also function as an auxiliary power source.

[0438] In addition to the antenna 5404 that can receive power, an antenna that can transmit physiological signals may be provided, and a system for monitoring cardiac activity may be configured in which physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be confirmed on an external monitor device.

[0439] [PC expansion device] The semiconductor device described in the above embodiment can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0440] Fig. 24A shows an example of such an expansion device: a portable expansion device 6100 mounted on a chip capable of storing information and externally attached to a PC. The expansion device 6100 can store information using the chip by connecting to a PC via, for example, a USB (Universal Serial Bus). Note that while Fig. 24A shows a portable expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this; for example, it may be a relatively large expansion device equipped with a cooling fan or the like.

[0441] The expansion device 6100 has a housing 6101, a cap 6102, a USB connector 6103, and a board 6104. The board 6104 is housed in the housing 6101. The board 6104 is provided with circuits that drive the semiconductor devices and the like described in the above embodiments. For example, an electronic component 4700 and a controller chip 6106 are attached to the board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0442] [SD card] The semiconductor device described in the above embodiment can be applied to an SD card which can be attached to an electronic device such as an information terminal or a digital camera.

[0443] FIG. 24B is a schematic diagram of the external appearance of an SD card, and FIG. 24C is a schematic diagram of the internal structure of the SD card. The SD card 5110 has a housing 5111, a connector 5112, and a substrate 5113. The connector 5112 functions as an interface for connecting to an external device. The substrate 5113 is housed in the housing 5111. A semiconductor device and a circuit for driving the semiconductor device are provided on the substrate 5113. For example, an electronic component 4700 and a controller chip 5115 are attached to the substrate 5113. Note that the circuit configurations of the electronic component 4700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the write circuit, row driver, read circuit, etc. provided in the electronic component may be incorporated into the controller chip 5115 rather than the electronic component 4700.

[0444] The capacity of the SD card 5110 can be increased by providing the electronic component 4700 also on the back side of the substrate 5113. A wireless chip with a wireless communication function may be provided on the substrate 5113. This allows wireless communication between an external device and the SD card 5110, and enables reading and writing of data from and to the electronic component 4700.

[0445] [SSD] The semiconductor device described in the above embodiment can be applied to an SSD (Solid State Drive) that can be attached to electronic devices such as information terminals.

[0446] FIG. 24D is a schematic diagram of the external appearance of an SSD, and FIG. 24E is a schematic diagram of the internal structure of the SSD. The SSD 5150 includes a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to an external device. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is provided with a semiconductor device and a circuit for driving the semiconductor device. For example, the circuit board 5153 is provided with an electronic component 4700, a memory chip 5155, and a controller chip 5156. The capacity of the SSD 5150 can be increased by providing an electronic component 4700 on the back side of the circuit board 5153 as well. The memory chip 5155 incorporates a work memory. For example, a DRAM chip may be used for the memory chip 5155. The controller chip 5156 incorporates a processor, an ECC circuit, and the like. The circuit configurations of the electronic component 4700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be changed as appropriate depending on the situation. For example, the controller chip 5156 may also be provided with a memory that functions as a work memory.

[0447] [Calculator] 25A is an example of a large-scale computer. The computer 5600 has a rack 5610 in which a plurality of rack-mounted computers 5620 are stored.

[0448] Computer 5620 can have the configuration shown in the perspective view in Fig. 25B, for example. In Fig. 25B, computer 5620 has motherboard 5630, which has a plurality of slots 5631 and a plurality of connection terminals. PC card 5621 is inserted into slot 5631. In addition, PC card 5621 has connection terminal 5623, connection terminal 5624, and connection terminal 5625, which are each connected to motherboard 5630.

[0449] PC card 5621 shown in FIG. 25C is an example of a processing board including a CPU, a GPU, a semiconductor device, and the like. PC card 5621 includes board 5622. Board 5622 includes connection terminal 5623, connection terminal 5624, connection terminal 5625, semiconductor device 5626, semiconductor device 5627, semiconductor device 5628, and connection terminal 5629. Note that FIG. 25C illustrates semiconductor devices other than semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628, but for these semiconductor devices, the following descriptions of semiconductor device 5626, semiconductor device 5627, and semiconductor device 5628 may be referred to.

[0450] The connection terminal 5629 has a shape that allows it to be inserted into a slot 5631 of a motherboard 5630, and the connection terminal 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. An example of the standard for the connection terminal 5629 is PCIe.

[0451] Connection terminals 5623, 5624, and 5625 can be interfaces for supplying power to PC card 5621, inputting signals, and the like. They can also be interfaces for outputting signals calculated by PC card 5621, and the like. Examples of standards for connection terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). Examples of standards for outputting video signals from connection terminals 5623, 5624, and 5625 include HDMI (registered trademark).

[0452] The semiconductor device 5626 has a terminal (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting the terminal into a socket (not shown) provided on the board 5622.

[0453] The semiconductor device 5627 has a plurality of terminals, and the semiconductor device 5627 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5627 include an FPGA (Field Programmable Gate Array), a GPU, and a CPU. For example, the electronic component 4730 can be used as the semiconductor device 5627.

[0454] The semiconductor device 5628 has a plurality of terminals, and the semiconductor device 5628 can be electrically connected to the board 5622 by, for example, reflow soldering the terminals to wiring provided on the board 5622. Examples of the semiconductor device 5628 include a semiconductor device. For example, the electronic component 4700 can be used as the semiconductor device 5628.

[0455] The computer 5600 can also function as a parallel computer. By using the computer 5600 as a parallel computer, it is possible to perform large-scale calculations required for, for example, learning and inference in artificial intelligence.

[0456] By using the semiconductor device of one embodiment of the present invention in the various electronic devices, power consumption of the electronic devices can be reduced.

[0457] The structure described in this embodiment mode can be combined as appropriate with structures described in other embodiments. [Example]

[0458] Below, an evaluation result will be described which shows that in the memory cell MC2 described in FIG. 11 of the first embodiment, a voltage is applied to the ferroelectric capacitor C1 and multiple read operations can be performed without performing a write-back operation.

[0459] 26A to 26D, it was confirmed that in the memory cell MC2, the potential of the node SN changes when a voltage for a read operation is applied to the wiring PL, and the amount of current flowing through the transistor M2 changes. In FIG. 26A, when the horizontal axis (Vc) represents the change in the voltage of the wiring PL from 0 V to 0.5 V and the vertical axis (I) represents the amount of current flowing through the transistor M2, when the ferroelectric in the ferroelectric capacitor C1 is polarized to the state "0" (Pr - ) and when polarized in state “1” (Pr + ) and the graph comparing the changes in voltage and current.

[0460] In FIG. 26A, when the horizontal axis (Vc) represents the change in voltage of the wiring PL from 0V to 0.5V and the vertical axis (I) represents the amount of current flowing through the transistor M2, the ferroelectric in the ferroelectric capacitor C1 is polarized to the state “0” (Pr - ) and when polarized in state “1” (Pr + ) and the graph comparing the changes in voltage and current.

[0461] In FIG. 26B, after the read operation of FIG. 26A, when the horizontal axis (Vc) represents the change in voltage of the wiring PL from 0 V to 1.0 V and the vertical axis (I) represents the amount of current flowing through the transistor M2, the ferroelectric in the ferroelectric capacitor C1 is polarized to the state “0” (Pr - ) and when polarized in state “1” (Pr + ) and the graph comparing the changes in voltage and current.

[0462] In FIG. 26C, after the read operation of FIG. 26B, the horizontal axis (Vc) represents the change in voltage of the wiring PL from 0 V to 1.5 V, and the vertical axis (I) represents the amount of current flowing through the transistor M2. In this case, when the ferroelectric in the ferroelectric capacitor C1 is polarized to the state “0” (Pr - ) and when polarized in state “1” (Pr + ) and the graph comparing the changes in voltage and current.

[0463] In FIG. 26D, after the read operation of FIG. 26C, when the horizontal axis (Vc) represents the change in voltage of the wiring PL from 0 V to 2.0 V and the vertical axis (I) represents the amount of current flowing through the transistor M2, the ferroelectric in the ferroelectric capacitor C1 is polarized to the state “0” (Pr - ) and when polarized in state “1” (Pr + ) and the graph comparing the changes in voltage and current.

[0464] In Figures 26A and 26B, no difference in read current was observed when the voltage of the wiring PL was changed. On the other hand, in Figure 26C, it was confirmed that when the voltage of the wiring PL was changed, a difference in read current occurred depending on the difference in polarization. Next, in Figure 26D, when the voltage of the wiring PL was changed, no difference in read current was observed when the voltage was changed up to 1.5V because the polarization was destroyed during the read operation in Figure 26C. However, it was confirmed that a difference in read current occurred depending on the difference in polarization when the voltage was changed from 1.5V to 2.0V.

[0465] From the above results, it was possible to confirm the difference in current corresponding to the difference in polarization over multiple read operations. [Example]

[0466] The following describes the analysis results of the relationship between the channel area of ​​transistor M1 and the breakdown voltage of the transistor in memory cell MC described in FIG. 1A etc. of embodiment 1. The channel area is the area based on the product of the channel length (L) and the channel width (W).

[0467] The graph shown in FIG. 27A is a modified graph based on the graph showing the relationship between channel area and voltage shown in the above-mentioned Non-Patent Document 3. The channel area is estimated assuming that the channel length (L) and the channel width (W) are equal. For example, when the channel area is 0.01 μm 2corresponds to a channel length of 100 nm. In FIG. 27A, the points indicated by black circles correspond to the withstand voltage of a Si transistor, and the points indicated by white circles correspond to the withstand voltage of an OS transistor.

[0468] The breakdown voltage of Si transistors decreases as the channel area is reduced. X When using HZO, the polarization of HZO in zero electric field (2P r ) is 40μC / cm 2 In this case, a voltage of about 3 V is required to rewrite data, so the transistor must have a breakdown voltage of 3 V or more (dotted line 201 in the figure).

[0469] To reduce the area of ​​the ferroelectric capacitor C1, the area of ​​the HZO is set to 0.05 μm 2 If the transistor channel area is set to 0.05 μm or less, 2 However, in the case of a Si transistor, it is preferable to design it as a channel area of ​​0.05 μm 2 In this case, the withstand voltage is 3V or less, so it is difficult to apply a voltage of 3V or more to the ferroelectric capacitor C1 in order to rewrite data.

[0470] On the other hand, OS transistors have a higher breakdown voltage than Si transistors, even with the progress of miniaturization due to the reduction of channel area. Figure 27A shows examples of transistors with channel lengths (L) of 30 nm and 60 nm, and both transistors can meet the breakdown voltage of 3 V or more. In addition, when the channel length (L) is 30 nm or 60 nm, the channel area is converted to 0.0009 μm 2 and 0.0036 μm 2 Therefore, the area of ​​HZO is 0.05 μm 2 The OS transistor can be located in the region 203, which satisfies the requirements for miniaturization and high integration. The OS transistor satisfies both the requirements for high breakdown voltage and miniaturization.

[0471] Similarly, in Figure 27B, the polarization of HZO in an electric field of 0 (2P r ) is 50μC / cm 2 The graph shows the relationship between the channel area and the voltage when the polarization of HZO is 50 μC / cm 2 In this case, a voltage of 4V (dotted line 204 in the figure) is required to drive the HZO, and the area of ​​the HZO is reduced to 0.04 μm 2 (Dotted line 205 in the figure) or less.

[0472] Even under the conditions of FIG. 27B, the OS transistor can be a transistor that satisfies both the conditions of high breakdown voltage and miniaturization.

[0473] 27A, the graph in Fig. 28 is a graph that overlays the voltage required to rewrite data when the HZO breakdown voltage is set to 3 MV / cm and the HZO film thickness is set to 10 nm, 8 nm, and 6 nm. For breakdown voltages at HZO thicknesses of around 10 nm, which is the standard range, a configuration in which HZO is used in combination with OS transistors, which have excellent breakdown voltage, is effective, and is also effective for high integration of transistors and ferroelectric capacitors.

[0474] (Notes regarding the present specification) The above-described embodiments and the respective components in the embodiments will be described below with additional notes.

[0475] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. Furthermore, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0476] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or with the content (or even a part of the content) described in one or more other embodiments.

[0477] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0478] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0479] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0480] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0481] In this specification and the like, when describing the connection relationship of a transistor, the term "one of the source or drain" (or first electrode or first terminal) is used, and the other of the source and drain is referred to as "the other of the source or drain" (or second electrode or second terminal). This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0482] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0483] Furthermore, in this specification and the like, voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0484] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0485] In this specification, a switch refers to a device that has the function of being in a conductive state (on state) or a non-conductive state (off state) and controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows.

[0486] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0487] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0488] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, it enables the exchange of electrical signals between A and B. [Explanation of symbols]

[0489] BL: wiring, FE: ferroelectric layer, LE: electrode, MC: memory cell, M1: transistor, PL: wiring, UE: electrode, WL: wiring

Claims

[Claim 1] a memory cell having a capacitor with a ferroelectric layer between a first electrode and a second electrode; a first read operation of data from the memory cell is performed by applying a first voltage to the capacitor that does not cause polarization inversion of the ferroelectric layer; a second read operation of data from the memory cell is performed by applying a second voltage to the capacitor that does not cause polarization inversion of the ferroelectric layer; The second voltage is greater than the first voltage.

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