Semiconductor package

Abstract

To improve solder connection reliability by reducing solder stress caused by temperature change during package mounting.SOLUTION: A semiconductor package 1 includes: a semiconductor chip 20 in which an electrode 23 is formed on a first surface 21a that is a surface of a chip substrate 21 on which light is incident; a through hole 24 that reaches the electrode 23 from a second surface 21b side facing the first surface 21a of the chip substrate 21; a wiring layer 30 that is disposed on the second surface 21b side of the chip substrate 21 and is electrically connected to the electrode 23 via the through hole 24; a columnar electrode 50 that is electrically connected to the wiring layer 30; and a first conductive part 40 that is interposed between the columnar electrode 50 and the wiring layer 30. A side surface 53 of the columnar electrode 50 and the side surface 41 of the first conductive part 40 are covered with a sealing resin layer 60, and a second end part 52 of the columnar electrode 50 opposite to a first end part 51 connected to the first conductive part 40 is exposed from the sealing resin layer 60.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to semiconductor packages. [Background technology]

[0002] In recent years, in order to cope with the miniaturization and high integration of semiconductor chips, flip-chip mounting using CSP (Chip Scale Package) as a semiconductor package has been actively adopted.

[0003] Because the package size of a CSP is about the same as that of a semiconductor chip, it is small and has good productivity in wafer-level processes, but on the other hand, it has the disadvantage of low solder joint reliability during package assembly.The reason for the low solder joint reliability in CSP package assembly is that there is a large difference between the linear expansion coefficient (up to 3 ppm / °C) of the silicon that makes up the chip substrate of the semiconductor chip that is the CSP's base, and the linear expansion coefficient (15 to 20 ppm / °C) of the mounting substrate such as the motherboard on which the CSP is mounted.This difference in thermal expansion causes large stresses to be applied to the connection terminals and their surrounding areas due to temperature changes such as temperature cycles.

[0004] Patent document 1 discloses a device that includes a rewiring layer, a covering layer stacked on an insulating layer that covers a wiring layer formed on a semiconductor chip, and a stress relief layer that relieves stress applied to the semiconductor device between the rewiring layer and the covering layer, and a post that relieves stress associated with the solder (connection terminal portion). [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2012-19121 Summary of the Invention [Problem to be solved by the invention]

[0006] The device disclosed in Patent Document 1 has a stress relief layer below the redistribution layer, but this stress relief layer alone has a very small stress relief effect. Furthermore, in the device disclosed in Patent Document 1, the posts on which the connection terminals are formed are directly attached to the redistribution layer formed on the device surface, so stress applied to the solder is directly transmitted to the redistribution layer, etc., which may cause damage to the redistribution layer. Therefore, the device disclosed in Patent Document 1 has room for improvement in terms of solder connection reliability.

[0007] The present invention has been made in consideration of the above-mentioned circumstances, and specifically, an object of the present invention is to provide a semiconductor package that can reduce solder stress caused by temperature changes during package mounting and thereby improve solder connection reliability. [Means for solving the problem]

[0008] The above object can be achieved by any one of the following means (1) to (12).

[0009] (1) A semiconductor package comprising: a semiconductor chip having an electrode formed on a first surface of the chip substrate, the surface on which light is incident; a through hole extending from a second surface side of the chip substrate opposite the first surface to the electrode; a wiring layer disposed on the second surface side of the chip substrate and electrically connected to the electrode via the through hole; a pillar electrode electrically connected to the wiring layer; and a first conductive portion interposed between the pillar electrode and the wiring layer, wherein a side surface of the pillar electrode and a side surface of the first conductive portion are covered with a sealing resin layer, and a second end portion of the pillar electrode opposite a first end portion connected to the first conductive portion is exposed from the sealing resin layer.

[0010] (2) The semiconductor package according to (1), wherein the first conductive portion has a lower elastic modulus than the columnar electrode.

[0011] (3) A semiconductor package according to (1) or (2) above, wherein a second conductive portion having an area equal to or larger than the exposed surface is formed on the exposed surface of the second end of the columnar electrode.

[0012] (4) The semiconductor package according to any one of (1) to (3) above, wherein the columnar electrodes are formed of metal pins.

[0013] (5) The semiconductor package according to any one of (1) to (4) above, wherein the sealing resin layer contains a non-conductive filler.

[0014] (6) The semiconductor package according to any one of (1) to (5) above, wherein the sealing resin layer has a linear expansion coefficient equal to or greater than the linear expansion coefficient of the chip substrate of the semiconductor chip.

[0015] (7) The semiconductor package according to any one of (1) to (6) above, wherein the first conductive portion is formed of a conductive paste or solder.

[0016] (8) The semiconductor package according to (3) above, wherein the second conductive portion is formed of a material containing copper as a main component.

[0017] (9) The semiconductor package according to any one of (1) to (8) above, wherein the sealing resin layer has a groove formed in at least a part of the periphery of the columnar electrode.

[0018] (10) The semiconductor package according to (3) above, wherein a connection terminal portion is provided on the second end portion of the columnar electrode or the second conductive portion.

[0019] (11) The semiconductor package according to any one of (1) to (10) above, wherein the semiconductor chip is an image sensor.

[0020] (12) The semiconductor package according to (11), wherein the sealing resin layer has a light-shielding portion that blocks light having a wavelength sensitive to the image sensor. [Effects of the Invention]

[0021] A semiconductor package according to an embodiment of the present invention can reduce solder stress caused by temperature changes during package mounting, thereby improving solder connection reliability. [Brief explanation of the drawings]

[0022] [Figure 1] 1 is a cross-sectional view showing a state in which the semiconductor package according to the embodiment is mounted on a mounting substrate. [Figure 2] FIG. 1 is a cross-sectional view of a semiconductor package. [Figure 3A] FIG. 1 is a diagram showing step 1 of the method for manufacturing a semiconductor package. [Figure 3B] FIG. 10 is a diagram showing step 2 of the method for manufacturing a semiconductor package. [Figure 3C] FIG. 10 is a diagram showing step 3 of the method for manufacturing a semiconductor package. [Figure 3D] FIG. 10 is a diagram showing step 4 of the method for manufacturing a semiconductor package. [Figure 3E] FIG. 10 is a diagram showing step 5 of the method for manufacturing a semiconductor package. [Figure 3F] FIG. 10 is a diagram showing step 6 of the method for manufacturing a semiconductor package. [Figure 3G] FIG. 10 is a diagram showing step 7 of the semiconductor package manufacturing method. [Figure 3H] FIG. 10 is a diagram showing step 8 of the semiconductor package manufacturing method. [Figure 3I] FIG. 10 is a diagram showing step 9 of the semiconductor package manufacturing method. [Figure 3J] FIG. 1 is a diagram showing step 10 of the method for manufacturing a semiconductor package. [Figure 3K] FIG. 11 is a diagram showing step 11 of the method for manufacturing a semiconductor package. [Figure 3L] FIG. 12 is a diagram showing step 12 of the method for manufacturing a semiconductor package. [Figure 3M] 1A and 1B are diagrams illustrating a semiconductor package manufactured by a semiconductor package manufacturing method. [Figure 4] FIG. 10 is a cross-sectional view showing one form of a semiconductor package according to a first modified example. [Figure 5A] FIG. 10 is a cross-sectional view showing one form of a semiconductor package according to a second modified example. [Figure 5B] 10A and 10B are diagrams showing another form of the semiconductor package of the second modified example. [Figure 6]10 is a graph showing the results of a solder life simulation for an example and a comparative example. DETAILED DESCRIPTION OF THE INVENTION

[0023] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience. Meanwhile, the embodiments described below are merely examples, and various modifications are possible from such embodiments.

[0024] Hereinafter, the terms "upper" and "above" may include not only what is directly above in contact with something, but also what is above without contact. Similarly, the terms "lower" and "below" may include not only what is directly below in contact with something, but also what is below without contact.

[0025] The singular expression includes the plural expression unless the context clearly dictates otherwise. Furthermore, when a part "includes," "comprises," or "has" a certain element, it does not mean that it excludes other elements, but that it may further include other elements, unless otherwise specified to the contrary.

[0026] Unless explicitly stated or stated to the contrary, steps constituting a method may be performed in any suitable order, and are not necessarily limited to the order of the steps described. The use of any examples or exemplary terms is merely for the purpose of illustrating the technical idea, and the scope of the invention is not limited by the examples or exemplary terms, except as limited by the scope of the claims.

[0027] In the following description, when ordinal numbers such as "first" and "second" are used, unless otherwise specified, they are used for convenience and do not stipulate any particular order.

[0028] The semiconductor package 1 according to this embodiment will be described below. As shown in Figures 1 and 2, the semiconductor package 1 is a package (CSP) in which a semiconductor chip 20 is configured by a solid-state imaging element (CMOS image sensor).

[0029] 1, the semiconductor package 1 includes a transparent substrate 10, a semiconductor chip 20, a wiring layer 30, a first conductive portion 40, columnar electrodes 50, and a sealing resin layer 60. The semiconductor package 1 can be mounted on a mounting substrate 200 via connection terminal portions 80, as shown in FIG.

[0030] The transparent substrate 10 is made of a transparent material having optical transparency, such as a glass material or a resin material such as polyimide. The planar size of the transparent substrate 10 is equal to or larger than the planar size of the chip substrate 21 of the semiconductor chip 20. As shown in FIG. 2, the transparent substrate 10 has a first surface 10a, which is a light incident surface, and a second surface 10b opposite the first surface 10a. The second surface 10b of the transparent substrate 10 and the first surface 21a of the chip substrate 21 of the semiconductor chip 20 are bonded together via a bonding part 2 made of a sealant (DAM agent) or the like in a facing state. In FIG. 1, the first surface 10a of the transparent substrate 10 is the upper surface of the transparent substrate 10, and the second surface 10b of the transparent substrate 10 is the lower surface of the transparent substrate 10.

[0031] The semiconductor chip 20 has a chip substrate 21 made of silicon or the like. An IC circuit pattern or the like is formed on a first surface 21a of the chip substrate 21. In Fig. 2, the first surface 21a of the chip substrate 21 of the semiconductor chip 20 is the upper surface (incident surface) of the chip substrate 21, and the second surface 21b of the chip substrate 21 is the lower surface of the chip substrate 21.

[0032] The semiconductor chip 20 has a light receiving area in which multiple pixels that convert incident light into electrical signals are arranged in rows and columns, and can be configured as a CMOS image sensor that is equipped with a microlens (on-chip lens) 22, as well as color filters, photodiodes, pixel circuits, etc. (not shown).

[0033] Electrodes 23 are formed on the first surface 21a of the semiconductor chip 20, and through holes (vias) 24 are formed from the second surface 21b of the chip substrate 21 to the electrodes 23 so as to be electrically connected to the electrodes 23. The through holes 24 can be formed by a known processing method such as deep reactive ion etching (DRIE).

[0034] An insulating layer 70 is formed on the second surface 21b and side surfaces of the semiconductor chip 20 and the side surfaces of the through-holes 24. The insulating layer 70 is formed by a known thin film formation method such as vapor deposition, sputtering, or CVD, and at least the portion formed on the surface facing the electrode 23, which corresponds to the bottom of the through-holes 24, is removed.

[0035] The wiring layer 30 is formed by laminating on the insulating layer 70. The wiring layer 30 can be formed by laminating a single layer or multiple layers of metal materials such as copper (Cu), aluminum (Al), gold (Au), etc. The wiring layer 30 can be formed by a known wiring formation method such as photolithography.

[0036] A first conductive portion 40 is formed by laminating on the wiring layer 30. The first conductive portion 40 is interposed between the columnar electrode 50 and the wiring layer 30, and electrically connects the columnar electrode 50 and the wiring layer 30. The first conductive portion 40 can be formed from a conductive paste such as a conductive adhesive containing copper particles, or solder. The first conductive portion 40 can be formed by a known printing method such as screen printing or inkjet printing.

[0037] The elastic modulus of the first conductive part 40 is preferably lower than that of the columnar electrode 50. In other words, the relationship in magnitude between the elastic moduli of the first conductive part 40 and the columnar electrode 50 preferably satisfies the relationship "elastic modulus of first conductive part < elastic modulus of columnar electrode." When the semiconductor package 1 has a first conductive part 40 having an elastic modulus lower than that of the columnar electrode 50 formed between the wiring layer 30 and the columnar electrode 50, the stress acting on the connection terminal part 80 due to the difference in thermal expansion can be effectively reduced.

[0038] The columnar electrode 50 is formed by being laminated on the first conductive portion 40. The columnar electrode 50 is an electrode member having a first end portion 51 connected to the first conductive portion 40, a second end portion 52 on the axially opposite side of the first end portion 51 where the connection terminal portion 80 and the like are formed, and a side surface 53 connecting the first end portion 51 and the second end portion 52. The columnar electrode 50 can be formed from a metal pin (copper pin) whose main component is copper, or a columnar member made of copper plating formed by a known plating method such as electroplating or chemical plating. By using a copper pin for the columnar electrode 50, it is possible to simply place the metal pin that functions as an electrode at the position where the first conductive portion 40 is formed, thereby improving assembly efficiency during manufacturing.

[0039] The sealing resin layer 60 is formed so as to cover at least the side surfaces of the first conductive parts 40 and the side surfaces of the columnar electrodes 50. As shown in Fig. 2, the sealing resin layer 60 is formed so as to cover the wiring layer 30 while exposing the second ends 52 of the columnar electrodes 50. A connection terminal part 80 and the like can be formed on the exposed surface 52a of the second ends 52.

[0040] The encapsulating resin layer 60 is made of an insulating resin such as an epoxy resin that can be used as a potting resin. The encapsulating resin layer 60 preferably contains a non-conductive filler such as a spherical or flat inorganic filler such as silica. The content of the non-conductive filler in the encapsulating resin layer 60 can be adjusted to maximize the solder connection reliability of the semiconductor package 1. By adjusting the filler content of the encapsulating resin layer 60, the linear expansion coefficient and elastic modulus of the encapsulating resin layer 60 itself can be adjusted. Therefore, by including the encapsulating resin layer 60 with a filler content adjusted to maximize the solder connection reliability, the semiconductor package 1 becomes a package with excellent solder connection reliability.

[0041] The sealing resin layer 60 has a linear expansion coefficient equal to or greater than that of the chip substrate 21 of the semiconductor chip 20. The linear expansion coefficient of the sealing resin layer 60 is 5 to 15 ppm / °C, which is higher than that of the chip substrate 21 of the semiconductor chip 20 (up to 3 ppm / °C) and close to that of the mounting substrate 200 (15 to 20 ppm / °C). By being formed between the semiconductor chip 20 and the mounting substrate 200, the sealing resin layer 60 can function as a stress relaxation layer that significantly reduces stress on the connection terminal portions 80 due to temperature changes that may occur between the semiconductor chip 20 and the mounting substrate 200.

[0042] When the semiconductor chip 20 is configured as an image sensor, the encapsulating resin layer 60 preferably has a light-shielding portion 61 that blocks light of the wavelength to which the image sensor is sensitive. The encapsulating resin layer 60 may contain a light-shielding material such as carbon or a filler to achieve the above-mentioned light-shielding properties, allowing the entire layer to function as the light-shielding portion 61. Alternatively, the encapsulating resin layer 60 may be formed with a film material or layer that achieves the above-mentioned light-shielding properties, so as to cover part or all of the encapsulating resin layer 60 as the light-shielding portion 61. By forming the light-shielding portion 61 in the encapsulating resin layer 60, the semiconductor package 1 equipped with an image sensor can reduce the adverse effects on the sensor of stray light such as reflected light and scattered light.

[0043] The connection terminal portion 80 is formed of a conductive material such as solder, and is formed to be connected to the exposed surface 52a of the second end portion 52 of the columnar electrode 50. Note that the semiconductor package 1 may also be configured so that the connection terminal portion 80 is not formed on the second end portion 52 of the columnar electrode 50.

[0044] Next, a description will be given of a method for manufacturing the semiconductor package 1. The method for manufacturing the semiconductor package 1 includes the following steps 1 to 12. FIGS. 3A to 3L show configuration diagrams of each step (step 1 to step 12) included in the manufacturing process of the semiconductor package 1.

[0045] (Process 1) 3A, in step 1, a sealant S that functions as a bonding portion 2 is applied to a second surface Gb that faces a first surface Ga of a glass substrate G that will become a transparent substrate 10. The sealant S is applied so as to cover the periphery of each package and the boundary portion where the packages will be separated.

[0046] (Process 2) In step 2, as shown in Fig. 3B, a process is performed in which the second surface Gb of the glass substrate G, on which the sealant S has been applied, and the first surface Wa of the semiconductor wafer W, which will become the chip substrate 21 of the semiconductor chip 20, are bonded in a facing state. The semiconductor wafer W has microlenses 22, electrodes 23, and other components that make up the image sensor mounted in the light receiving area for each package on the first surface Wa. In step 2, the sealant S is cured to form a bonded portion 2.

[0047] (Step 3) In step 3, as shown in FIG. 3C, the second surface Wb of the semiconductor wafer W is subjected to back grinding so as to have a thickness corresponding to a predetermined chip size.

[0048] (Step 4) In step 4, as shown in FIG. 3D, a process of forming through-holes 24 by etching from the second surface Wb side of the semiconductor wafer W is performed. The through-holes 24 can be formed by deep reactive ion etching (DRIE). The through-holes 24 are formed at the positions where the electrodes 23 are to be formed and at the boundary positions of the package. By forming the through-holes 24, part of the electrodes 23 and part of the bonding portions 2 at the boundary portions are exposed.

[0049] (Step 5) 3E, step 5 involves forming an insulating layer 70 over the entire second surface Wb of the semiconductor wafer W. The insulating layer 70 can be formed by evaporation, sputtering, CVD, or the like.

[0050] (Step 6) 3F, in step 6, the insulating layer 70 located at the bottom of the through-hole 24 is removed to expose a portion of the electrode 23 so as to enable electrical conduction to the electrode 23. The process of removing the insulating layer 70 can be performed by etching or the like.

[0051] (Step 7) 3G, step 7 involves forming the wiring layer 30 on the insulating layer 70. The wiring layer 30 is formed so as to be electrically connected to the electrode 23 using photolithography and plating.

[0052] (Step 8) In step 8, as shown in FIG. 3H, a conductive paste is applied to form the first conductive portion 40. The first conductive portion 40 is formed on the wiring layer 30 at a position corresponding to the position where the columnar electrode 50 is to be formed. The process of forming the first conductive portion 40 can be performed by screen printing, inkjet printing, or the like, with a mask applied to areas other than the formation position.

[0053] (Step 9) In step 9, as shown in FIG. 3I, a process of placing the columnar electrode 50 on the first conductive portion 40 is performed. The process of placing the columnar electrode 50 is similar to the ball mounting method and can be performed by applying a mask to the area other than the first conductive portion 40 so that the first conductive portion 40 is exposed, as shown in FIG. 3H, transferring multiple copper pins that will become the columnar electrodes 50 over the mask and placing the copper pins on each of the first conductive portions 40 through openings in the mask to make contact with them, and then removing the mask and drying, baking, and hardening the first conductive portion 40. The end of the columnar electrode 50 that contacts the first conductive portion 40 is the first end 51.

[0054] (Step 10) 3J, step 10 involves forming a sealing resin layer 60. The sealing resin layer 60 is formed by applying a resin containing a non-conductive filler in an epoxy resin or the like, and then performing a grinding process so that the exposed surface 52a of the second end 52 of the columnar electrode 50 is exposed. As a result, the sealing resin layer 60 is formed to cover the first conductive part 40, the side surface of the columnar electrode 50, and the wiring layer 30, with the second end 52 of the columnar electrode 50 exposed.

[0055] (Step 11) 3K, step 11 involves forming the connection terminal portion 80 on the exposed surface 42a of the second end portion 52 of the columnar electrode 50. The process of forming the connection terminal portion 80 can be performed by a ball mounting method, a screen printing method, or the like. In step 11, from the viewpoint of ease of mounting, it is preferable to form the height positions of the contact surfaces of the connection terminal portions 80 relative to the mounting substrate 200 so that they are at approximately the same position in the thickness direction of the semiconductor package 1.

[0056] (Step 12) 3L, step 12 involves cutting the semiconductor wafer W at predetermined locations to singulate the semiconductor packages 1. Through the above steps, the semiconductor packages 1 shown in FIG. 3M are manufactured.

[0057] The above-described method for manufacturing a semiconductor package 1 may include, as necessary, a step of carrying out a process other than steps 1 to 12 (such as a step of carrying out a cleaning process). In addition, in the method for manufacturing a semiconductor package 1, the order of the steps may be appropriately changed as long as the configuration and function of the manufactured semiconductor package 1 do not deviate from the gist of the present invention.

[0058] In the manufacturing method described above, the semiconductor package 1 may be configured so that the connection terminal portion 80 is not formed at the second end portion 52 of the columnar electrode 50. In this case, the processing of step 11 is omitted.

[0059] The semiconductor package 1 of the present invention can be implemented by appropriately modifying it as shown in the following modified examples. Note that the following description of each modified example mainly focuses on the differences from the above-described embodiment, and components having equivalent functions to those of other embodiments are denoted by the same or related reference numerals, and detailed description thereof is omitted, and no particular mention is made. Furthermore, the configuration, members, and usage method may be the same as those of each embodiment. Furthermore, each modified example can be implemented in combination with other embodiments by appropriately selecting necessary components from those shown in each modified example, within the scope of the gist of the present invention.

[0060] A semiconductor package 1A according to the first modified example will be described.

[0061] 4 shows a configuration diagram of a semiconductor package 1A of Modified Example 1. The semiconductor package 1A differs from other types of packages in that a second conductive portion 90 is formed at the second end 52 of the columnar electrode 50.

[0062] The second conductive portion 90 is a conductive layer interposed between the columnar electrode 50 and the connection terminal portion 80, and electrically connects the columnar electrode 50 and the connection terminal portion 80. The second conductive portion 90 is made of a conductive material, and is preferably formed of a material containing copper as a main component, such as copper paste or copper plating. The second conductive portion 90 can be formed by screen printing, inkjet printing, or the like, with a mask applied to areas other than the formation position.

[0063] The second conductive portion 90 is formed to have an area equal to or larger than the area of ​​the exposed surface 52a of the second end portion 52 of the columnar electrode 50. This allows the semiconductor package 1 to adjust the size of the connection terminal portion 80 in accordance with the area size of the second conductive portion 90 when forming the connection terminal portion 80 on the second conductive portion 90. Note that, although the semiconductor package 1A in the configuration shown in FIG. 4 has the connection terminal portion 80 formed on the second conductive portion 90, it may also be configured not to have the connection terminal portion 80.

[0064] In the method for manufacturing the semiconductor package 1A, the step of forming the second conductive portion 90 can be performed between step 10 shown in Fig. 3J and step 11 shown in Fig. 3K. That is, after the sealing resin layer 60 is formed in step 10, the second conductive portion 90 can be formed on the exposed surface 52a of the second end portion 52 of the columnar electrode 50 exposed from the sealing resin layer 60.

[0065] Next, a semiconductor package 1B according to a second modified example will be described.

[0066] 5 shows a configuration diagram of a semiconductor package 1B. The semiconductor package 1B differs from other types of packages in that a groove 62 is formed in a sealing resin layer 60.

[0067] The sealing resin layer 60 has a groove 62. The groove 62 has the effect of significantly reducing deformation (warping, etc.) of the package itself due to stress when the sealing resin layer 60 is soldered and temperature changes.

[0068] As shown in Fig. 5A, the groove 62 can be formed between adjacent columnar electrodes 50 in a direction intersecting the thickness direction of the semiconductor package 1B (the left-right direction in the figure). As shown in Fig. 5B, the groove 62 can have a shape in which a portion of the periphery of the semiconductor package 1B is removed. The groove 62 shown in Figs. 5A and 5B may be formed in advance by forming the sealing resin layer 60 into the shape shown in the figure, or may be shaped by removing a portion from the shape shown in Fig. 2, etc.

[0069] Note that the groove portion 62 is not limited to the shape or the position shown in Figures 5A and 5B, as long as it is formed at a position where the stress acting on the sealing resin layer 60 can be alleviated and has a shape that provides a stress alleviation effect.

[0070] In the method for manufacturing the semiconductor package 1B, the step of forming the groove 62 can be performed between step 10 shown in Fig. 3J and step 11 shown in Fig. 3K. That is, after the encapsulating resin layer 60 is formed in step 10, the groove 62 can be formed by removing a portion of the encapsulating resin layer 60. Note that if the encapsulating resin layer 60 is formed with the groove 62 already formed, the above-mentioned removal step is unnecessary.

[0071] As described above, the semiconductor packages 1, 1A, and 1B according to the present invention comprise a semiconductor chip 20 having an electrode 23 formed on a first surface 21a of the chip substrate 21, which is the surface onto which light is incident; a through hole 24 extending from the second surface 21b of the chip substrate 21 opposite the first surface 21a to the electrode 23; a wiring layer 30 arranged on the second surface 21b of the chip substrate 21 and electrically connected to the electrode 23 via the through hole 24; a columnar electrode 50 electrically connected to the wiring layer 30; and a first conductive portion 40 interposed between the columnar electrode 50 and the wiring layer 30, wherein a side surface 53 of the columnar electrode 50 and a side surface 41 of the first conductive portion 40 are covered with a sealing resin layer 60, and a second end portion 52 opposite to the first end portion 51 of the columnar electrode 50 connected to the first conductive portion 40 is exposed from the sealing resin layer 60.

[0072] The semiconductor package 1 has the first conductive portion 40 interposed between the wiring layer 30 and the columnar electrode 50, and the sealing resin layer 60 formed so as to cover the side surface 41 of the first conductive portion 40 and the side surface 53 of the columnar electrode 50, so that the solder stress caused by temperature changes when the semiconductor package 1 is mounted on the mounting substrate 200 is significantly reduced. Therefore, the semiconductor package 1 has a dramatically improved solder connection reliability. [Example]

[0073] The effects of the present invention will be explained using the following examples and comparative examples, although the technical scope of the present invention is not limited to the following examples.

[0074] In the following evaluation test, the solder connection reliability of the semiconductor package according to the present invention was evaluated based on the results of a simulation of solder life.

[0075] <Test Overview> The evaluation test was carried out as follows. The structural analysis software used in the evaluation test was "Marc2023 (manufactured by MSC Software Co., Ltd.)." The solder life simulation can be carried out by a known method such as the method described in a prior art document ("Thermal Fatigue Life Prediction of Lead-Free Solder Joints," Technical Report, Technology Introduction, 2013-12, No. 49, by Tetsuya Ima, Yamaha Motor Co., Ltd.).

[0076] The following conditions were set for the simulation. The example model was a semiconductor package of the present invention as shown in Figure 2, while the comparative example model was a typical CSP semiconductor package. A quarter-scale model was used for each model to ensure symmetry. The "quarter-scale model" refers to a simulation model that simulates only a quarter of the package, with horizontal and vertical symmetry, rather than the entire package. The element class was a hexahedron with 20 nodes. The boundary conditions included symmetry constraints and time-dependent temperature for all nodes. The temperature-dependent temperature test conditions were as follows: the initial temperature was 175°C, the curing temperature of the stress relief layer, and after cooling to room temperature (25°C), 10 cycles of temperature cycling from -55°C to 125°C were performed. Temperature-independent elastic properties were defined for the substrate, semiconductor chip, transparent substrate, wiring layer, first conductive layer, and DAM agent, while viscoelasticity was set for the encapsulation resin layer (potting resin). Plasticity was also set for the solder.

[0077] In order to determine the solder life, the test obtained the time-plastic strain history of the node with the maximum total plastic strain from the simulation results, and from this, the plastic strain at the 10th cycle was extracted and used as the plastic strain amplitude. The number of solder life cycles was calculated from the obtained plastic strain amplitude and the Coffin-Manson law. It is known that the number of solder fatigue life cycles follows the Coffin-Manson law.

[0078] <Evaluation results> The evaluation results are shown in Figure 6. The evaluation results shown in Figure 6 show the predicted results for the number of temperature cycles for the example and comparative example. The predicted results in Figure 6 show that the greater the number of temperature cycles, the longer the solder life, indicating higher solder connection reliability.

[0079] As shown in Figure 6, the number of temperature cycles in the comparative example was 182. In contrast, the number in the working example was 952. From these results, it was confirmed that the solder life was increased by approximately five times when the structure of the present invention was adopted.

[0080] As described above, the semiconductor package of the present invention comprises a first conductive portion interposed between a columnar electrode electrically connected to the wiring layer of the semiconductor chip, and a sealing resin layer covering the side surfaces of the columnar electrode and the side surfaces of the first conductive portion, and therefore can be said to be able to reduce solder stress caused by temperature changes during package assembly and improve solder connection reliability. [Explanation of symbols]

[0081] 1, 1A, 1B semiconductor packages, 2 joints, 10 transparent substrate, 20 semiconductor chips, 21 chip substrate, 21a: a first surface of the chip substrate; 21b a second surface of the chip substrate; 22 microlenses, 23 electrodes, 24 through holes, 30 wiring layers, 40 first conductive part, 41 side surface of the first conductive part, 50 columnar electrodes, 51 first end; 52 second end; 52a: exposed surface of the second end; 53 Side of the columnar electrode, 60 Sealing resin layer, 61 light-shielding part, 62 groove, 70 insulating layer, 80 connection terminal portion, 90 second conductive portion, 200 mounting boards, S sealant.

Claims

1. a semiconductor chip having an electrode formed on a first surface of the chip substrate, the first surface being a surface on which light is incident; a through hole extending from a second surface side of the chip substrate opposite the first surface to the electrode; a wiring layer disposed on the second surface side of the chip substrate and electrically connected to the electrode via the through hole; a pillar-shaped electrode electrically connected to the wiring layer; and a first conductive portion interposed between the pillar-shaped electrode and the wiring layer; a side surface of the columnar electrode and a side surface of the first conductive portion are covered with a sealing resin layer; a second end of the columnar electrode opposite to a first end connected to the first conductive portion, the second end being exposed from the sealing resin layer;

2. The semiconductor package according to claim 1 , wherein the first conductive portion has a lower elastic modulus than the columnar electrode.

3. The semiconductor package according to claim 1 , wherein a second conductive portion having an area equal to or larger than the exposed surface is formed on the exposed surface of the second end of the columnar electrode.

4. The semiconductor package according to claim 1 , wherein the pillar-shaped electrodes are formed of metal pins.

5. The semiconductor package according to claim 1 , wherein the sealing resin layer contains a non-conductive filler.

6. 2. The semiconductor package according to claim 1, wherein the coefficient of linear expansion of the sealing resin layer is equal to or greater than the coefficient of linear expansion of the chip substrate of the semiconductor chip.

7. The semiconductor package according to claim 1 , wherein the first conductive portion is formed of a conductive paste or a solder.

8. The semiconductor package according to claim 3 , wherein the second conductive portion is formed of a material containing copper as a main component.

9. The semiconductor package according to claim 1 , wherein the sealing resin layer has a groove formed in at least a part of the periphery of the columnar electrode.

10. The semiconductor package according to claim 3 , wherein a connection terminal portion is provided on the second end portion of the columnar electrode or the second conductive portion.

11. The semiconductor package according to claim 1 , wherein the semiconductor chip is an image sensor.

12. The semiconductor package according to claim 11 , wherein the sealing resin layer has a light-shielding portion that blocks light having a sensitivity wavelength of the image sensor.

Images