Arithmetic device, physical arithmetic device, arithmetic method, and arithmetic program

Abstract

To provide an arithmetic device capable of performing high-speed processing.SOLUTION: An arithmetic device includes a first arithmetic unit that secures, in a first memory space, a data arrangement memory area for storing data arranged in two or more dimensions, separates the data stored in the data arrangement memory area into communication target data and non-communication target data, secures, in the first memory space, a first table memory area for storing a first table in which a memory address of the communication target data and an identification number are associated with each other, generates the first table and stores the first table in the first table memory area, secures a first transmission buffer that stores the data in order of the identification number in the first memory space, and stores the communication target data in the first transmission buffer with reference to the memory address of the first table corresponding to the identification number.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a calculation device, a physical calculation device, a calculation method, and a calculation program. [Background technology]

[0002] Stencil calculations using a computing device can simulate changes in physical quantities in a spatial grid (mesh). In stencil calculations, when calculating data for each element arranged in a spatial grid, data in a predetermined area (stencil) around the element is referenced. Then, by applying the finite difference method or finite volume method to the stencil calculations and solving partial differential equations, changes in data such as physical quantities for each element can be simulated.

[0003] Non-Patent Document 1 describes simulating changes in data in a mesh that is refined by adaptive mesh refinement (AMR).

[0004] To reproduce real-world phenomena using stencil calculations, huge arrays of two or more dimensions are required, which increases the calculation load and memory usage. Therefore, to speed up calculations and distribute memory usage, parallelization is implemented, in which the array is divided into multiple parts and assigned to multiple calculation units. Parallelization can be achieved, for example, by distributing memory space into multiple memory areas and having each calculation unit refer to its assigned memory area.

[0005] Distributed memory can reduce the amount of memory used. On the other hand, distributed memory requires data transfer between memories to build stencils for each element near the boundaries of the divided array. When using the finite difference method or finite volume method, this data transfer between memories is required almost every step, so it is necessary to reduce this processing time. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Marsha J. Berger, Joseph Oliger, “Adaptive Mesh Refinement for Hyperbolic Partial Differential Equations”, Journal of Computational Physics, Volume 53, Issue 3, 484-512 (1984) Summary of the Invention [Problem to be solved by the invention]

[0007] In Non-Patent Document 1, the data of each mesh is managed using a tree structure, which makes the discontinuity of physical addresses particularly noticeable. In this case, it is preferable to pack the data into continuous memory, but the packing process itself requires complex random access, which tends to reduce processing speed. In particular, when using a GPU as a computation accelerator, a straightforward implementation of packing processing can easily lead to a reduction in processing speed due to the warp processing and memory access mechanisms in the streaming multiprocessor within the GPU.

[0008] The present invention has been made in view of the above, and has an object to provide a calculation device, a physics calculation device, a calculation method, and a calculation program that are capable of high-speed processing. [Means for solving the problem]

[0009] In order to solve the above problems and achieve the objectives, [1] A calculation device according to one aspect of the present invention includes a first calculation unit that allocates a memory area for data array in a first memory space to store data arranged in two or more dimensions, separates the data stored in the memory area for data array into data to be communicated and data not to be communicated, allocates a memory area for a first table in the first memory space to store a first table that corresponds memory addresses of the data to be communicated with identification numbers, generates the first table and stores it in the memory area for the first table, allocates a first transmission buffer in the first memory space to store the data in the order of the identification numbers, and stores the data to be communicated in the first transmission buffer by referring to the memory address of the first table to which the identification number corresponds.

[0010] [2] In addition, in a calculation device according to one aspect of the present invention, in the above [1], the first calculation unit reserves a memory area for a second table in the first memory space to store the second table generated by the second calculation unit and stored in the second memory space, reserves a receiving buffer in the first memory space to store the second transmission buffer generated by the second calculation unit and stored in the second memory space, stores the second table in the memory area for the second table, stores the second transmission buffer in the receiving buffer, and stores the communication target data of the receiving buffer in the memory area for data array by referencing the memory addresses of the second table in the order of the identification numbers of the second table.

[0011] [3] Furthermore, in the arithmetic device according to an aspect of the present invention, in the above [2], the second memory space is adjacent to the first memory space.

[0012] [4] Furthermore, in the calculation device according to one aspect of the present invention, in any one of the above [1] to [3], the data is a physical quantity held by a spatial lattice arranged in two or more dimensions.

[0013] [5] Furthermore, in the calculation device according to one aspect of the present invention, in the above [4], the spatial grid is subdivided by an adaptive subdivision method.

[0014] [6] Furthermore, in the calculation device according to one aspect of the present invention, in the above [5], the first calculation unit includes a predetermined number of the spatial lattices, and stores the data generated by arranging outer shell leaves that are adjacent to the boundary of the process calculated by the first calculation unit in the spatial lattice in the memory area for data arrangement.

[0015] [7] Furthermore, in the calculation device according to one aspect of the present invention, in any one of the above [4] to [6], the first calculation unit simulates a change in the physical quantity in the spatial lattice by stencil calculation.

[0016] [8] A calculation device according to one aspect of the present invention allocates, in a first memory space, a memory area for data arrays for storing data arranged in two or more dimensions, separates the data stored in the memory area for data arrays into data to be communicated and data not to be communicated, allocates, in the first memory space, a memory area for first tables for storing a first table that associates memory addresses of the data to be communicated with identification numbers, generates the first table and stores it in the memory area for first tables, allocates, in the first memory space, a first transmission buffer for storing the data in the order of the identification numbers, and stores the data to be communicated in the first transmission buffer by referring to the memory addresses of the first table corresponding to the identification numbers. a second calculation unit that allocates a second data array memory area in a second memory space adjacent to the first memory space, the second memory space being adjacent to the first memory space, the first table memory area for storing the first table, the second memory space being adjacent to the first memory space, a receiving buffer for storing the first transmission buffer, the first table in the memory area for the first table in the second memory space, the first transmission buffer in the receiving buffer, and stores the communication target data of the receiving buffer in the second data array memory area by referring to the memory addresses of the first table in the order of the identification numbers of the first table.

[0017] [9] A physical calculation device according to one aspect of the present invention is a physical calculation device that simulates changes in physical quantities in a spatial grid that is subdivided by an adaptive refinement method by using multiple calculation units, including a first calculation unit and a second calculation unit, in parallel, wherein the first calculation unit secures a memory area for data arrangement in a first memory space for storing data that is arranged in two or more dimensions, includes a predetermined number of the spatial grids, stores the data generated by arranging outer leaves that are in contact with the boundary of a process calculated by the first calculation unit in the spatial grid in the memory area for data arrangement, separates the data stored in the memory area for data arrangement into data to be communicated and data not to be communicated, secures a memory area for first table in the first memory space for storing a first table that associates memory addresses of the data to be communicated with identification numbers, generates the first table and stores it in the memory area for first table, and stores the data in the order of the identification numbers. a second table memory area is allocated in the first memory space to store a second table that is generated by the second calculation unit and stored in a second memory space adjacent to the first memory space; a receiving buffer is allocated in the first memory space to store the second transmission buffer that is generated by the second calculation unit and stored in the second memory space; the second table is stored in the second table memory area; the second transmission buffer is stored in the receiving buffer; the memory addresses of the second table are referenced in the order of the identification numbers of the second table to store the communication target data in the receiving buffer in the data array memory area; and a change in the physical quantity in the spatial lattice is simulated by stencil calculation.

[0018]

[10] Furthermore, a calculation method according to one aspect of the present invention allocates a memory area for data array in a first memory space for storing data arranged in two or more dimensions, separates the data stored in the memory area for data array into data to be communicated and data not to be communicated, allocates a memory area for a first table in the first memory space for storing a first table that corresponds memory addresses of the data to be communicated with identification numbers, generates the first table and stores it in the memory area for the first table, allocates a first transmission buffer in the first memory space for storing the data in the order of the identification numbers, and stores the data to be communicated in the first transmission buffer by referencing the memory address of the first table to which the identification number corresponds.

[0019]

[11] Furthermore, a calculation program according to one aspect of the present invention causes a first calculation unit to execute the following processes: allocating a memory area for data array in a first memory space for storing data arranged in two or more dimensions; separating the data stored in the memory area for data array into data to be communicated and data not to be communicated; allocating a memory area for a first table in the first memory space for storing a first table that corresponds memory addresses of the data to be communicated with identification numbers; generating the first table and storing it in the memory area for the first table; allocating a first transmission buffer in the first memory space for storing the data in the order of the identification numbers; and referencing the memory address of the first table to which the identification number corresponds, and storing the data to be communicated in the first transmission buffer. [Effects of the Invention]

[0020] According to the present invention, it is possible to realize a calculation device, a physical calculation device, a calculation method, and a calculation program capable of high-speed processing. [Brief explanation of the drawings]

[0021] [Figure 1] FIG. 1 is a block diagram showing the configuration of a physical calculation device according to one embodiment of the present invention. [Figure 2]FIG. 2 is a flowchart showing the process of packing data by the calculation unit. [Figure 3] FIG. 3 is a diagram showing the boundaries of a process in a spatial grid. [Figure 4] FIG. 4 is a diagram illustrating an example of a two-dimensional data array. [Figure 5] FIG. 5 is a diagram showing how data is transmitted from leaf L12 to leaf L20. [Figure 6] FIG. 6 is a diagram showing how data is transmitted from leaf L12 to leaf L23. [Figure 7] FIG. 7 is a diagram showing how data is transmitted from leaf L12 to leaf L24. [Figure 8] FIG. 8 is a diagram showing the lattice with which leaf L12 communicates. [Figure 9] FIG. 9 is a diagram showing the relationship between a two-dimensional data array and a transmission buffer and table. [Figure 10] FIG. 10 is a flowchart showing the process of storing communication target data in the transmission buffer by referring to a table. [Figure 11] FIG. 11 is a flowchart showing the process of unpacking data by the calculation unit. [Figure 12] FIG. 12 is a diagram showing an outline of the embodiment. [Figure 13] FIG. 13 is a diagram showing a spatial grid in an embodiment. [Figure 14] FIG. 14 is a diagram showing the processing speed in the embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, embodiments of a calculation device, a physical calculation device, a calculation method, and a calculation program according to the present invention will be described with reference to the drawings. Note that the present invention is not limited to these embodiments. In the following embodiments, the present invention can be generally applied to a calculation device, a physical calculation device, a calculation method, and a calculation program that include multiple calculation units.

[0023] In addition, in the drawings, the same or corresponding elements are appropriately designated by the same reference numerals. It should be noted that the drawings are schematic, and the dimensional relationships and ratios of each element may differ from the actual situation. The dimensional relationships and ratios may also differ between the drawings.

[0024] (Embodiment) [Configuration of the arithmetic unit] Fig. 1 is a block diagram showing the configuration of a physics calculation device according to one embodiment of the present invention. As shown in Fig. 1, calculation device 1 according to this embodiment includes a control unit 11, a GPU 12, and a storage unit 13. Using GPU 12, which has multiple calculation units in parallel, calculation device 1 simulates changes in physical quantities in a spatial grid (hereinafter also referred to as a "mesh" or simply a "grid") that has been refined by adaptive mesh refinement (AMR).

[0025] The calculation device 1 simulates changes in physical quantities at each spatial grid by applying the finite difference method or the finite volume method to the spatial grid and solving partial differential equations. The calculation device 1 distributes memory space into multiple contiguous memory areas, and each calculation unit references an assigned memory area. Similarly, the calculation device 1 also divides the spatial grid into multiple areas, and each divided area is assigned to a different calculation unit.

[0026] Each calculation unit packs data to be communicated, such as physical quantities, held by the spatial grid, and stores it in an allocated memory area. On the other hand, each calculation unit reads and unpacks data that has been packed and stored in a memory area by a calculation unit that calculates an adjacent area in the spatial grid.

[0027] The control unit 11 includes, as hardware, processors such as a CPU (Central Processing Unit), a DSP (Digital Signal Processor), an FPGA (Field-Programmable Gate Array), and a GPU (Graphics Processing Unit), as well as a main memory such as a RAM (Random Access Memory) and a ROM (Read Only Memory).

[0028] The GPU 12 is a GPU that includes a plurality of calculation units (calculation units 21, 22, 23, . . . ) and a device memory. The GPU 12 executes a physics calculation program stored in the storage unit 13 to perform a physics calculation method.

[0029] The storage unit 13 is configured with a storage medium selected from a volatile memory such as RAM, a non-volatile memory such as ROM, an erasable programmable ROM (EPROM), a hard disk drive (HDD), and removable media. The main memory may be included in the storage unit 13. The removable media is, for example, a universal serial bus (USB) memory or a disc storage medium such as a compact disc (CD), a digital versatile disc (DVD), or a Blu-ray (registered trademark) disc (BD). The storage unit 13 may also be configured with a computer-readable storage medium such as an externally attachable memory card.

[0030] The storage unit 13 can store an operating system (OS), various programs, various tables, various databases, and the like for executing the operations of the control unit 11 and the GPU 12. Here, the various programs include a physics calculation program that realizes the physics calculation method according to this embodiment. These various programs can also be recorded on computer-readable recording media such as a hard disk, flash memory, CD-ROM, DVD-ROM, or flexible disk, and widely distributed. The storage unit 13 may also be provided in another server that can communicate via various networks.

[0031] [Physical calculation method] Next, the physics calculation method will be described. The physics calculation method is realized by the calculation unit 21 executing a physics calculation program stored in the storage unit 13.

[0032] The calculation device 1 uses a GPU 12 in which multiple calculation units (calculation units 21, 22, 23, etc.) are arranged in parallel to simulate changes in physical quantities in a spatial grid that has been subdivided using an adaptive subdivision method. To speed up calculations, the calculation device 1 divides the spatial grid into multiple processes, and assigns the calculation of one of the processes to each calculation unit.

[0033] Each processing unit packs data of the assigned process and stores it in the assigned memory area, while each processing unit reads data of adjacent processes from the memory area and unpacks it.

[0034] First, the packing process by the arithmetic unit 21 will be described. FIG. 2 is a flowchart showing the process of packing data by the arithmetic unit. As shown in FIG. 2, the arithmetic unit 21 reserves a two-dimensional data array memory area in memory space for storing data that is arranged two-dimensionally (step S1). The memory space is, for example, a device memory mounted on the GPU 12. Note that the data may be arranged three-dimensionally. Furthermore, if possible, the data may be arranged four or more dimensions.

[0035] Next, the calculation unit 21 stores the data in a two-dimensional data array memory area (step S2). FIG. 3 is a diagram showing the boundaries of processes in a spatial lattice. As shown in FIG. 3, the spatial lattice is subdivided using an adaptive subdivision method and consists of a plurality of spatial lattices of different sizes. FIG. 3 also shows a portion of the spatial lattice, process 0, which is calculated by the calculation unit 21, a portion of process 1, which is adjacent to process 0 and is calculated by the calculation unit 22, and the boundary line L between process 0 and process 1. Each leaf, assigned a number from 0 to 24, is a set of spatial lattices including a predetermined number of spatial lattices (for example, 16, 4 vertically and 4 horizontally). However, the number of spatial lattices included in a leaf is not particularly limited, and the leaf may include spatial lattices arranged three-dimensionally (for example, 64, 4 x 4 x 4). The leaves include an Inner leaf IL that is spaced apart from the boundary line L within process 0, an Outer leaf OL that is in contact with the boundary line L within process 0, and a Halo leaf HL that is in contact with the boundary line L within process 1 adjacent to process 0.

[0036] The calculation unit 21 stores data generated by arranging outer shell leaves OL that are in contact with the boundary of process 0 in the spatial lattice, which is calculated by the calculation unit 21, in a two-dimensional data array memory area. Specifically, the calculation unit 21 executes a kernel along the outer shell leaves OL that are in contact with the boundary line L, and generates a two-dimensional data array by one-dimensionally arranging leaf L0, leaf L1, leaf L12, leaf L13, leaf L14, leaf L15, and leaf L16 in this order.

[0037] Fig. 4 is a diagram showing an example of a two-dimensional data array. As shown in Fig. 4, the two-dimensional data array DA generated by the calculation unit 21 corresponds to 16 spatial lattices contained in leaves L0, L1, and L12, in that order from left to right. In the two-dimensional data array DA, memory addresses corresponding to the positions of the two-dimensionally arranged data are defined. For example, memory addresses 0 to F are assigned to positions (0,00) to (3,03) of leaf L0.

[0038] 2, the calculation unit 21 separates the data held by the spatial lattice into communication target data and non-communication target data (step S3). Here, as an example, a method for separating the data of leaf L12 into communication target data and non-communication target data will be described.

[0039] Figure 5 is a diagram showing how data is sent from leaf L12 to leaf L20. As shown in Figure 5, leaf L20 is one leaf size larger than leaf L12. Therefore, the four lattices from the upper right of leaf L12, which correspond to the size of one lattice of leaf L20, are the communication targets. Expressed in bits in the order of the arrows, this becomes 0b1100110000000000.

[0040] Figure 6 is a diagram showing how data is sent from leaf L12 to leaf L23. As shown in Figure 6, leaf L23 is the same size as leaf L12. Therefore, the communication target is one lattice from the bottom right of leaf L12, which corresponds to the size of one lattice of leaf L23. This is expressed in bits as 0b0000000000001000.

[0041] Figure 7 is a diagram showing how data is sent from leaf L12 to leaf L24. As shown in Figure 7, leaf L24 is the same size as leaf L12. Therefore, the vertical column of cells to the right of leaf L12, which is adjacent to leaf L24, is the target of communication. Expressed in bits, this is 0b1000100010001000.

[0042] Fig. 8 is a diagram showing the lattice of communication targets of leaf L12. If the lattice of communication targets as a whole is expressed from the communication target data of Figs. 5 to 7, it will look like Fig. 8. This can be expressed in bits as 0b1100110010001000.

[0043] Returning to Fig. 4, for leaf L12, the data held by the spatial lattice can be separated into communication target data and non-communication target data by referring to the communication target data in Fig. 8. By performing similar processing, the data held by the spatial lattice can also be separated into communication target data and non-communication target data for leaf L0, leaf L1, and other leaves.

[0044] Returning to FIG. 2, the calculation unit 21 reserves a table memory area in the memory space for storing a table that associates the memory addresses of the data to be communicated with the identification numbers (step S4).

[0045] Next, the calculation unit 21 generates a table and stores it in the table memory area (step S5). FIG. 9 is a diagram showing the relationship between the two-dimensional data array DA and the transmission buffer SB and table TA. In FIG. 9, the upper part shows an example of table TA, the middle part shows an example of the two-dimensional data array DA, and the lower part shows an example of the transmission buffer SB. Here, the data in table TA and transmission buffer SB are each arranged one-dimensionally. This is because storing data in contiguous memory areas in table TA and transmission buffer SB improves data access performance during communication and simplifies addressing of data to be communicated. Of course, the arrangement of each memory area is not limited to one-dimensional, and may be two-dimensional, three-dimensional, or higher. Even with a two-dimensional or higher-dimensional arrangement, the same effect can be achieved as long as the memory area and address of the data are contiguous. As shown in FIG. 9, the calculation unit 21 generates table TA, which associates the memory address of data to be communicated with an identification number (Index), and stores it in the table memory area.

[0046] Returning to FIG. 2, the calculation unit 21 reserves a transmission buffer SB in the memory space for storing data arranged one-dimensionally in the order of the identification numbers (step S6).

[0047] Then, the calculation unit 21 refers to the memory address in the table TA corresponding to the identification number, and stores the communication target data in the transmission buffer SB (step S7). Fig. 10 is a flowchart showing the process of referring to the table and storing the communication target data in the transmission buffer. As shown in Fig. 10, the calculation unit 21 sets a variable i to 1 (step S11). The variable i corresponds to the index of the transmission buffer SB.

[0048] Next, the calculation unit 21 determines whether the variable i is smaller than the number of elements N (step S12). The number of elements N is the total number of indexes in the sending buffer SB, and matches the total number of communication target data in the two-dimensional data array DA.

[0049] If the calculation unit 21 determines that the variable i is smaller than the number of elements N (step S12: Yes), the calculation unit 21 assigns the variable i to the function f to generate a variable j. The function f is a function that represents the table TA, and the variable j is a memory address of the data to be communicated in the two-dimensional data array DA.

[0050] Thereafter, the calculation unit 21 executes the process of send_buffer[i]=data_array[j] to store the communication target data corresponding to variable j of the two-dimensional data array DA in the area corresponding to variable i of the sending buffer SB. In the example of Fig. 9, the communication target data corresponding to variable j=2 of the two-dimensional data array DA corresponding to variable i=0 of the table TA is stored in the area corresponding to variable i=0 of the sending buffer SB.

[0051] Finally, the calculation unit 21 increments the variable i to i+1 (step S15) and returns to step S12.

[0052] In step S12, if the calculation unit 21 determines that the variable i is equal to or greater than the number of elements N (step S12: No), all of the data to be communicated in the two-dimensional data array DA has been stored in the transmission buffer SB, and the series of processes is terminated. As a result, the transmission buffer SB shown in FIG. 9 is generated.

[0053] Next, unpacking by the calculation unit 21 will be described. Fig. 11 is a flowchart showing the process of unpacking data by the calculation unit. As shown in Fig. 11, the calculation unit 21 reserves a table memory area in the memory space allocated to the calculation unit 21 for storing a table that is generated by the calculation unit 22 and stored in the memory space allocated to the calculation unit 22 (step S21).

[0054] Next, the calculation unit 21 secures a receiving buffer in the memory space allocated to the calculation unit 21 to store the transmitting buffer generated by the calculation unit 22 and stored in the memory space allocated to the calculation unit 22 (step S22).

[0055] Furthermore, the calculation unit 21 stores the table generated by the calculation unit 22 in a table memory area in the memory space allocated to the calculation unit 21 (step S23).

[0056] Similarly, the calculation unit 21 stores the transmission buffer created by the calculation unit 22 in the reception buffer in the memory space allocated to the calculation unit 21 (step S24).

[0057] Then, the calculation unit 21 refers to the memory addresses of the table in the order of the table identification numbers generated by the calculation unit 22, and stores the communication target data in the receiving buffer in the two-dimensional data array memory area (step S25).

[0058] By performing the unpacking described above, the calculation unit 21 can acquire data such as the physical quantities of each spatial lattice included in the Halo leaf HL in Fig. 3. As a result, the calculation unit 21 can simulate changes in the physical quantities in the spatial lattice by stencil calculation using the physical quantities of each spatial lattice included in the Halo leaf HL.

[0059] Similarly, by having the calculation unit 22 read and unpack the transmission buffer SB and the table TA generated by the calculation unit 21, the calculation unit 22 can acquire data such as the physical quantities of each spatial lattice included in the outer leaf OL of Fig. 3. As a result, the calculation unit 22 can simulate changes in the physical quantities in the spatial lattice by stencil calculation using the physical quantities of each spatial lattice included in the outer leaf OL.

[0060] When packing data to be communicated within arrayed data in stencil calculation, a memory copy is essentially performed from the data array to the transmission buffer. Therefore, if this memory copy is made more efficient, the packing process can be sped up. Factors that reduce the speed of memory copy include random access to memory and branching (whether to pack or not) for each data array element. However, according to the embodiment, by improving these factors, the packing speed can be improved.

[0061] In the memory access using the table TA in the embodiment, rather than a one-to-one correspondence between leaves and the GPU's streaming multiprocessor, parallel processing is performed for the number of elements in the table TA, so no conditional branching occurs within the streaming multiprocessor. Furthermore, by using the table TA, the thread number and the identification number of the memory address for packing become equal, and memory access becomes continuous, thereby improving memory access speed through coreless access. In the AMR method, the physical addresses of the data to be communicated in the data array are particularly varied, which is highly effective in accelerating processing speed.

[0062] Similarly, by constructing a table TA for unpacking, the processing speed can be increased.

[0063] (Example) Next, an example in which packing and unpacking processing was actually performed will be described. FIG. 12 is a diagram showing an overview of the example. As shown in FIG. 12, two GPUs were used in the example. The GPU used in the example was an NVIDIA V100. The two GPUs were connected by four NVLink 3.0 cables, and the communication speed between the GPUs was 50 GB / s one way.

[0064] FIG. 13 is a diagram showing a spatial grid in an embodiment. As shown in FIG. 13, in this embodiment, a spatial grid using the AMR method was assigned to a three-dimensional cubic space with a side length of 1, and the spatial grid was subdivided around a sphere with a radius of 0.25 from the center of this space. Specifically, as an initial condition, leaves arranged in a three-dimensional 2x2x2 array were assigned to this cube, and these leaves were subdivided up to a maximum of 6 levels around the sphere. Each leaf contained 64 spatial grids, or 4x4x4. After the subdivision using the AMR method, the total number of grids was 15,805,952.

[0065] This spatial grid was divided in half by planes passing through the midpoints of the four parallel sides of the cube, and each divided area was assigned to two GPUs. Memory communication between the GPUs was set to a thickness of two grids from the divided plane.

[0066] Fig. 14 is a diagram showing processing speeds in an embodiment. Fig. 14 shows traffic, processing speeds before the introduction of the table structure (a comparative example using conventional technology, where packing and unpacking using tables is not performed), and processing speeds after the introduction of the table structure (an embodiment using the present invention, where packing and unpacking using tables is performed). Fig. 14 shows that the processing speed is up to about 60 times faster after the introduction of the table structure than before the introduction of the table structure.

[0067] Therefore, this example shows that by implementing the present invention, the processing speed can be increased by approximately 60 times at maximum.

[0068] In the above-described embodiment, an example has been described in which a GPU 12 having a plurality of cores (computing units) and a device memory is used. The GPU 12 is equipped with several thousand or more computing cores, and these cores each refer to an allocated memory area of ​​one device memory. However, when performing parallel computation using a plurality of GPUs as in the embodiment, communication between the GPUs occurs because each GPU has a different memory.

[0069] The computing device may also be a CPU. When stencil calculations are performed using a CPU, each node has one physical memory space. Generally, high-performance CPUs are equipped with multiple computing cores, and stencil calculations are parallelized across each core. For example, if one node is equipped with two 16-core CPUs, a maximum of 32 parallel calculations can be performed within the node. Although it is possible to allocate more threads than the number of cores, stencil calculations that require parallel calculations are highly demanding, and therefore, such threads are rarely allocated. When calculations are completed within a node, a shared memory type is often adopted, and no communication occurs. In the case of inter-node calculations using multiple nodes, each node has a different physical memory space, so a distributed memory type is inevitably adopted. In this case, communication occurs between nodes. Furthermore, different programming methods are often used for distributed memory and shared memory types. In stencil calculations programmed using distributed memory, communication processing may be performed even within a node. This is to avoid the need to distinguish between intra-node and inter-node communication processing between processes due to program specifications. Intra-node communication processing is essentially data transfer within the same physical memory, and therefore can be performed in a much shorter time than inter-node communication processing.

[0070] Further advantages and modifications will readily occur to those skilled in the art. Thus, the invention in its broader aspects is not limited to the specific details and representative embodiments shown and described above. Accordingly, various modifications may be made without departing from the spirit or scope of the general inventive concept as defined by the appended claims and their equivalents. [Explanation of symbols]

[0071] 1 Computing device 11 Control section 12 GPU 13 Storage section 21, 22, 23 Arithmetic section

Claims

1. a data array memory area for storing data arrayed in two or more dimensions is reserved in the first memory space; Separating the data stored in the data array memory area into data to be communicated and data not to be communicated; a memory area for a first table is reserved in the first memory space for storing a first table in which memory addresses of the communication target data correspond to identification numbers; generating the first table and storing it in a memory area for the first table; a first transmission buffer for storing the data in the order of the identification numbers is reserved in the first memory space; a first calculation unit that stores the communication target data in the first transmission buffer by referring to the memory address in the first table that corresponds to the identification number;

2. The first calculation unit a second table memory area is reserved in the first memory space for storing a second table generated by a second calculation unit and stored in the second memory space; a receiving buffer is allocated in the first memory space to store a second transmitting buffer generated by the second calculation unit and stored in the second memory space; storing the second table in a memory area for the second table; storing the second transmission buffer in the reception buffer; 2. The arithmetic unit according to claim 1, wherein the memory addresses of the second table are referenced in the order of the identification numbers of the second table, and the communication target data of the receiving buffer is stored in the data array memory area.

3. The computing device according to claim 2 , wherein the second memory space is adjacent to the first memory space.

4. The computing device according to claim 1 , wherein the data is a physical quantity held by a spatial lattice arranged in two or more dimensions.

5. 5. The computing device of claim 4, wherein the spatial grid is subdivided by an adaptive subdivision method.

6. The arithmetic device according to claim 5, wherein the first calculation unit includes a predetermined number of the spatial lattices, and stores the data generated by arranging outer shell leaves that are adjacent to the boundary of the process calculated by the first calculation unit in the spatial lattice in the memory area for data arrangement.

7. The computing device according to claim 4 , wherein the first computing unit simulates a change in the physical quantity in the spatial lattice by stencil calculation.

8. a data array memory area for storing data arrayed in two or more dimensions is reserved in the first memory space; Separating the data stored in the data array memory area into data to be communicated and data not to be communicated; a memory area for a first table is reserved in the first memory space for storing a first table in which memory addresses of the communication target data correspond to identification numbers; generating the first table and storing it in a memory area for the first table; a first transmission buffer for storing the data in the order of the identification numbers is reserved in the first memory space; a first calculation unit that stores the communication target data in the first transmission buffer by referring to the memory address of the first table corresponding to the identification number; a second data array memory area for storing the data arranged in two or more dimensions is reserved in a second memory space adjacent to the first memory space; a memory area for the first table for storing the first table is reserved in the second memory space; a receiving buffer for storing the first transmitting buffer is secured in the second memory space; storing the first table in a memory area for the first table in the second memory space; storing the first transmission buffer in the reception buffer; a second calculation unit that stores the communication target data of the receiving buffer in the second data array memory area by referring to the memory addresses of the first table in the order of the identification numbers of the first table; A computing device comprising:

9. A physics calculation device that simulates changes in physical quantities in a spatial grid that is subdivided by an adaptive refinement method using a plurality of calculation units in parallel, including a first calculation unit and a second calculation unit, The first calculation unit a data array memory area for storing data arrayed in two or more dimensions is reserved in the first memory space; a predetermined number of the spatial lattices are included, and the data generated by arranging outer leaves that contact the boundary of the process operated by the first operation unit in the spatial lattice is stored in the data arrangement memory area; Separating the data stored in the data array memory area into data to be communicated and data not to be communicated; a memory area for a first table is reserved in the first memory space for storing a first table in which memory addresses of the communication target data correspond to identification numbers; generating the first table and storing it in a memory area for the first table; a first transmission buffer for storing the data in the order of the identification numbers is reserved in the first memory space; storing the communication target data in the first transmission buffer by referring to the memory address in the first table corresponding to the identification number; a second table memory area is reserved in the first memory space for storing a second table generated by the second calculation unit and stored in a second memory space adjacent to the first memory space; a receiving buffer is allocated in the first memory space to store a second transmitting buffer generated by the second calculation unit and stored in the second memory space; storing the second table in a memory area for the second table; storing the second transmission buffer in the reception buffer; referring to the memory addresses of the second table in the order of the identification numbers of the second table, and storing the communication target data of the receiving buffer in the data array memory area; A physics calculation device that simulates changes in the physical quantity in the spatial lattice by stencil calculation.

10. a data array memory area for storing data arrayed in two or more dimensions is reserved in the first memory space; Separating the data stored in the data array memory area into data to be communicated and data not to be communicated; a memory area for a first table is reserved in the first memory space for storing a first table in which memory addresses of the communication target data correspond to identification numbers; generating the first table and storing it in a memory area for the first table; a first transmission buffer for storing the data in the order of the identification numbers is reserved in the first memory space; a calculation method for storing the communication target data in the first transmission buffer by referring to the memory address in the first table corresponding to the identification number;

11. a data array memory area for storing data arrayed in two or more dimensions is reserved in the first memory space; Separating the data stored in the data array memory area into data to be communicated and data not to be communicated; a memory area for a first table is reserved in the first memory space for storing a first table in which memory addresses of the communication target data correspond to identification numbers; generating the first table and storing it in a memory area for the first table; a first transmission buffer for storing the data in the order of the identification numbers is reserved in the first memory space; a computing program that causes a first computing unit to execute a process of referencing the memory address of the first table corresponding to the identification number and storing the communication target data in the first transmission buffer;

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