Manufacturing method of semiconductor device

Abstract

To provide a manufacturing method of a semiconductor device capable of improving an efficiency percentage rate.SOLUTION: A surface electrode 14 has a two-layer structure of first and second electrode films 31 and 32 formed at a different timing. After the first electrode film 31 is formed to have a thickness t1 smaller than a product thickness t10 of the surface electrode 14 to cause a convex defect due to a foreign matter 1a having a relatively large size on a surface of the first electrode film 31, an entire surface of the first electrode film 31 is covered with a resist film. The resist film intentionally causes a resist defect due to a convex defect on the surface of the first electrode film 31. Then, the convex defect exposed at a resist defect part is etched to change the concave defect 4a or the convex part having a relatively low height, and then the second electrode film 32 is formed. Even if a foreign matter 1a remains in the concave defect 4a, since an apparent height h3 of the foreign matter 1a becomes low, the first electrode film 31 and the foreign matter 1a are completely covered with the second electrode film 32, and the convex defect does not occur on the surface of the surface electrode 14 (the surface of the second electrode film 32).SELECTED DRAWING: Figure 8

Description

[Technical Field]

[0001] This disclosure relates to a method for manufacturing a semiconductor device. [Background technology]

[0002] BACKGROUND ART Conventionally, it is known that electrodes of semiconductor devices are formed of an aluminum (Al) film and a nickel (Ni) film for solder bonding that covers the aluminum film (see, for example, Patent Document 1 below). [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2018-060885 Summary of the Invention [Problem to be solved by the invention]

[0004] However, if a foreign substance adheres to the surface of a semiconductor substrate, an aluminum film forms to cover the foreign substance, causing a convex defect in the aluminum film due to the foreign substance. The coverage of the aluminum film deteriorates near the convex defect, causing a slit (gap) in the aluminum film. Furthermore, the resist mask used in patterning the aluminum film is interrupted (stepped) by the convex defect, causing a concave defect that penetrates the aluminum film in the depth direction at the resist defect site. These metal defects (slits, concave defects) in the aluminum film can cause defects in semiconductor devices.

[0005] An object of this disclosure is to provide a method for manufacturing a semiconductor device that can improve the yield rate. [Means for solving the problem]

[0006] A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is as follows: a first step is performed to form a first electrode film on the surface of a semiconductor wafer; a second step is performed to cover the surface of the first electrode film with a resist film, and to interrupt the resist film at a portion of the surface of the first electrode film corresponding to a convex defect, thereby creating a resist defect; a third step is performed to etch the convex defect exposed in the resist defect; after the third step, a fourth step is performed to remove the resist film; after the fourth step, a fifth step is performed to form a second electrode film on the surface of the first electrode film, thereby forming a surface electrode composed of the first electrode film and the second electrode film; and a sixth step is performed to pattern the surface electrode. [Effects of the Invention]

[0007] The method for manufacturing a semiconductor device according to the present disclosure has the effect of improving the yield rate. [Brief explanation of the drawings]

[0008] [Figure 1] 1 is a flowchart showing an outline of a method for manufacturing a semiconductor device according to an embodiment; [Figure 2] FIG. 2 is a plan view showing the semiconductor wafer as viewed from the front surface side. [Figure 3] 1 is a cross-sectional view (part 1) showing a state during the manufacturing process of a semiconductor device according to an embodiment. [Figure 4] 10 is a cross-sectional view (part 2) showing a state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 5] 10 is a cross-sectional view (part 3) showing a state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 6] 4 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the embodiment (part 4). FIG. [Figure 7] 5 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the embodiment (part 5). FIG. [Figure 8] 6 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the embodiment (part 6). FIG. [Figure 9]10 is a cross-sectional view (part 1) showing another state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 10] 10 is a cross-sectional view (part 2) showing another state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 11] 10 is a cross-sectional view (part 3) showing another state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 12] 10 is a cross-sectional view (part 4) showing another state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 13] 5 is a cross-sectional view showing another state during the manufacturing process of the semiconductor device according to the embodiment (part 5). FIG. [Figure 14] 10 is a cross-sectional view (part 6) showing another state during the manufacturing process of the semiconductor device according to the embodiment. FIG. [Figure 15] 7 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the embodiment (part 7). FIG. [Figure 16] 8 is a cross-sectional view showing a state during the manufacturing process of the semiconductor device according to the embodiment; FIG. [Figure 17] 1A and 1B are cross-sectional views (part 1) schematically showing a state during the manufacturing process of a semiconductor device according to a reference example. [Figure 18] 10 is a cross-sectional view (part 2) schematically showing a state during the manufacturing process of the semiconductor device of the reference example. FIG. [Figure 19] 10A and 10B are cross-sectional views schematically showing a state during the formation of surface electrodes in Examples and Comparative Examples. [Figure 20] 1 is a cross-sectional view showing an example of the structure of a semiconductor device manufactured by applying a method for manufacturing a semiconductor device according to an embodiment; [Figure 21] FIG. 10 is a characteristic diagram showing the results of an experiment on the relationship between the thickness of the resist film and the rate of change in bump defects to divot defects on the surface of the first electrode film. [Figure 22] FIG. 10 is a characteristic diagram showing the results of an experiment on the relationship between the thickness of the resist film and the rate of change in bump defects to divot defects on the surface of the first electrode film. [Figure 23] FIG. 10 is a characteristic diagram showing the results of an experiment on the relationship between the thickness of the resist film and the rate of change in bump defects to divot defects on the surface of the first electrode film. [Figure 24]1A and 1B are cross-sectional views (part 1) schematically showing a state during the manufacturing process of a semiconductor device according to a reference example. [Figure 25] 10 is a cross-sectional view (part 2) schematically showing a state during the manufacturing process of the semiconductor device of the reference example. FIG. [Figure 26] 10A and 10B are cross-sectional views (part 3) schematically showing a state during the manufacturing process of the semiconductor device of the reference example. [Figure 27] 10 is a cross-sectional view (part 4) schematically showing a state during the manufacturing process of the semiconductor device of the reference example. FIG. [Figure 28] 10 is a cross-sectional view (part 1) schematically showing another state during the manufacturing process of the semiconductor device of the reference example. FIG. [Figure 29] 10 is a cross-sectional view (part 2) schematically showing another state during the manufacturing process of the semiconductor device of the reference example. FIG. [Figure 30] 10 is a cross-sectional view (part 3) schematically showing another state during the manufacturing process of the semiconductor device of the reference example. FIG. [Figure 31] 10 is a cross-sectional view (part 4) schematically showing another state during the manufacturing process of the semiconductor device of the reference example. FIG. DETAILED DESCRIPTION OF THE INVENTION

[0009] <Summary of Embodiments of the Present Disclosure> (1) A method for manufacturing a semiconductor device according to one embodiment of the present disclosure is as follows: a first step is performed to form a first electrode film on the surface of a semiconductor wafer; a second step is performed to cover the surface of the first electrode film with a resist film, and to interrupt the resist film at a portion of the surface of the first electrode film corresponding to a convex defect, thereby creating a resist defect; a third step is performed to etch the convex defect exposed in the resist defect; after the third step, a fourth step is performed to remove the resist film; after the fourth step, a fifth step is performed to form a second electrode film on the surface of the first electrode film, thereby forming a surface electrode composed of the first electrode film and the second electrode film; and a sixth step is performed to pattern the surface electrode.

[0010] According to the above disclosure, since the height position of the surface of the portion of the first electrode film exposed in the resist defect portion can be lowered in the third step, no convex defects occur on the surface of the second electrode film (surface of the front electrode). Any concave defects (metal defects) that occur on the first electrode film can be covered by the second electrode film. Since no convex defects occur on the surface of the front electrode, it is possible to reduce the occurrence of concave defects in the front electrode during patterning of the front electrode, and the yield rate of semiconductor devices can be improved.

[0011] (2) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (1), the bump defect may be changed into a pit defect in the third step.

[0012] According to the disclosure above, in the third step, the height position of the surface of the portion of the first electrode film exposed in the resist-defective portion can be made lower than the height position of the surface of the flat portion of the first electrode film.

[0013] (3) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (1) or (2), the third step may change the bump defect into a bump having a height shorter than that of the bump defect.

[0014] According to the above disclosure, in the third step, the height position of the surface of the portion of the first electrode film exposed in the resist-defective portion can be made closer to the height position of the surface of the flat portion of the first electrode film.

[0015] (4) In addition, in the method for manufacturing a semiconductor device according to the present disclosure, in any one of (1) to (3) above, the resist film may have a thickness of 2.6 μm or more and 3.2 μm or less.

[0016] According to the above disclosure, the rate at which bump defects on the surface of the first electrode film change to pit defects (pit defect change rate) can be increased in the third step.

[0017] (5) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (4), the resist film may have a thickness of 3.0 μm or less.

[0018] According to the above disclosure, the rate at which bump defects on the surface of the first electrode film are converted into pit defects (pit defect conversion rate) can be further increased in the third step.

[0019] (6) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in any one of (1) to (5) described above, the height from the flat surface of the first electrode film to the top of the bump defect may be 4 μm or more.

[0020] According to the above disclosure, in the second step, a resist defect can be reliably generated in the resist film at a portion corresponding to the convex defect on the surface of the first electrode film.

[0021] (7) Furthermore, in the method for manufacturing a semiconductor device according to the present disclosure, in any one of (1) to (6) above, the thickness of the first electrode film may be 25% or more and 75% or less of the thickness of the surface electrode.

[0022] According to the above disclosure, convex defects are generated on the surface of the first electrode film during the first step, and convex defects caused by unevenness in the lower layer (unevenness on the surface of the first electrode film) on the surface of the second electrode film can be prevented during the fifth step.

[0023] (8) In the method for manufacturing a semiconductor device according to the present disclosure, in the above-mentioned (7), the thickness of the first electrode film may be 50% of the thickness of the surface electrode.

[0024] According to the above disclosure, since the thicknesses of the first and second electrode films are equal, it is easy to simultaneously cause convex defects on the surface of the first electrode film in the first step and prevent convex defects on the surface of the second electrode film caused by unevenness in the lower layer (unevenness on the surface of the first electrode film) in the fifth step.

[0025] (9) In addition, in the method for manufacturing a semiconductor device according to the present disclosure, in any one of the above-mentioned (1) to (8), the thickness of the surface electrode may be 4 μm or more and 6 μm or less.

[0026] According to the above disclosure, the surface electrodes can be formed without changing the design conditions (product thickness) and the like, and therefore, fluctuations in the characteristics of the semiconductor device can be prevented.

[0027] (10) In the method for manufacturing a semiconductor device according to any one of (1) to (9) above, the surface electrode may be mainly composed of aluminum.

[0028] According to the above disclosure, the surface electrode can be formed without changing the design conditions (materials) and the like, and therefore, fluctuations in the characteristics of the semiconductor device can be prevented.

[0029] (11) In addition, in the method for manufacturing a semiconductor device according to any one of (1) to (10) above, in the third step, the etching may be wet etching.

[0030] According to the disclosure above, in the third step, the bump defects can be etched to a substantially uniform thickness on the surface of the first electrode film.

[0031] <Findings underlying this disclosure> First, a method for manufacturing a semiconductor device according to a reference example will be described. FIGS. 24 to 27 are cross-sectional views schematically illustrating a state (defective) of a semiconductor device according to a reference example during manufacturing. FIGS. 28 to 31 are cross-sectional views schematically illustrating another state (good) of a semiconductor device according to a reference example during manufacturing. In the method for manufacturing a semiconductor device according to a reference example, a bump defect 102 may occur on the surface of a surface electrode 114 of the semiconductor device due to a foreign substance 101 originating from a previous manufacturing process (FIGS. 24, 25, 28, and 29). For example, when the opening width of a contact hole 111a in an interlayer insulating film 111 is narrow, a contact plug 113 is formed by filling the contact hole 111a with a conductive film such as a tungsten (W) film via a barrier metal 112 by chemical vapor deposition (CVD) before forming a surface electrode 114 mainly composed of aluminum (Al), thereby improving the embeddability of the electrode.

[0032] In this case, after the conductive film that will become the contact plug 113 is etched back to remove unnecessary portions, foreign matter 101 adheres to the front surface of the semiconductor wafer 110 (the surface of the interlayer insulating film 111 and the contact plug 113) (FIGS. 24 and 28). If the front surface electrode 114 is formed to a product thickness t110 (for example, about 5 μm) with the foreign matter 101 adhered to the front surface of the semiconductor wafer 110, the foreign matter 101 (101a, 101b) is incorporated into the front surface electrode 114 (FIGS. 25 and 29). The front surface electrode 114 bulges in the area where the relatively large foreign matter 101a has been incorporated, causing a bump defect 102 on the surface of the front surface electrode 114. The coverage of the front surface electrode 114 deteriorates near this bump defect 102, resulting in a slit (gap) 114a in the front surface electrode 114 (FIG. 25). Relatively high protrusions (hereinafter referred to as base protrusions; not shown) occurring on the surface of the layer below the surface electrode 114 also cause the protrusion defects 102 on the surface of the surface electrode 114 .

[0033] Furthermore, the thickness t101 of the resist film 121 used as a mask during patterning of the surface electrode 114 is, for example, about 3.2 μm. The resist film 121 is interrupted (stepped) at a portion corresponding to the bump defect 102 (lower diagram in FIG. 26 ). The bump defect 102 is etched at the resist missing portion 121a, resulting in a dent defect 103 (center and right diagrams in FIG. 27 ). The dent defect 103 penetrates the surface electrode 114 in the depth direction. Therefore, regardless of whether the foreign matter 101a remains in the dent defect 103, in subsequent testing and assembly processes, for example, during plating processing to form a nickel (Ni) film for solder bonding, plating solution may penetrate into the lower layer through the dent defect 103, resulting in element destruction due to penetration of the nickel film. In the case of a MOS gate (an insulated gate having a three-layer structure of metal-oxide film-semiconductor), gate characteristics may fluctuate due to diffusion of sodium (Na) ions in the plating solution, resulting in a defective semiconductor device (semiconductor chip).

[0034] Even if the bump defect 102 is completely covered with the resist film 121 (upper diagram of FIG. 26 ), the bump defect 102 and the slit 114a are exposed in the surface electrode 114 after the resist film 121 is removed (left diagram of FIG. 27 ). During plating on the surface of the surface electrode 114, plating solution penetrates through the slit 114a into the lower layer, resulting in a defective semiconductor device. On the other hand, relatively small foreign particles 101b are embedded in the surface electrode 114 and do not create bump defects 102, so slits 114a in the surface electrode 114 and resist defects 121a in the resist film 121 do not occur ( FIGS. 29 and 30 ). Therefore, the semiconductor device is judged to be pass-grade without the above-described causes of failure occurring, even with the relatively small foreign particles 101b embedded in the surface electrode 114 ( FIG. 31 ). Therefore, a problem to be solved in this embodiment is to reduce metal defects (slits and pit defects) in the surface electrode and improve the yield rate of products (semiconductor devices).

[0035] Preferred embodiments of the method for manufacturing a semiconductor device according to this disclosure will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. The + and - prefixed with n or p indicate that the impurity concentration is higher or lower than that of layers or regions not prefixed with that prefix, respectively. In the following description of the embodiments and the accompanying drawings, similar components are denoted by the same reference numerals, and redundant explanations will be omitted. In addition, in this specification, in the notation of Miller indices, "-" refers to a bar attached to the index immediately following it, and adding "-" before an index indicates a negative index.

[0036] (Details of the embodiment) A method for manufacturing a semiconductor device according to an embodiment that solves the above-mentioned problems will be described below. FIG. 1 is a flowchart illustrating an outline of a method for manufacturing a semiconductor device according to an embodiment. FIG. 2 is a plan view showing a semiconductor wafer as viewed from the front surface side. FIGS. 3 to 8, 15, and 16 are cross-sectional views showing states during the manufacturing of a semiconductor device according to an embodiment. FIGS. 9 to 14 are cross-sectional views showing other states during the manufacturing of a semiconductor device according to an embodiment. FIGS. 3 to 8 show a portion of a semiconductor wafer 10 to which a relatively large foreign particle 1a is attached, and FIGS. 9 to 14 show a portion to which a relatively small foreign particle 1b is attached. FIGS. 17 and 18 are cross-sectional views schematically showing states during the manufacturing of a semiconductor device of a reference example.

[0037] First, as shown in Figures 2, 3, and 9, a predetermined element structure 20 is formed in each chip region 21 on the front surface side of a semiconductor wafer 10 (step S1). Next, an interlayer insulating film 11 is formed over the entire front surface of the semiconductor wafer 10, and contact holes 11a are formed that penetrate the interlayer insulating film 11 in the depth direction. In the contact holes 11a, contacts (electrical contact portions) between the element structure 20 and front surface electrodes 14 (described later) are formed. The element structure 20 will be described later (see Figure 20). For example, if the element structure 20 has a narrow cell pitch for miniaturization or low on-resistance, the width of the contact holes 11a will be narrowed, and therefore, the fillability of the contact holes 11a will be improved by using contact plugs 13 (described later).

[0038] The size of the semiconductor wafer 10 can be set as appropriate. The material of the semiconductor wafer 10 is, for example, silicon (Si) or silicon carbide (SiC). The chip regions 21 are regions that are cut from the semiconductor wafer 10 along dicing lines 22 and separated into semiconductor chips 40. For example, the chip regions 21 are arranged in a matrix pattern in approximately the center of the semiconductor wafer 10, and the dicing lines 22 extend in a lattice pattern surrounding all of the chip regions 21. The area between the edge (wafer edge) of the semiconductor wafer 10 and the dicing line 22 closest to the wafer edge is an ineffective area 23 that is not used as a semiconductor chip 40. The semiconductor wafer 10 may have an orientation flat 24 or a notch (not shown) that indicates the plane orientation.

[0039] Next, a barrier metal 12 is formed by sputtering along the surface of the interlayer insulating film 11 and the inner wall of the contact hole 11a. The barrier metal 12 is formed by laminating, for example, a titanium (Ti) film and a titanium nitride (TiN) film in this order. Next, a conductive film, such as a tungsten (W) film, is deposited (formed) on the barrier metal 12 by chemical vapor deposition (CVD) so as to fill the contact hole 11a. Next, this conductive film is etched back to remove unnecessary portions (portions on the interlayer insulating film 11), leaving only the portion of the conductive film filled in the contact hole 11a as the contact plug 13 (step S2).

[0040] Foreign matter 1 (1a, 1b) resulting from the manufacturing process, such as the processing in step S2, adheres to the front surface of the semiconductor wafer 10 (the surfaces of the interlayer insulating film 11 and contact plug 13) (see FIGS. 3 and 9). The foreign matter 1 can be, for example, a carbon (C)-based organic substance, an oxide, silicon (Si) fragments peeled off from the semiconductor wafer 10, or a metal (e.g., Ti or W) constituting the barrier metal 12 or contact plug 13. For example, the barrier metal 12 formed by sputtering tends to peel off and become relatively large foreign matter 1a. Because the heat applied to the front electrode 14 during the manufacturing process of the semiconductor device is relatively low, the foreign matter 1 embedded in the front electrode 14 remains in the product (semiconductor device) without disappearing (e.g., vaporizing) even if it is organic.

[0041] Next, as shown in FIGS. 4 and 10, a first electrode film 31, which will become the lower part (first layer) of the surface electrode 14, is formed on the front surface of the semiconductor wafer 10 by sputtering (step S3: first process). The first electrode film 31 covers the entire surfaces of the interlayer insulating film 11 and the contact plug 13. The first electrode film 31 is, for example, an aluminum (Al) film or an Al alloy film containing Al as the main component (e.g., 99%) and Si or copper (Cu), or both. Because the thickness t1 of the first electrode film 31 is thinner than the product thickness t10 of the surface electrode 14 (see FIGS. 8 and 14), it is possible to reliably generate a convex defect 2 (convex surface defect) caused by a relatively large foreign particle 1a on the surface of the first electrode film 31 (FIG. 4).

[0042] The convex defect 2 on the surface of the first electrode film 31 is a relatively high convex portion (for example, a height of about 4 μm or more) among the convex portions generated on the surface of the first electrode film 31 when the first electrode film 31 rises in a portion covering the foreign matter 1. The relatively large foreign matter 1a is an attachment that forms a convex portion protruding from the front surface (wafer surface) of the semiconductor wafer 10 at a height h1 (for example, a height of about 4 μm or more), causing the convex defect 2 on the surface of the first electrode film 31. Convex portions (base convex portions: not shown) generated on the front surface of the semiconductor wafer 10 due to factors other than the foreign matter 1 also cause convex portions on the surface of the first electrode film 31. Therefore, convex portions generated on the surface of the first electrode film 31 in a portion where the first electrode film 31 covers the relatively high base convex portions (for example, a height of about 4 μm or more) also become convex defects 2.

[0043] Specifically, a convex portion having a height h11 of approximately 4 μm or more that has occurred on the surface of the first electrode film 31 due to a convex portion caused by a foreign substance 1 and an underlying convex portion on the front surface of the semiconductor wafer 10 is the convex defect 2. The height h11 of the convex defect 2 on the surface of the first electrode film 31 is equal to or greater than the height h1 of the convex portion caused by the foreign substance 1 and the underlying convex portion on the front surface of the semiconductor wafer 10. The height h11 of the convex defect 2 on the surface of the first electrode film 31 is the height from the surface of a normal portion 31b of the first electrode film 31 to the top of the convex defect 2. The normal portion 31b of the first electrode film 31 is a substantially flat portion on the surface of the first electrode film 31 that does not have any convex portion (convex defect 2 or convex portion 3) or concave defect (for example, a concave surface defect caused by variations in the thickness t1 of the first electrode film 31 during deposition).

[0044] Furthermore, the height h11 of the bump defect 2 on the surface of the first electrode film 31 is lower than the height h111 (see FIG. 25) of the bump defect 102 occurring on the surface of the surface electrode 114 that has been thickened to the product thickness t110 in a single process, as in the above-described reference example. A slit (notch) 31a may occur in the first electrode film 31 around the bump defect 2 due to poor coverage of the first electrode film 31 near the bump defect 2. The thickness t1 of the first electrode film 31 is, for example, approximately 10% to 90% of the product thickness t10 of the surface electrode 14. More preferably, the thickness t1 of the first electrode film 31 is approximately 25% to 75% of the product thickness t10 of the surface electrode 14, taking into account the film thickness controllability of the surface electrode 14. Even more preferably, the thickness t1 of the first electrode film 31 is approximately 50% of the product thickness t10 of the surface electrode 14. The apparent height h3 of the foreign substance 1a is reduced by the thickness t1 of the first electrode film 31 due to the formation of the first electrode film 31 (the formation of the surface electrode 14 (first time)).

[0045] By reducing the apparent height h3 of the foreign object 1a, it is possible to prevent discontinuities (step discontinuities) in the resist film 34 used as a mask in the patterning of the surface electrode 14 in step S8 (described later), thereby preventing concave defects from occurring in resist-deficient portions of the resist film 34, and to prevent the slits 31a closed by the second electrode film 32 during the deposition of the second electrode film 32 (deposition (second) of the surface electrode 14) in step S7 (described later) from opening during pretreatment for the plating process (etching to clean the surface of the surface electrode 14) in step S12 (described later). That is, the thickness t1 of the first electrode film 31 is set so that the apparent height h3 of the foreign object 1a can be reduced and the thickness of the surface electrode 14 during the second deposition (thickness t2 of the second electrode film 32) can be left thicker than the amount (thickness) of the surface electrode 14 etched during the pretreatment for the plating process in step S12.

[0046] Relatively small foreign matter 1b is incorporated into and buried in the first electrode film 31 during the processing of step S3, and does not cause a bump defect 2 (see FIG. 19). The first electrode film 31 has a substantially flat surface close to the surface of a normal portion 31b in the portion covering the relatively small foreign matter 1b (not shown), or has a protrusion 3 on its surface that rises to a height h12 that does not cause a bump defect 2 (FIG. 10). In other words, a relatively small foreign matter 1b is an attachment having a height h2 from the front surface of the semiconductor wafer 10 that does not cause a bump defect 2 on the surface of the first electrode film 31 even if it is incorporated into the first electrode film 31. A relatively low base protrusion (not shown) that occurs on the surface of the layer below the first electrode film 31 also does not cause a bump defect 2.

[0047] Next, as shown in FIGS. 5 and 11, the entire surface of the first electrode film 31 is covered with a resist film 33 (step S4: second process). The thickness t3 of the resist film 33 is thin enough to cause the resist film 33 to be interrupted (step-disconnected) at portions corresponding to the bump defects 2 on the surface of the first electrode film 31, thereby generating resist defects 33a and exposing the bump defects 2 in the resist defects 33a (FIG. 5). Exposing the bump defects 2 means that at least the top or side of the bump defects 2 is not covered by the resist film 33. The thickness t3 of the resist film 33 is obtained in advance according to the size of the foreign matter 1 generated before the processing of step S3, and is appropriately set so that resist defects 33a are generated in portions corresponding to all bump defects 2 on the surface of the first electrode film 31 (see FIGS. 21 to 23).

[0048] Furthermore, the thickness t3 of the resist film 33 is thick enough to function as an etching mask that protects portions of the first electrode film 31 other than the bump defect 2 during the processing (etching) in step S5, which will be described later. Specifically, if the thickness t3 of the resist film 33 is, for example, about 3.2 μm or less, a resist vacant portion 33a that exposes the bump defect 2 can be generated. The thickness t3 of the resist film 33 may be thinner than the thickness t4 of the resist film 34, and is preferably, for example, about 2.6 μm or more and 3.0 μm or less. The thinner the thickness t3 of the resist film 33, the higher the rate at which bump defects 2 on the surface of the first electrode film 31 change into pit defects 4a (hereinafter referred to as the pit defect conversion rate) during the processing in step S5, which will be described later.

[0049] Next, as shown in FIGS. 6 and 12, the first electrode film 31 exposed in the resist-vacant portion 33a is etched using the resist film 33 as a mask (step S5: third process). At this time, the bump defect 2 is almost completely removed in the resist-vacant portion 33a, and a concave defect 4a with a depth d1 penetrating the first electrode film 31 in the depth direction is formed. The slit 31a around the bump defect 2 becomes, for example, the inner wall of the concave defect 4a. The bump defect 2 may be changed into a convex portion with a low height h13 to such an extent that a bump defect 5 (see FIG. 19) is not generated on the surface of the second electrode film 32 during the processing of step S7 described later. In other words, the processing of step S5 can lower the height position of the surface of the portion of the first electrode film 31 exposed in the resist-vacant portion 33a.

[0050] After the processing of step S5, the foreign matter 1a may remain in the dent defect 4a (left and center diagrams in FIG. 6), or the first electrode film 31 may remain on the foreign matter 1a with an extremely thin thickness t11 (center diagram in FIG. 6), or the foreign matter 1a may detach from the semiconductor wafer 10 during the processing of step S5 and not remain in the dent defect 4a (right diagram in FIG. 6). The processing conditions for step S5 (etching conditions for the first electrode film 31) are acquired in advance depending on the thickness t1, material composition, etc. of the first electrode film 31. Specifically, the processing of step S5 is preferably performed under etching conditions that allow the first electrode film 31 to be etched in the depth direction by the thickness t1 of the first electrode film 31. The reason for this is that even if the etching amount of the first electrode film 31 exceeds the thickness t1 of the first electrode film 31, or even if the etching amount of the first electrode film 31 is insufficient and becomes less than the thickness t1 of the first electrode film 31, it is estimated that the coverage and embeddability of the second electrode film 32 will be poor in the processing of step S7 described below.

[0051] The etching amount of the first electrode film 31 in the process of step S5 will be described with reference to FIG. 19. FIG. 19 is a cross-sectional view schematically illustrating a state during the formation of the surface electrode in the example and the comparative example. In FIG. 19, the upper part shows the state after the process of step S5 (etching of the first electrode film 31 (first-layer electrode film)), and the lower part shows the state after the process of step S7 (deposition of the second electrode film 32 (second-layer electrode film)). The left, center, and right parts of FIG. 19 show the etching amount of the first electrode film 31, respectively, when the etching amount is less than the thickness t1 of the first electrode film 31 (comparative example), when the etching amount is the same as the thickness t1 of the first electrode film 31 (example), and when the etching amount exceeds the thickness t1 of the first electrode film 31 (comparative example). In the judgment of FIG. 19, "◯" indicates a portion that is judged as good, and "×" indicates a portion that is judged as bad. In other words, a chip region 21 (see FIG. 2) including a state judged as "×" in FIG. 19 is defective.

[0052] By etching the first electrode film 31 by the process of step S5 to approximately the thickness t1 of the first electrode film 31 (upper part of the central diagram in FIG. 19), the bump defect 2 (the portion of the first electrode film 31 above the foreign matter 1a) is almost completely removed, and the progress of etching in the lateral direction (the direction parallel to the front surface of the semiconductor wafer 10) of the first electrode film 31 in the resist defect 33a is suppressed. A concave defect 4a having approximately the same width as the width of the resist defect 33a is formed. The slits 31a around the bump defect 2 become the inner walls of the concave defect 4a without changing their lateral positions. For example, a concave defect 4a is formed so as to connect one or more slits 31a, and the slits 31a disappear. Even if a foreign matter 1a remains in the recessed defect 4a, the portion of the first electrode film 31 above the foreign matter 1a is completely removed (or has an extremely thin thickness t11), thereby widening the gap between the foreign matter 1a and the inner wall of the recessed defect 4a on the opening side, improving the embeddability of the second electrode film 32 into the recessed defect 4a (lower part of the central diagram in Figure 19).

[0053] On the other hand, if the etching amount of the first electrode film 31 in the process of step S5 is insufficient, the bump defect 2 cannot be sufficiently removed (upper part of the left diagram in FIG. 19 ). If the foreign matter 1a remains in the dent defect 4a, the bump defect 2 and the slit 31a are inherited by the second electrode film 32 due to the shadowing effect during sputtering of the second electrode film 32 (lower part of the left diagram in FIG. 19 ). If the etching amount of the first electrode film 31 in the process of step S5 is too large, the bump defect 2 (the portion of the first electrode film 31 above the foreign matter 1a) is completely removed, but the first electrode film 31 is etched laterally, widening the width of the dent defect 4a (upper part of the right diagram in FIG. 19 ). If the gap between the foreign matter 1a and the inner wall of the dent defect 4a is not wide enough, the second electrode film 32 will be embedded in the dent defect 4a to a thickness equal to the product thickness t10 of the surface electrode 14. Therefore, as in the reference example (see Figure 25), a convex defect 5 may occur on the surface of the second electrode film 32 due to a foreign matter 1a, and a slit 32a penetrating the second electrode film 32 may also occur around the convex defect 5 (lower part of the right diagram in Figure 19).

[0054] That is, by etching the first electrode film 31 to a thickness t1 of the first electrode film 31 in step S5, no bump defect 5 or slit 32a is formed in the surface electrode 14. Step S5 is preferably performed by wet etching. This is because the first electrode film 31 is etched to a substantially uniform thickness. Even if the first electrode film 31 remains on the foreign object 1a, the first electrode film 31 remains at a substantially uniform thickness t11 along the surface of the foreign object 1a. If step S5 were performed by dry etching, the first electrode film 31 would remain on the top of the foreign object 1a, protruding upward with a substantially rectangular cross-sectional shape (not shown), potentially causing the bump defect 2 to remain. The temperature during step S5 is relatively low, for example, between 60°C and 70°C. Therefore, even if the foreign object 1a remaining in the recessed defect 4a and the foreign object 1b trapped in the first electrode film 31 are organic, they will not disappear and will remain embedded in the surface electrode 14 of the product. Thereafter, the resist film 33 is removed (ashed) (step S6: fourth process).

[0055] Next, as shown in FIGS. 7 and 13, a second electrode film 32, which will be the upper layer (second layer) of the surface electrode 14, is deposited (formed) on the entire surface of the first electrode film 31 by sputtering (step S7: fifth process). The thickness t2 of the second electrode film 32 is calculated by subtracting the thickness t1 of the first electrode film 31 from the product thickness t10 of the surface electrode 14. The material and deposition conditions for the second electrode film 32 are the same as those for the first electrode film 31. The surface of the second electrode film 32 is recessed by the depth d1 of the recessed defect 4a (= the thickness t1 of the first electrode film 31), and a recess 7 with a depth d2 that does not penetrate the surface electrode 14 is formed on the surface of the surface electrode 14. Even if a relatively large foreign object 1a remains in the recessed defect 4a, the gap between the foreign object 1a and the inner wall of the recessed defect 4a can be filled with the second electrode film 32.

[0056] Furthermore, even if a relatively large foreign substance 1a remains in the dent defect 4a, the apparent height h3 of the foreign substance 1a is reduced by the thickness t1 of the first electrode film 31 (see FIG. 6 ), as described above. The apparent height h3 of the foreign substance 1a is the height h13 from the surface of the normal portion 31b of the first electrode film 31 to the top of the foreign substance 1a. That is, the foreign substance 1a becomes a convex portion with a height h13 lower than the height h11 of the bump defect 2. Furthermore, even if a bump 6 occurs on the surface of the second electrode film 32 due to this foreign substance 1a, the height h14 of the bump 6 (see FIGS. 7 and 13 ) is approximately the thickness t2 of the second electrode film 32, which is lower than the height h111 of the bump defect 102 (see FIG. 25 ) occurring on the surface of the surface electrode 114 of the reference example. Therefore, no bump defect 5 or slit 32a (see FIG. 19 ) due to the foreign substance 1a occurs in the second electrode film 32.

[0057] The relatively large foreign matter 1a introduced into the second electrode film 32 and the relatively small foreign matter 1b introduced into the first electrode film 31 during the processing of step S3 remain embedded in the first and second electrode films 31, 32 (surface electrodes 14) in the product (semiconductor device). Regardless of the size of the foreign matter 1 (1a, 1b), the second electrode film 32 has a substantially flat surface close to the surface of the normal portion 32b in the portion covering the foreign matter 1 (1a, 1b) (not shown), or has a protrusion 6 on its surface that rises to a height h14 that does not become a bump defect 5 (see FIG. 19) (see FIGS. 8 and 14). The height h14 of the protrusion 6 on the surface of the second electrode film 32 is the height from the surface of the normal portion 32b of the second electrode film 32 to the top of the protrusion 6.

[0058] Next, the first and second electrode films 31 and 32 are patterned by photolithography and etching to leave portions that will become the surface electrodes 14 (step S8: sixth process). In step S8, a resist film (resist mask) 34 that covers the active region of each chip region 21 is formed on the second electrode film 32 (FIGS. 7 and 13). The thickness t4 of the resist film 34 is, for example, approximately 3.2 μm. An edge termination region (not shown) and a dicing line 22 (see FIG. 2) are exposed in openings (not shown) in the resist film 34. Then, as shown in FIGS. 8 and 14, etching is performed using the resist film 34 as a mask to leave portions of the first and second electrode films 31 and 32 that will become the surface electrodes 14 in the active region of each chip region 21. The process of step S8 is performed, for example, by wet etching. Then, the resist film 34 is removed.

[0059] As described above, no bump defect 5 occurs on the surface of the second electrode film 32. Therefore, during the process of step S8, no step discontinuities occur in the resist film 34 due to the surface irregularities of the surface electrode 14 (depressions 7 due to the depression defect 4a, and protrusions 6 with a relatively low height h14 due to the foreign matter 1a). Therefore, the occurrence of depression defects (metal defects; not shown) caused by partial etching of the surface electrode 14 during the process of step S8 can be reduced. The product thickness t10 of the surface electrode 14 is the total thickness of the first and second electrode films 31 and 32, and is specifically between 4 μm and 6 μm, for example, approximately 5 μm. Because the process of step S8 is performed at a relatively low temperature, for example, between 155°C and 165°C, any foreign matter 1 introduced into the surface electrode 14 (first and second electrode films 31 and 32) does not disappear, even if it is organic, and remains in the surface electrode 14 of the product.

[0060] Next, a visual inspection of the semiconductor wafer 10 is performed using a general visual inspection device (not shown) (step S9). As described above, because no convex defect 5 has occurred on the surface of the front electrode 14 (the surface of the second electrode film 32), only concave defects on the front electrode 14 can be automatically detected by the visual inspection device in the inspection of step S9. For example, among the recesses 7 formed on the surface of the front electrode 14 due to the concave defect 4a and recesses (not shown) formed by local etching of the front electrode 14 at resist defects (e.g., defects due to thickness variations) in the resist film 34 during the processing of step S8, recesses having a concave shape that can cause product defects are detected as concave defects. For example, recesses formed at resist defects in the resist film 34 can penetrate the front electrode 14 in the depth direction and cause product defects due to intrusion of plating solution into underlying layers through the recesses.

[0061] Next, annealing (heat treatment) is performed to sinter the surface electrodes 14. The annealing temperature for sintering the surface electrodes 14 is, for example, approximately 378°C or higher and 382°C or lower. During this annealing, ohmic contact may be formed between the barrier metal 12 and the semiconductor wafer 10. Next, a surface protective film (passivation film: not shown) made of, for example, polyimide is formed on the front surface of the semiconductor wafer 10 (the surface of the surface electrodes 14) (step S10). Next, openings are made in the surface protective film by photolithography and etching, and the surface electrodes 14 of each chip region 21 are exposed in each opening in the surface protective film. The portions of the surface electrodes 14 exposed in the openings in the surface protective film become electrode pads. Next, various parts on the back side of the semiconductor wafer 10 are formed by a general method (step S11).

[0062] In the process of step S11, for example, the semiconductor wafer 10 is ground from the back surface side to a product thickness to be used as the semiconductor device 50 (see FIG. 20). A predetermined diffusion region (n in FIG. 20) is formed in the surface region of the back surface of the ground semiconductor wafer 10 by impurity activation treatment using ion implantation and laser annealing from the back surface of the semiconductor wafer 10. + type FS layer 49, p + collector region 51 and n +A type cathode region 52) is formed. A lifetime killer may be introduced into a predetermined region inside the semiconductor wafer 10 by irradiating the semiconductor wafer 10 with, for example, helium (He) from the front or back surface. Next, a surface electrode (back surface electrode 15 in FIG. 20) is formed on the back surface of the semiconductor wafer 10 by sputtering.

[0063] Next, a plating film (not shown), such as a nickel (Ni) film for solder bonding, is formed on the surface of the front electrode 14 by plating (step S12). During the processing of step S12, it is possible to prevent the plating solution from penetrating into the layers below the front electrode 14 (the interlayer insulating film 11 and the contact plug 13). This is because, as described above, no slits 32a (see FIG. 19) due to the bump defects 5 are formed in the front electrode 14. In addition, by forming the front electrode 14 as a two-layer structure of the first and second electrode films 31 and 32 formed at different times, even if recesses 4b are formed in the front electrode 14 by etching during pretreatment for the plating processing in step S12, the recesses 4b do not penetrate the front electrode 14 in the depth direction.

[0064] Al films and Al alloy films formed by sputtering tend to be oriented in the (111) plane, which is the closest packed plane of atoms in a face-centered cubic (fcc) crystal (crystal grains grow in a crystal orientation perpendicular to the (111) plane, exposing the (111) plane on the Al surface; hereafter, this is referred to as (111) orientation). They also contain a small amount of {001}- and {101}-oriented crystal grains. The inventors have confirmed this Al orientation using electron backscatter diffraction (EBSD) analysis. The inventors have also confirmed that the (100) plane of Al is easily etched, depending on the etching solution composition.

[0065] When the surface electrode 114 is thickened to a product thickness t110 in a single sputtering process as in the reference example, the crystal grains grow in the same crystal orientation through the product thickness t110 of the surface electrode 114, and the crystal grain boundaries between the (111)-oriented Al crystal grains and the crystal grains oriented in other crystal planes of Al penetrate the surface electrode 114 in the thickness direction (FIG. 17). In FIG. 17, the portion where the Al (100)-oriented crystal grains have grown is illustrated as Al(100), and the portion where the Al (111)-oriented crystal grains have grown is illustrated as Al(111) (the same applies to FIGS. 15, 16, and 18). As a result, the surface electrode 114 is locally etched on the Al (100) plane during pretreatment for plating, resulting in a concave defect 114b penetrating the surface electrode 114 in the depth direction (FIG. 18).

[0066] In contrast, in the present embodiment, the first and second electrode films 31 and 32 that become the surface electrode 14 are formed at different times. Therefore, the positions at which the (100)-oriented Al crystal grains grow are different in the first and second electrode films 31 and 32 ( FIG. 15 ). It is therefore presumed that the (100)-oriented Al crystal grains in the first electrode film 31 and the (100)-oriented Al crystal grains in the second electrode film 32 are almost never opposed to each other in the thickness direction of the surface electrode 14. Therefore, even if the second electrode film 32 is locally etched at the (100) plane of Al during pretreatment for plating, causing recesses 4b, it is presumed that the recesses 4b penetrate only the second electrode film 32 in the depth direction and terminate at the interface between the first and second electrode films 31 and 32.

[0067] Next, various tests are performed on the semiconductor wafer 10 (step S13), thereby completing the wafer process. The test in step S13 may be, for example, an electrical characteristic test that tests basic functions and characteristics by inputting and outputting electrical signals to screen out chip regions 21 that do not meet the specifications and are therefore defective. This test may be performed on all chip regions 21 on the semiconductor wafer 10, or may be performed only on chip regions 21 that are not determined to be defective by the test in step S9. Thereafter, the semiconductor wafer 10 is cut (diced) along dicing lines 22 to separate each chip region 21 into individual semiconductor chips 40 (see FIG. 20), thereby completing the product (semiconductor device 50).

[0068] An example of the structure of a semiconductor device manufactured by applying the manufacturing method of a semiconductor device according to the embodiment described above will be described with reference to FIG. 20. FIG. 20 is a cross-sectional view showing an example of the structure of a semiconductor device manufactured by applying the manufacturing method of a semiconductor device according to the embodiment. In FIG. 20, an active region is shown, and an edge termination region is not shown. The semiconductor device 50 shown in FIG. 20 is an RC (reverse conducting)-IGBT in which a trench gate IGBT (insulated gate bipolar transistor) and a diode connected in anti-parallel to the IGBT are integrated into the same semiconductor chip (semiconductor substrate) 40.

[0069] The semiconductor chips 40 are formed by dividing the chip regions 21 of the semiconductor wafer 10 after the processing of step S13 described above (after the wafer process is completed) (see FIGS. 1 and 2). When the semiconductor device 50 has a breakdown voltage of 1200V class, the thickness of the semiconductor chip 40 is, for example, approximately 725 μm. When the material of the semiconductor chip 40 is, for example, Si, the front surface of the semiconductor chip 40 is, for example, a (001) plane. In the active region of the semiconductor chip 40, an IGBT region 61 that serves as the operating region of the IGBT and an FWD region 62 that serves as the operating region of a free wheeling diode (FWD) are provided adjacent to each other in a direction parallel to the front surface of the semiconductor chip 40.

[0070] The active region is a region through which a main current flows when the semiconductor device 50 is turned on. The edge termination region is a region between the active region and the side surface of the semiconductor chip 40, and surrounds the periphery of the active region. A predetermined breakdown voltage structure is provided in the edge termination region. The above-described element structure 20, barrier metal 12, contact plug 13, and surface electrode 14 are provided on the front surface side of the semiconductor chip 40 in the active region. An interlayer insulating film 11 such as BPSG (Boro Phospho Silicate Glass) is provided over the entire front surface of the semiconductor chip 40. In the edge termination region, a field oxide film formed, for example, by thermally oxidizing the front surface of the semiconductor chip 40 is provided between the front surface of the semiconductor chip 40 and the interlayer insulating film 11.

[0071] The semiconductor chip 40 has an element structure 20 and n + type FS layer 49, p + collector region 51 and n + The portion excluding the cathode region 52 is n - The device structure 20 includes a p-type base region 42, an n-type drift region 41, and a n-type base region 42. + type emitter region 43, p + The p-type base region 42 is formed of a p-type contact region 44, a trench 46, a gate insulating film 47, and a gate electrode 48. The p-type base region 42 is connected to the front surface of the semiconductor chip 40 in the active region. - The p-type base region 42 is formed on the bottom surface (p + collector region 51 side and n + the surface on the side of the cathode region 52) - The p-type base region 42 is in contact with the p-type drift region 41. The p-type base region 42 functions as a p-type anode region in the FWD region 62.

[0072] n + type emitter region 43 and p + The n-type contact region 44 is selectively provided between the front surface of the semiconductor chip 40 and the p-type base region 42 in the IGBT region 61, and is not provided in the FWD region 62. + type emitter region 43 and p +The n-type contact region 44 contacts the p-type base region 42 on the bottom surface and contacts the barrier metal 12 on the front surface of the semiconductor chip 40. + The emitter region 43 contacts the gate insulating film 47 on the sidewall of the trench 46 and faces the gate electrode 48 via the gate insulating film 47. + The mold contact region 44 may not be provided. + When the contact region 44 is not provided, + Instead of the p-type contact region 44, the p-type base region 42 reaches the front surface of the semiconductor chip 40.

[0073] In the IGBT region 61, the p-type base region 42 and the n - An n-type carrier storage (CS) region 45 may be provided between the n-type drift region 41 and the n-type base region 42 in contact with these regions. The n-type carrier storage 45 acts as a barrier for minority carriers (holes) and has the function of storing minority carriers. The n-type carrier storage 45 may be in contact with the gate insulating film 47 on the side wall of the trench 46. The trench 46 extends from the front surface of the semiconductor chip 40 through the p-type base region 42 and - The trench 46 terminates inside the type drift region 41. The trench 46 is provided in the IGBT region 61 and the FWD region 62. A gate electrode 48 made of, for example, polysilicon (poly-Si) is provided inside the trench 46 with a gate insulating film 47 interposed therebetween.

[0074] A contact hole 11a is provided that penetrates the interlayer insulating film 11 in the depth direction and reaches the front surface of the semiconductor chip 40. The contact hole 11a in the IGBT region 61 has an n + type emitter region 43 and p + The p-type contact region 44 is exposed. The p-type base region 42 is exposed in the contact hole 11a of the FWD region 62. The barrier metal 12 is provided along the inner wall of the contact hole 11a (the side surface of the interlayer insulating film 11 and the front surface of the semiconductor chip 40). The barrier metal 12 is provided along the n-type contact region 44 in the contact hole 11a of the IGBT region 61. + type emitter region 43 and p +The p-type contact region 44 is in ohmic contact with the p-type base region 42 within the contact hole 11 a of the FWD region 62 .

[0075] The contact plug 13 is buried on the barrier metal 12 inside the contact hole 11a. The surface electrode 14 is provided on the interlayer insulating film 11 and the contact plug 13, and is connected to the p-type base region 42 and the n-type base region 43 via the contact plug 13 and the barrier metal 12. + type emitter region 43 and p + The surface electrode 14 functions as an emitter electrode in the IGBT region 61 and as an anode electrode in the FWD region 62. - Within the drift region 41, the n-type + A lifetime control region (not shown) may be provided at a position shallower than the mold FS layer 49, in which a lifetime killer is introduced by, for example, helium (He) irradiation.

[0076] n + The FS layer 49 is in contact with the back surface of the semiconductor chip 40 and the n-type FS layer 49. - The electrode is provided over the entire area between the electrode and the drift region 41. + The n-type collector region 51 is connected to the back surface of the semiconductor chip 40. + The FS layer 49 is provided in the region excluding the FWD region 62. + The cathode region 52 is connected to the back surface of the semiconductor chip 40 in the FWD region 62. + It is provided between the mold FS layer 49. + The cathode region 52 is p-type in a direction parallel to the back surface of the semiconductor chip 40. + The back electrode 15 is provided on the back surface of the semiconductor chip 40 and is adjacent to the p-type collector region 51. + collector region 51 and n + The back electrode 15 is in contact with the cathode region 52. The back electrode 15 functions as a collector electrode in the IGBT region 61 and as a cathode electrode in the FWD region 62.

[0077] As described above, according to the embodiment, the surface electrode on the front surface of the semiconductor substrate has a two-layer structure consisting of first and second electrode films formed at different times. The first electrode film is formed to a thickness thinner than the product thickness of the surface electrode. After convex defects are generated on the surface of the first electrode film due to relatively large foreign particles attached to the front surface of the semiconductor substrate or relatively high convex defects generated on the front surface of the semiconductor substrate resulting from processes prior to the formation of the first electrode film, the entire surface of the first electrode film is covered with a resist film. Resist defects caused by the convex defects on the surface of the first electrode film are intentionally generated in this resist film. Then, the convex defects exposed in the resist defects are etched to turn them into concave defects or convex portions with relatively low heights, thereby lowering the height position of the surface of the portion of the first electrode film exposed in the resist defects. Therefore, convex defects are not generated on the surface of the second electrode film formed on the entire surface of the first electrode film.

[0078] The concave defects and relatively low-height convex portions occurring in the first electrode film, as well as the slits remaining in the first electrode film, are completely covered by the second electrode film. Even if relatively large foreign particles remain in the concave defects, the apparent height of the foreign particles is low, making it less likely that a shadowing effect will occur during sputtering, and the relatively large foreign particles are completely covered by the second electrode film. Since no convex defects occur on the surface of the second electrode film (the surface of the front electrode), the occurrence of concave defects (metal defects) in the front electrode during patterning of the front electrode can be reduced, improving the yield rate of semiconductor devices (products). Although concave defects in the surface of the front electrode occur due to the concave defects in the first electrode film, the concaves in the surface of the front electrode are minute indentations with a depth approximately equal to the thickness of the first electrode film, and therefore do not adversely affect the quality of the semiconductor device. Furthermore, since only concave defects in the front electrode need to be detected after patterning of the front electrode, the accuracy of visual inspection of semiconductor wafers can be improved.

[0079] Furthermore, according to the embodiment, it is possible to prevent fluctuations in the characteristics of the semiconductor device because the surface electrodes can be formed without changing the design conditions (product thickness, material, etc.) Furthermore, according to the embodiment, it is possible to use existing semiconductor manufacturing equipment, so it is possible to suppress increases in costs such as capital investment.

[0080] (Verification example) The thickness t3 (see FIGS. 1 and 5) of the resist film 33 during the processing in step S4 of the semiconductor device manufacturing method according to the embodiment described above was examined. FIGS. 21 to 23 are characteristic diagrams showing experimental results of the relationship between the thickness of the resist film and the rate of change of bump defects to pit defects on the surface of the first electrode film. Samples in which the height h1 of the convex portions on the front surface (wafer surface) of the semiconductor wafer 10 due to foreign matter 1a or underlying convex portions was 4 μm, 5 μm, and 6 μm were subjected to the processing in steps S3 to S5. The thickness (resist thickness) t3 of the resist film 33 during the processing in step S4 was variously changed, and the results of the processing in step S5 are shown in FIGS. 21 to 23. The horizontal axis of FIGS. 21 to 23 represents the size of the bump defects 2 occurring on the surface of the first electrode film 31, which may be the height h11 of the bump defects 2 or the width (not shown) of the bump defects 2. The vertical axis represents the rate of change of pit defects during the processing in step S5 (the rate at which bump defects 2 change to pit defects 4a: see FIG. 6). Generally, if the height of the foreign matter 1a is greater than the width, a dent defect is likely to be formed, and if the height of the foreign matter 1a is smaller than the width, a dent defect is unlikely to be formed.

[0081] As shown in FIGS. 21 to 23, it was confirmed that bump defects 2 occurring on the surface of the first electrode film 31 due to convex portions with a height h1 of 4 μm or more on the front surface of the semiconductor wafer 10 can be changed into pit defects 4a during the processing of step S5. In addition, it was confirmed that the thinner the thickness t3 of the resist film 33 during the processing of step S4, and the higher the height h1 of the convex portions on the front surface of the semiconductor wafer 10, the higher the pit defect conversion rate during the processing of step S5. Therefore, it is preferable to appropriately adjust the thickness t1 of the first electrode film 31 to cause bump defects 2 with a relatively high height h11 on the surface of the first electrode film 31. Specifically, it is preferable that the height h11 of all bump defects 2 on the surface of the first electrode film 31 be equal to or greater than the height h1 of the convex portions on the wafer surface of the sample shown in FIGS. 21 to 23 (i.e., 4 μm or more, preferably 5 μm or more).

[0082] As a result, by appropriately adjusting the thickness t3 of the resist film 33 during the subsequent processing in step S4, a step break in the resist film 33 occurs at each of the bump defects 2 on the surface of the first electrode film 31, exposing all bump defects 2 as resist vacancies 33a. Therefore, in the processing in step S5, all bump defects 2 on the surface of the first electrode film 31 can be transformed into pit defects 4a or into relatively low convex portions. For example, the results shown in FIG. 22 confirm that the pit defect change rate during processing in step S5 can be 100% in a sample in which the thickness t3 of the resist film 33 during processing in step S4 was 2.6 μm. Here, the first electrode film 31 was an Al-Si alloy film, but it is expected that similar effects can be obtained with Al alloy films of different compositions containing Al.

[0083] The present disclosure is not limited to the above-described embodiments, and various modifications are possible without departing from the spirit of the present disclosure. For example, in the processes of steps S3 and S7 (particularly step S7), the first and second electrode films (lower and upper portions of the surface electrode) may be formed by a high-temperature reflow sputtering method (a method of sputtering while reflowing an Al-based material by heating the semiconductor wafer at a high temperature of, for example, about 450°C or higher and 500°C or lower). The present disclosure is applicable to various semiconductor devices regardless of the semiconductor wafer material, wafer size, or element structure. [Industrial Applicability]

[0084] As described above, the method for manufacturing a semiconductor device according to the present disclosure is useful for power semiconductor devices used in power conversion devices and power supply devices for various industrial machines. [Explanation of symbols]

[0085] 1,1a,1b,101,101a,101b, foreign matter 2. Convex defect on the surface of the first electrode film 3. Convex portion on the surface of the first electrode film 4a Pit defect in the first electrode film 4b,7 Concave portion on the surface of the surface electrode 6. Convex portion on the surface of the second electrode film 10,110 semiconductor wafers 11,111 Interlayer insulating film 11a, 111a contact holes 12,112 Barrier metal 13,113 Contact plug 14,114 surface electrode 15 Back electrode 20 Element structure 21 Chip area of ​​semiconductor wafer 22 Dicing Line 23 Ineffective area of ​​semiconductor wafer 24 Orientation Flat 31 First electrode film 31a Slit in first electrode film 31b Normal portion of first electrode film 32 Second electrode film 32b Normal part of second electrode film 33,34,121 Resist film 33a, 121a Resist missing area 40 Semiconductor Chips 41n - Type Drift Region 42 p-type base region 43n + Type emitter area 44 pages + Mold contact area 45 n-type carrier accumulation region 46 Trench 47 Gate insulating film 48 gate electrode 49n + type FS layer 50 Semiconductor devices 51 pages + Type Collector Region 52n + Type cathode area 61 IGBT area 62 FWD area 102 Convex defect on the surface of the surface electrode 103,114b Depression defect on surface electrode 114a Slit of surface electrode d1 Depth of the concave defect in the first electrode film d2 Depth of the recess on the surface of the surface electrode h1,h2 Height of foreign object h3 Apparent height of foreign matter h11 Height of the convex defect on the surface of the first electrode film h12, h13 Height of the convex part on the surface of the first electrode film h14 Height of the convex part on the surface of the second electrode film h111 Height of the convex defect on the surface of the surface electrode t1, t11 Thickness of the first electrode film t2 Thickness of the second electrode film t3, t4, t101 Resist film thickness t10,t110 Product thickness of surface electrode

Claims

1. a first step of forming a first electrode film on a surface of a semiconductor wafer; a second step of covering a surface of the first electrode film with a resist film and interrupting the resist film at a portion corresponding to a convex defect on the surface of the first electrode film to generate a resist defect; a third step of etching the bump defect exposed in the resist defect portion; a fourth step of removing the resist film after the third step; a fifth step of forming a second electrode film on the surface of the first electrode film after the fourth step to form a surface electrode composed of the first electrode film and the second electrode film; a sixth step of patterning the surface electrode; 10. A method for manufacturing a semiconductor device, comprising:

2. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the bump defect is changed into a pit defect in the third step.

3. 2. The method for manufacturing a semiconductor device according to claim 1, wherein in the third step, the bump defect is changed into a bump having a height smaller than that of the bump defect.

4. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the resist film has a thickness of 2.6 [mu]m or more and 3.2 [mu]m or less.

5. 5. The method for manufacturing a semiconductor device according to claim 4, wherein the resist film has a thickness of 3.0 [mu]m or less.

6. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the height from the flat surface of the first electrode film to the top of the bump defect is 4 [mu]m or more.

7. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the first electrode film is 10% to 90% of the thickness of the surface electrode.

8. 8. The method for manufacturing a semiconductor device according to claim 7, wherein the thickness of the first electrode film is 50% of the thickness of the surface electrode.

9. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the thickness of the surface electrode is 4 [mu]m or more and 6 [mu]m or less.

10. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the surface electrode is mainly made of aluminum.

11. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the etching in the third step is wet etching.

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