Polysilicon-based word line for 3D memory

Abstract

To provide a memory device having low word line resistance and a method for manufacturing the memory device.SOLUTION: There is provided a method for manufacturing a memory device that reduces the resistance of a word line by forming a word line including a low-resistance material having a resistivity in the range from 5 μΩ cm to 100 μΩ cm, the method including: forming a recess in the word line; and selectively growing the low-resistance material in a recessed portion of the word line to form the low-resistance material. Alternatively, the low-resistance material is formed by depositing a metal layer and siliciding the metal in a word line region and in a common source line region.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] FIELD OF THE DISCLOSURE Embodiments of the present disclosure relate to the field of electronic devices and methods and apparatus for fabricating electronic devices. More particularly, embodiments of the present disclosure provide a method for forming a 3D-NAND memory cell. [Background technology]

[0002] Semiconductor technology is advancing rapidly, with device dimensions shrinking with technology advancements to provide faster processing and storage per unit space. In NAND devices, the string current needs to be high enough to obtain enough current to distinguish between on and off cells. The string current depends on carrier mobility, which is enhanced by enlarging the grain size of the silicon channel.

[0003] Existing 3D-NAND memory stacks with alternating oxide and nitride layers require a replacement metal gate (RMG) process to build the word lines. Many commercial 3D NAND devices use charge trapping (CT) as the storage medium, where an oxide / nitride (ON) mold is used. The nitride layer of the oxide / nitride mold is replaced by the word line metal, typically tungsten (W). This word line replacement process is an extremely challenging part of the 3D NAND process.

[0004] One way to avoid the word line replacement process is to use alternating layers of silicon (Si) and silicon germanium (SiGe), where the silicon remains as the word line and the SiGe is replaced with an insulator (e.g., silicon oxide (SiO)). One of the problems with Si / SiGe molds is the high word line resistance compared to tungsten in ON molds.

[0005] Therefore, there is a need in the art for a 3D-NAND device having a silicon / silicon germanium mold with low word line resistance. Summary of the Invention

[0006] One or more embodiments of the present disclosure are directed to semiconductor devices, particularly 3D NAND devices. In one embodiment, the semiconductor device includes a memory stack on a common source line, the memory stack including alternating silicon oxide layers and word lines, the common source line including slit regions having a low-resistance material, and the word lines including silicon and the low-resistance material, and a plurality of memory strings extending through the memory stack.

[0007]

[0010] Additional embodiments of the present disclosure are directed to methods of forming a semiconductor device. In one embodiment, a method of forming an electronic device includes forming a plurality of memory hole channels through a memory stack, the memory stack overlying a common source line and comprising alternating layers of silicon word lines and a first sacrificial layer, the silicon word lines having first ends, patterning at least one opening extending through the memory stack, the at least one opening exposing the common source line, replacing the first sacrificial layer with an oxide layer, and forming a low resistance material over the exposed common source line and over the first ends of the silicon word lines.

[0008] Further embodiments of the present disclosure are directed to a processing tool. In one embodiment, the processing tool includes a central transfer station including a robot configured to move wafers, a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations, the plurality of process stations including one or more of a pre-clean chamber, a silicidation chamber, a nitridation chamber, an ohmic layer deposition chamber, a metal deposition chamber, and an annealing chamber, and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move wafers between the process stations and to control processes occurring at each of the process stations.

[0009] So that the above-recited features of the present disclosure may be understood in detail, a more particular description of the present disclosure briefly summarized above can be had by reference to embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the accompanying drawings illustrate only typical embodiments of the present disclosure and should not therefore be considered limiting of its scope, as the present disclosure may admit of other equally effective embodiments. The embodiments described herein are illustrated by way of example, and not limitation, in the figures of the accompanying drawings, in which like reference numerals indicate like elements. [Brief explanation of the drawings]

[0010] [Figure 1] FIG. 2 is a flow process diagram of one embodiment of a method of forming a memory device according to embodiments described herein. [Figure 2] 1 is a cross-sectional view of a device with a memory stack according to one or more embodiments. [Figure 3] 1 is a cross-sectional view of a substrate after forming a staircase pattern of a memory stack according to one or more embodiments. [Figure 4]1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 5A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 5B] FIG. 5B is an expanded view of region 120 of FIG. 5A according to one or more embodiments. [Figure 6A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 6B] FIG. 6B is an expanded view of region 120 of FIG. 6A according to one or more embodiments. [Figure 7A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 7B] FIG. 7B is an expanded view of region 120 of FIG. 7A according to one or more embodiments. [Figure 8] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 9] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 10A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 10B] FIG. 10B is an expanded view of region 120 of FIG. 10A according to one or more embodiments. [Figure 11A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 11B] FIG. 11B is an enlarged view of region 120 of FIG. 11A according to one or more embodiments. [Figure 12] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 13A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 13B] FIG. 13B is an enlarged view of region 120 of FIG. 13A according to one or more embodiments. [Figure 14A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 14B]FIG. 14B is an enlarged view of region 120 of FIG. 14A according to one or more embodiments. [Figure 15A] 1 is a cross-sectional view of an electronic device according to one or more alternative embodiments. [Figure 15B] 1 is a cross-sectional view of an electronic device according to one or more alternative embodiments. [Figure 15C] 1 is a cross-sectional view of an electronic device according to one or more alternative embodiments. [Figure 16] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 17] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 18A] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 18B] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 18C] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 19] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 20] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 21] FIG. 1 is a top view of an electronic device according to one or more embodiments. [Figure 22] 1 is a cross-sectional view of an electronic device according to one or more embodiments. [Figure 23] FIG. 1 illustrates a cluster tool, according to one or more embodiments. DETAILED DESCRIPTION OF THE INVENTION

[0011] Before describing several example embodiments of the present disclosure, it is to be understood that the present disclosure is not limited to the details of structure or process steps set forth in the following description. The present disclosure is capable of other embodiments and of being practiced or of being carried out in various ways.

[0012] In the following description, numerous specific details are set forth, such as particular materials, chemical properties, dimensions of elements, etc., to provide a thorough understanding of one or more embodiments of the present disclosure. However, it will be apparent to one skilled in the art that one or more embodiments of the present disclosure may be practiced without these specific details. In other instances, semiconductor manufacturing processes, techniques, materials, equipment, etc. have not been described in great detail to avoid unnecessarily obscuring this description. Using the included description, one skilled in the art will be able to implement the appropriate functionality without undue experimentation.

[0013] While several exemplary embodiments of the present disclosure have been described and shown in the accompanying drawings, it is to be understood that such embodiments are illustrative only and do not limit the present disclosure, and that the present disclosure is not limited to the specific constructions and arrangements shown and described, as modifications may occur to those skilled in the art.

[0014] Existing 3D-NAND memory stacks with alternating layers of oxide and nitride require a replacement metal gate (RMG) process to build word lines. As stack heights become thicker, the high aspect ratio (HAR) memory hole etching / fill process and stress control become more challenging.

[0015] One or more embodiments provide a non-replacement metal gate (RMG) process that advantageously results in word lines having comparable resistance compared to word lines made from oxide / nitride mold and replacement metal gate processes. In one or more embodiments, a portion of the polysilicon word lines includes a low-resistance material, e.g., a metal silicide, that lowers the resistance of the word lines compared to non-replacement silicon-based word lines including tungsten (W). One or more embodiments provide a common source line (CSL) that includes a low-resistance material such that the CSL has lower resistance without filling a conductive layer in the slits.

[0016] To control the interface between polysilicon and metal, metal deposition and other processes can be performed in an isolated / integrated environment (e.g., a cluster process tool) without breaking vacuum. Accordingly, some embodiments of the present disclosure provide an integrated tool system with associated process modules for implementing the methods.

[0017] FIG. 1 illustrates a process flow diagram for an exemplary method 10 for forming a memory device. Those skilled in the art will recognize that method 10 can include any or all of the illustrated processes. Furthermore, the order of the individual processes may be varied in some respects. Method 10 can begin with any of the listed processes without departing from this disclosure. Referring to FIG. 1 , in operation 15, a memory stack is formed. In operation 20, word line staircases are formed in the memory stack. In operation 25, openings, e.g., memory hole channels, are patterned in the word line staircases. In operation 30, a transistor layer is deposited. In operation 35, bit line pads are formed. In operation 40, the memory staircases are slit-patterned. In operation 45, the sacrificial layer of the common source line is replaced. In operation 50, the sacrificial layer, e.g., silicon germanium, of the memory stack is removed. In operation 55, the openings formed by removing the sacrificial layer are filled with an oxide layer. In operation 60, low-resistance word lines are formed. In operation 65, the slits are filled. In operation 70, bit line contacts are formed. In operation 75, word line contacts are formed.

[0018] 2-18 show cross-sectional views of a portion of memory device 100 following the process flow illustrated for method 10 in Fig. 1. Fig. 19 shows a top-down view of a portion of memory device 100 following the process flow illustrated for method 10 in Fig. 1.

[0019] 2 illustrates an initial or starting memory stack for an electronic device 100 according to one or more embodiments of the present disclosure. In some embodiments, the electronic device 100 illustrated in FIG. 2 is formed on a bare substrate 102 in layers as shown. The electronic device of FIG. 2 consists of the substrate 102, a common source line 103, and a memory stack 130.

[0020] The substrate 102 can be any suitable material known to those skilled in the art. As used herein and in the appended claims, the term "substrate" refers to a surface or portion of a surface upon which a process acts. Those skilled in the art will also understand that a reference to a substrate can refer to only a portion of a substrate unless the context clearly indicates otherwise. Furthermore, a reference to deposition on a substrate can refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0021] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing can be performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials, depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates may be subjected to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such underlying layers as the context indicates. Thus, for example, if a film / layer or partial film / layer is deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0022] In one or more embodiments, a common source line 103 is on the substrate 102. The common source line 103 is sometimes referred to as a semiconductor layer. The common source line 103 may be formed by any suitable technique known to those skilled in the art and may be made from any suitable material, including, but not limited to, polysilicon (poly-Si). In some embodiments, the common source line 103 comprises several different conductive or semiconductor materials. For example, in one or more embodiments, as shown in FIG. 2 , the common source line 103 comprises a polysilicon layer 104 on the substrate 102, a sacrificial layer 106 on the polysilicon layer, and a second polysilicon layer 104 on the sacrificial layer 106.

[0023] In one or more embodiments, the sacrificial layer 106 may be formed on the polysilicon layer 104 and may be made of any suitable material. In some embodiments, the sacrificial layer 106 is removed and replaced in a later process. In some embodiments, the sacrificial layer 106 is not removed and remains in the memory device 100. In this case, the term "sacrificial" has an expanded meaning to include a permanent layer, which may also be referred to as a conductive layer. In the illustrated embodiment, the sacrificial layer 106 is removed in operation 45, as described further below. In one or more embodiments, the sacrificial layer 106 comprises a material that can be selectively removed relative to the neighboring polysilicon layer 104. In one or more embodiments, the sacrificial layer comprises a nitride material, e.g., silicon nitride (SiN), or an oxide material, e.g., silicon oxide (SiOx).

[0024] A memory stack 130 is formed on the sacrificial layer 120. In the illustrated embodiment, the memory stack 130 comprises a plurality of alternating first material layers 110 and second material layers 112. While the memory stack 130 is shown in FIG. 2 with five pairs of alternating first layers 108 and second layers 110, those skilled in the art will recognize that this is for illustrative purposes only. The memory stack 130 may have any number of alternating first layers 110 and second layers 112. For example, in some embodiments, the memory stack 130 comprises 192 pairs of alternating first layers 110 and second layers 112. In other embodiments, the memory stack 130 comprises more than 50 pairs of alternating first layers 110 and second layers 112, or more than 100 pairs of alternating first layers 110 and second layers 112, or more than 300 pairs of alternating first layers 110 and second layers 112.

[0025] In one or more embodiments, the first material layer 110 and the second material layer 112 may include any suitable material known to those skilled in the art. In one or more embodiments, the first material layer 110 includes silicon (Si) and the second material layer 112 includes silicon germanium (SiGe). In one or more embodiments, the silicon germanium includes germanium in an amount ranging from 1% to 100% on a molar basis. In one or more embodiments, the first material layer 110 and the second material layer 112 are deposited by chemical vapor deposition (CVD) or physical vapor deposition (PVD).

[0026] The individual alternating layers may be formed to any suitable thickness. In some embodiments, the thickness of each second material layer 112 is approximately equal. In one or more embodiments, each second material layer 112 has a second material layer thickness. In some embodiments, the thickness of each first material layer 110 is approximately equal. As used in this regard, approximately equal thicknesses are within + / - 5% of each other.

[0027] In one or more embodiments, the first material layer 110 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the first material layer 110 has a thickness in the range of about 0.5 to about 40 nm. In one or more embodiments, the second material layer 112 has a thickness in the range of about 0.5 nm to about 30 nm, including about 1 nm, about 3 nm, about 5 nm, about 7 nm, about 10 nm, about 12 nm, about 15 nm, about 17 nm, about 20 nm, about 22 nm, about 25 nm, about 27 nm, and about 30 nm. In one or more embodiments, the second material layer 112 has a thickness in the range of about 0.5 to about 40 nm.

[0028] 3, in one or more embodiments, step 20 of method 10 creates staircase structure 131. Oxide layer 114 is formed on the top surface of memory stack 130. Oxide layer 114 may include any suitable oxide material known to those skilled in the art.

[0029] In one or more embodiments, the staircase structure 131 exposes a top surface 134 of the second material layer 112. The top surface 134 may be used to provide space for word line contacts to be formed, as described below. A suitable fill material 135 may be deposited to occupy the space outside the staircase structure 131. As will be understood by those skilled in the art, the suitable fill material 135 may be any material that prevents electrical shorting between adjacent word lines. The staircase structure 131 has each word line having a width (shown from left to right in the figure) that is smaller than the word line below it. The use of relative terms such as "above" and "below" should not be taken as limiting the scope of the present disclosure to physical directions in space.

[0030] It should be noted that for ease of explanation, the staircase structure 131 is not shown in Figures 4-20, but as will be recognized by those skilled in the art, the staircase structure 131 is present.

[0031] 4-5B illustrate the formation of a memory string 119 through a memory stack 130. Referring to FIG. 4, in operation 25, in one or more embodiments, an opening 116 is opened through the memory stack 130. In some embodiments, the opening 116 comprises a memory hole channel. In some embodiments, forming the opening 116 comprises etching through the oxide layer 114, the memory stack 130, and the common source line 103, and into the substrate 102. The memory hole channel 116 has sidewalls that extend through the memory stack 130 and expose the surface 111 of the first material layer 110 and the surface 109 of the second material layer 112.

[0032] The oxide layer 114 has a surface 113 exposed as a sidewall of a memory hole channel 116. The memory hole channel 116 extends a distance into the substrate 102 such that sidewall surfaces 109, 111, 113 and a bottom 115 of the memory hole channel 116 are formed within the substrate 102. The bottom 115 of the memory hole channel 116 can be formed at any point within the thickness of the substrate 102. In some embodiments, the memory hole channel 116 extends into the substrate 102 a thickness that is within a range of about 10% to about 90%, or within a range of about 20% to about 80%, or within a range of about 30% to about 70%, or within a range of about 40% to about 60% of the thickness of the substrate 102. In some embodiments, the memory hole channel 116 extends into the substrate 102 a distance that is greater than or equal to 10 nm. In some embodiments, the memory hole channel 116 extends from the top surface of the oxide layer 114 through the memory stack to the bottom surface of the substrate.

[0033] 5A illustrates process 30, in which a transistor layer 118 is formed in the memory hole channel 116. The transistor layer 118 may be formed by any suitable technique known to those skilled in the art. In some embodiments, the transistor layer is formed by a conformal deposition process. In some embodiments, the transistor layer is formed by one or more of atomic layer deposition or chemical vapor deposition.

[0034] In one or more embodiments, the deposition of the transistor layer 118 is substantially conformal. As used herein, a "substantially conformal" layer refers to a layer that has approximately the same thickness throughout (e.g., at the top, middle, and bottom of the sidewalls, and at the bottom of the memory hole channel 116). A substantially conformal layer varies in thickness by less than or equal to about 5%, 2%, 1%, or 0.5%. The transistor layer 118 in the memory hole channel may comprise one or more of a blocking oxide layer, a trap layer, a tunnel oxide layer, a channel layer, and a core oxide material.

[0035] 5B, which is an expanded view of region 120 of FIG. 5A, in one or more embodiments, the transistor layer 118 comprises a blocking oxide layer 118a, a nitride trapping layer 118b, a tunnel oxide layer 118c, a channel material 118d, and a core oxide material 118e (or core oxide layer 118e) in the memory hole channel 116. In one or more embodiments, the channel material 118d comprises polysilicon.

[0036] The transistor layer 118 can have any suitable thickness, depending, for example, on the dimensions of the memory hole channel 116. In some embodiments, the transistor layer 118 has a thickness in the range of about 0.5 nm to about 50 nm, or in the range of about 0.75 nm to about 35 nm, or in the range of about 1 nm to about 20 nm.

[0037] 6A-7B illustrate step 35 of method 10, in which bit line pads 124 are formed on the top surface of transistor layer 118 and in oxide layer 114. Bit line pads 124 may be any suitable material known to those skilled in the art, including, but not limited to, polysilicon. With reference to FIGS. 6A and 6B, transistor layer 118 is etched back to form recesses 122. As shown in FIGS. 7A and 7B, recesses 122 are then filled with bit line pads 124.

[0038] Referring to FIG. 8, in act 40 of method 10, memory stack 130 is slit patterned to form slit pattern openings 128 extending from the top surface of oxide layer 114 to sacrificial layer 106 of common source line 103.

[0039] 9-11B, in operation 45 of method 10, sacrificial layer 106 in common source line 103 is removed to form opening 130. Sacrificial layer 106 may be removed by any suitable technique known to those skilled in the art, including, but not limited to, selective etching, hot phosphoric acid, etc.

[0040] 10A and 10B, the blocking oxide layer 118a, the nitride trapping layer 118b, and the tunnel oxide layer 118c are removed through the opening 130 to expose the channel layer 118d in the common source line region. The blocking oxide layer 118a, the nitride trapping layer 118b, and the tunnel oxide layer 118c may be removed by any suitable means known to those skilled in the art. In one or more embodiments, the blocking oxide layer 118a, the nitride trapping layer 118b, and the tunnel oxide layer 118c are removed using a hydrogen fluoride (HF) and phosphoric acid (H3PO4) etch. Referring to FIGS. 11A and 11B, the opening 130 is filled with a polysilicon layer 132. The polysilicon layer 132 may be doped or undoped. In some embodiments, the polysilicon layer 132 is an n-type doped polysilicon layer.

[0041] 12 illustrates process 50, in which second material layer 112, e.g., silicon germanium, is removed. Second material layer 112 may be removed by any suitable means known to those skilled in the art. In one or more embodiments, second material layer 112 is removed by selective etching, e.g., selective wet etching or selective dry etching. Removal of second material layer 112 forms opening 134.

[0042] 13A and 13B, blocking oxide layer 118a, nitride trapping layer 118b, and tunnel oxide layer 118c are removed through opening 134 to expose channel layer 118d in region 135. Blocking oxide layer 118a, nitride trapping layer 118b, and tunnel oxide layer 118c may be removed by any suitable means known to those skilled in the art. In one or more embodiments, blocking oxide layer 118a, nitride trapping layer 118b, and tunnel oxide layer 118c are removed using a hydrogen fluoride (HF) and phosphoric acid (H3PO4) etch.

[0043] 14A and 14B, in operation 55, oxide layer 136 is conformally deposited in opening / region 135. Oxide layer 136 may include any suitable oxide material known to those skilled in the art. In one or more embodiments, oxide layer 136 includes silicon oxide. While the term "silicon oxide" may be used to describe oxide layer 136, those skilled in the art will recognize that the present disclosure is not limited to a particular stoichiometry. For example, the terms "silicon oxide" and "silicon dioxide" may both be used to describe a material having silicon atoms and oxygen atoms in any suitable stoichiometric ratio. The same is true for other materials listed in this disclosure, such as silicon nitride, silicon oxynitride, aluminum oxide, zirconium oxide, etc.

[0044] In process 60, low resistance word lines are advantageously formed. In one or more embodiments, it may be advantageous for the word lines to comprise a low resistance material. In some embodiments, the low resistance material has a resistivity in the range of 5 μΩcm to 100 μΩcm. In some embodiments, the low resistance material may be formed by recessing the word lines and selectively growing a low resistance material in the recessed portions of the word lines, as shown in FIGS. 15A-15C. In other embodiments, the low resistance material may be formed by depositing a metal layer and silicidating the metal in the word line regions and in the common source line regions, as shown in FIGS. 18A-18C.

[0045] Referring to FIG. 15A, the word line first material layer 110 and oxide layer 104 and the common source line 132 are recessed to form recessed regions 129 .

[0046] Referring to FIG. 15B, device 100 is pre-cleaned using any suitable means known to those skilled in the art, including, but not limited to, SiCoNi® cleaning. In one or more embodiments, ohmic layer 131a is deposited in recessed regions 129 within slits 128. Ohmic layer 131a may be deposited by any suitable means known to those skilled in the art. In one or more embodiments, ohmic layer 131a is deposited by selective atomic layer deposition (ALD). Ohmic layer 131a may include any suitable material known to those skilled in the art. In one or more embodiments, ohmic layer 131a includes titanium (Ti). Ohmic layer 131a may have any suitable thickness. For example, in one or more embodiments, ohmic layer 131a has a thickness in the range of 1 nm to 10 nm. In some embodiments, ohmic layer 131a is nitrided to form nitrided ohmic layer 131b. In one or more embodiments, when the ohmic layer 131a comprises titanium and is then nitrided, the nitrided ohmic layer 131b comprises titanium nitride (TiN).

[0047] 15C, a low-resistivity material 133 is conformally deposited in the recessed regions 129 in the slits 128 and on the nitride ohmic layer 131b. The low-resistivity material 133 may include any suitable material known to those skilled in the art. In one or more embodiments, the low-resistivity material 133 includes one or more of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), and nickel (Ni).

[0048] 16 illustrates step 65 of method 10, in which slits 128 are filled with an insulator material 144. The insulator material 144 may be any suitable material known to those skilled in the art. In one or more embodiments, the filled slits 128 include an insulator material 144 selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. In one or more embodiments, the insulator material 144 is silicon oxide.

[0049] 17 illustrates operation 70 of method 10, in which bitline pad studs 145 are formed. Bitline studs 145 may be formed by any suitable means known to those skilled in the art.

[0050] In other embodiments, a low resistance material may be formed by depositing a metal layer and silicidating the metal layer in the word line and common source line regions. Referring to Figure 18A, a metal layer 140 is conformally deposited in the slits 128. The metal layer 140 may comprise any suitable metal known to those skilled in the art. In one or more embodiments, the metal layer 140 comprises a metal selected from the group consisting of cobalt (Co), nickel (Ni), molybdenum (Mo), titanium (Ti), platinum (Pt), tantalum (Ta), and ruthenium (Ru).

[0051] Metal layer 140 may be deposited by any suitable means known to those skilled in the art. Metal layer 140 may have any suitable thickness. In one or more embodiments, metal layer 140 has a thickness in the range of 5 nm to 150 nm, or in the range of 10 nm to 35 nm.

[0052] 18B, metal layer 140 is annealed to form a suicided metal layer 142. The annealing can be any suitable annealing process known to those skilled in the art. In one or more embodiments, metal layer 140 is annealed at a temperature ranging from 600°C to 800°C in an inert atmosphere, such as nitrogen (N2), for a duration of 1 second to 60 seconds. In one or more embodiments, suicided metal layer 142 comprises a metal silicide. The metal silicide can be selected from one or more of cobalt silicide (CoSi), nickel silicide (NiSi), molybdenum silicide (MoSi), titanium silicide (TiSi), platinum silicide (PtSi), tantalum silicide (TaSi), and ruthenium silicide (RuSi).

[0053] 18C, in one or more embodiments, the portions of metal layer 140 that are unreacted, i.e., the portions of metal layer 140 that are not converted to a metal silicide through annealing, are removed. The unreacted metal layer 140 may be removed by any suitable means known to those skilled in the art. In one or more embodiments, the unreacted metal layer 140 may be removed chemically, for example, using hydrochloric acid (HCl) and hydrogen peroxide (HO).

[0054] 19 illustrates operation 65 of method 10, in which slits 128 are filled with an insulator material 144. Insulator material 144 may be any suitable material known to those of skill in the art. In one or more embodiments, filled slits 128 include an insulator material 144 selected from one or more of silicon oxide, silicon nitride, and silicon oxynitride. In one or more embodiments, insulator material 144 is silicon oxide.

[0055] 20 illustrates operation 70 of method 10, in which bitline pad studs 145 are formed. Bitline studs 145 may be formed by any suitable means known to those skilled in the art.

[0056] 21 shows a top-down view of device 100. In one or more embodiments, a low resistance material 146 is formed in portions of word lines 136 adjacent to filled slits 144. Each level of word lines is electrically connected to a word line contact 148. In one or more embodiments, signals to the word lines can be transported through the word lines where the lower resistance material 146 helps increase the transport speed of the signal.

[0057] 22 illustrates operation 75 of method 10 in which word line (W / L) contacts are formed. Word line contacts 225 extend through memory stack 130 a sufficient distance to terminate at one of the word lines. In the illustrated cross-sectional view, low resistance layer 146 is visible. Low resistance layer 146 is formed by the method of one or more embodiments described above. Low resistance layer 146 may include a metal silicide layer or may include a low resistance material.

[0058] In one or more embodiments, word line contact 225 may comprise any suitable material known to those skilled in the art. In one or more embodiments, word line contact 225 comprises one or more of a metal, a metal suicide, polysilicon, amorphous silicon, or EPI silicon. In one or more embodiments, word line contact 225 is doped with either an N-type dopant or a P-type dopant to reduce contact resistance. In one or more embodiments, the metal of word line contact 225 is selected from one or more of copper (Cu), cobalt (Co), tungsten (W), titanium (Ti), molybdenum (Mo), nickel (Ni), ruthenium (Ru), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), or platinum (Pt).

[0059] An additional embodiment of the present disclosure is directed to a processing tool 900 for the formation of the described memory devices and methods, as shown in FIG.

[0060] The cluster tool 900 includes at least one central transfer station 921, 931 with multiple sides. Robots 925, 935 are disposed within the central transfer stations 921, 931 and configured to move a robot blade and wafer to each of the multiple sides.

[0061] The cluster tool 900 includes multiple processing chambers, also referred to as process stations, 902, 904, 906, 908, 910, 912, 914, 916, and 918, connected to a central transfer station. The various processing chambers provide separate processing regions isolated from adjacent process stations. The processing chambers may be any suitable chambers, including, but not limited to, pre-clean chambers, silicidation chambers, nitridation chambers, ohmic layer deposition chambers, metal deposition chambers, annealing chambers, transfer space(s), wafer orienter / degassing chambers, cryogenic cooldown chambers, deposition chambers, and etch chambers. The specific arrangement of process chambers and components may vary depending on the cluster tool and should not be taken as limiting the scope of the present disclosure.

[0062] In some embodiments, the cluster tool 900 includes a silicidation chamber, a nitridation chamber, an ohmic layer deposition chamber, and a metal deposition chamber, hi some embodiments, the cluster tool 900 includes a pre-clean chamber connected to a central transfer station.

[0063] 23, a factory interface 950 is connected to the front of the cluster tool 900. The factory interface 950 includes a loading chamber 954 and an unloading chamber 956 on the front 951 of the factory interface 950. Although the loading chamber 954 is shown on the left and the unloading chamber 956 is shown on the right, one skilled in the art will understand that this represents only one possible configuration.

[0064] The size and shape of the loading chamber 954 and unloading chamber 956 can vary depending, for example, on the substrates to be processed in the cluster tool 900. In the illustrated embodiment, the loading chamber 954 and unloading chamber 956 are sized to hold a wafer cassette, with multiple wafers placed within the cassette.

[0065] A robot 952 resides within the factory interface 950 and can move between a loading chamber 954 and an unloading chamber 956. The robot 952 can transfer wafers from a cassette in the loading chamber 954 to a load lock chamber 960 through the factory interface 950. The robot 952 can transfer wafers from the load lock chamber 962 to a cassette in the unloading chamber 956 through the factory interface 950. As will be appreciated by those skilled in the art, the factory interface 950 can have more than one robot 952. For example, the factory interface 950 can have a first robot that transfers wafers between the loading chamber 954 and the load lock chamber 960 and a second robot that transfers wafers between the load lock 962 and the unloading chamber 956.

[0066] The illustrated cluster tool 900 has a first section 920 and a second section 930. The first section 920 is connected to a factory interface 950 through load lock chambers 960 and 962. The first section 920 includes a first transfer chamber 921 with at least one robot 925 disposed therein. The robot 925 is also referred to as a robotic wafer transfer mechanism. The first transfer chamber 921 is centrally located relative to the load lock chambers 960 and 962, the process chambers 902, 904, 916, and 918, and the buffer chambers 922 and 924. In some embodiments, the robot 925 is a multi-arm robot capable of independently moving two or more wafers at a time. In some embodiments, the first transfer chamber 921 includes two or more robotic wafer transfer mechanisms. The robot 925 in the first transfer chamber 921 is configured to move wafers between chambers around the first transfer chamber 921. Individual wafers are transferred onto a wafer transport blade located at the distal end of the first robotic mechanism.

[0067] After processing the wafer in the first section 920, the wafer may be passed through a pass-through chamber to the second section 930. For example, chambers 922, 924 may be unidirectional or bidirectional pass-through chambers. The pass-through chambers 922, 924 may be used, for example, to cryo-cool the wafer before processing in the second section 930 or to allow wafer cooling or post-processing before moving back to the first section 920.

[0068] A system controller 990 is in communication with the first robot 925, the second robot 935, the first plurality of processing chambers 902, 904, 916, 918, and the second plurality of processing chambers 906, 908, 910, 912, 914. The system controller 990 may be any suitable component capable of controlling the processing chambers and robots. For example, the system controller 990 may be a computer including a central processing unit (CPU) 992, memory 994, input / output (I / O) 996, and support circuits 998. The controller 990 may control the processing tool 900 and / or support system components directly or through computers (or controllers) associated with particular process chambers.

[0069] In one or more embodiments, the controller 990 may be one of any form of general-purpose computer processor that may be used in an industrial environment to control various chambers and sub-processors. The memory 994 or computer-readable medium of the controller 990 may be one or more of readily available memory, such as non-transitory memory (e.g., random access memory (RAM)), read-only memory (ROM), a floppy disk, a hard disk, an optical storage medium (e.g., a compact disk or digital video disk), a flash drive, or any other form of local or remote digital storage. The memory 994 may hold a set of instructions that are operable by the processor (CPU 992) to control parameters and components of the processing tool 900.

[0070] The support circuits 998 are coupled to the CPU 992 for supporting the processor in a conventional manner. These circuits include cache, power supplies, clock circuits, input / output circuits and subsystems, etc. One or more processes may be stored in the memory 994 as software routines that, when executed or invoked by the processor, cause the processor to control the operation of the processing tool 900 or individual processing units in the manner described herein. The software routines may also be stored and / or executed by a second CPU (not shown) located remotely from the hardware being controlled by the CPU 992.

[0071] Also, some or all of the processes and methods of the present disclosure may be implemented in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation so that a process is performed.

[0072] In some embodiments, the controller 990 has one or more configurations for executing individual processes or sub-processes to implement the method. The controller 990 may be connected to and configured to operate intermediate components to implement the functions of the method. For example, the controller 990 may be connected to and configured to control a silicidation chamber.

[0073] The processes may generally be stored in the memory of the system controller 990 as software routines that, when executed by a processor, cause the process chamber to perform the processes of the present disclosure. The software routines may also be stored and / or executed by a second processor (not shown) located remotely from the hardware being controlled by the processor. Also, some or all of the methods of the present disclosure may be implemented in hardware. Thus, the processes may be implemented in software and executed in hardware using a computer system, for example, as an application-specific integrated circuit or other type of hardware implementation, or as a combination of software and hardware. The software routines, when executed by a processor, transform a general-purpose computer into a special-purpose computer (controller) that controls chamber operation to perform the processes.

[0074] In one or more embodiments, the processing tool includes a central transfer station including a robot configured to move wafers; a plurality of process stations, each process station connected to the central transfer station and providing a processing area separated from the processing areas of adjacent process stations, the plurality of process stations including one or more of a pre-clean chamber, a silicidation chamber, a nitridation chamber, an ohmic layer deposition chamber, a metal deposition chamber, and an annealing chamber; and a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move wafers between the process stations and to control processes occurring at each of the process stations.

[0075] In the context of describing the materials and methods described herein (particularly in the context of the claims that follow), the use of the terms "a," "an," and "the" and similar referents should be construed to cover both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended to serve as a shorthand method for individually referring to each separate value falling within the range, unless otherwise indicated herein, and each separate value is incorporated herein as if it were individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or otherwise clearly contradicted by context. The use of any and all examples or exemplary language (e.g., "such as") provided herein is intended merely to better describe the materials and methods and does not impose a limitation on the scope unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0076] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "in certain embodiments," or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment of the present disclosure. Furthermore, particular features, structures, materials, or characteristics may be combined in any suitable manner in one or more embodiments.

[0077] Although the disclosure herein has been described with reference to particular embodiments, it is to be understood that these embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the disclosed method and apparatus without departing from the spirit and scope of the disclosure. Therefore, it is intended that the disclosure cover modifications and variations that come within the scope of the appended claims and their equivalents.

Claims

1. a memory stack on a common source line, the memory stack comprising alternating silicon oxide layers and word lines, the common source line comprising slit regions having a low resistance material, the word lines comprising silicon and the low resistance material, the low resistance material being selected from one or more of molybdenum silicide (MoSi), titanium silicide (TiSi), platinum silicide (PtSi), tantalum silicide (TaSi), tungsten silicide (WSi), iridium silicide (IrSi), and ruthenium silicide (RuSi); a plurality of memory strings extending through the memory stack; A semiconductor device comprising:

2. The semiconductor device of claim 1 , wherein the low resistance material has a thickness in the range of 5 nm to 150 nm.

3. 10. The semiconductor device of claim 1, wherein the plurality of memory strings comprises one or more of an oxide layer, a nitride layer, a polysilicon layer, and a core oxide layer.

4. The semiconductor device of claim 3 , further comprising bit line pads on top surfaces of the plurality of memory strings.

5. The semiconductor device of claim 4 further comprising a bitline contact extending from a top surface of the bitline pad.

6. 2. The semiconductor device of claim 1, wherein the low resistivity material has a resistivity in the range of 5 μΩcm to 100 μΩcm.

7. 1. A method of forming an electronic device, the method comprising: forming a plurality of memory hole channels through a memory stack, the memory stack being on a common source line and comprising alternating layers of silicon word lines and first sacrificial layers, the silicon word lines having first ends; patterning at least one opening extending through the memory stack, the at least one opening exposing the common source line; replacing the first sacrificial layer with an oxide layer; forming a low resistance material on the exposed common source line and on the first end of the silicon word line; A method comprising:

8. The method of claim 7 , wherein the low resistance material has a thickness in the range of 5 nm to 150 nm.

9. The method of claim 7 , wherein the common source line comprises one or more of a substrate, a semiconductor layer, and a second sacrificial layer.

10. forming a plurality of memory hole channels extending through the memory stack; depositing a first oxide layer in the plurality of memory hole channels; depositing a nitride layer over the first oxide layer; depositing a second oxide layer over the nitride layer; forming a polysilicon layer on the second oxide layer; depositing a core oxide in the plurality of memory hole channels; forming a bit line pad on the polysilicon layer; The method of claim 7 further comprising:

11. 8. The method of claim 7, wherein the low resistance material comprises one or more of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), nickel (Ni), cobalt silicide (CoSi), nickel silicide (NiSi), molybdenum silicide (MoSi), titanium silicide (TiSi), platinum silicide (PtSi), tantalum silicide (TaSi), and ruthenium silicide (RuSi).

12. 8. The method of claim 7, wherein forming the low resistance material comprises: recessing the first end of the silicon word line through the at least one opening to form a recessed region; forming an ohmic layer in the recessed region; and depositing a low resistance material on the ohmic layer, the low resistance material comprising one or more of tungsten (W), ruthenium (Ru), iridium (Ir), tantalum (Ta), titanium (Ti), platinum (Pt), molybdenum (Mo), and nickel (Ni).

13. The method of claim 12 , further comprising nitriding the ohmic layer prior to depositing the low resistance material.

14. 8. The method of claim 7, wherein forming the low resistance material comprises depositing a metal layer in the at least one opening; annealing the metal layer to form a metal suicide layer; and removing unreacted metal layer, the metal suicide layer comprising one or more of cobalt suicide (CoSi), nickel suicide (NiSi), molybdenum suicide (MoSi), titanium suicide (TiSi), platinum suicide (PtSi), tantalum suicide (TaSi), and ruthenium suicide (RuSi).

15. 8. The method of claim 7, wherein the first sacrificial layer comprises silicon germanium, the silicon germanium comprising germanium in an amount ranging from 1% to 100% on a molar basis.

16. 10. The method of claim 9, further comprising removing the second sacrificial layer and replacing it with a polysilicon layer.

17. The method of claim 10 further comprising forming a bit line contact on the bit line pad.

18. a central transfer station comprising a robot configured to move the wafer; a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from the processing region of an adjacent process station, the plurality of process stations comprising one or more of a pre-clean chamber, a silicidation chamber, a nitridation chamber, an ohmic layer deposition chamber, a metal deposition chamber, and an annealing chamber; a controller connected to the central transfer station and the plurality of process stations, the controller configured to operate the robot to move the wafer between the process stations and to control a process occurring at each of the process stations; A processing tool comprising:

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