Back-contact solar cell and solar module

Abstract

To provide a back contact solar cell that cannot only achieve good passivation effect and doping concentration but also save materials.SOLUTION: A back-contact solar cell includes a silicon substrate 1 having opposing first and second sides, a P-type doped polycrystalline silicon layer 2 located in a first region on the first side of the silicon substrate 1, and an N-type doped polycrystalline silicon layer 3 located in a second region on the first side of the silicon substrate 1 different from the first region, and the ratio of the thickness of the P-type doped polycrystalline silicon layer 2 to the thickness of the N-type doped polycrystalline silicon layer 3 is between 1 and 2, a surface of the P-type doped polycrystalline silicon layer 2 closer to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than a surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1, and a height difference between the surface of the P-type doped polycrystalline silicon layer 2 closer to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1 is greater than 0 and not greater than 4.85 microns.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to the field of photovoltaics, and in particular to back-contact solar cells and solar modules. [Background technology]

[0002] Back contact (BC) solar cells have the greatest advantage of having both the emitter and metal contact located on the back surface of the cell, with no front surface shielded by a metal electrode, resulting in higher short-circuit current (Jsc). Furthermore, the back surface allows for wide metal grid lines, reducing series resistance (Rs) and increasing fill factor (FF). Furthermore, these unshielded front-surface cells not only have high conversion efficiency, but also a better appearance. They also facilitate the assembly of full-back-electrode solar modules, demonstrating broad development potential. For example, interdigitated back contact (IBC) solar cells within BC cells are currently one of the technological trends toward achieving high-efficiency crystalline silicon cells.

[0003] However, current back-contact solar cells do not adequately consider optimizing the coupling between the P and N region structures to reduce losses while ensuring passivation, resulting in poor performance of current back-contact solar cells. Summary of the Invention [Problem to be solved by the invention]

[0004] The present invention provides a back contact solar cell and solar module that aims to solve the problem of the poor performance of current back contact solar cells. [Means for solving the problem]

[0005] A first aspect of the present invention is a silicon substrate having opposing first and second sides; a P-type doped polycrystalline silicon layer located in a first region on a first side of the silicon substrate; an N-type doped polycrystalline silicon layer located in a second region on the first side of the silicon substrate, the second region being different from the first region; The back-contact solar cell has a thickness ratio of the P-type doped polycrystalline silicon layer to the N-type doped polycrystalline silicon layer of 1 to 2.

[0006] In the embodiment of the present invention, the thickness of the P-type doped polysilicon layer is large, which can improve the passivation effect of the P-type doped polysilicon layer and ensure small metallization damage and small contact resistance. If the thickness of the P-type doped polysilicon layer is slightly larger than that of the N-type doped polysilicon layer, the thicknesses of the P-type doped polysilicon layer and the N-type doped polysilicon layer can be set according to the corresponding doping concentration, passivation effect, etc., so that not only can the passivation effect and doping concentration be good, but also material can be saved.

[0007] Optionally, the P-type doped polycrystalline silicon layer comprises a plurality of P-type current collecting regions and a plurality of P-type bus regions; the N-type doped polycrystalline silicon layer includes a plurality of N-type current collecting regions and a plurality of N-type bus regions; the N-type current collecting regions and the P-type current collecting regions are alternately arranged along a first direction and both extend along a second direction, the N-type bus regions and the P-type bus regions are alternately arranged along the second direction and both extend along the first direction, the first direction and the second direction are different and both are perpendicular to the thickness direction, each of the N-type current collecting regions located between one of the N-type bus regions and one of the P-type bus regions adjacent thereto communicates with the N-type bus region; each of the P-type current collecting regions located between one of the N-type bus regions and one of the P-type bus regions adjacent thereto communicates with the P-type bus region; The ratio of the length of one current collecting region to the width of one bus region is 22 to 64, the current collecting region is the P-type current collecting region or the N-type current collecting region, the bus region is the P-type bus region or the N-type bus region, and the length direction of the current collecting region and the width direction of the bus region are both parallel to the second direction.

[0008] a first gap between the N-type current collecting region and the P-type current collecting region adjacent to each other; a second gap between the current collecting region and the different type bus region; The size of the second gap in the second direction is equal to or greater than the size of the first gap in the first direction.

[0009] Optionally, a ratio of the size of the second gap in the second direction to the size of the first gap in the first direction is 1-4.

[0010] Optionally, the volume of one of said P-type bus regions is equal to or greater than the volume of one of said N-type bus regions.

[0011] Optionally, the ratio of the volume of one of said P-type bus regions to the volume of one of said N-type bus regions is 1-2.

[0012] Optionally, the silicon substrate has N-type doping; The ratio of the width of one of the N-type current collecting regions to the width of one of the P-type current collecting regions is 0.5 to 1.5, and the width directions of the N-type current collecting regions and the P-type current collecting regions are both parallel to the first direction.

[0013] Optionally, the ratio of the width of one of the N-type current collecting regions to the width of one of the P-type current collecting regions is 0.85 to 1.2.

[0014] Optionally, the silicon substrate has N-type doping, and the ratio of the volume of one of the P-type current collecting regions to the volume of one of the N-type current collecting regions is 0.5-4.

[0015] Optionally, the ratio of the volume of one of the P-type current collecting regions to the volume of one of the N-type current collecting regions is 0.8 to 2.4.

[0016] Optionally, the silicon substrate has P-type doping, and the volume of one of the P-type current collecting regions is smaller than the volume of one of the N-type current collecting regions.

[0017] Optionally, the ratio of the volume of one of the P-type current collecting regions to the volume of one of the N-type current collecting regions is 0.1 to 0.8.

[0018] Optionally, the silicon substrate has P-type doping, a width of one of the N-type current collecting regions is greater than a width of one of the P-type current collecting regions, and a width direction of the N-type current collecting region and a width direction of the P-type current collecting region are both parallel to the first direction.

[0019] Optionally, the ratio of the width of one of said N-type current collecting regions to the width of one of said P-type current collecting regions is 2.5-8.

[0020] optionally, a ratio of the width of one of the P-type bus regions to the width of one of the N-type bus regions is 0.95 to 1.05; Alternatively, the ratio of the length of one of the P-type current collecting regions to the length of one of the N-type current collecting regions is 0.95 to 1.05.

[0021] Optionally, the back contact solar cell comprises: P-type current collecting grid lines located in the P-type current collecting region; P-type bus grid lines located in the P-type bus region; N-type current collecting grid lines located in the N-type current collecting region; an N-type bus grid line located in the N-type bus region, Each of the N-type current collecting grid lines located between one of the N-type bus grid lines and one of the P-type bus grid lines adjacent thereto is electrically connected to the N-type bus grid line, and each of the P-type current collecting grid lines is electrically connected to the P-type bus grid line.

[0022] Optionally, the ratio of the length of one current collecting grid line to the width of one bus grid line is 22 to 64, the current collecting grid line is the P-type current collecting grid line or the N-type current collecting grid line, the bus grid line is the P-type bus grid line or the N-type bus grid line, and the length direction of the current collecting grid line and the width direction of the bus grid line are both parallel to the second direction.

[0023] Optionally, a surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate is farther from the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate, and a height difference between the surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate is greater than 0 and not greater than 4.85 microns; Alternatively, a surface of the P-type doped polycrystalline silicon layer close to the silicon substrate and a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate are arranged in the same plane, Alternatively, a surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate is closer to the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate, and the difference in height between the surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate is greater than 0 and not greater than 0.3 microns.

[0024] Optionally, a surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate is farther from the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate, and a difference in height between the surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate is greater than 0 and not greater than 1.6 microns.

[0025] Optionally, the back contact solar cell comprises: The device further includes a first dielectric layer located between the P-type doped polycrystalline silicon layer and a first region on the first side of the silicon substrate.

[0026] Optionally, a surface of the first dielectric layer closer to the silicon substrate is farther from the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate, and a height difference between the surface of the first dielectric layer closer to the silicon substrate and a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate is greater than 0 and not greater than 4.85 microns; Alternatively, a surface of the first dielectric layer close to the silicon substrate and a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate are arranged in the same plane, Alternatively, a surface of the first dielectric layer closer to the silicon substrate is closer to the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate, and the difference in height between the surface of the first dielectric layer closer to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite to the silicon substrate is greater than 0 and not greater than 0.3 microns.

[0027] Optionally, a surface of the first dielectric layer closer to the silicon substrate is farther from the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate, and a difference in height between the surface of the first dielectric layer closer to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate is greater than 0 and not greater than 1.6 microns.

[0028] A second aspect of the present invention provides a solar module comprising a plurality of any one of the back contact solar cells described above. [Effects of the Invention]

[0029] The back contact solar cells and solar modules described above have the same or similar beneficial effects and will be omitted here to avoid duplication. [Brief explanation of the drawings]

[0030] In order to more clearly describe the technical solutions of the embodiments of the present invention, the following will briefly describe the drawings used in describing the embodiments of the present invention. Of course, the drawings described below are only a part of the embodiments of the present invention, and those skilled in the art can conceive of other drawings based on these drawings without any creative efforts.

[0031] [Figure 1] 1 shows a schematic diagram of a front view structure of a back contact solar cell in an embodiment of the present invention. [Figure 2] 1 shows a schematic diagram of a planar structure of a back contact solar cell in an embodiment of the present invention. [Figure 3] 1 is a schematic diagram showing a partial planar structure of a back contact solar cell according to an embodiment of the present invention. [Figure 4] 1 shows a schematic diagram of a first partial front view structure of a back contact solar cell in an embodiment of the present invention. [Figure 5] 2 shows a schematic diagram of a second partial front view structure of a back contact solar cell in an embodiment of the present invention. [Figure 6] 1 shows a schematic diagram of a third partial front view structure of a back contact solar cell in an embodiment of the present invention. [Figure 7] 1 shows a schematic diagram of a fourth partial front view structure of a back contact solar cell in an embodiment of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0032] Hereinafter, the technical solutions in the embodiments of the present invention will be clearly and completely described with reference to the drawings in the embodiments of the present invention, and it should be understood that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without any creative efforts shall fall within the protection scope of the present invention.

[0033] The main reason for the poor passivation effect in prior art back-contact solar cells is the difficulty of fabricating a highly P-doped polycrystalline silicon layer due to process limitations and other factors. In prior art, the thickness of the P-doped polycrystalline silicon layer in back-contact solar cells is small, resulting in excessive metallization damage or excessive contact resistance in the P-doped polycrystalline silicon layer. For example, the solid solubility of boron is relatively low, making it difficult to achieve a high doping concentration. If the polycrystalline silicon layer is too thin, the metallization damage in the P region increases and the ablation ability of the metal slurry decreases, resulting in excessive metal-silicon contact resistance and efficiency loss.

[0034] FIG. 1 shows a schematic diagram of a front view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 2 shows a schematic diagram of a plan view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 3 shows a schematic diagram of a partial plan view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 4 shows a schematic diagram of a first partial front view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 5 shows a schematic diagram of a second partial front view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 6 shows a schematic diagram of a third partial front view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 7 shows a schematic diagram of a fourth partial front view structure of a back contact solar cell according to an embodiment of the present invention. FIG. 3 is a schematic diagram of a portion between two bus grid lines of different types in FIG. 2. Note that the size representations in FIGS. 1 to 3 are merely illustrative and do not represent the actual relative size relationships of the sizes.

[0035] The present invention provides a back-contact solar cell. Referring to Figure 1, the back-contact solar cell may include a silicon substrate 1 having opposing first and second sides, where the first side is closer to an electrode. For example, in Figure 1, the first side of the silicon substrate 1 is the bottom side and the second side is the top side.

[0036] In Figure 1, dashed lines L1 and L2 are shown merely to distinguish the first and second regions and do not actually exist in the back-contact solar cell. Referring to Figure 1, the back-contact solar cell further includes a P-type doped polycrystalline silicon layer 2 located in a first region on a first side of a silicon substrate 1. On the first side of the silicon substrate 1, the region to the left of dashed line L1 is the first region, and the region to the right of dashed line L2 is the second region. The P-type doped polycrystalline silicon layer 2 is located in the region to the left of dashed line L1 on the first side of the silicon substrate 1.

[0037] The N-type doped polycrystalline silicon layer 3 is located in a second region on the first side of the silicon substrate 1. The first region is different from the second region. As shown in FIG. 1, the N-type doped polycrystalline silicon layer 3 is located in a region to the right of the dashed line L2 on the first side of the silicon substrate 1.

[0038] The ratio of the thickness d1 of the P-type doped polycrystalline silicon layer 2 to the thickness d2 of the N-type doped polycrystalline silicon layer 3 is 1-2. That is, the thickness d1 of the P-type doped polycrystalline silicon layer 2 and the thickness d2 of the N-type doped polycrystalline silicon layer 3 may be equal, i.e., the ratio between them is equal to 1; or the thickness d1 of the P-type doped polycrystalline silicon layer 2 may be slightly greater than the thickness d2 of the N-type doped polycrystalline silicon layer 3, i.e., the ratio between them is greater than 1 and less than or equal to 2, or may be the set (1, 2). In these two cases, the larger thickness d1 of the P-type doped polycrystalline silicon layer 2 can improve the passivation effect of the P-type doped polycrystalline silicon layer 2 and ensure small metallization damage and small contact resistance. When the thickness d1 of the P-type doped polycrystalline silicon layer 2 is slightly greater than the thickness d2 of the N-type doped polycrystalline silicon layer 3, the thicknesses of the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 can be set according to their respective doping concentrations and passivation effects, etc., which not only improves the passivation effect and doping concentration but also saves materials.

[0039] For example, the ratio of the thickness d1 of the P-type doped polycrystalline silicon layer 2 to the thickness d2 of the N-type doped polycrystalline silicon layer 3 may be 1, 1.01, 1.05, 1.1, 1.15, 1.2, 1.25, 1.3, 1.35, 1.4, 1.45, 1.5, 1.55, 1.6, 1.65, 1.7, 1.75, 1.8, 1.85, 1.9, 1.92, or 2.

[0040] It should be noted that the thickness direction mentioned in the present specification corresponds to the direction in which the silicon substrate 1 and the P-type doped polycrystalline silicon layer 2 are stacked.

[0041] Optionally, when the ratio of d1 to d2 is 1 to 2, the thickness d1 of the P-type doped polycrystalline silicon layer 2 may be 100 nm (nano) to 500 nm, and the thickness d2 of the N-type doped polycrystalline silicon layer 3 may be 50 nm to 300 nm. When d1 and d2 are within the above ranges, on the one hand, it is easy to achieve good doping effects for both the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3, and on the other hand, both have good passivation effects, ensure small metallization damage and small contact resistance, and are relatively low cost.

[0042] For example, the thickness d1 of the P-type doped polycrystalline silicon layer 2 may be 100 nm, 103 nm, 130 nm, 143 nm, 172 nm, 190 nm, 205 nm, 250 nm, 283 nm, 300 nm, 301 nm, 342 nm, 367 nm, 370 nm, 420 nm, 456 nm, 482 nm, or 500 nm. For example, the thickness d2 of the N-type doped polycrystalline silicon layer 3 may be 50 nm, 52 nm, 60 nm, 66.7 nm, 73 nm, 81 nm, 90 nm, 92 nm, 100 nm, 112 nm, 133 nm, 144 nm, 175 nm, 190 nm, 211 nm, 243 nm, 270 nm, 282 nm, 296 nm, or 300 nm.

[0043] 2 and 3, the P-type doped polycrystalline silicon layer 2 includes a plurality of P-type current collecting regions 21 and a plurality of P-type bus regions 22. The N-type doped polycrystalline silicon layer 3 includes a plurality of N-type current collecting regions 31 and a plurality of N-type bus regions 32. In FIGS. 2 and 3, the up-down direction indicated by the dashed line L3 is the first direction, and the left-right direction indicated by the dashed line L4 is the second direction. The N-type current collecting regions 31 and the P-type current collecting regions 21 are alternately arranged along the first direction L3 and both extend along the second direction L4. That is, the N-type current collecting regions 31 and the P-type current collecting regions 21 both extend along the second direction L4, and in the first direction L3, one N-type current collecting region 31, then one P-type current collecting region 21, another N-type current collecting region 31, and yet another P-type current collecting region 21 are alternately arranged in this manner. The first direction L3 and the second direction L4 are different and are both perpendicular to the thickness direction. The size of the angle between the first direction L3 and the second direction L4 is not specifically limited. For example, in Figures 2 and 3, the first direction L3 and the second direction L4 are perpendicular.

[0044] The N-type bus regions 32 and the P-type bus regions 22 are alternately arranged along the second direction L4, and all extend along the first direction L3. That is, the N-type bus regions 32 and the P-type bus regions 22 both extend along the first direction L3, and in the second direction L4, one N-type bus region 32, then one P-type bus region 22, another N-type bus region 32, and yet another P-type bus region 22 are alternately arranged in this manner.

[0045] Referring to FIG. 3, each of the N-type current collecting regions 31 located between one N-type bus region 32 and one adjacent P-type bus region 22 communicates with the N-type bus region 32, and each of the P-type current collecting regions 21 communicates with the P-type bus region 22, and the back contact solar cell thus formed is an IBC solar cell.

[0046] Here, the P-type current collecting region 21 or the N-type current collecting region 31 is collectively referred to as a current collecting region. Here, the N-type bus region 32 and the P-type bus region 22 are collectively referred to as a bus region. The ratio of the length of one current collecting region to the width of one bus region is 22 to 64. The length direction of the current collecting region and the width direction of the bus region are both parallel to the second direction L4. Typically, the length d3 of one P-type current collecting region 21 and the length of one N-type current collecting region 31 are equal or nearly equal, and the width d4 of one N-type bus region 32 and the width d5 ​​of one P-type bus region 22 are equal or nearly equal. Therefore, here, the ratio of the length of one current collecting region to the width of one bus region is 22 to 64, corresponding to four situations. In the first situation, the ratio of the length d3 of one P-type current collecting region 21 to the width d5 ​​of one P-type bus region 22 is between 22 and 64. In the second situation, the ratio of the length d5 ​​of one N-type current collecting region 31 to the width d5 ​​of one P-type bus region 22 is between 22 and 64. In the third situation, the ratio of the length d3 of one P-type current collecting region 21 to the width d4 of one N-type bus region 32 is between 22 and 64. If the ratio of the length of one current collecting region to the width of one bus region is too small, the battery efficiency will be reduced. If this ratio is too large, the battery's series resistance will increase. A ratio of 22 to 64 is appropriate, ensuring better battery performance and avoiding material waste.

[0047] For example, the ratio of the length of one current collecting area to the width of one bus area may be 22, 22.4, 27, 29, 31.2, 33, 36, 38, 40, 45.4, 48.7, 51.2, 53.7, 57.3, 60, 62.4, or 64.

[0048] Optionally, the ratio of the width d5 ​​of one P-type bus region 22 to the width d4 of one N-type bus region 32 is 0.95 to 1.05, and the width d5 ​​of one P-type bus region 22 is equal to or approximately equal to the width d4 of one N-type bus region 32. The process is simple, making it easy to manufacture, and the carrier focusing effect is also good.

[0049] For example, the ratio of the width d5 ​​of one P-type bus region 22 to the width d4 of one N-type bus region 32 may be 0.95, 0.96, 0.968, 0.977, 0.986, 0.99, 0.993, 1.0, 1.01, 1.016, 1.02, 1.03, 1.04, 1.043, or 1.05.

[0050] Optionally, the width d5 ​​of one P-type bus region 22 is 300 μm (microns) to 800 μm, and the width d4 of one N-type bus region 32 is 300 μm to 800 μm. Both have a good carrier convergence effect and do not result in wasted material.

[0051] For example, the width d5 ​​of one P-type bus region 22 may be 300 μm, 312 μm, 343 μm, 350 μm, 362 μm, 391 μm, 410 μm, 442 μm, 467 μm, 492 μm, 500 μm, 532 μm, 550 μm, 589.2 μm, 632.3 μm, 662 μm, 711 μm, 753.2 μm, 763 μm, 788 μm, or 800 μm. For example, the width d4 of one N-type bus region 32 may be 300 μm, 333 μm, 351 μm, 360.1 μm, 374 μm, 391 μm, 423 μm, 451 μm, 499 μm, 513 μm, 531 μm, 550 μm, 591 μm, 625 μm, 678.1 μm, 743 μm, 762.1 μm, 777 μm, or 800 μm.

[0052] Optionally, the volume of one P-type bus region 22 is equal to or greater than the volume of one N-type bus region 32. The large volume of the P-type bus region 22 can improve the passivation effect of the P-type bus region 22 and ensure small metallization damage and small contact resistance.

[0053] Optionally, the ratio of the volume of one P-type bus region 22 to the volume of one N-type bus region 32 is 1 to 2. Specifically, the length of one P-type bus region 22 is approximately equal to the length of one N-type bus region 32, the width d5 ​​of one P-type bus region 22 is approximately equal to the width d4 of one N-type bus region 32, and the ratio of the thickness of one P-type bus region 22 to the thickness of one N-type bus region 32 is 1 to 2, so the ratio of the volume of one P-type bus region 22 to the volume of one N-type bus region 32 is 1 to 2. The ratio of the two volumes may be equal, i.e., the ratio is equal to 1; or the volume of one P-type bus region 22 may be slightly larger than the volume of one N-type bus region 32, i.e., the ratio is greater than 1 but less than or equal to 2, or may be the set (1, 2). In these two cases, the larger volume of the P-type bus region 22 improves the passivation effect of the P-type bus region 22 and ensures small metallization damage and small contact resistance. If the volume of the P-type bus region 22 is slightly larger than the N-type bus region 32, the P-type bus region 22 and the N-type bus region 32 can each be set to a corresponding thickness according to the corresponding doping concentration, passivation effect, etc., in this way, not only can the passivation effect and doping concentration be improved, but material can also be saved.

[0054] For example, the ratio of the volume of one P-type bus region 22 to the volume of one N-type bus region 32 may be 1, 1.01, 1.1, 1.21, 1.32, 1.37, 1.44, 1.46, 1.5, 1.58, 1.63, 1.71, 1.79, 1.8, 1.86, 1.92, 1.96, or 2.

[0055] Optionally, the ratio of the length d3 of one P-type current collecting region 21 to the length of one N-type current collecting region 31 is 0.95 to 1.05, and the length d3 of one P-type current collecting region 21 is equal to or approximately equal to the length of one N-type current collecting region 31. The process is simple, making it easy to manufacture, and the carrier focusing effect is also good.

[0056] For example, the ratio of the length d3 of one P-type current collecting region 21 to the length of one N-type current collecting region 31 may be 0.95, 0.951, 0.962, 0.985, 0.99, 0.993, 1.0, 1.01, 1.017, 1.02, 1.028, 1.03, 1.04, 1.047, or 1.05.

[0057] Optionally, there is a first gap between adjacent N-type current collecting regions 31 and P-type current collecting regions 21, and the size of the first gap in the first direction L3 is d6. There is a second gap between a current collecting region and a bus region of a different type, and the size of the second gap in the second direction L4 is d7. Here, the P-type current collecting regions 21 or the N-type current collecting regions 31 are collectively referred to as current collecting regions. Here, the N-type bus region 32 or the P-type bus region 22 are collectively referred to as bus regions. That is, there is a second gap between the P-type current collecting region 21 and the N-type bus region 32. There is a second gap between the N-type current collecting region 31 and the P-type bus region 22. The size d7 of the second gap in the second direction L4 is equal to or greater than the size d6 of the first gap in the first direction L3. Specifically, since the current flowing through the bus region is typically large, and the size d7 in the second direction L4 of the second gap between the current collecting region and the bus region of a different type is equal to or larger than the size d6 in the first direction L3 of the first gap between the adjacent N-type current collecting region 31 and P-type current collecting region 21, the possibility of a short circuit is lower, and high yield and reliability can be maintained.

[0058] Optionally, the ratio of the size d7 of the second gap in the second direction L4 to the size d6 of the first gap in the first direction L3 is 1 to 4. If this ratio is too large, there is a possibility of waste, and if it is too small, there is a risk of short circuit. If this ratio is between 1 and 4, the ratio range is appropriate, and not only is there a low possibility of short circuit, but there is also essentially no waste.

[0059] For example, the ratio of the size d7 of the second gap in the second direction L4 to the size d6 of the first gap in the first direction L3 may be 1, or the ratio may be a set (1, 4), or the ratio may be 1.01, 1.05, 1.09, 1.095, 1.1, 1.12, 1.143, 1.16, 1.17, 1.19, 1.20, 1.24, 1.28, 1.3, 1.32, 1.329, 1.34, 1.45, 1.62, 1.95, 2.1, 2.32, 2.66, 2.93, 3.16, 3.57, 3.71, 3.89, or 4.

[0060] Optionally, the size d6 of the first gap in the first direction L3 is 50 μm to 150 μm, and the size d7 of the second gap in the second direction L4 is 50 μm to 200 μm, and the two gaps not only reduce the possibility of short circuits but also essentially eliminate waste.

[0061] For example, the size d6 of the first gap in the first direction L3 may be 50 μm, 58 μm, 69 μm, 72 μm, 78 μm, 81 μm, 86 μm, 93 μm, 97.2 μm, 99 μm, 100 μm, 100.3 μm, 102 μm, 105.7 μm, 109.2 μm, 111 μm, 117 μm, 123 μm, 130 μm, 142.2 μm, 147.3 μm or 150 μm. For example, the size d7 of the second gap in the second direction L4 may be 50 μm, 53.2 μm, 58 μm, 61 μm, 63 μm, 74 μm, 75.2 μm, 80 μm, 83 μm, 86 μm, 99 μm, 101 μm, 109 μm, 113 μm, 118 μm, 120.3 μm, 125 μm, 131 μm, 137 μm, 143 μm, 155 μm, 161 μm, 177 μm, 185 μm or 200 μm.

[0062] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 is 0.5 to 1.5. Here, the direction of the width d8 of the N-type current collecting region 31 and the direction of the width d9 of the P-type current collecting region 21 are both parallel to the first direction L3. Specifically, the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 is 0.5 to 1.5. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow, and balanced passivation of the P and N regions can be achieved to ensure better open-circuit voltage of the battery, thereby ensuring good collection effects for both holes and electrons and improving battery efficiency.

[0063] For example, the silicon substrate 1 has N-type doping and the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 may be 0.5, 0.53, 0.61, 0.67, 0.7, 0.76, 0.79, 0.85, 0.863, 0.87, 0.89, 0.9, 0.93, 0.97, 1.0, 1.09, 1.15, 1.23, 1.3, 1.46 or 1.5.

[0064] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 is 0.85 to 1.2. Here, the direction of the width d8 of the N-type current collecting region 31 and the direction of the width d9 of the P-type current collecting region 21 are both parallel to the first direction L3. Specifically, the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 is 0.85 to 1.2. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow, and balanced passivation of the P and N regions can be achieved to ensure better open-circuit voltage of the battery, thereby ensuring good collection effects for both holes and electrons and improving battery efficiency.

[0065] For example, the silicon substrate 1 has N-type doping and the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 may be 0.85, 0.859, 0.86, 0.862, 0.868, 0.87, 0.876, 0.88, 0.896, 0.9, 0.92, 0.935, 0.961, 0.973, 0.98, 1.0, 1.06, 1.08, 1.139, 1.15, 1.199 or 1.2.

[0066] Optionally, the silicon substrate 1 has N-type doping, with the width d8 of one N-type current collecting region 31 being 380 μm to 500 μm, and the width d9 of one P-type current collecting region 21 being 300 μm to 450 μm. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow, and the passivation of the P and N regions can be balanced to ensure better open-circuit voltage of the battery, thereby ensuring good collection of both holes and electrons and improving battery efficiency.

[0067] For example, the silicon substrate 1 has N-type doping and the width d8 of one N-type current collecting region 31 may be 380 μm, 387 μm, 394.3 μm, 401 μm, 406 μm, 410 μm, 427 μm, 430 μm, 440 μm, 446.5 μm, 453.1 μm, 466 μm, 472 μm, 479 μm, 483 μm, 493 μm or 500 μm. For example, the silicon substrate 1 may have N-type doping and the width d9 of one P-type current collecting region 21 may be 300 μm, 301 μm, 323 μm, 352.1 μm, 363 μm, 369 μm, 375 μm, 379.2 μm, 380 μm, 390 μm, 395.4 μm, 413 μm, 415.1 μm, 420.3 μm, 427.3 μm, 435 μm, 440 μm, 443 μm or 450 μm.

[0068] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 is 0.5 to 4. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow, and the passivation of the P and N regions can be balanced to improve the passivation effect and ensure better open-circuit voltage of the battery. In addition, small metallization damage and small contact resistance can be ensured, and good collection effect for both holes and electrons can be ensured, thereby improving the efficiency of the battery.

[0069] For example, the silicon substrate 1 has N-type doping and the ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 may be 0.5, 0.52, 0.57, 0.61, 0.68, 0.7, 0.79, 0.85, 0.97, 0.985, 1.07, 1.13, 1.25, 1.37, 1.45, 1.57, 1.61, 1.72, 1.83, 1.93, 2.11, 2.27, 2.4, 2.77, 2.885, 2.97, 3, 3.1, 3.37, 3.45, 3.57, 3.61, 3.72, 3.83, 3.93 or 4.

[0070] Optionally, the silicon substrate 1 has N-type doping, and the ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 is 0.8 to 2.4. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow, and the passivation of the P and N regions can be balanced to improve the passivation effect and ensure better open-circuit voltage of the battery. In addition, small metallization damage and small contact resistance can be ensured, and good collection effect for both holes and electrons can be ensured, thereby improving the efficiency of the battery.

[0071] For example, the silicon substrate 1 has N-type doping and the ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 may be 0.8, 0.82, 0.87, 0.91, 0.93, 0.975, 1.01, 1.16, 1.25, 1.35, 1.45, 1.53, 1.64, 1.72, 1.83, 1.91, 2.11, 2.29 or 2.4.

[0072] Optionally, the silicon substrate 1 has P-type doping, and the volume of one P-type current collecting region 21 is smaller than the volume of one N-type current collecting region 31. In this way, a reasonable junction area ratio can be ensured, which can ensure better current, improve the passivation effect, ensure better open circuit voltage of the battery, and also ensure small metallization damage and small contact resistance, and ensure good collection effect for both holes and electrons, thereby improving the efficiency of the battery.

[0073] Optionally, the silicon substrate 1 has P-type doping, and the ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 is 0.1 to 0.8. In this case, electrons collected in the N-type current collecting region 31 are minority carriers, and the volume ratio between the two is appropriate. In this way, a good collection effect for both holes and electrons can be ensured, improving the efficiency of the battery.

[0074] For example, the silicon substrate 1 has P-type doping and the ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 may be 0.1, 0.17, 0.27, 0.31, 0.38, 0.41, 0.43, 0.45, 0.5, 0.57, 0.63, 0.67, 0.69, 0.72, 0.77, 0.79 or 0.8.

[0075] Optionally, the silicon substrate 1 has P-type doping, and the width d8 of one N-type current collecting region 31 is larger than the width d9 of one P-type current collecting region 21. In this case, the electrons collected in the N-type current collecting region 31 are minority carriers, and the width d8 of the N-type current collecting region 31 is large. This contributes to the collection of minority carriers and can improve the efficiency of the back-contact solar cell. Note that the direction of the width d8 of the N-type current collecting region 31 and the direction of the width d9 of the P-type current collecting region 21 are both parallel to the first direction L3.

[0076] Optionally, the silicon substrate 1 has P-type doping, and the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 is appropriately set to 2.5 to 8. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow, and the passivation of the P and N regions can be balanced to improve the passivation effect, resulting in better open-circuit voltage of the battery, and a good collection effect for both holes and electrons, thereby improving battery efficiency.

[0077] For example, the silicon substrate 1 has P-type doping and the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 may be 2.5, 2.69, 2.72, 2.89, 2.93, 3.1, 3.3, 3.89, 4.0, 4.56, 4.99, 5.15, 5.25, 5.5, 6.64, 6.87, 7.32, 7.59 or 8.

[0078] Optionally, the silicon substrate 1 has P-type doping, and the width d8 of one N-type current collecting region 31 is 500 μm to 800 μm, and the width d9 of one P-type current collecting region 21 is 100 μm to 200 μm. In this way, a reasonable junction area ratio can be ensured, resulting in better current flow. The passivation of the P and N regions can be balanced to improve the passivation effect, resulting in better open-circuit voltage of the battery. A good collection effect for both holes and electrons can be ensured, improving the efficiency of the battery.

[0079] For example, the silicon substrate 1 may have P-type doping and the width d8 of one N-type current collecting region 31 may be 500 μm, 522 μm, 531.3 μm, 541.3 μm, 588 μm, 601 μm, 623 μm, 647 μm, 650 μm, 666 μm, 683.1 μm, 672 μm, 694 μm, 713 μm, 756 μm, 783.2 μm or 800 μm. For example, the silicon substrate 1 may have P-type doping and the width d9 of one P-type current collecting region 21 may be 100 μm, 101 μm, 111.3 μm, 125 μm, 133 μm, 146 μm, 150 μm, 158.7 μm, 161 μm, 169 μm, 173 μm, 180.3 μm, 187.7 μm, 191 μm, 193 μm, 199.7 μm or 200 μm.

[0080] Optionally, referring to FIGS. 2 and 3 , the back-contact solar cell further includes a P-type current collecting grid line 41 located in the P-type current collecting region 21 and used to collect holes from the P-type current collecting region 21, a P-type bus grid line 42 located in the P-type bus region 22 and constituting a positive electrode 4 together with the P-type current collecting grid line 41, an N-type current collecting grid line 51 located in the N-type current collecting region 31 and used to collect electrons from the N-type current collecting region 31, and an N-type bus grid line 52 located in the N-type bus region 32 and constituting a negative electrode 5 together with the N-type current collecting grid line 51. Each of the N-type current collecting grid lines 51 located between one N-type bus grid line 52 and its adjacent P-type bus grid line 42 is electrically connected to the N-type bus grid line 52, and the N-type bus grid line 52 is for conducting electrons from the N-type current collecting grid line 51 electrically connected to it, and each of the P-type current collecting grid lines 41 is electrically connected to the P-type bus grid line 42, and the P-type bus grid line 42 is for conducting holes from the P-type current collecting grid line 41 electrically connected to it. The back-contact solar cell is an IBC solar cell, which not only has high conversion efficiency but also good appearance and is easier to assemble into a solar module.

[0081] Here, the P-type current collecting grid lines 41 or the N-type current collecting grid lines 51 are collectively referred to as current collecting grid lines. Here, the N-type bus grid lines 52 or the P-type bus grid lines 42 are collectively referred to as bus grid lines. The ratio of the length of one current collecting grid line to the width of one bus grid line is 22 to 64. The length direction of the current collecting grid lines and the width direction of the bus grid lines are both parallel to the second direction L4. Typically, the length of one P-type current collecting grid line 41 and the length of one N-type current collecting grid line 51 are equal or nearly equal, and the width of one N-type bus grid line 52 and the width of one P-type bus grid line 42 are equal or nearly equal. Therefore, here, the ratio of the length of one current collecting grid line to the width of one bus grid line is 22 to 64, corresponding to four situations. In the first situation, the ratio of the length of one P-type current collecting grid line 41 to the width of one P-type bus grid line 42 is 22 to 64. In the second situation, the ratio of the length of one N-type current collecting grid line 51 to the width of one P-type bus grid line 42 is 22 to 64. In the third situation, the ratio of the length of one P-type current collecting grid line 41 to the width of one N-type bus grid line 52 is 22 to 64. In the fourth situation, the ratio of the length of one N-type current collecting grid line 51 to the width of one N-type bus grid line 52 is 22 to 64. If the ratio of the length of one current collecting grid line to the width of one bus grid line is too small, battery efficiency will be lost; if this ratio is too large, series resistance may increase. When the ratio of the length of one current collecting grid line to the width of one bus grid line is 22 to 64, this ratio is appropriate, ensuring better battery performance and avoiding material waste.

[0082] For example, the ratio of the length of one current collecting grid line to the width of one bus grid line may be 22, 23.1, 24.7, 27, 28, 29, 30.1, 31.2, 32.7, 33, 33.6, 37, 39.2, 40, 42.7, 44.8, 45.4, 49.1, 51.2, 53.7, 57.3, 58.1, 60, 62.4, 63, or 64.

[0083] Optionally, the surface of the second side of the silicon substrate 1 has a textured structure 11, thus providing a good light trapping effect and increasing the conversion efficiency of the back contact solar cell.

[0084] Optionally, the back contact solar cell further comprises a front surface passivation anti-reflective coating layer 6 located on the surface of the second side of the silicon substrate 1, and a back surface composite passivation film layer 7 located on the surfaces of the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3.

[0085] In Figures 4 to 7, dashed lines L1 and L2 are merely used to distinguish the first and second regions and do not actually exist in a back-contact solar cell. In Figures 4 to 7, on the first side of the silicon substrate 1, the region to the left of dashed line L1 is the first region, and the region to the right of dashed line L2 is the second region. A P-type doped polycrystalline silicon layer 2 is located in the region to the left of dashed line L1 on the first side of the silicon substrate 1. An N-type doped polycrystalline silicon layer 3 is located in the second region on the first side of the silicon substrate 1. The first region is different from the second region. The N-type doped polycrystalline silicon layer 3 is located in the region to the right of dashed line L2 on the first side of the silicon substrate 1.

[0086] Optionally, referring to FIG. 4 , the surface of the P-type doped polycrystalline silicon layer 2 close to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1. A height difference H1 between the surface of the P-type doped polycrystalline silicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 is greater than 0 and not greater than 4.85 microns (μm). Alternatively, the surface of the P-type doped polycrystalline silicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 are arranged on the same plane. Here, being arranged on the same plane means that the height difference between the surface of the P-type doped polycrystalline silicon layer 2 close to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 is 0. Alternatively, referring to FIG. 5 , the surface of the P-type doped polycrystalline silicon layer 2 close to the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1. The height difference H2 between the surface of P-type doped polycrystalline silicon layer 2 closest to silicon substrate 1 and the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1 is greater than 0 and not greater than 0.3 microns. If the relative positional relationship between the surface of P-type doped polycrystalline silicon layer 2 closest to silicon substrate 1 and the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1 satisfies the above three conditions, firstly, of P-type doped polycrystalline silicon layer 2 and N-type doped polycrystalline silicon layer 3, the previously fabricated doped polycrystalline silicon layer can be used as a positional reference during fabrication of the latter doped polycrystalline silicon layer, making it easier to control the thickness of the latter doped polycrystalline silicon layer and reducing the difficulty of the process. Second, in the above three situations, before the formation of the latter doped polycrystalline silicon layer, the portion of the first doped polycrystalline silicon layer that needs to be etched is completely etched away, and the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 in the gap between the first region and the second region are both completely etched away, resulting in good electrical performance, a high electrical insulation effect, and a low risk of short circuit or leakage.Thirdly, in the above three situations, the silicon substrate 1 is not over-etched, and hidden cracks and the like are less likely to occur in the back contact solar cell, and the mechanical performance is good.

[0087] 4 and 5, for example, the surface of P-type doped polycrystalline silicon layer 2 close to silicon substrate 1 is the lower surface of P-type doped polycrystalline silicon layer 2, and the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1 is the upper surface of N-type doped polycrystalline silicon layer 3. The second side of silicon substrate 1 is the lower side of silicon substrate 1. In FIG. 4, the lower surface of P-type doped polycrystalline silicon layer 2 is higher than the upper surface of N-type doped polycrystalline silicon layer 3, that is, the surface of P-type doped polycrystalline silicon layer 2 close to silicon substrate 1 is farther from the second side of silicon substrate 1 than the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1. In FIG. 4, the height difference H1 between the lower surface of the P-type doped polycrystalline silicon layer 2 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be a set of values ​​(0, 4.85 μm). For example, in FIG. 4, the height difference H1 between the lower surface of the P-type doped polycrystalline silicon layer 2 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be a set of values ​​(0.02 μm, 0.05 μm, 0.08 μm, 0.1 μm, 0.42 μm). , 0.92 μm, 1.02 μm, 1.46 μm, 1.57 μm, 1.83 μm, 1.95 μm, 2.03 μm, 2.21 μm, 2.37 μm, 2.42 μm, 2.64 μm, 2.97 μm, 3.11 μm, 3.53 μm, 3.69 μm, 3.92 μm, 4.07 μm, 4.26 μm, 4.37 μm, 4.62 μm or 4.85 μm.

[0088] In FIG. 5, the lower surface of the P-type doped polycrystalline silicon layer 2 is lower than the upper surface of the N-type doped polycrystalline silicon layer 3. That is, the surface of the P-type doped polycrystalline silicon layer 2 closer to the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1. In FIG. 5, the height difference H2 between the lower surface of the P-type doped polycrystalline silicon layer 2 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be set to a set of (0, 0.3 μm). For example, in FIG. 5, the height difference H2 between the lower surface of the P-type doped polycrystalline silicon layer 2 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be set to a set of (0, 0.3 μm). , 0.1 μm, 0.12 μm, 0.15 μm, 0.16 μm, 0.17 μm, 0.19 μm, 0.2 μm, 0.21 μm, 0.24 μm, 0.246 μm, 0.251 μm, 0.253 μm, 0.261 μm, 0.273 μm, 0.281 μm, 0.287 μm, 0.290 μm, 0.293 μm, 0.296 μm or 0.3 μm.

[0089] Optionally, referring to FIG. 4 , the surface of the P-type doped polycrystalline silicon layer 2 closest to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1. The height difference H1 between the surface of the P-type doped polycrystalline silicon layer 2 closest to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1 is greater than 0 and not greater than 1.6 μm. In this way, the relative positions of the two surfaces are more precisely controlled, the positional reference function is more accurate, and the portion to be etched in the first doped polycrystalline silicon layer formed earlier is more cleanly etched before the second doped polycrystalline silicon layer is formed. In addition, both the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 in the gap between the first and second regions are more cleanly etched, resulting in better electrical performance, a stronger electrical insulation effect, a lower risk of short circuits or leakage current, a lower risk of hidden cracks in the back-contact solar cell, and better mechanical performance.

[0090] In FIG. 4, the height difference H1 between the lower surface of the P-type doped polycrystalline silicon layer 2 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be within the range of 0 to 1.6 μm. For example, in FIG. 4, the height difference H1 between the lower surface of the P-type doped polycrystalline silicon layer 2 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be 0.02 μm, 0.03 μm, 0.04 μm, 0.05 μm, 0.07 μm, 0.08 μm, 0.1 μm, 0.15 μm, 0.22 μm, 0.34 μm, 0.41 μm, 0.52 μm, 0.63 μm, 0.72 μm, 0.8 μm, 0.95 μm, 1.02 μm, 1.22 μm, 1.34 μm, 1.46 μm, 1.57 μm, or 1.6 μm.

[0091] Optionally, referring to FIGS. 6 and 7, the back-contact solar cell further includes a first dielectric layer 8 located between the P-type doped polycrystalline silicon layer 2 and a first region on the first side of the silicon substrate 1. Whether the back-contact solar cell further includes a second dielectric layer is not specifically limited. For example, in FIGS. 6 and 7, the back-contact solar cell further includes a second dielectric layer 9 located between the N-type doped polycrystalline silicon layer 3 and a second region on the first side of the silicon substrate 1. Here, the thickness of each of the first and second dielectric layers 8 and 9 may be 1 nm to 2 nm, and the material of the first and second dielectric layers 8 and 9 may be silicon oxide, silicon nitride, silicon oxynitride, or the like. Here, both the first and second dielectric layers 8 and 9 can perform tunneling and passivation functions.

[0092] 6 , the surface of the first dielectric layer 8 close to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1, and a height difference H3 between the surface of the first dielectric layer 8 close to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 is greater than 0 and not greater than 4.85 microns. Alternatively, the surface of the first dielectric layer 8 close to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 are arranged on the same plane. Here, being arranged on the same plane means that the height difference between the surface of the first dielectric layer 8 close to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 is 0. 7 , the surface of first dielectric layer 8 close to silicon substrate 1 is closer to the second side of silicon substrate 1 than the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1, and the height difference H4 between the surface of first dielectric layer 8 close to silicon substrate 1 and the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1 is greater than 0 and not greater than 0.3 microns. If the relative positional relationship between the surface of first dielectric layer 8 close to silicon substrate 1 and the surface of N-type doped polycrystalline silicon layer 3 opposite to silicon substrate 1 satisfies the above three conditions, firstly, first dielectric layer 8 or N-type doped polycrystalline silicon layer 3 can serve as a certain positional reference, and appropriately reduce the difficulty of the process. Second, in the above three situations, the portion of the first doped polysilicon layer that needs to be etched is completely etched before the second doped polysilicon layer is formed, and the P-type doped polysilicon layer 2 and the N-type doped polysilicon layer 3 in the gap between the first and second regions are both completely etched, resulting in good electrical performance, high electrical insulation, and low risk of short circuits or leakage. Third, in the above three situations, the silicon substrate 1 is not over-etched, making it less likely for hidden cracks to occur in the back contact solar cell and resulting in good mechanical performance.

[0093] 6 and 7, for example, the surface of the first dielectric layer 8 close to the silicon substrate 1 is the lower surface of the first dielectric layer 8, and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 is the upper surface of the N-type doped polycrystalline silicon layer 3. The second side of the silicon substrate 1 is the lower side of the silicon substrate 1. In FIG. 6, the lower surface of the first dielectric layer 8 is higher than the upper surface of the N-type doped polycrystalline silicon layer 3, that is, the surface of the first dielectric layer 8 close to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1. In FIG. 6, the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be a set of (0, 4.85 μm). For example, in FIG. 6, the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be 0.02 μm, 0.05 μm, 0.072 μm, 0.1 μm, 0.42 μm, 0.92 μm, The thickness may be 1.02 μm, 1.46 μm, 1.57 μm, 1.84 μm, 1.95 μm, 2.03 μm, 2.21 μm, 2.37 μm, 2.42 μm, 2.64 μm, 2.97 μm, 3.11 μm, 3.53 μm, 3.69 μm, 3.92 μm, 4.07 μm, 4.26 μm, 4.37 μm, 4.62 μm or 4.85 μm.

[0094] 7, the lower surface of the first dielectric layer 8 is lower than the upper surface of the N-type doped polycrystalline silicon layer 3. That is, the surface of the first dielectric layer 8 closer to the silicon substrate 1 is closer to the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1. In FIG. 7, the height difference H4 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be set to a set of (0, 0.3 μm). For example, in FIG. 7, the height difference H4 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be set to a set of (0, 0.3 μm). It may be 0.12 μm, 0.15 μm, 0.16 μm, 0.17 μm, 0.19 μm, 0.2 μm, 0.21 μm, 0.24 μm, 0.246 μm, 0.251 μm, 0.253 μm, 0.261 μm, 0.273 μm, 0.281 μm, 0.287 μm, 0.290 μm, 0.293 μm, 0.296 μm or 0.3 μm.

[0095] Optionally, referring to FIG. 6 , the surface of the first dielectric layer 8 closest to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1, and the height difference H3 between the surface of the first dielectric layer 8 closest to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1 is greater than 0 and not greater than 1.6 microns. In this way, the relative positions of the two surfaces are more precisely controlled, the positional reference function is more accurate, and the portion to be etched in the first doped polycrystalline silicon layer formed earlier is more cleanly etched before the formation of the latter doped polycrystalline silicon layer. In addition, both the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3 in the gap between the first and second regions are more cleanly etched, resulting in better electrical performance, a stronger electrical insulation effect, a lower risk of short circuits or leakage current, a lower risk of hidden cracks in the back-contact solar cell, and better mechanical performance.

[0096] For example, referring to FIG. 6 , the lower surface of the first dielectric layer 8 is higher than the upper surface of the N-type doped polycrystalline silicon layer 3, i.e., the surface of the first dielectric layer 8 closer to the silicon substrate 1 is farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1. In FIG. 6, the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be a set (0, 1.6 μm). For example, in FIG. 6, the height difference H3 between the lower surface of the first dielectric layer 8 and the upper surface of the N-type doped polycrystalline silicon layer 3 may be 0.01 μm, 0.02 μm, 0.05 μm, 0.09 μm, 0.1 μm, 0.12 μm, 0.23 μm, 0.46 μm, 0.57 μm, 0.8 μm, 0.84 μm, 0.95 μm, 1.03 μm, 1.13 μm, 1.21 μm, 1.37 μm, 1.40 μm, 1.42 μm, 1.51 μm, or 1.6 μm.

[0097] The present invention also provides a solar module comprising a plurality of any one of the above back contact solar cells, and further comprising a package adhesive film or the like located on opposite sides of the back contact solar cells, although the specific structure of the solar module is not limited.

[0098] It should be noted that the solar module and the back contact solar cell have the same or similar beneficial effects, and the relevant points between them can be cross-referenced, which will be omitted here to avoid duplication.

[0099] The present application will be further explained with reference to the following specific examples, where pitch = width d9 of P-type current collecting region 21 + width d8 of N-type current collecting region 31 + 2 × size d6 of first gap in first direction L3.

[0100] Example 1 Referring to FIG. 1 , silicon substrate 1 is an N-type silicon substrate, and the second surface of silicon substrate 1 has a textured structure 11. A front surface passivation anti-reflective coating layer 6 is further provided on the second surface of silicon substrate 1. A P-type doped polycrystalline silicon layer 2 is provided in a first region on a first side of silicon substrate 1, and an N-type doped polycrystalline silicon layer 3 is provided in a second region on the first side, with a gap between the first and second regions. P-type doped polycrystalline silicon layer 2, N-type doped polycrystalline silicon layer 3, and the gap are covered with a rear surface composite passivation film layer 7. By using effective process means such as mask fabrication and laser grooving, the line width and length of the mask patterning and the line width and length of the laser grooving are controlled so that the P-type current collecting region 21, P-type bus region 22, N-type current collecting region 31, N-type bus region 32, and the gap have the following sizes and proportions:

[0101] 2 and 3, the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 was 0.5 to 1.5. The width d8 of one N-type current collecting region 31 was 380 μm to 500 μm, and the width d9 of one P-type current collecting region 21 was 300 μm to 450 μm. A first gap was present in the first direction L3 between adjacent N-type current collecting regions 31 and P-type current collecting regions 21, and the size d6 of the first gap in the first direction L3 was 50 μm to 150 μm.

[0102] The ratio of the width d4 of one N-type bus region 32 to the width d5 ​​of one P-type bus region 22 was approximately 1. The width d4 of one N-type bus region 32 and the width d5 ​​of one P-type bus region 22 were both 300 μm to 800 μm. The ratio of the length of one current collecting region to the width of one bus region was 22 to 64. The current collecting region here was the P-type current collecting region 21 or the N-type current collecting region 31, and the bus region here was the N-type bus region 32 or the P-type bus region 22. A second gap was present in the second direction L4 between the current collecting region and the bus region of a different type, and the size d7 of the second gap in the second direction L4 was 50 μm to 200 μm. The ratio of the length of one current collecting grid line to the width of one bus grid line was 22 to 64. The current collecting grid lines here were P-type current collecting grid lines 41 or N-type current collecting grid lines 51, and the bus grid lines here were P-type bus grid lines 42 or N-type bus grid lines 52. The length direction of the current collecting grid lines and the width direction of the bus grid lines were both parallel to the second direction L4. The ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 was 0.5 to 4.

[0103] 1, the ratio of the thickness d1 of the P-type doped polycrystalline silicon layer 2 to the thickness d2 of the N-type doped polycrystalline silicon layer 3 was 1 to 2. The thickness d1 of the P-type doped polycrystalline silicon layer 2 was 100 nm to 500 nm. The thickness d2 of the N-type doped polycrystalline silicon layer 3 was 50 nm to 300 nm.

[0104] The manufacturing method of the back contact solar cell corresponding to Example 1 is basically as follows.

[0105] S1: An N-type single crystal silicon wafer was selected, and the N-type single crystal silicon wafer was subjected to double-side polishing to remove damaged layers, thereby obtaining an N-type silicon substrate. S2: A tunnel oxide layer having a thickness of 1 nm to 3 nm and a polycrystalline silicon layer having a thickness of 100 nm to 500 nm were formed in a first region on a first side of an N-type silicon substrate. S3: Boron was deposited and diffused into the polycrystalline silicon layer to form a P-type doped polycrystalline silicon layer 2. S4: Using a block layer or laser grooving, the width d9 of one P-type current collecting region 21 is designed to be 300 μm to 450 μm (or the laser grooving width is 550 μm to 700 μm) (here, the width design is based on the pitch of adjacent same-type regions = 1000 μm). The block layer is designed so that the length of the current collecting region is 18.3 mm to 19.1 mm (or the laser grooving length is 18.7 mm to 19.2 mm). The block layer is designed so that the width of the bus region is 300 μm to 800 μm (or the laser grooving width of the bus region is 400 μm to 1200 μm). Next, the P-type doped polycrystalline silicon layer 2 is etched and removed by alkaline etching to an etching depth of 0.1 μm to 5 μm down to the silicon substrate, forming adjacent upper and middle layers arranged at a distance from each other. S5: On the first side of the silicon substrate 1 and the first side of the remaining P-type doped polycrystalline silicon layer 2, an N-region tunnel oxide layer having a thickness of 1 nm to 3 nm and a polycrystalline silicon layer having a thickness of 50 nm to 300 nm were formed. S6: Phosphorus was deposited and diffused into the polycrystalline silicon layer after step S5 to form an N-type doped polycrystalline silicon layer 3. S7: Printing a corrosion slurry or laser grooving was performed on the structure after step S6, at a position facing the P-type doped polycrystalline silicon layer 2 remaining after step S4, with the corrosion width or laser grooving width of the current collecting grid lines being 400 μm to 750 μm, and the corrosion width or laser grooving width of the bus grid lines being 400 μm to 1200 μm. S8: The second side of the N-type silicon substrate in the structure after step S7 is acid-etched, followed by alkali texturing to form a textured structure 11, which may be a pyramidal structure with optical trapping properties, on the front surface, and a staggered pattern of high, low, and middle regions on the back surface to isolate the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3. The size d6 of the first gap in the first direction L3 is 50 μm to 150 μm, the size d7 of the second gap in the second direction L4 is 50 μm to 200 μm, and the etching depth is 0.05 μm to 5 μm (compared to the middle layer N-type doped polycrystalline silicon layer 3. That is, the etching depth of the first gap and the etching depth of the second gap are both the distance from the surface of the silicon substrate adjacent to the middle layer N-type doped polycrystalline silicon layer 3 to the bottom of the gap area). S9: The structure after step S8 is passivated, and a multi-layer front surface passivation anti-reflection coating layer 6 is coated on the front surface, and a multi-layer passivation film is coated on the back surface to form a back surface composite passivation film layer 7. S10: Electrodes were printed at intervals on the rear surface composite passivation film layer 7, and a positive electrode 4 and a negative electrode 5 were formed on the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3, respectively, to form a low-layer gap region between the upper layer and the middle layer on the rear surface.

[0106] In Example 1, the first dielectric layer 8 and the second dielectric layer 9 were both tunnel oxide layers. In Example 1, the surface of the first dielectric layer 8 closest to the silicon substrate 1 was farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1, as shown in FIG. 6 , where the height difference H3 between the surface of the first dielectric layer 8 closest to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 was greater than 0 and less than or equal to 4.85 μm. This Example 1 ensures passivation effect and electrical performance, significantly reduces the risk of leakage, and allows for a rational design of each size, improving the mechanical performance of the battery and increasing the battery conversion efficiency.

[0107] Example 2 Example 2 differs from Example 1 only in that the etching depth in step S4 is 0.5 μm to 2 μm, and the etching depth in step S8 is 0.5 μm to 3 μm. Other aspects of Example 2 are the same as those of Example 1.

[0108] In Example 2, both the first dielectric layer 8 and the second dielectric layer 9 were tunnel oxide layers. In Example 2, the surface of the first dielectric layer 8 closest to the silicon substrate 1 was farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1, as shown in FIG. 6 , where the height difference H3 between the surface of the first dielectric layer 8 closest to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1 was greater than 0 and less than 1.6 μm. Example 2 also ensured passivation and electrical performance, significantly reduced the risk of leakage, rationalized the design of various dimensions, and improved the cell conversion efficiency. Furthermore, compared to Example 1, Example 2 had better electrical performance, a stronger electrical insulation effect, a lower risk of short circuits or leakage, a lower risk of hidden cracks in the back-contact solar cell, and better mechanical performance.

[0109] Example 3 Referring to FIG. 1 , the silicon substrate 1 is a P-type silicon substrate, and the second surface of the silicon substrate 1 has a textured structure 11. A front surface passivation anti-reflective coating layer 6 is further provided on the second surface of the silicon substrate 1. A P-type doped polycrystalline silicon layer 2 is provided in a first region on the first side of the silicon substrate 1, and an N-type doped polycrystalline silicon layer 3 is provided in a second region on the first side, with a gap between the first and second regions. The P-type doped polycrystalline silicon layer 2, the N-type doped polycrystalline silicon layer 3, and the gap are covered with a rear surface composite passivation film layer 7. Using effective process means such as mask fabrication and laser grooving, the line width and length of the mask patterning and the line width and length of the laser grooving are controlled so that the P-type current collecting region 21, the P-type bus region 22, the N-type current collecting region 31, the N-type bus region 32, the gap, etc., reach the following sizes and proportions:

[0110] 2 and 3, the ratio of the width d8 of one N-type current collecting region 31 to the width d9 of one P-type current collecting region 21 was 2.5 to 8. The width d8 of one N-type current collecting region 31 was 500 μm to 800 μm, and the width d9 of one P-type current collecting region 21 was 100 μm to 200 μm. A first gap was present in the first direction L3 between adjacent N-type current collecting regions 31 and P-type current collecting regions 21, and the size d6 of the first gap in the first direction L3 was 50 μm to 150 μm.

[0111] The ratio of the width d4 of one N-type bus region 32 to the width d5 ​​of one P-type bus region 22 was approximately 1. The width d4 of one N-type bus region 32 and the width d5 ​​of one P-type bus region 22 were both 300 μm to 800 μm. The ratio of the length of one current collecting region to the width of one bus region was 22 to 64. The current collecting region here was the P-type current collecting region 21 or the N-type current collecting region 31, and the bus region here was the N-type bus region 32 or the P-type bus region 22. A second gap was present in the second direction L4 between the current collecting region and the bus region of a different type, and the size d7 of the second gap in the second direction L4 was 50 μm to 200 μm. The ratio of the length of one current collecting grid line to the width of one bus grid line was 22 to 64. The current collecting grid lines here were P-type current collecting grid lines 41 or N-type current collecting grid lines 51, and the bus grid lines here were P-type bus grid lines 42 or N-type bus grid lines 52. The length direction of the current collecting grid lines and the width direction of the bus grid lines were both parallel to the second direction L4. The ratio of the volume of one P-type current collecting region 21 to the volume of one N-type current collecting region 31 was 0.1 to 0.8.

[0112] 1, the ratio of the thickness d1 of the P-type doped polycrystalline silicon layer 2 to the thickness d2 of the N-type doped polycrystalline silicon layer 3 was 1 to 2. The thickness d1 of the P-type doped polycrystalline silicon layer 2 was 100 nm to 500 nm. The thickness d2 of the N-type doped polycrystalline silicon layer 3 was 50 nm to 300 nm.

[0113] The fabrication method of the back contact solar cell corresponding to Example 3 is basically as follows.

[0114] S1: A P-type single crystal silicon wafer was selected, and the P-type single crystal silicon wafer was subjected to double-side polishing to remove damaged layers, thereby obtaining a P-type silicon substrate. S2: A tunnel oxide layer having a thickness of 1 nm to 3 nm and a polycrystalline silicon layer having a thickness of 100 nm to 500 nm were formed in a first region on a first side of a P-type silicon substrate. S3: Boron was deposited and diffused into the polycrystalline silicon layer to form a P-type doped polycrystalline silicon layer 2. S4: Using a block layer or laser grooving, the width d9 of one P-type current collecting region 21 is designed to be 100 μm to 200 μm (or the laser grooving width is 800 μm to 900 μm) (here, the width design is based on the pitch of adjacent same-type regions = 1000 μm). The block layer is designed so that the length of the current collecting region is 18.3 mm to 19.1 mm (or the laser grooving length is 18.7 mm to 19.2 mm). The block layer is designed so that the width of the bus region is 300 μm to 800 μm (or the laser grooving width of the bus region is 400 μm to 1200 μm). Next, the P-type doped polycrystalline silicon layer 2 is etched and removed by alkaline etching to an etching depth of 0.1 μm to 5 μm down to the silicon substrate, forming adjacent upper and middle layers arranged at a distance from each other. S5: On the first side of the silicon substrate 1 and the first side of the remaining P-type doped polycrystalline silicon layer 2, an N-region tunnel oxide layer having a thickness of 1 nm to 3 nm and a polycrystalline silicon layer having a thickness of 50 nm to 300 nm were formed. S6: Phosphorus was deposited and diffused into the polycrystalline silicon layer after step S5 to form an N-type doped polycrystalline silicon layer 3. S7: Printing a corrosion slurry or laser grooving was performed on the structure after step S6, at a position facing the P-type doped polycrystalline silicon layer 2 remaining after step S4, with the corrosion width or laser grooving width of the current collecting grid lines being 200 μm to 500 μm, and the corrosion width or laser grooving width of the bus grid lines being 400 μm to 1200 μm. S8: The second side of the N-type silicon substrate 1 in the structure after step S7 is acid-etched, followed by alkali texturing to form a textured structure 11, which may be a pyramidal structure with optical trapping effect, on the front surface, and a staggered pattern of high, low, and middle regions on the back surface to separate the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3. The size d6 of the first gap in the first direction L3 is 50 μm to 150 μm, the size d7 of the second gap in the second direction L4 is 50 μm to 200 μm, and the etching depth is 0.05 μm to 5 μm (compared to the middle layer N-type doped polycrystalline silicon layer 3. That is, the etching depth of the first gap and the etching depth of the second gap are both the distance from the surface of the silicon substrate adjacent to the middle layer N-type doped polycrystalline silicon layer 3 to the bottom of the gap area). S9: The structure after step S8 is passivated, and a multi-layer front surface passivation anti-reflection coating layer 6 is coated on the front surface, and a multi-layer passivation film is coated on the back surface to form a back surface composite passivation film layer 7. S10: Electrodes were printed at intervals on the rear surface composite passivation film layer 7, and a positive electrode 4 and a negative electrode 5 were formed on the P-type doped polycrystalline silicon layer 2 and the N-type doped polycrystalline silicon layer 3, respectively, to form a low-layer gap region between the upper layer and the middle layer on the rear surface.

[0115] In Example 3, the first dielectric layer 8 and the second dielectric layer 9 were both tunnel oxide layers. In Example 3, the surface of the first dielectric layer 8 closest to the silicon substrate 1 was farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1, as shown in FIG. 6 , where the height difference H3 between the surface of the first dielectric layer 8 closest to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite to the silicon substrate 1 was greater than 0 and less than or equal to 4.85 μm. Example 3 ensures passivation effect and electrical performance, significantly reduces the risk of leakage, and allows for a rational design of each size, improving the mechanical performance of the battery and increasing the battery conversion efficiency.

[0116] Example 4 Example 4 differs from Example 3 only in that the etching depth in step S4 is 0.5 μm to 2 μm, and the etching depth in step S8 is 0.5 μm to 3 μm. Other aspects of Example 4 are the same as those of Example 3.

[0117] In Example 4, both the first dielectric layer 8 and the second dielectric layer 9 were tunnel oxide layers. In Example 4, the surface of the first dielectric layer 8 closest to the silicon substrate 1 was farther from the second side of the silicon substrate 1 than the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1, as shown in FIG. 6 , where the height difference H3 between the surface of the first dielectric layer 8 closest to the silicon substrate 1 and the surface of the N-type doped polycrystalline silicon layer 3 opposite the silicon substrate 1 was greater than 0 and less than 1.6 μm. Example 4 also ensured passivation and electrical performance, significantly reduced the risk of leakage, rationalized the design of various dimensions, and improved the cell conversion efficiency. Furthermore, compared to Example 3, Example 4 had better electrical performance, a stronger electrical insulation effect, a lower risk of short circuits or leakage, a lower risk of hidden cracks in the back-contact solar cell, and better mechanical performance.

[0118] Although the method embodiments are expressed as a combination of a series of operations for ease of explanation, those skilled in the art should understand that the embodiments of the present application are not limited by the order of operations described, as some steps may be performed in other orders or simultaneously according to the embodiments of the present application. Furthermore, those skilled in the art should understand that all of the embodiments described in the specification are preferred embodiments, and that such operations are not necessarily required for the embodiments of the present application.

[0119] It should be noted that, as used herein, the terms "comprises," "consists of," or any other variation thereof, are intended to include a non-exclusive inclusion, whereby a process, method, article, or apparatus comprising a set of elements includes not only those elements but also other elements not expressly stated or inherent in such process, method, article, or apparatus. Unless otherwise specified, an element qualified by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0120] Although the embodiments of the present invention have been described above with reference to the drawings, the present invention is not limited to the above-mentioned specific embodiments, which are merely illustrative and not limiting. Based on the teachings of the present invention, many forms that a person skilled in the art can make without departing from the spirit of the present invention and the scope of protection of the claims are all within the scope of protection of the present invention. [Explanation of symbols]

[0121] 1. Silicon substrate 11 Texture Structure 2 P-type doped polycrystalline silicon layer 21 P-type current collection area 22 P-type bus area 3 N-type doped polycrystalline silicon layer 31 N-type current collecting area 32 N-type bus area 4 positive electrode 41 P-type current collecting grid lines 42 P-type bus grid lines 5 negative electrode 51 N-type current collecting grid lines 52 N-type bus grid lines 6 Surface passivation anti-reflection layer 7. Rear composite passivation film layer 8 First Dielectric Layer 9 Second dielectric layer d1 Thickness of P-type doped polycrystalline silicon layer 2 d2 Thickness of N-type doped polycrystalline silicon layer 3 d3 Length of one P-type current collecting region 21 d4 Width of one N-type bus region 32 d5 Width of one P-type bus region 22 d6 Size of the first gap in the first direction L3 d7 Size of the second gap in the second direction L4 d8 Width of one N-type current collecting region 31 d9 Width of one P-type current collecting region 21

Claims

1. a silicon substrate having opposing first and second sides; a P-type doped polycrystalline silicon layer located in a first region on a first side of the silicon substrate; an N-type doped polycrystalline silicon layer located in a second region on the first side of the silicon substrate, the second region being different from the first region; the thickness of the P-type doped polycrystalline silicon layer is greater than the thickness of the N-type doped polycrystalline silicon layer, and the ratio of the thickness of the P-type doped polycrystalline silicon layer to the thickness of the N-type doped polycrystalline silicon layer is 2 or less; a surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate is farther from the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate, and a difference in height between the surface of the P-type doped polycrystalline silicon layer closer to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate is greater than 0 and not greater than 4.85 microns.

2. further comprising a gap region; the P-type doped polycrystalline silicon layer has an upper layer structure, the N-type doped polycrystalline silicon layer has an intermediate layer structure, and the gap region has a lower layer structure; the upper layer structure and the intermediate layer structure are adjacently arranged and spaced apart on a first side of the silicon substrate; 10. The back contact solar cell of claim 1, wherein a gap region of a lower layer structure is disposed between the upper layer structure and the middle layer structure.

3. 3. The back contact solar cell of claim 2, wherein the depth of a gap region where the N-type doped polycrystalline silicon layer of the intermediate layer structure is close to the surface of the silicon substrate is 0.05 μm or more and 5 μm or less.

4. 10. The back contact solar cell of claim 1, wherein a staggered structure of high regions, low regions, and medium regions is formed on the first side of the silicon substrate.

5. the P-type doped polycrystalline silicon layer includes a plurality of P-type current collecting regions; the N-type doped polycrystalline silicon layer includes a plurality of N-type current collecting regions; 2. The back contact solar cell of claim 1 , wherein the N-type current collecting regions and the P-type current collecting regions are alternately arranged along a first direction and both extend along a second direction, the first direction and the second direction being different and both perpendicular to the thickness direction.

6. the P-type doped polycrystalline silicon layer further includes a plurality of P-type bus regions; the N-type doped polycrystalline silicon layer further includes a plurality of N-type bus regions; the N-type bus regions and the P-type bus regions are alternately arranged along the second direction and extend along the first direction; each of the N-type current collecting regions located between one of the N-type bus regions and one of the P-type bus regions adjacent thereto communicates with the N-type bus region; each of the P-type current collecting regions located between one of the N-type bus regions and one of the P-type bus regions adjacent thereto communicates with the P-type bus region; 6. The back contact solar cell of claim 5, wherein a ratio of the length of one current collecting region to the width of one bus region is 22 to 64, the current collecting region is the P-type current collecting region or the N-type current collecting region, the bus region is the P-type bus region or the N-type bus region, and the length direction of the current collecting region and the width direction of the bus region are both parallel to the second direction.

7. a first gap between the N-type current collecting region and the P-type current collecting region adjacent to each other; a second gap between the current collecting region and the different type bus region; 7. The back contact solar cell of claim 6, wherein the size of the second gap in the second direction is equal to or greater than the size of the first gap in the first direction.

8. a first gap between the N-type current collecting region and the P-type current collecting region adjacent to each other; a second gap between the current collecting region and the different type bus region; 7. The back contact solar cell of claim 6, wherein a ratio of the size of the second gap in the second direction to the size of the first gap in the first direction is between 1 and 4.

9. 7. The back contact solar cell of claim 6, wherein the volume of one of said P-type bus regions is equal to or greater than the volume of one of said N-type bus regions.

10. 7. The back contact solar cell of claim 6, wherein the ratio of the volume of one of said P-type bus regions to the volume of one of said N-type bus regions is 1-2.

11. the silicon substrate has N-type doping; 11. The back contact solar cell of claim 2, wherein a ratio of the width of one of the N-type current collecting regions to the width of one of the P-type current collecting regions is 0.5 to 1.5, and the width directions of the N-type current collecting regions and the P-type current collecting regions are both parallel to the first direction.

12. 11. The back contact solar cell of any one of claims 2 to 10, wherein the silicon substrate has N-type doping and the ratio of the volume of one of the P-type current collecting regions to the volume of one of the N-type current collecting regions is between 0.5 and 4.

13. 12. The back contact solar cell of claim 11 , wherein a surface of the P-type doped polycrystalline silicon layer closest to the silicon substrate is farther from the second side of the silicon substrate than a surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate, and a difference in height between the surface of the P-type doped polycrystalline silicon layer closest to the silicon substrate and the surface of the N-type doped polycrystalline silicon layer opposite the silicon substrate is greater than 0 and less than or equal to 1.6 microns.

14. a first dielectric layer located between the P-type doped polycrystalline silicon layer and a first region on the first side of the silicon substrate; 10. The back contact solar cell of claim 1.

15. A solar module comprising a plurality of back contact solar cells according to any one of claims 1 to 14.

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