Resistor chip

Abstract

To provide a resistor chip capable of improving dielectric strength.SOLUTION: A resistor chip 10 includes an insulating member 20 and a resistive element 30 provided on the insulating member 20. The resistive element 30 includes an insulator 31 and a resistive layer 40 provided within the insulator 31. The insulating member 20 includes an insulating substrate 21 made of glass or sapphire.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present disclosure relates to resistor chips. [Background technology]

[0002] Conventionally, semiconductor devices that detect high voltages using resistive voltage division have been known. For example, Patent Document 1 discloses a semiconductor device that includes a resistive element mounted on a high-voltage die pad and a semiconductor element mounted on a low-voltage die pad. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] International Publication No. 2022 / 176963

[0004] [overview] There is room for improvement in the dielectric strength of the above-mentioned resistance elements.

[0005] A resistor chip according to one aspect of the present disclosure includes an insulating member and a resistor disposed on the insulating member, the resistor including an insulator and a resistive layer disposed within the insulator, and the insulating member including a first insulating substrate made of glass or sapphire.

[0006] A resistor chip according to one aspect of the present disclosure includes an insulating member and a resistor disposed on the insulating member, the resistor including an insulator and a resistive layer disposed within the insulator, and the insulating member including a first substrate made of a material including a semiconductor material and a resin layer disposed on the first substrate. [Brief explanation of the drawings]

[0007] [Figure 1] FIG. 1 is a schematic plan view showing an example of a semiconductor package. [Figure 2] FIG. 2 is a circuit diagram showing an example of the electrical configuration of the semiconductor package of FIG. [Figure 3] FIG. 3 is a schematic perspective view showing an example of the resistor chip of FIG. [Figure 4] FIG. 4 is a schematic plan view showing an example of the resistor chip of FIG. [Figure 5] FIG. 5 is a schematic cross-sectional view showing an example of the resistor chip of FIG. [Figure 6] FIG. 6 is a schematic cross-sectional view showing a resistor chip of a comparative example. [Figure 7] FIG. 7 is a schematic cross-sectional view showing a modified resistor chip. [Figure 8] FIG. 8 is a schematic cross-sectional view showing a modified resistor chip. [Figure 9] FIG. 9 is a schematic cross-sectional view showing a modified resistor chip. [Figure 10] FIG. 10 is a schematic cross-sectional view showing a modified resistor chip. [Figure 11] FIG. 11 is a schematic cross-sectional view showing a modified resistor chip.

[0008] [Detailed explanation] Hereinafter, several embodiments of the semiconductor package of the present disclosure will be described with reference to the accompanying drawings. Note that for simplicity and clarity of description, the components shown in the drawings are not necessarily drawn to scale. Also, for ease of understanding, hatching lines may be omitted in cross-sectional views. The accompanying drawings merely illustrate embodiments of the present disclosure and should not be considered to limit the present disclosure. Terms such as "first," "second," and "third" in the present disclosure are used merely to distinguish between objects and do not rank the objects.

[0009] The following detailed description includes devices, systems, and methods embodying exemplary embodiments of the present disclosure. This detailed description is merely illustrative in nature and is not intended to limit the embodiments of the present disclosure or the application and uses of such embodiments.

[0010] The phrase "at least one" as used in this disclosure means "one or more" of the desired options. As an example, the phrase "at least one" as used in this disclosure means "only one option" or "both of two options" when the number of options is two. As another example, the phrase "at least one" as used in this disclosure means "only one option" or "any combination of two or more options" when the number of options is three or more.

[0011] (Embodiment) A semiconductor package 100 according to an embodiment will be described with reference to FIGS. (Schematic structure of semiconductor package) FIG. 1 shows an example of a planar structure of a semiconductor package 100 according to an embodiment.

[0012] As shown in FIG. 1, the semiconductor package 100 is connected to a battery 800 in one example. The semiconductor package 100 has a high withstand voltage and is used as a high-voltage monitor. The battery 800 is the object to be monitored and may be, for example, a battery for an electric vehicle or a hybrid vehicle. The rated voltage of the semiconductor package 100 may be, for example, 1200 V.

[0013] The semiconductor package 100 includes a case 110. The case 110 includes a first surface 111 and a second surface 112 opposite the first surface 111. The case 110 includes a side surface 113 connecting the first surface 111 and the second surface 112. The case 110 includes a recess 114 in the first surface 111. The case 110 is made of an insulating material. The thickness direction of the case 110 is defined as the Z-axis direction. Directions perpendicular to the Z-axis direction and perpendicular to each other are defined as the X-axis direction and the Y-axis direction. The recess 114 is recessed from the first surface 111 in the Z-axis direction. The term "plan view" used in this disclosure refers to viewing the semiconductor package 100 in the Z-axis direction of the XYZ axes shown in FIG. 1.

[0014] The semiconductor package 100 includes a support member 120 disposed within a case 110. The support member 120 includes a first die pad 121 and a second die pad 122. In one example, the first die pad 121 and the second die pad 122 are disposed within a recess 114. The first die pad 121 and the second die pad 122 are disposed spaced apart from each other in the Y-axis direction.

[0015] The semiconductor package 100 includes a resistor chip 10 and an amplifier chip 70. The resistor chip 10 is disposed on a first die pad 121. The resistor chip 10 is bonded to the first die pad 121 by a bonding material 131. The bonding material 131 may be an insulating bonding material such as epoxy resin. The amplifier chip 70 is disposed on a second die pad 122. The amplifier chip 70 is bonded to the second die pad 122 by the bonding material 132. The bonding material 132 may be a conductive bonding material such as solder or Ag paste, for example.

[0016] The semiconductor package 100 includes a lid 115 that seals the recess 114. FIG. 1 shows the interior of the recess 114 through the lid 115. The lid 115 may be made of an insulating material such as a metal material or a resin. The interior of the recess 114 may be a sealed space formed by the lid 115. The interior of the recess 114 may be filled with an insulating material. The insulating material filled in the recess 114 may be the same as the insulating material that constitutes the lid 115.

[0017] The support member 120 includes a plurality of leads 140. The plurality of leads 140 may include a first lead 141 and a second lead 142. The resistor chip 10 includes a first electrode 61 and a second electrode 62. The first electrode 61 is electrically connected to the first lead 141 by a wire W1. The second electrode 62 is electrically connected to the second lead 142 by a wire W2. The resistor chip 10 includes a plurality of third electrodes 63. The plurality of third electrodes 63 are electrically connected to a plurality of first electrodes 71 of the amplifier chip 70 by a wire W3. The first lead 141 and the second lead 142 are connected to a battery 800. In one example, the first lead 141 is electrically connected to a positive electrode of the battery 800, and the second lead 142 is electrically connected to a negative electrode of the battery 800.

[0018] The amplifier chip 70 includes a plurality of first electrodes 71 and a plurality of second electrodes 72. The plurality of second electrodes 72 may be used to supply a power supply voltage to the amplifier chip 70 and to output or input various signals. The plurality of leads 140 of the support member 120 include a plurality of fourth leads 143. The plurality of fourth leads 143 include a lead 143A connected to the first die pad 121. The lead 143A may be a ground lead that sets the first die pad 121 at a predetermined potential (for example, ground potential (GND)). The plurality of fourth leads 143 include a lead 143B connected to the second die pad 122. The lead 143B may be a lead that sets the second die pad 122 at a predetermined potential (ground potential (GND)). The potential of the first die pad 121 and the potential of the second die pad 122 may be the same or different from each other.

[0019] The multiple fourth leads 143 may include multiple leads 143C connected to the second electrodes 72 of the amplifier chip 70. The multiple leads 143C are electrically connected to the second electrodes 72 of the amplifier chip 70 by multiple wires W4. The multiple leads 143C may include leads that supply power supply voltage to the amplifier chip 70. The multiple leads 143C may include leads used for outputting or inputting signals, etc. One of the second electrodes 72 of the amplifier chip 70 may be electrically connected to the second die pad 122 by the wire W4. The multiple fourth leads 143 may include leads that are not connected to the amplifier chip 70.

[0020] (Circuit configuration of semiconductor package) FIG. 2 shows an example of the electrical configuration of the semiconductor package 100. As shown in FIG. The semiconductor package 100 includes a resistor chip 10 and an amplifier chip 70. The amplifier chip 70 is connected to the resistor chip 10.

[0021] The resistor chip 10 includes a resistor layer 40 connected between a first electrode 61 and a second electrode 62. The resistor layer 40 includes a first resistor layer 41, a second resistor layer 42, a third resistor layer 43, and a fourth resistor layer 44. The first to fourth resistor layers 41 to 44 form a voltage divider circuit that divides the voltage between the first electrode 61 and the second electrode 62.

[0022] The first resistive layer 41 is connected to the first electrode 61. The fourth resistive layer 44 is connected to the second electrode 62. The second resistive layer 42 and the third resistive layer 43 connect the first resistive layer 41 and the second resistive layer 42. The connection point between the first resistive layer 41 and the second resistive layer 42 is connected to a first detection electrode 63A. The connection point between the second resistive layer 42 and the third resistive layer 43 is connected to a reference electrode 63B. The connection point between the third resistive layer 43 and the fourth resistive layer 44 is connected to a second detection electrode 63C. It can be said that the connection points between the first to fourth resistive layers 41 to 44 are connected to the third electrode 63.

[0023] In one example, the first resistive layer 41 and the fourth resistive layer 44 have the same resistance value. In one example, the second resistive layer 42 and the third resistive layer 43 have the same resistance value. In one example, the resistance value of the second resistive layer 42 is smaller than the resistance value of the first resistive layer 41. The resistance value RB of the second resistive layer 42 may be 1 / 100 or less of the resistance value RA of the first resistive layer 41. In one example, the ratio (RB / RA) of the resistance value RB of the second resistive layer 42 to the resistance value RA of the first resistive layer 41 is 1 / 999. In one example, the resistance value RC of the third resistive layer 43 is smaller than the resistance value RD of the fourth resistive layer 44. The resistance value RC of the third resistive layer 43 may be 1 / 100 or less of the resistance value RD of the fourth resistive layer 44. In one example, the ratio (RC / RD) of the resistance value RC of the third resistive layer 43 to the resistance value RD of the fourth resistive layer 44 is 1 / 999. The resistive layer 40 generates a voltage by dividing the voltage between the first electrode 61 and the second electrode 62 in accordance with the ratio of the resistance values ​​RA to RD of the first to fourth resistive layers 41 to 44. The resistance values ​​of the first to fourth resistive layers 41 to 44 included in the resistive layer 40 may be set in accordance with the input voltage applied between the first electrode 61 and the second electrode 62 and the input voltage of the amplifier chip 70. The resistance value of the resistive layer 40 may be, for example, 20 MΩ or more.

[0024] The amplifier chip 70 includes an amplifier circuit 75. The amplifier circuit 75 may include a differential amplifier circuit, a voltage adjustment circuit, etc. The amplifier circuit 75 is connected to the first detection electrode 63A, the reference electrode 63B, and the second detection electrode 63C of the resistor chip 10. The amplifier circuit 75 generates a reference voltage Vr to be supplied to the reference electrode 63B. The reference voltage Vr may be, for example, 1 / 2 of the power supply voltage VCC. The amplifier chip 70 outputs an output voltage Vout according to the reference voltage Vr, the voltage of the first detection electrode 63A, and the voltage of the second detection electrode 63C.

[0025] (Resistor chip overview) Fig. 3 is a schematic perspective view of the resistor chip 10. Fig. 4 is a schematic plan view showing an example of the resistor chip 10. Fig. 5 shows an outline of the cross-sectional structure of the resistor chip. In Fig. 5, the resistive layer 40 is shown as a single member connected between the first electrode 61 and the second electrode 62.

[0026] 3 to 5, the resistor chip 10 has a generally rectangular shape in a plan view. The resistor chip 10 includes a first element surface 11 and a second element surface 12 opposite the first element surface 11. The resistor chip 10 includes a plurality of element side surfaces 13, 14, 15, and 16 connecting the first element surface 11 and the second element surface 12. The resistor chip 10 has a rectangular shape in a plan view with its short side direction aligned in the X-axis direction and its long side direction aligned in the Y-axis direction. That is, the resistor chip 10 includes element side surfaces 13 and 14 extending along the X-axis direction and element side surfaces 15 and 16 extending along the Y-axis direction.

[0027] 3 and 4, the resistor chip 10 includes a plurality of electrodes 60 provided on the first element surface 11. In one example, the plurality of electrodes 60 include a first electrode 61, a second electrode 62, and a third electrode 63. In one example, the first electrode 61 and the second electrode 62 are arranged in the central portion of the resistor chip 10 in the X-axis direction. In one example, the first electrode 61 and the second electrode 62 are arranged spaced apart in the Y-axis direction.

[0028] The resistor chip 10 includes a plurality of third electrodes 63. The plurality of third electrodes 63 include a reference electrode 63B, a first detection electrode 63A, and a second detection electrode 63C. In one example, the reference electrode 63B, the first detection electrode 63A, and the second detection electrode 63C are arranged in a central region of the resistor chip 10 in the Y-axis direction, closer to the element side surface 16. In one example, the first detection electrode 63A and the second detection electrode 63C are arranged on either side of the reference electrode 63B in the Y-axis direction. The reference electrode 63B, the first detection electrode 63A, and the second detection electrode 63C are arranged along the element side surface 16 of the resistor chip 10.

[0029] As shown in FIGS. 4 and 5, the resistor chip 10 includes a first electrode 61, a second electrode 62, and a third electrode 63 (a first detection electrode 63A, a reference electrode 63B, and a second detection electrode 63C). The resistor chip 10 includes an annular conductor 46. The annular conductor 46 has an annular shape extending along the element side surfaces 13 to 16 of the resistor chip 10. The annular conductor 46 is arranged inside the resistor chip 10 relative to the element side surfaces 13 to 16. The multiple electrodes 60 (61 to 63) and the resistive layer 40 are arranged inside the annular conductor 46. The annular conductor 46, for example, prevents moisture from penetrating the insulator 31 on which the resistive layer 40 and the multiple electrodes 60 (61 to 63) are arranged, and prevents cracks from penetrating due to dicing. The annular conductor 46 may be omitted.

[0030] Resistive layer 40 includes a plurality of thin-film resistive layers 40A. The plurality of thin-film resistive layers 40A may extend linearly. The plurality of thin-film resistive layers 40A extend in the Y-axis direction. The plurality of thin-film resistive layers 40A are arranged at intervals in the X-axis direction. The plurality of thin-film resistive layers 40A are connected in series between first electrode 61 and second electrode 62 by via conductors and connecting conductors. First to fourth resistive layers 41 to 44 may include thin-film resistive layers 40A in numbers corresponding to their respective resistance values.

[0031] As shown in FIGS. 3 and 5, the resistor chip 10 includes an insulating member 20. The insulating member 20 may have a rectangular flat plate shape with its thickness direction in the Z-axis direction. The insulating member 20 includes a first insulating surface 20S and a second insulating surface 20R opposite to the first insulating surface 20S. The second insulating surface 20R of the insulating member 20 forms the second element surface 12 of the resistor chip 10.

[0032] The insulating member 20 includes an insulating substrate 21. In one example, the insulating substrate 21 is a glass substrate. The insulating substrate 21 may be a sapphire substrate. It can be said that the insulating member 20 includes an insulating substrate 21 made of glass or sapphire. The insulating substrate 21 corresponds to a "first insulating substrate."

[0033] 5, insulating substrate 21 has a rectangular flat plate shape with its thickness direction in the Z-axis direction. Insulating substrate 21 includes a first substrate surface 21S and a second substrate surface 21R opposite to first substrate surface 21S. Second substrate surface 21R of insulating substrate 21 constitutes second insulating surface 20R of insulating member 20. Second substrate surface 21R of insulating substrate 21 constitutes second element surface 12 of resistor chip 10. Thickness T1 of insulating substrate 21 may be 300 μm, for example.

[0034] The insulating member 20 may include an insulating layer 22 disposed on an insulating substrate 21. The insulating layer 22 covers a first substrate surface 21S of the insulating substrate 21. The insulating layer 22 is in contact with the first substrate surface 21S of the insulating substrate 21. The insulating layer 22 constitutes a first insulating surface 20S of the insulating member 20. The insulating layer 22 may be composed of an inorganic insulating layer. The insulating layer 22 may be composed of a material containing silicon (Si). The insulating layer 22 may be composed of a material containing at least one of silicon oxide (SiO2), silicon nitride (SiN), silicon carbide (SiC), and nitrogen-doped silicon carbide (SiCN).

[0035] The resistor chip 10 includes a resistive element 30. The resistive element 30 is disposed on an insulating member 20. The resistor chip 10 includes the resistive element 30 disposed on a first insulating surface 20S of the insulating member 20.

[0036] The resistor 30 includes an insulator 31 and a resistive layer 40. More specifically, the resistor 30 includes an insulator 31 and a resistive layer 40 provided within the insulator 31. The insulator 31 includes a first surface 31S and a second surface 31R opposite to the first surface 31S. The second surface 31R of the insulator 31 contacts the first insulating surface 20S of the insulating member 20. The first surface 31S of the insulator 31 constitutes the first element surface 11 of the resistor chip 10.

[0037] The insulator 31 may include first to fourth insulating layers 32 to 35. The first to fourth insulating layers 32 to 35 are stacked in the Z-axis direction from the first insulating surface 20S of the insulating member 20. In the resistor chip 10, the Z-axis direction can be said to be the thickness direction of the insulator 31, or the stacking direction of the first to fourth insulating layers 32 to 35. The number of insulating layers included in the insulator 31 may be changed as appropriate.

[0038] The first insulating layer 32 is provided on the insulating member 20. The first insulating layer 32 is in contact with the first insulating surface 20S of the insulating member 20. The first insulating layer 32 may be an insulating layer that covers the first insulating surface 20S of the insulating member 20. The first insulating layer 32 forms the second surface 31R of the insulator 31. The fourth insulating layer 35 forms the first surface 31S of the insulator 31.

[0039] The first to fourth insulating layers 32 to 35 are made of a material containing Si. The first to fourth insulating layers 32 to 35 may be made of a material containing SiO2, SiN, SiC, SiCN, etc. In one example, the first to fourth insulating layers 32 to 35 are made of a material containing SiO2. The first to fourth insulating layers 32 to 35 may be made of different materials. The first to fourth insulating layers 32 to 35 may be oxide films formed by different methods.

[0040] 4, resistive layer 40 includes a plurality of thin-film resistive layers 40A. The plurality of thin-film resistive layers 40A are provided within insulator 31 shown in FIG. 5. It can be said that resistor 30 includes a plurality of thin-film resistive layers 40A provided within insulator 31.

[0041] The resistive layer 40 is disposed on the second insulating layer 33. The resistive layer 40 is in contact with the upper surface of the second insulating layer 33. The resistive layer 40 is covered with the third insulating layer . The resistive layer 40 is made of a resistive material having a desired resistivity. For example, the resistive layer 40 may be made of a resistive material having a resistivity higher than that of polysilicon. The resistive layer 40 is made of a material containing Cr (chromium) and Si. The resistive layer 40 may be made of a material containing one of CrSi, CrSiC, and CrSiN. The resistive layer 40 may also be made of a material other than a material containing Cr and Si. For example, the resistive layer 40 may be made of a material containing at least one of TaN and TiN.

[0042] The first electrode 61 and the second electrode 62 are disposed on the fourth insulating layer 35. The first electrode 61 and the second electrode 62 are in contact with a first surface of the resistor 30, which is formed by the upper surface of the fourth insulating layer 35. The first surface of the resistor 30 is formed by the first surface 31S of the insulator 31. It can be said that the first electrode 61 and the second electrode 62 are disposed on the resistor 30. It can also be said that the first electrode 61 and the second electrode 62 are disposed on the insulator 31. It can also be said that the first electrode 61 and the second electrode 62 are disposed on the first surface 31S of the insulator 31. Note that the first detection electrode 63A, the reference electrode 63B, and the second detection electrode 63C shown in FIG. 4 are disposed on the fourth insulating layer 35, similar to the first electrode 61 and the second electrode 62.

[0043] The first electrode 61 and the second electrode 62 may be made of a material containing one or more appropriately selected from Cu (copper), Al (aluminum), Ti (titanium), TiN (titanium nitride), Ta (tantalum), TaN (tantalum nitride), Au (gold), Ag (silver), and W (tungsten). In one example, the first electrode 61 and the second electrode 62 are made of a material containing Al and Cu. The first electrode 61 and the second electrode 62 may be made of multiple metal layers.

[0044] The resistor chip 10 includes a resistor connection portion 45 that connects the first electrode 61 and the second electrode 62 to the resistor layer 40. The resistor connection portion 45 is disposed within the insulator 31. The resistor connection portion 45 includes a connection wiring 45A and connection vias 45B and 45C.

[0045] The connection wiring 45A is disposed on the insulating member 20. More specifically, the connection wiring 45A is disposed on the insulating layer 22 of the insulating member 20. The insulating layer 22 is interposed between the connection wiring 45A and the insulating substrate 21. The connection wiring 45A is in contact with the upper surface of the insulating layer 22.

[0046] The connection wiring 45A is covered with a first insulating layer 32 of the insulator 31. The connection wiring 45A may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. The connection wiring 45A may be made of multiple metal layers.

[0047] The connection between the first electrode 61 and the resistance layer 40 by the resistance connection portion 45 will be described. A first end 45A1 of the connection wiring 45A is disposed so as to overlap the first electrode 61 in a plan view. The connection via 45B penetrates the first to fourth insulating layers 32 to 35 between the first electrode 61 and the connection wiring 45A. The first end 45A1 of the connection wiring 45A is electrically connected to the first electrode 61 by the connection via 45B. A second end 45A2 of the connection wiring 45A is disposed so as to overlap the resistive layer 40 in a plan view. The connection via 45C penetrates the first insulating layer 32 and the second insulating layer 33 between the resistive layer 40 and the connection wiring 45A. The second end 45A2 of the connection wiring 45A is electrically connected to the resistive layer 40 by the connection via 45C. The connection vias 45B and 45C may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W.

[0048] Similar to the first electrode 61 , the second electrode 62 is electrically connected to the resistance layer 40 via a resistance connection portion 45 . 5 shows resistive layer 40. Resistive layer 40 includes a plurality of thin-film resistive layers 40A, as shown in FIG. 4. The plurality of thin-film resistive layers 40A are connected in series between first electrode 61 and second electrode 62 by resistive connectors 45. Furthermore, predetermined thin-film resistive layers 40A among the plurality of thin-film resistive layers 40A are electrically connected by resistive connectors 45 to first detection electrode 63A, reference electrode 63B, and second detection electrode 63C shown in FIG. 4.

[0049] The annular conductor 46 may include a peripheral wiring 46A, a peripheral via conductor 46B, and a peripheral resistive film 46C. The peripheral wiring 46A is disposed on the insulating layer 22 of the insulating member 20. The peripheral wiring 46A is in contact with the upper surface of the insulating layer 22 of the insulating member 20. The peripheral wiring 46A is covered with the first insulating layer 32. The peripheral wiring 46A may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. The peripheral wiring 46A may be made of multiple metal layers. The peripheral wiring 46A may be made of the same material as the connection wiring 45A, or may be made of a different material.

[0050] The peripheral resistive film 46C is disposed on the second insulating layer 33. The peripheral resistive film 46C is in contact with the upper surface of the second insulating layer 33. The peripheral resistive film 46C is disposed at a position overlapping the peripheral wiring 46A in plan view. The peripheral resistive film 46C may have a continuous annular shape or an intermittent annular shape in plan view. The peripheral resistive film 46C is covered with the third insulating layer 34. The peripheral resistive film 46C may be made of a material containing at least one of CrSi, CrSiC, CrSiN, TaN, and TiN. The peripheral resistive film 46C may be made of the same material as the resistive layer 40, or may be made of a different material.

[0051] The peripheral via conductor 46B is provided between the peripheral wiring 46A and the peripheral resistive film 46C. The peripheral via conductor 46B penetrates the first insulating layer 32 and the second insulating layer 33. The peripheral via conductor 46B electrically connects the peripheral wiring 46A and the peripheral resistive film 46C. The peripheral via conductor 46B may be made of a material containing one or more appropriately selected from Cu, Al, Ti, TiN, Ta, TaN, Au, Ag, and W. The peripheral via conductor 46B may be made of the same material as the connection vias 45B and 45C, or may be made of a different material.

[0052] The resistor chip 10 may include a passivation film 51 disposed on the fourth insulating layer 35. The passivation film 51 includes a plurality of openings 51D. The plurality of openings 51D includes openings that expose portions of the first electrode 61 and the second electrode 62. The plurality of openings 51D also includes openings that expose portions of the first detection electrode 63A, the reference electrode 63B, and the second detection electrode 63C shown in FIG. 4 .

[0053] The passivation film 51 may include a first passivation film 52 and a second passivation film 53. The first passivation film 52 is disposed on the fourth insulating layer 35, and the second passivation film 53 is disposed on the first passivation film 52. The opening 51D of the passivation film 51 may be composed of an opening in the first passivation film 52 and an opening in the second passivation film 53.

[0054] The first passivation film 52 and the second passivation film 53 may be made of a material containing Si. For example, the first passivation film 52 is made of a material containing SiO2. For example, the second passivation film 53 is made of a material containing SiN.

[0055] The resistor chip 10 may include a resin film 54 disposed on the passivation film 51. The resin film 54 is made of a material containing, for example, polyimide (PI). The resin film 54 includes a plurality of openings 54D. The plurality of openings 54D includes openings that expose parts of the first electrode 61 and the second electrode 62 and a part of the passivation film 51. The plurality of openings 54D also includes openings that expose parts of the first detection electrode 63A, the reference electrode 63B, and the second detection electrode 63C shown in FIG. 4 and a part of the passivation film 51.

[0056] (Comparative Example) Fig. 6 shows a schematic cross-sectional structure of a comparative resistor chip 700. Note that, in the comparative resistor chip 700 shown in Fig. 6, the same components as those in the resistor chip 10 of the above embodiment are denoted by the same reference numerals. Fig. 6 also shows a cross-sectional structure corresponding to Fig. 5 showing the resistor chip 10 of the embodiment.

[0057] The resistor chip 700 of the comparative example includes a semiconductor substrate 701. The semiconductor substrate 701 is a substrate made of a material containing Si. The resistor chip 700 of the comparative example includes a laminated insulator 702 disposed on a semiconductor substrate 701. The resistor 30 is disposed on the laminated insulator 702.

[0058] The laminated insulator 702 is composed of a plurality of laminated insulating films 703. The plurality of insulating films 703 are organic insulating films. In one example, the laminated insulator 702 is composed of six insulating films 703.

[0059] The insulating film 703 is composed of a first insulating film 704 and a second insulating film 705 disposed on the first insulating film 704. The first insulating film 704 is thinner than the second insulating film 705. The first insulating film 704 is composed of a material containing SiN, SiC, SiCN, etc. In one example, the first insulating film 704 is composed of a material containing SiN. The second insulating film 705 is a film that is thicker than the first insulating film 704. The second insulating film 705 is composed of a material containing SiO2 (silicon oxide).

[0060] The resistor chip 700 of the comparative example is bonded to the first die pad 121 by a conductive bonding material, for example. The voltage of the battery 800 shown in FIG. 1 is applied between the first electrode 61 and the second electrode 62 of the resistor chip 700. Therefore, in the resistor chip 700 of the comparative example, the distance between the semiconductor substrate 701 and the first electrode 61 and the distance between the semiconductor substrate 701 and the second electrode 62 affect the dielectric strength. The dielectric strength is determined by the thickness of the laminated insulator 702 disposed between the semiconductor substrate 701 and the resistor 30, i.e., the number of insulating films 703 constituting the laminated insulator 702. The thickness T1X of the laminated insulator 702 is approximately 12 μm.

[0061] The dielectric strength can be increased by increasing the number of layers of the insulating film 703 that constitutes the laminated insulator 702. The insulating film 703 includes a first insulating film 704 and a second insulating film 706. Increasing the number of layers of the insulating film can cause warping of the resistor chip 700. Furthermore, increasing the number of layers of the insulating film increases the number of steps required to form the laminated insulator 702, increasing manufacturing costs.

[0062] (Operation of the embodiment) The resistor chip 10 includes an insulating member 20 and a resistor 30 provided on the insulating member 20. The resistor 30 includes an insulator and a resistive layer provided within the insulator. The insulating member 20 includes an insulating substrate 21 made of glass or sapphire.

[0063] The use of the insulating substrate 21 ensures the dielectric strength of the resistor chip 10. Furthermore, the use of the insulating substrate 21 eliminates the need for the laminated insulator 702 of the comparative example, thereby preventing the resistor chip 10 from warping. Furthermore, the elimination of the laminated insulator 702 of the comparative example reduces the number of steps required to manufacture the resistor chip 10, thereby reducing the cost of the resistor chip 10.

[0064] The insulating member 20 includes an insulating layer 22 disposed on an insulating substrate 21. The insulating layer 22 is made of a material containing Si. The insulating layer 22 may be made of a material containing at least one of SiO2, SiN, SiC, and SiCN. The resistor 30 is disposed on the insulating layer 22. The insulating layer 22 prevents impurities and the like from penetrating from the insulating substrate 21 into the resistor 30. Therefore, the insulating layer 22 can further stabilize the characteristics of the resistor 30.

[0065] (Effects of the embodiment) As described above, the semiconductor package 100 provides the following advantages. (1-1) The resistor chip 10 includes an insulating member 20 and a resistor 30 provided on the insulating member 20. The resistor 30 includes an insulator and a resistive layer provided in the insulator. The insulating member 20 includes an insulating substrate 21 made of glass or sapphire. By using the insulating substrate 21, the dielectric strength of the resistor chip 10 can be ensured.

[0066] (1-2) The insulating member 20 includes an insulating substrate 21 made of glass or sapphire. By using the insulating substrate 21, the laminated insulator 702 of the comparative example becomes unnecessary, and warping of the resistor chip 10 can be suppressed.

[0067] (1-3) The insulating member 20 includes an insulating substrate 21 made of glass or sapphire. Since the laminated insulator 702 of the resistor chip 700 of the comparative example is not required, the number of steps required to manufacture the resistor chip 10 can be reduced, and the cost of the resistor chip 10 can be reduced.

[0068] (1-4) The insulating member 20 includes an insulating layer 22 disposed on an insulating substrate 21. The insulating layer 22 is made of a material containing Si. The insulating layer 22 may be made of a material containing at least one of SiO2, SiN, SiC, and SiCN. The resistor 30 is disposed on the insulating layer 22. The insulating layer 22 prevents impurities and the like from penetrating from the insulating substrate 21 into the resistor 30. Therefore, the insulating layer 22 can further stabilize the characteristics of the resistor 30.

[0069] (Example of change) The above embodiment can be modified, for example, as follows: The above embodiment and each of the following modified examples can be combined with each other as long as no technical contradiction occurs. In the following modified examples, parts that are common to the above embodiment and other modified examples will be assigned the same reference numerals as the above embodiment and other modified examples, and their description will be omitted.

[0070] The configuration of the resistor chip 10 may be changed as appropriate. 7, a resistor chip 10A of the modified example may include an insulating member 220. The insulating member 220 may include a laminate 221 disposed on an insulating substrate 21.

[0071] The laminate 221 may be composed of one first insulating film 222 and second insulating films 223 and 224 that sandwich the first insulating film 222. The first insulating film 222 may be composed of a material containing SiN, for example. The second insulating films 223 and 224 may be composed of a material containing SiO2, for example. The laminate 221 may be composed of one first insulating film 222 and one second insulating film 223. A thickness T21 of the laminate 221 may be thinner than a thickness T1 of the insulating substrate 21.

[0072] The resistor chip 10A of this modified example has a laminate 221 provided on an insulating substrate 21. Therefore, the laminate 221 of this modified example requires fewer insulating layers than the laminated insulator 702 described in the comparative example above. This reduces the number of steps required to manufacture the resistor chip 10A, thereby reducing the cost of the resistor chip 10A. Furthermore, the resistor chip 10A of the comparative example can improve its withstand voltage due to the insulating substrate 21 and the laminate 221.

[0073] 8, the resistor chip 10B of the modified example may include an insulating member 320. The insulating member 320 may include a first substrate 321 and a resin layer 322 disposed on the first substrate 321. The insulating member 320 may include an insulating layer 22. The insulating layer 22 may be omitted.

[0074] The first substrate 321 includes a first surface 321S and a second surface 321R opposite to the first surface 321S. The second surface 321R of the first substrate 321 constitutes the second element surface 12 of the resistor chip 10B. The first substrate 321 is, for example, a Si substrate. The first substrate 321 may be a glass substrate, a sapphire substrate, or the like. The first substrate 321 may also be a substrate using a wide bandgap semiconductor such as SiC (silicon nitride) or a compound semiconductor such as AlN (aluminum nitride).

[0075] The resin layer 322 includes a first surface 322S and a second surface 322R opposite to the first surface 322S. The second surface 322R of the resin layer 322 contacts the first surface 321S of the first substrate 321. The resin layer 322 may be made of an insulating material. The resin layer 322 may be made of an insulating resin material such as a molded resin, a polyimide (PI) resin, or a polybenzoxazole (PBO) resin. The molded resin may be made of, for example, an epoxy resin. The molded resin may be colored, for example, black. A thickness T32 of the resin layer 322 may be thinner than a thickness T31 of the first substrate 321.

[0076] The insulating layer 22 covers the first surface 322S of the resin layer 322. The insulating layer 22 is in contact with the first surface 322S of the resin layer 322. The resistor 30 is disposed on the insulating layer 22. The resistor chip 10B of this modified example has the same effects as the above embodiment by including a resin layer 322 disposed on a first substrate 321. The withstand voltage can be easily set by changing the thickness T32 of the resin layer 322. The withstand voltage can be further improved by using a glass substrate or a sapphire substrate for the first substrate 321.

[0077] As shown in FIG. 9, a modified resistor chip 10C may include an insulating member 420. The insulating member 420 may include a first resin layer 421 disposed on the first substrate 321 , and a second substrate 422 disposed between the first resin layer 421 and the resistor 30 .

[0078] The first resin layer 421 includes a first surface 421S and a second surface 421R opposite to the first surface 421S. The second surface 421R of the first resin layer 421 contacts the first surface 321S of the first substrate 321.

[0079] The first resin layer 421 may be made of an insulating material. The first resin layer 421 may be made of an insulating resin material such as a mold resin, a polyimide (PI) resin, or a polybenzoxazole (PBO) resin. The mold resin may be made of, for example, an epoxy resin. The mold resin may be colored, for example, black. The thickness T41 of the first resin layer 421 may be thinner than the thickness T31 of the first substrate 321.

[0080] The second substrate 422 includes a first surface 422S and a second surface 422R opposite to the first surface 422S. The second surface 422R of the second substrate 422 contacts the first surface 421S of the first resin layer 421.

[0081] The second substrate 422 is, for example, a Si substrate. The second substrate 422 may be a glass substrate, a sapphire substrate, or the like. The second substrate 422 may also be a substrate using a wide bandgap semiconductor such as silicon nitride (SiC) or a compound semiconductor such as aluminum nitride (AlN). The second substrate 422 may be made of the same material as the first substrate 321, or may be made of a different material from the first substrate 321. The thickness T42 of the second substrate 422 may be equal to the thickness T31 of the first substrate 321. The thickness T42 of the second substrate 422 may be different from the thickness T31 of the first substrate 321. The thickness T42 of the second substrate 422 may be thicker or thinner than the thickness T31 of the first substrate 321.

[0082] The insulating member 420 may include a second resin layer 423 disposed between the first resin layer 421 and the resistor 30. In one example, the second resin layer 423 may be disposed between the second substrate 422 and the resistor 30. The insulating member 420 may include an insulating layer 22 disposed on the second resin layer 423. The second resin layer 423 may be disposed between the first resin layer 421 and the second substrate 422.

[0083] The second resin layer 423 includes a first surface 423S and a second surface 423R opposite to the first surface 423S. The second surface 423R of the second resin layer 423 contacts the first surface 422S of the second substrate 422.

[0084] The second resin layer 423 may be made of an insulating material. The second resin layer 423 may be made of an insulating resin material such as a mold resin, a polyimide (PI) resin, or a polybenzoxazole (PBO) resin. The mold resin may be made of, for example, an epoxy resin. The mold resin may be colored, for example, black. The thickness T43 of the second resin layer 423 may be thinner than the thickness T31 of the first substrate 321. The thickness T43 of the second resin layer 423 may be equal to the thickness T41 of the first resin layer 421. The thickness T43 of the second resin layer 423 may be different from the thickness T41 of the first resin layer 421. The thickness T43 of the second resin layer 423 may be thicker or thinner than the thickness T41 of the first resin layer 421.

[0085] The insulating layer 22 covers the first surface 423S of the second resin layer 423. The insulating layer 22 is in contact with the first surface 423S of the second resin layer 423. The resistor 30 is disposed on the insulating layer 22.

[0086] The resistor chip 10C of this modified example has the same effects as the above embodiment by including the first resin layer 421 and the second resin layer 423. In addition, by appropriately setting the thickness T41 of the first resin layer 421 and the thickness T43 of the second resin layer 423, it is possible to improve the dielectric strength voltage.

[0087] As shown in FIG. 10, a modified resistor chip 10D may include an insulating member 520. The insulating member 520 may include a first resin layer 421 disposed on the first substrate 321, and a second substrate 422 disposed between the first resin layer 421 and the resistor 30. The insulating member 520 may include a laminate 221 disposed between the first resin layer 421 and the resistor 30. In one example, the laminate 221 may be disposed between the second substrate 422 and the resistor 30.

[0088] The laminate 221 may be disposed between the first resin layer 421 and the second substrate 422. In this case, the insulating member 520 may include an insulating layer 22 (see FIG. 9) disposed on the second substrate 422.

[0089] The resistor chip 10D of this modified example has the same effects as the above embodiment by including the first resin layer 421 and the laminate 221. In addition, by appropriately setting the thickness T41 of the first resin layer 421, it is possible to improve the dielectric strength voltage.

[0090] In the resistor chip 10D of this modified example, the laminate 221 may be disposed between the first substrate 321 and the second substrate 422, and the first resin layer 421 may be disposed between the second substrate 422 and the resistor 30.

[0091] In the resistor chip 10D of this modified example, the laminate 221 may be disposed between the first resin layer 421 and the second substrate 422. In this case, the insulating member 520 may include an insulating layer 22 (see FIG. 9) disposed on the second substrate 422.

[0092] 11, the resistor chip 10E of the modified example does not include the second substrate 422 as compared to the resistor chip 10D shown in FIG. 10. That is, the insulating member 620 of the resistor chip 10E of the modified example includes a first resin layer 421 disposed between the first substrate 321 and the resistor element 30, and a laminate 221 disposed between the first resin layer 421 and the resistor element 30. By including the first resin layer 421 and the laminate 221, the resistor chip 10E of this modified example achieves the same effects as the above-described embodiment. Furthermore, by appropriately setting the thickness T41 of the first resin layer 421, it is possible to improve the dielectric strength voltage.

[0093] In the modified resistor chip 10E, the laminate 221 may be disposed between the first substrate 321 and the first resin layer 421. In this case, the insulating member 520 may include an insulating layer 22 (see FIG. 9) disposed on the first resin layer 421.

[0094] The term "on" as used in this disclosure includes both "on" and "above" unless the context clearly indicates otherwise. Thus, the phrase "a first layer is formed on a second layer" is intended to mean that in some embodiments, the first layer may be disposed directly on the second layer in contact with the second layer, while in other embodiments, the first layer may be disposed above the second layer without contacting the second layer. In other words, the term "on" does not exclude a structure in which another layer is formed between the first and second layers.

[0095] The Z-axis direction used in this disclosure does not necessarily have to be the vertical direction, nor does it have to completely coincide with the vertical direction. Therefore, various structures according to this disclosure (for example, the structure shown in FIG. 1 ) are not limited to the "up" and "down" in the Z-axis direction described in this disclosure being "up" and "down" in the vertical direction. For example, the X-axis direction may be the vertical direction, or the Y-axis direction may be the vertical direction.

[0096] (Addendum) The technical ideas that can be understood from the present disclosure are described below. Note that, for the purpose of aiding understanding and not intending to be limiting, the components described in the appendices are given the reference numerals of the corresponding components in the embodiments. The reference numerals are shown as examples to aid understanding, and the components described in each appendix should not be limited to the components indicated by the reference numerals.

[0097] (Appendix 1) an insulating member (110); a resistor (30) provided on the insulating member (110); Including, The resistor (30) is an insulator (31); a resistive layer (40) provided within the insulator (31); Including, The insulating member (110) includes an insulating substrate (21) made of glass or sapphire. Resistor chip.

[0098] (Appendix 2) The insulating member (110) is provided on the insulating substrate (21) and includes an insulating layer made of a material containing silicon. 10. The resistor chip of claim 1.

[0099] (Appendix 3) the insulating layer is a silicon oxide film or a silicon nitride film; 1. The resistor chip of claim 2.

[0100] (Appendix 4) The insulating member (110) includes a laminate (221) provided between the insulating substrate (21) and the resistor (30). 10. The resistor chip of claim 1.

[0101] (Appendix 5) The laminate (221) is composed of a laminate of a silicon oxide film and a silicon nitride film. 5. The resistor chip of claim 4.

[0102] (Appendix 6) The thickness of the laminate (221) is thinner than the thickness of the insulating substrate (21). 6. The resistor chip of claim 4 or 5.

[0103] (Appendix 7) The thickness of the laminate (221) is thinner than the thickness of the resistor (30). 7. The resistor chip of any one of claims 4 to 6.

[0104] (Appendix 8) an insulating member (220, 320, 420, 520); a resistor (30) provided on the insulating member; Including, The resistor (30) is an insulator (31); a resistive layer (40) provided within the insulator (31); Including, The insulating member is a first substrate (321) made of a material including a semiconductor material; a first resin layer (322) provided on the first substrate (321); Including, Resistor chip.

[0105] (Appendix 9) The first substrate (321) is made of a material containing silicon. 9. The resistor chip of claim 8.

[0106] (Appendix 10) The first resin layer (322) is made of a molding resin, a polyimide resin, or a polybenzoxazole resin. 10. The resistor chip of claim 8 or 9.

[0107] (Appendix 11) The thickness of the first resin layer (322) is thinner than the thickness of the first substrate (321). 11. The resistor chip of any one of claims 8 to 10.

[0108] (Appendix 12) and a second substrate (422) disposed between the first substrate (321) and the resistor (30). 12. The resistor chip of any one of claims 8 to 11.

[0109] (Appendix 13) The second substrate (422) is disposed between the first resin layer (322) and the resistor (30). 13. The resistor chip of claim 12.

[0110] (Appendix 14) The first substrate (321) and the second substrate (422) have the same thickness. 14. The resistor chip of claim 12 or 13.

[0111] (Appendix 15) The first substrate (321) and the second substrate (422) are Si substrates. 15. The resistor chip of any one of claims 12 to 14.

[0112] (Appendix 16) The insulating member includes a laminate (221) provided between the first substrate (321) and the resistor (30). 16. The resistor chip of any one of claims 8 to 15.

[0113] (Appendix 17) The laminate (221) is provided between the first resin layer (322) and the resistor (30). 17. The resistor chip of claim 16.

[0114] (Appendix 18) The laminate (221) is provided between the first substrate (321) and the first resin layer (322). 17. The resistor chip of claim 16.

[0115] (Appendix 19) The laminate (221) is composed of a laminate of a silicon oxide film and a silicon nitride film. 19. The resistor chip of any one of claims 16 to 18.

[0116] (Appendix 20) The thickness of the laminate (221) is thinner than the thickness of the first substrate (321). 19. The resistor chip of claim 16.

[0117] (Appendix 21) The thickness of the laminate (221) is thinner than the thickness of the first resin layer (322). 21. The resistor chip of any one of claims 16 to 20.

[0118] (Appendix 22) The thickness of the laminate (221) is thinner than the thickness of the resistor (30). 22. The resistor chip of any one of claims 16 to 21.

[0119] (Appendix 23) The insulating member (420) includes a second resin layer (423) provided between the first substrate (321) and the resistor (30). 16. The resistor chip of any one of claims 12 to 15.

[0120] (Appendix 24) the first resin layer (322) is provided between the first substrate (321) and the second substrate (422); The second resin layer (423) is provided between the second substrate (422) and the resistor (30). 24. The resistor chip of claim 23.

[0121] (Appendix 25) The first resin layer (322) and the second resin layer (423) are made of the same material. 25. The resistor chip of claim 23 or 24.

[0122] (Appendix 26) The first resin layer (322) and the second resin layer (423) are made of different materials. 25. The resistor chip of claim 23 or 24.

[0123] (Appendix 27) an insulating member (620); a resistor (30) provided on the insulating member; Including, The resistor (30) is an insulator (31); a resistive layer (40) provided within the insulator (31); Including, The insulating member (620) a first substrate (321) made of a material including a semiconductor material; a first resin layer (322) provided between the first substrate (321) and the resistor (30); a laminate (221) provided between the first substrate (321) and the resistor (30); Including, Resistor chip.

[0124] (Appendix 28) The resistive layer (40) is made of a material containing CrSi. 28. The resistor chip of any one of claims 1 to 27.

[0125] (Appendix 29) a plurality of electrodes (60) spaced apart from one another on the resistor (30); The plurality of electrodes (60) are electrically connected to the resistance layer (40). 29. The resistor chip of any one of claims 1 to 28.

[0126] (Appendix 30) The resistor (30) includes a resistor connection portion (45) that electrically connects the electrode (60) and the resistance layer (40). 20. The resistor chip of claim 29.

[0127] The above description is merely illustrative. Those skilled in the art will recognize that many more possible combinations and permutations are possible other than the components and methods (manufacturing processes) listed for the purpose of illustrating the technology of the present disclosure. The present disclosure is intended to embrace all alternatives, modifications, and variations that fall within the scope of the present disclosure, including the claims. [Explanation of symbols]

[0128] 10, 10A~10E resistor chip 11 First element surface 12 Second element surface 13~16 Side of element 20 Insulating material 20R Second insulating surface 20S First insulating surface 21 Insulating substrate 21R Second board surface 21S 1st board surface 22 Insulating layer 30 resistors 31 Insulator 31R 2nd side 31S 1st page 32 First insulating layer 33 Second insulating layer 34 Third insulating layer 35 Fourth insulating layer 40 resistance layer 40A thin film resistive layer 41~44 1st~4th resistance layer 45 Resistor connection 45A connection wiring 45A1 1st end 45A2 2nd end 45B, 45C connection vias 46 Annular Conductor 46A peripheral wiring 46B Peripheral via conductor 46C Peripheral Resistive Film 51 Passivation film 51D opening 52 First passivation film 53 Second passivation film 54 Resin Film 54D opening 60 electrodes 61 1st electrode 62 2nd electrode 63 3rd electrode 63A First detection electrode 63B Reference electrode 63C Second detection electrode 100 Semiconductor Packages 110 cases 111 Page 1 112 Side 2 113 Side 114 recess 115 Lid material 120 Support member 121 First die pad 122 Second die pad 131 Bonding materials 132 Bonding material 140 leads 141 First Lead 142 Second Lead 143 Third Lead 220 Insulating materials 221 Laminate 222 First insulating film 223 Second insulating film 224 Second insulating film 320 Insulating materials 321 First board 321R 2nd side 321S 1st page 322 Resin layer 322R 2nd side 322S 1st page 420 Insulating materials 421 1st resin layer 421R 2nd side 421S 1st page 422 Second board 422R 2nd page 422S 1st page 423 2nd resin layer 423R 2nd side 423S 1st page 520 Insulating materials 700 resistor chips 701 Semiconductor substrate 702 Laminated Insulator 703 Insulating film 704 First insulating film 705 Second insulating film 706 Second insulating film RA~RD resistance value W1~W4 wires

Claims

1. An insulating member; a resistor provided on the insulating member; Including, The resistor is An insulator; a resistive layer disposed within the insulator; Including, The insulating member includes an insulating substrate made of glass or sapphire. Resistor chip.

2. the insulating member is provided on the insulating substrate and includes an insulating layer made of a material containing silicon; The resistor chip of claim 1 .

3. the insulating layer is a silicon oxide film or a silicon nitride film; The resistor chip of claim 2 .

4. the insulating member includes a laminate provided between the insulating substrate and the resistor; The resistor chip of claim 1 .

5. The laminate is formed by laminating a silicon oxide film and a silicon nitride film. The resistor chip according to claim 4 .

6. The thickness of the laminate is smaller than the thickness of the insulating substrate. The resistor chip according to claim 4 .

7. The thickness of the laminate is smaller than the thickness of the resistor. The resistor chip according to claim 4 .

8. An insulating member; a resistor provided on the insulating member; Including, The resistor is An insulator; a resistive layer disposed within the insulator; Including, The insulating member is a first substrate made of a material including a semiconductor material; a first resin layer provided on the first substrate; Including, Resistor chip.

9. the first substrate is made of a material containing silicon; The resistor chip of claim 8.

10. the first resin layer is made of a molding resin, a polyimide resin, or a polybenzoxazole resin; The resistor chip of claim 8.

11. The thickness of the first resin layer is thinner than the thickness of the first substrate. The resistor chip of claim 8.

12. a second substrate disposed between the first substrate and the resistor; The resistor chip of claim 8.

13. the second substrate is disposed between the first resin layer and the resistor; The resistor chip of claim 12.

14. the first substrate and the second substrate are Si substrates; The resistor chip of claim 12.

15. the insulating member includes a laminate provided between the first substrate and the resistor; The resistor chip of claim 8.

16. the laminate is provided between the first resin layer and the resistor; The resistor chip of claim 15.

17. The laminate is provided between the first substrate and the first resin layer. The resistor chip of claim 15.

18. The laminate is formed by laminating a silicon oxide film and a silicon nitride film. The resistor chip of claim 15.

19. the insulating member includes a second resin layer provided between the first substrate and the resistor; The resistor chip of claim 12.

20. the first resin layer is provided between the first substrate and the second substrate, the second resin layer is provided between the second substrate and the resistor; 20. The resistor chip of claim 19.

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