Laminate for forming semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a laminate for forming a semiconductor device and a manufacturing method for the semiconductor device, in which a support body can be easily peeled off from a redistribution layer.SOLUTION: A laminate L1 for forming a semiconductor device includes a support body 1, a preliminary redistribution layer 3 provided on one surface side of the support body 1, and a seed layer 5 provided on one surface side of the preliminary redistribution layer 3.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, with the miniaturization of electronic devices, there has been an increasing need for smaller and more highly integrated semiconductor packages to be mounted on electronic devices. Currently, the mainstream packaging technology is FCBGA (Flip Chip-Ball Grid Array), which provides solder bumps on a semiconductor chip to connect it to a circuit board. However, as an alternative technology, FOWLP (Fan-Out Wafer Level Packaging), which provides solder balls directly on a semiconductor chip via a re-distribution layer (RDL) without using a circuit board, is being considered (see, for example, Patent Document 1).

[0003] FOWLP is mainly divided into the Die-First method and the RDL-First method. The Die-First method is a method in which a semiconductor chip is placed on a support via a release layer, the semiconductor chip is sealed, and then the support is peeled off from the semiconductor chip to form a rewiring layer. The RDL-First method is a method in which a rewiring layer is formed on a support via a release layer, and then a semiconductor chip is formed and sealed, and then the support is peeled off from the rewiring layer (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. WO2020 / 105485 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-35551 Summary of the Invention [Problem to be solved by the invention]

[0005] In the Die-First method, the semiconductor chip is encapsulated before the formation of the redistribution layer, so if there is a defect in the redistribution layer, the good semiconductor chip must also be discarded. In the RDL-First method, the redistribution layer is formed before the semiconductor chip is encapsulated, so this issue can be overcome, but there is also a need for the support to be able to be easily peeled off from the redistribution layer without damaging the redistribution layer that has already been formed.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device that allow the support to be easily peeled off from the rewiring layer. [Means for solving the problem]

[0007] The gist of the present disclosure is as follows.

[0008] [1] A laminate for forming a semiconductor device, comprising: a support; a spare rewiring layer provided on one surface of the support; and a seed layer provided on one surface of the spare rewiring layer.

[0009] In this semiconductor device forming laminate, a preliminary rewiring layer is provided on one side of the support, and a seed layer is provided on one side of the preliminary rewiring layer. When manufacturing a semiconductor device using this laminate, a plating layer is formed in a predetermined pattern on the rewiring laminated on the preliminary rewiring layer, and after mounting and sealing a semiconductor chip, the support can be easily peeled from the rewiring layer at the preliminary rewiring layer. By being able to easily peel the support from the rewiring layer, damage to the rewiring layer is suppressed, and the reliability of the manufactured semiconductor device is improved.

[0010] [2] The laminate for forming a semiconductor device according to [1], wherein a metal layer is provided between the support and the preliminary redistribution layer, In this case, the support can be easily peeled off from the redistribution layer, for example, by irradiating the metal layer with incoherent light and heating the preliminary redistribution layer through the metal layer.

[0011] [3] The laminate for forming a semiconductor device according to claim [1], wherein the spare rewiring layer is provided directly on one surface of the support body. In this case, for example, the spare rewiring layer is irradiated with coherent light, and the spare rewiring layer is divided by the irradiation of the coherent light, whereby the support body can be easily peeled off from the rewiring layer.

[0012] [4] A method for manufacturing a semiconductor device, comprising: a preparation step of preparing a support; a preliminary rewiring layer formation step of forming a preliminary rewiring layer on one side of the support; a seed layer formation step of forming a seed layer on one side of the preliminary rewiring layer; a plating layer formation step of forming a plating layer on the seed layer in a rewiring layer on the preliminary rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; a sealing step of sealing the semiconductor chip; and a peeling step of peeling the support from the preliminary rewiring layer.

[0013] In this semiconductor device manufacturing method, a preliminary rewiring layer is formed on one side of the support, and a seed layer is formed on one side of the preliminary rewiring layer. This allows a plating layer to be formed in a predetermined pattern on the rewiring layer stacked on the preliminary rewiring layer, and after mounting and sealing the semiconductor chip, the support can be easily peeled off from the rewiring layer at the preliminary rewiring layer. Being able to easily peel off the support from the rewiring layer reduces damage to the rewiring layer and improves the reliability of the manufactured semiconductor device.

[0014] [5] The method for manufacturing a semiconductor device according to [4], further comprising a metal layer forming step of forming a metal layer on one surface of the support between the preparing step and the preliminary redistribution layer forming step, wherein the peeling step irradiates the metal layer with incoherent light to peel the support from the preliminary redistribution layer. In this case, the support can be easily peeled from the redistribution layer by, for example, irradiating the metal layer with incoherent light and heating the preliminary redistribution layer via the metal layer.

[0015] [6] The method for manufacturing a semiconductor device according to [4], wherein in the preliminary redistribution layer forming step, the preliminary redistribution layer is directly formed on one surface of the support, and in the peeling step, the preliminary redistribution layer is irradiated with coherent light to peel off the support from the preliminary redistribution layer. In this case, by irradiating the preliminary redistribution layer with coherent light and dividing the preliminary redistribution layer by the irradiation of coherent light, the support can be easily peeled off from the redistribution layer.

[0016] [7] A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor device forming laminate according to [1]; a plating layer forming step of forming a plating layer on the seed layer in a rewiring layer on the preliminary rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; a sealing step of sealing the semiconductor chip; and a peeling step of peeling the support from the preliminary rewiring layer.

[0017] This semiconductor device manufacturing method uses a semiconductor device forming laminate in which a preliminary redistribution layer is formed on one side of a support and a seed layer is formed on one side of the preliminary redistribution layer. This allows a plating layer to be formed in a predetermined pattern on the redistribution layer laminated on the preliminary redistribution layer, and after mounting and sealing a semiconductor chip, the support can be easily peeled from the redistribution layer at the preliminary redistribution layer. Being able to easily peel the support from the redistribution layer reduces damage to the redistribution layer and improves the reliability of the manufactured semiconductor device.

[0018] [8] The method for manufacturing a semiconductor device according to [7], further comprising the steps of: preparing the semiconductor device forming laminate in which a metal layer is provided between the support and the preliminary redistribution layer; and irradiating the metal layer with incoherent light to peel off the support from the preliminary redistribution layer in the peeling step. In this case, the support can be easily peeled off from the redistribution layer by irradiating the metal layer with incoherent light and heating the preliminary redistribution layer through the metal layer.

[0019] [9] The method for manufacturing a semiconductor device according to [7], further comprising the steps of: preparing a semiconductor device forming laminate in which the spare redistribution layer is provided directly on one surface of the support; and irradiating the spare redistribution layer with coherent light to peel off the support from the spare redistribution layer in the peeling step. In this case, the spare redistribution layer is irradiated with coherent light and the spare redistribution layer is divided by the irradiation of the coherent light, thereby easily peeling off the support from the redistribution layer. [Effects of the Invention]

[0020] According to the present disclosure, the support can be easily peeled off from the rewiring layer. [Brief explanation of the drawings]

[0021] [Figure 1] 3 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 2] 1A is a schematic cross-sectional view showing a preparation step, and FIG. 1B is a schematic cross-sectional view showing a metal layer formation step. [Figure 3] 1A is a schematic cross-sectional view showing a preliminary rewiring layer forming step, and FIG. 1B is a schematic cross-sectional view showing a stacked body for forming a semiconductor device obtained after a seed layer forming step. [Figure 4] 5(a) to 5(c) are schematic cross-sectional views showing a plating layer forming step. [Figure 5] 1A is a schematic cross-sectional view showing a seed layer removing step performed after a plating layer forming step, and FIG. 1B is a schematic cross-sectional view showing the next step of forming a rewiring layer. [Figure 6] FIG. 10 is a schematic cross-sectional view showing a structure after repeatedly performing a seed layer formation step, a plating layer formation step, and the formation of a subsequent rewiring layer. [Figure 7] FIG. 1(a) is a schematic cross-sectional view showing a mounting step, and FIG. 1(b) is a schematic cross-sectional view showing a sealing step. [Figure 8] 10(a) and 10(b) are schematic cross-sectional views showing a peeling step. [Figure 9]1A is a schematic cross-sectional view showing a processing step, and FIG. 1B is a schematic cross-sectional view showing a ball mounting step. [Figure 10] 1(a) is a schematic cross-sectional view showing a modified example of a semiconductor device forming laminate obtained after a seed layer forming process, and (b) and (c) are schematic cross-sectional views showing a peeling process in that case. DETAILED DESCRIPTION OF THE INVENTION

[0022] Hereinafter, preferred embodiments of a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device according to one aspect of the present disclosure will be described in detail with reference to the drawings.

[0023] In the following description, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. Furthermore, in a numerical range that is stated in stages, the upper or lower limit value stated in one numerical range may be replaced with the upper or lower limit value of another numerical range that is stated in stages. The upper or lower limit value of a numerical range may be replaced with a value shown in the examples.

[0024] [First embodiment] Fig. 1 is a flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. The method for manufacturing a semiconductor device shown in Fig. 1 is a method belonging to Fan-Out Wafer Level Packaging (FOWLP), in which solder balls are provided directly on a semiconductor chip via a re-distribution layer (RDL) without using a circuit board. Here, the RDL-First method of FOWLP, in which a re-distribution layer is formed before sealing the semiconductor chip, is adopted.

[0025] As shown in FIG. 1, the method for manufacturing the semiconductor device according to the first embodiment includes a preparation step S01, a metal layer formation step S02, a spare redistribution layer formation step S03, a seed layer formation step S04, a plating layer formation step S05, a mounting step S06, a sealing step S07, a peeling step S08, a processing step S09, and a ball mounting step S10.

[0026] The preparation step S01 is a step of preparing a support 1, as shown in FIG. 2(a). The support 1 is not particularly limited, and may be, for example, a glass substrate, a resin substrate, a silicon wafer, or a metal thin film. In the example of FIG. 2(a), the support 1 is made of a glass substrate. The thickness of the support 1 is, for example, about 0.1 mm to 2.0 mm. By making the thickness of the support 1 0.1 mm or more, the handleability of the support 1 can be sufficiently ensured. By making the thickness of the support 1 2.0 mm or less, the material cost of the support 1 can be reduced.

[0027] As shown in FIG. 2(b), the metal layer forming step S02 is a step of forming a metal layer 2 on one surface of the support 1. The metal layer 2 is a layer used to peel the support 1 from the rewiring layer 4 in the subsequent peeling step S09. The metal layer 2 is formed, for example, by sputtering or laminating a metal foil. The material for forming the metal layer 2 is not particularly limited as long as it is a conductor that absorbs light and generates heat. Examples include metals such as chromium, copper, titanium, silver, platinum, gold, and tungsten; alloys such as nickel-chromium, titanium-tungsten, copper-zinc, and stainless steel; and metal oxides such as indium tin oxide (ITO), zinc oxide, and niobium oxide. These materials may be used alone or in combination of two or more. When two or more metals are combined, a laminate structure of the respective metals may be used.

[0028] From the viewpoint of improving releasability, the thickness of the metal layer 2 may be, for example, 1 nm to 5,000 nm or 50 nm to 3,000 nm. When two types of metals are laminated in combination, the thickness of the first metal layer formed on the support 1 may be 1 nm to 1,000 nm, 5 nm to 500 nm, or 10 nm to 100 nm. By making the thickness of the first metal layer 1 equal to or greater than 1 nm, it is possible to prevent defects from occurring in the metal layer, and by making it equal to or less than 1,000 nm, it is possible to prevent a decrease in releasability. The thickness of the second metal layer formed on the first metal layer may be 1 nm to 5,000 nm, 10 nm to 500 nm, or 50 nm to 200 nm. By making the thickness of the second metal layer 1 nm or greater, it is possible to prevent defects from occurring in the metal layer, and by making it equal to or less than 5,000 nm, it is possible to prevent a decrease in releasability.

[0029] As shown in FIG. 3( a), the preliminary rewiring layer forming step S03 is a step of forming a preliminary rewiring layer 3 on one surface of the support 1. The preliminary rewiring layer 3 is a layer used to peel the support 1 from the rewiring layer 4 in the subsequent peeling step S08. Here, the preliminary rewiring layer 3 is formed on the metal layer 2 on one surface of the support 1. The preliminary rewiring layer 3 is formed, for example, by applying a rewiring material to the metal layer 2 and curing it. Examples of the rewiring material include an electrically insulating photosensitive resin material. Examples of the resin material include polyimide, polybenzoxazole, phenol novolac, and polyhydroxystyrene. The thickness of the preliminary rewiring layer 3 is, for example, approximately 5 μm to 20 μm. Setting the thickness of the preliminary rewiring layer 3 to 5 μm or more can prevent defects from occurring in the preliminary rewiring layer 3. Setting the thickness of the preliminary rewiring layer 3 to 20 μm or less can prevent variations in the thickness of the preliminary rewiring layer 3.

[0030] As shown in FIG. 3(b), the seed layer forming step S04 is a step of forming a seed layer 5 on one surface of the spare redistribution layer 3. The seed layer 5 is a layer used to supply power for growing the plating layer 7 formed in the subsequent plating layer forming step S05. In the example of FIG. 3(b), the seed layer 5 is formed flat on one surface of the spare redistribution layer 3. The seed layer 5 is formed by, for example, sputtering. Examples of materials for forming the seed layer 5 include titanium, copper, tungsten, nickel, and silver. The thickness of the seed layer 5 is, for example, approximately 1 nm to 100 nm. Setting the thickness of the seed layer 5 to 1 nm or more can prevent defects from occurring in the seed layer. Setting the thickness of the seed layer 5 to 100 nm or less can shorten the sputtering processing time and prevent variations in the thickness of the seed layer 5.

[0031] Formation of the seed layer 5 provides a semiconductor device forming laminate L1. That is, the semiconductor device forming laminate L1 includes a support 1, a spare redistribution layer 3 provided on one surface of the support 1, and a seed layer 5 provided on one surface of the spare redistribution layer 3. In the example of FIG. 3(b), a metal layer 2 is provided between the support 1 and the spare redistribution layer 3 in the semiconductor device forming laminate L1. In the method for manufacturing a semiconductor device according to this embodiment, the semiconductor device forming laminate L1 may be prepared in advance, and the subsequent steps may be carried out.

[0032] The plating layer forming step S05 is a step of forming a plating layer 7 on the seed layer 5. In the plating layer forming step S05, first, as shown in FIG. 4(a), a resist 6 is formed in a predetermined pattern on the seed layer 5. Next, as shown in FIG. 4(b), the plating layer 7 is formed on the seed layer 5 exposed from the resist 6. The plating layer 7 is formed, for example, by electrolytic plating. An example of a material for forming the plating layer 7 is copper. After the plating layer 7 is formed, the resist 6 is removed, as shown in FIG. 4(c).

[0033] After removing the resist 6, the seed layer 5 remaining on the rewiring layer 4 is removed as shown in FIG. 5( a). The seed layer 5 is removed by, for example, etching. After removing the seed layer 5, the next rewiring layer 4 is formed as shown in FIG. 5( b). The next rewiring layer 4 is formed, for example, by applying and curing a rewiring material on the preliminary rewiring layer 3. Here, the rewiring layer 4 is patterned to expose the plating layer 7 formed in the plating layer forming step S05 from the rewiring layer 4. In this embodiment, the rewiring layer 4 and the preliminary rewiring layer 3 are made of the same rewiring material, but they may be made of different rewiring materials. The rewiring material is appropriately selected from the perspectives of patternability and reliability. The thickness of the rewiring layer 4 may be the same as or different from the thickness of the preliminary rewiring layer 3. The thickness of the rewiring layer 4 is appropriately selected from the perspectives of workability and reliability.

[0034] Thereafter, the seed layer formation step S04, the plating layer formation step S05, and the formation of the next rewiring layer 4 are repeatedly performed to form plating layers 7 of a predetermined pattern on the desired number of rewiring layers 4, as shown in Fig. 6. The plating layers 7 of each layer are electrically connected to each other in the stacking direction of the rewiring layers 4, and form wiring portions that connect the semiconductor chip W (see Fig. 7(a)) and the external extraction electrodes (not shown).

[0035] As shown in FIG. 7(a), the mounting step S06 is a step of mounting a semiconductor chip W on the plating layer 7. The semiconductor chip W is formed by cutting a semiconductor wafer to a predetermined size and dividing it into individual chips. The thickness of the semiconductor chip W may be 1 μm to 1000 μm, 10 μm to 500 μm, or 20 μm to 200 μm, from the viewpoint of miniaturizing and thinning the semiconductor device and preventing cracks during transportation and processing. The semiconductor chip W is provided with solder bumps 8. As shown in FIG. 7(a), the mounting of the semiconductor chip W on the plating layer 7 is achieved by joining the solder bumps 8 to the outermost plating layer 7 exposed from the outermost rewiring layer 4.

[0036] The encapsulation step S07 is a step of encapsulating the semiconductor chip W, as shown in FIG. 7(b). In the encapsulation step S07, for example, an encapsulation layer 9 is formed on the outermost rewiring layer 4 so as to cover the semiconductor chip W and the solder bumps 8. There are no particular limitations on the material constituting the encapsulation layer 9, but from the viewpoints of heat resistance and reliability, a thermosetting resin composition may be used. The composition of the encapsulation layer 9 may contain additives such as a filler and a flame retardant.

[0037] The peeling step S08 is a step of peeling the support 1 from the rewiring layer 4. In this embodiment, the metal layer 2 provided between the support 1 and the spare rewiring layer 3 is used, and as shown in FIG. 8( a), incoherent light P1 is irradiated onto the metal layer 2 to peel the support 1 from the rewiring layer 4. A xenon lamp, for example, is used as a light source that outputs the incoherent light P1. In the example of FIG. 8( a), the incoherent light P1 from the light source is irradiated toward the metal layer 2 from the support 1 side. The metal layer 2 is heated by irradiating the metal layer 2 with the incoherent light P1, and the spare rewiring layer 3 is heated via the metal layer 2.

[0038] Heating the spare rewiring layer 3 hardens the resin component constituting the spare rewiring layer, and as shown in FIG. 8( b), the metal layer 2 is peeled off from the spare rewiring layer 3, thereby easily peeling the support 1 and the metal layer 2 from the spare rewiring layer 3. The irradiation conditions of the incoherent light P1 can be set arbitrarily, and may be set so that the support 1 and the metal layer 2 can be peeled off from the spare rewiring layer 3 with a single irradiation, or may be set so that the support 1 and the metal layer 2 can be peeled off from the spare rewiring layer 3 with two or more irradiations. From the viewpoint of reducing damage to the rewiring layer 4, the plating layer 7, and the semiconductor chip W, it is preferable that the irradiation conditions of the incoherent light P1 be set so that the support 1 and the metal layer 2 can be peeled off from the spare rewiring layer 3 with a single irradiation.

[0039] 9(a), the processing step S09 is a step of processing the spare rewiring layer 3 so as to expose the plating layer 7. In the processing step S09, holes are drilled in a predetermined pattern in the spare rewiring layer 3 on the side opposite to the semiconductor chip W by, for example, irradiating it with laser light, and the plating layer 7 (seed layer 5) is exposed in the spare rewiring layer 3.

[0040] 9(b), the ball mounting step S10 is a step of mounting solder balls 10 on the plating layer 7. In the ball mounting step S10, solder balls 10 are bonded to each of the plating layers 7 (seed layers 5) exposed from the spare rewiring layer 3 on the side opposite the semiconductor chip W by the processing step S09 so as to protrude from the spare rewiring layer 3. Through the above steps, a semiconductor device D1 is obtained in which the solder balls 10 are provided directly on the semiconductor chip W via the spare rewiring layer 3 and the rewiring layer 4.

[0041] As described above, in this semiconductor device forming laminate L1 and semiconductor device manufacturing method, the preliminary redistribution layer 3 is formed on one side of the support 1, and the seed layer 5 is formed on one side of the preliminary redistribution layer 3. As a result, a plating layer 7 is formed in a predetermined pattern on the redistribution layer 4 laminated on the preliminary redistribution layer 3, and after mounting and sealing the semiconductor chip W, the support 1 can be easily peeled off from the redistribution layer 4 at the portion of the preliminary redistribution layer 3. Being able to easily peel off the support 1 from the redistribution layer 4 reduces damage to the redistribution layer 4, improving the reliability of the manufactured semiconductor device D1.

[0042] In this embodiment, a metal layer 2 is provided between the support 1 and the spare redistribution layer 3. This allows the support 1 to be easily peeled off from the redistribution layer 4 by irradiating the metal layer 2 with incoherent light P1 and heating the spare redistribution layer 3 via the metal layer 2. The ability to easily peel the support 1 from the redistribution layer 4 makes it possible to suppress stress from being applied to the redistribution layer 4 during peeling, and to prevent the redistribution layers 4, 4 from peeling off from each other.

[0043] [Variations] In the above embodiment, the metal layer 2 is provided between the support 1 and the spare redistribution layer 3, but the formation of the metal layer 2 may be omitted. In this case, as shown in FIG. 10( a), the spare redistribution layer 3 is directly formed on one surface of the support 1 in the semiconductor device forming laminate L1 obtained by forming the seed layer 5. When this configuration is adopted, in the peeling step S08, as shown in FIG. 10( b), the spare redistribution layer 3 is irradiated with coherent light P2. An example of a light source that outputs the coherent light P2 is a light source that outputs an ultraviolet laser. The coherent light P2 is scanned in the in-plane direction of the spare redistribution layer 3, and the spare redistribution layer 3 is divided as shown in FIG. 10( c), thereby easily peeling the support 1 from the redistribution layer 4. [Explanation of symbols]

[0044] 1...support, 2...metal layer, 3...spare rewiring layer, 4...rewiring layer, 5...seed layer, 7...plating layer, L1, L2...laminated body for forming semiconductor device, W...semiconductor chip, P1...incoherent light, P2...coherent light.

Claims

1. A support; a spare rewiring layer provided on one surface of the support; a seed layer provided on one surface side of the spare rewiring layer.

2. 2. The laminate for forming a semiconductor device according to claim 1, wherein a metal layer is provided between said support and said preliminary rewiring layer.

3. 2. The laminate for forming a semiconductor device according to claim 1, wherein the spare rewiring layer is provided directly on one surface of the support.

4. a preparation step of preparing a support; a preliminary rewiring layer forming step of forming a preliminary rewiring layer on one surface of the support; a seed layer forming step of forming a seed layer on one surface of the preliminary rewiring layer; a plating layer forming step of forming a plating layer on the seed layer in the rewiring layer on the preliminary rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; an encapsulation step of encapsulating the semiconductor chip; and a peeling step of peeling the support from the preliminary rewiring layer.

5. a metal layer forming step for forming a metal layer on one surface of the support body is provided between the preparing step and the rewiring layer forming step; 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the peeling step, the support is peeled off from the spare rewiring layer by irradiating the metal layer with incoherent light.

6. In the preliminary rewiring layer forming step, the preliminary rewiring layer is formed directly on one surface of the support; 5. The method for manufacturing a semiconductor device according to claim 4, wherein in the peeling step, the support is peeled off from the preliminary rewiring layer by irradiating the preliminary rewiring layer with coherent light.

7. A step of preparing a laminate for forming a semiconductor device according to claim 1; a plating layer forming step of forming a plating layer on the seed layer in the rewiring layer on the preliminary rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; an encapsulation step of encapsulating the semiconductor chip; and a peeling step of peeling the support from the preliminary rewiring layer.

8. preparing a semiconductor device forming laminate in which a metal layer is provided between the support and the preliminary rewiring layer; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the peeling step, the support is peeled off from the spare redistribution layer by irradiating the metal layer with incoherent light.

9. preparing a semiconductor device forming laminate in which the preliminary rewiring layer is provided directly on one surface of the support; 8. The method for manufacturing a semiconductor device according to claim 7, wherein in the peeling step, the support is peeled off from the preliminary rewiring layer by irradiating the preliminary rewiring layer with coherent light.

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