Laminate for forming semiconductor device and manufacturing method for semiconductor device

Abstract

To provide a laminate for forming a semiconductor device and a manufacturing method for the semiconductor device, in which a support body can be easily peeled off from a redistribution layer.SOLUTION: A laminate L1 for forming a semiconductor device includes a support body 1, a temporary fixing layer 3 provided on one surface side of the support body 1, a redistribution layer 4 provided on one surface side of the temporary fixing layer 3, and a seed layer 5 provided on one surface side of the redistribution layer 4.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present disclosure relates to a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device. [Background technology]

[0002] In recent years, with the miniaturization of electronic devices, there has been an increasing need for smaller and more highly integrated semiconductor packages to be mounted on electronic devices. Currently, the mainstream packaging technology is FCBGA (Flip Chip-Ball Grid Array), which provides solder bumps on a semiconductor chip to connect it to a circuit board. However, as an alternative technology, FOWLP (Fan-Out Wafer Level Packaging), which provides solder balls directly on a semiconductor chip via a re-distribution layer (RDL) without using a circuit board, is being considered (see, for example, Patent Document 1).

[0003] FOWLP is mainly divided into the Die-First method and the RDL-First method. The Die-First method is a method in which a semiconductor chip is placed on a support via a release layer, the semiconductor chip is sealed, and then the support is peeled off from the semiconductor chip to form a rewiring layer. The RDL-First method is a method in which a rewiring layer is formed on a support via a release layer, and then a semiconductor chip is formed and sealed, and then the support is peeled off from the rewiring layer (see, for example, Patent Document 2). [Prior art documents] [Patent documents]

[0004] [Patent Document 1] International Publication No. WO2020 / 105485 [Patent Document 2] Japanese Patent Application Laid-Open No. 2015-35551 Summary of the Invention [Problem to be solved by the invention]

[0005] In the Die-First method, the semiconductor chip is encapsulated before the formation of the redistribution layer, so if there is a defect in the redistribution layer, the good semiconductor chip must also be discarded. In the RDL-First method, the redistribution layer is formed before the semiconductor chip is encapsulated, so this issue can be overcome, but there is also a need for the support to be able to be easily peeled off from the redistribution layer without damaging the redistribution layer that has already been formed.

[0006] The present disclosure has been made to solve the above-mentioned problems, and aims to provide a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device that allow the support to be easily peeled off from the rewiring layer. [Means for solving the problem]

[0007] The gist of the present disclosure is as follows.

[0008] [1] A laminate for forming a semiconductor device, comprising: a support; a temporary fixing layer provided on one side of the support; a rewiring layer provided on one side of the temporary fixing layer; and a seed layer provided on one side of the rewiring layer.

[0009] In this laminate for forming a semiconductor device, a temporary fixing layer is provided on one side of the support, and a rewiring layer and a seed layer are provided on one side of the temporary fixing layer. When manufacturing a semiconductor device using this laminate, a plating layer is formed in a predetermined pattern on the rewiring layer, and after mounting and sealing a semiconductor chip, the support can be easily peeled from the rewiring layer at the temporary fixing layer. By being able to easily peel the support from the rewiring layer, damage to the rewiring layer is suppressed, and the reliability of the manufactured semiconductor device is improved.

[0010] [2] The laminate for forming a semiconductor device according to [1], wherein a metal layer is provided between the support and the temporary fixing layer, In this case, the support can be easily peeled off from the rewiring layer, for example, by irradiating the metal layer with incoherent light and heating the temporary fixing layer through the metal layer.

[0011] [3] The laminate for forming a semiconductor device according to [1], wherein the temporary fixing layer is provided directly on one surface of the support. In this case, for example, the temporary fixing layer is irradiated with coherent light, and the temporary fixing layer is divided by the irradiation of the coherent light, whereby the support can be easily peeled off from the redistribution layer.

[0012] [4] The laminate for forming a semiconductor device according to any one of [1] to [3], wherein the rewiring layer is patterned to expose the temporary fixing layer. In this case, after peeling off the support and removing the temporary fixing layer, a processing step for exposing the plating layer from the rewiring layer is not required. This also eliminates the need for cleaning debris generated during the processing step, thereby simplifying the manufacturing process of the semiconductor device.

[0013] [5] A method for manufacturing a semiconductor device, comprising: a preparation step of preparing a support; a temporary fixing layer formation step of forming a temporary fixing layer on one side of the support; a rewiring layer formation step of forming a rewiring layer on one side of the temporary fixing layer; a seed layer formation step of forming a seed layer on one side of the rewiring layer; a plating layer formation step of forming a plating layer on the seed layer in the rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; a sealing step of sealing the semiconductor chip; a peeling step of peeling the support from the temporary fixing layer; and a removal step of removing the temporary fixing layer from the rewiring layer.

[0014] In this semiconductor device manufacturing method, a temporary fixing layer is formed on one side of the support, and a rewiring layer and a seed layer are formed on one side of the temporary fixing layer. As a result, after forming a plating layer in a predetermined pattern on the rewiring layer and mounting and sealing the semiconductor chip, the support can be easily peeled from the rewiring layer at the temporary fixing layer. By being able to easily peel the support from the rewiring layer, damage to the rewiring layer is suppressed, and the reliability of the manufactured semiconductor device is improved.

[0015] [6] The method for manufacturing a semiconductor device according to [5], further comprising a metal layer forming step of forming a metal layer on one surface of the support between the temporary fixing layer forming step and the rewiring layer forming step, wherein the peeling step comprises irradiating the metal layer with incoherent light to peel the support from the temporary fixing layer. In this case, the support can be easily peeled from the rewiring layer by irradiating the metal layer with incoherent light and heating the temporary fixing layer via the metal layer.

[0016] [7] The method for manufacturing a semiconductor device according to [5], wherein in the temporary fixing layer forming step, the temporary fixing layer is formed directly on one surface of the support, and in the peeling step, the temporary fixing layer is irradiated with coherent light to peel the support from the temporary fixing layer. In this case, by irradiating the temporary fixing layer with coherent light and dividing the temporary fixing layer by the irradiation of coherent light, the support can be easily peeled from the redistribution layer.

[0017] [8] The method for manufacturing a semiconductor device according to any one of [5] to [7], wherein the rewiring layer forming step involves patterning the rewiring layer to expose the temporary fixing layer. In this case, after peeling off the support and removing the temporary fixing layer, a processing step for exposing the plating layer from the rewiring layer is not required. This also eliminates the need for cleaning debris generated during the processing step, simplifying the manufacturing process of the semiconductor device.

[0018] [9] A method for manufacturing a semiconductor device, comprising: a step of preparing a semiconductor device forming laminate according to [1]; a plating layer forming step of forming a plating layer on the seed layer in the rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; a sealing step of sealing the semiconductor chip; a peeling step of peeling the support from the temporary fixing layer; and a removal step of removing the temporary fixing layer from the rewiring layer.

[0019] This semiconductor device manufacturing method uses a laminate for forming a semiconductor device, which has a temporary fixing layer formed on one side of a support and a rewiring layer and a seed layer on one side of the temporary fixing layer. This allows a plating layer to be formed on the rewiring layer in a predetermined pattern, and after mounting and sealing a semiconductor chip, the support can be easily peeled from the rewiring layer at the temporary fixing layer. Being able to easily peel the support from the rewiring layer reduces damage to the rewiring layer and improves the reliability of the manufactured semiconductor device.

[0020]

[10] The method for manufacturing a semiconductor device according to [9], wherein the semiconductor device forming laminate includes a metal layer provided between the support and the temporary fixing layer, and the peeling step includes irradiating the metal layer with incoherent light to peel the support from the temporary fixing layer. In this case, the support can be easily peeled from the rewiring layer by irradiating the metal layer with incoherent light and heating the temporary fixing layer via the metal layer.

[0021]

[11] The method for manufacturing a semiconductor device according to [9], further comprising the steps of: preparing a laminate for forming a semiconductor device in which the temporary fixing layer is provided directly on one surface of the support; and irradiating the temporary fixing layer with coherent light to peel the support from the temporary fixing layer in the peeling step. In this case, the temporary fixing layer is irradiated with coherent light, and the temporary fixing layer is divided by the irradiation of the coherent light, thereby easily peeling the support from the redistribution layer.

[0022]

[12] The method for manufacturing a semiconductor device according to any one of [9] to

[11] , further comprising preparing the semiconductor device-forming laminate, in which the rewiring layer is patterned to expose the temporary fixing layer. In this case, after peeling off the support and removing the temporary fixing layer, a processing step for exposing the plating layer from the rewiring layer is not required. This also eliminates the need for cleaning debris generated during the processing step, simplifying the semiconductor device manufacturing process. [Effects of the Invention]

[0023] According to the present disclosure, the support can be easily peeled off from the rewiring layer. [Brief explanation of the drawings]

[0024] [Figure 1] 3 is a flowchart showing a method for manufacturing a semiconductor device according to the first embodiment of the present disclosure. [Figure 2] 1A is a schematic cross-sectional view showing a preparation step, and FIG. 1B is a schematic cross-sectional view showing a metal layer formation step. [Figure 3] (a) is a schematic cross-sectional view showing the temporary fixing layer formation process, (b) is a schematic cross-sectional view showing the rewiring layer formation process, and (c) is a schematic cross-sectional view showing the semiconductor device formation laminate obtained after the seed layer formation process. [Figure 4] 5(a) to 5(c) are schematic cross-sectional views showing a plating layer forming step. [Figure 5] 1A is a schematic cross-sectional view showing a seed layer removing step performed after a plating layer forming step, and FIG. 1B is a schematic cross-sectional view showing the next step of forming a rewiring layer. [Figure 6] FIG. 10 is a schematic cross-sectional view showing a structure after repeatedly performing a seed layer formation step, a plating layer formation step, and the formation of a subsequent rewiring layer. [Figure 7] FIG. 1(a) is a schematic cross-sectional view showing a mounting step, and FIG. 1(b) is a schematic cross-sectional view showing a sealing step. [Figure 8] 10(a) and 10(b) are schematic cross-sectional views showing a peeling step, and 10(c) is a schematic cross-sectional view showing a removal step. [Figure 9] 1A is a schematic cross-sectional view showing a processing step, and FIG. 1B is a schematic cross-sectional view showing a ball mounting step. [Figure 10] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure. [Figure 11] 1A is a schematic cross-sectional view showing a preparation step, and FIG. 1B is a schematic cross-sectional view showing a metal layer formation step. [Figure 12] (a) is a schematic cross-sectional view showing the temporary fixing layer formation process, (b) is a schematic cross-sectional view showing the rewiring layer formation process, and (c) is a schematic cross-sectional view showing the semiconductor device formation laminate obtained in the seed layer formation process. [Figure 13] 5(a) to 5(c) are schematic cross-sectional views showing a plating layer forming step. [Figure 14] 1A is a schematic cross-sectional view showing a seed layer removing step performed after a plating layer forming step, and FIG. 1B is a schematic cross-sectional view showing the next step of forming a rewiring layer. [Figure 15] FIG. 10 is a schematic cross-sectional view showing a structure after repeatedly performing a seed layer formation step, a plating layer formation step, and the formation of a subsequent rewiring layer. [Figure 16] FIG. 1(a) is a schematic cross-sectional view showing a mounting step, and FIG. 1(b) is a schematic cross-sectional view showing a sealing step. [Figure 17] 10(a) and 10(b) are schematic cross-sectional views showing a peeling step, and 10(c) is a schematic cross-sectional view showing a removal step. [Figure 18] 1A is a schematic cross-sectional view showing a seed layer removal step performed after the removal step, and FIG. 1B is a schematic cross-sectional view showing a ball mounting step. [Figure 19] 1(a) is a schematic cross-sectional view showing a modified example of a semiconductor device forming laminate obtained after a seed layer forming process, and (b) and (c) are schematic cross-sectional views showing a peeling process in that case. DETAILED DESCRIPTION OF THE INVENTION

[0025] Hereinafter, preferred embodiments of a laminate for forming a semiconductor device and a method for manufacturing a semiconductor device according to one aspect of the present disclosure will be described in detail with reference to the drawings.

[0026] In the following description, a numerical range indicated using "to" indicates a range that includes the numerical values ​​before and after "to" as the minimum and maximum values, respectively. Furthermore, in a numerical range that is stated in stages, the upper or lower limit value stated in one numerical range may be replaced with the upper or lower limit value of another numerical range that is stated in stages. The upper or lower limit value of a numerical range may be replaced with a value shown in the examples.

[0027] [First embodiment] Fig. 1 is a flowchart showing a method for manufacturing a semiconductor device according to a first embodiment of the present disclosure. The method for manufacturing a semiconductor device shown in Fig. 1 is a method belonging to Fan-Out Wafer Level Packaging (FOWLP), in which solder balls are provided directly on a semiconductor chip via a re-distribution layer (RDL) without using a circuit board. Here, the RDL-First method of FOWLP, in which a re-distribution layer is formed before sealing the semiconductor chip, is adopted.

[0028] As shown in FIG. 1, the method for manufacturing a semiconductor device according to the first embodiment includes a preparation step S01, a metal layer formation step S02, a temporary fixing layer formation step S03, a redistribution layer formation step S04, a seed layer formation step S05, a plating layer formation step S06, a mounting step S07, a sealing step S08, a peeling step S09, a removal step S10, a processing step S11, and a ball mounting step S12.

[0029] The preparation step S01 is a step of preparing a support 1, as shown in FIG. 2(a). The support 1 is not particularly limited, and may be, for example, a glass substrate, a resin substrate, a silicon wafer, or a metal thin film. In the example of FIG. 2(a), the support 1 is made of a glass substrate. The thickness of the support 1 is, for example, about 0.1 mm to 2.0 mm. By making the thickness of the support 1 0.1 mm or more, the handleability of the support 1 can be sufficiently ensured. By making the thickness of the support 1 2.0 mm or less, the material cost of the support 1 can be reduced.

[0030] As shown in FIG. 2(b), the metal layer forming step S02 is a step of forming a metal layer 2 on one surface of the support 1. The metal layer 2 is a layer used to peel the support 1 from the rewiring layer 4 in the subsequent peeling step S09. The metal layer 2 is formed, for example, by sputtering or laminating a metal foil. The material for forming the metal layer 2 is not particularly limited as long as it is a conductor that absorbs light and generates heat. Examples include metals such as chromium, copper, titanium, silver, platinum, gold, and tungsten; alloys such as nickel-chromium, titanium-tungsten, copper-zinc, and stainless steel; and metal oxides such as indium tin oxide (ITO), zinc oxide, and niobium oxide. These materials may be used alone or in combination of two or more. When two or more metals are combined, a laminate structure of the respective metals may be used.

[0031] From the viewpoint of improving releasability, the thickness of the metal layer 2 may be, for example, 1 nm to 5,000 nm or 50 nm to 3,000 nm. When two types of metals are laminated in combination, the thickness of the first metal layer formed on the support 1 may be 1 nm to 1,000 nm, 5 nm to 500 nm, or 10 nm to 100 nm. By making the thickness of the first metal layer 1 equal to or greater than 1 nm, it is possible to prevent defects from occurring in the metal layer, and by making it equal to or less than 1,000 nm, it is possible to prevent a decrease in releasability. The thickness of the second metal layer formed on the first metal layer may be 1 nm to 5,000 nm, 10 nm to 500 nm, or 50 nm to 200 nm. By making the thickness of the second metal layer 1 nm or greater, it is possible to prevent defects from occurring in the metal layer, and by making it equal to or less than 5,000 nm, it is possible to prevent a decrease in releasability.

[0032] As shown in FIG. 3(a), the temporary fixing layer formation step S03 is a step of forming a temporary fixing layer 3 on one side of the support 1. The temporary fixing layer 3 is a layer used to peel the support 1 from the rewiring layer 4 in the subsequent peeling step S09. Here, the temporary fixing layer 3 is formed on the metal layer 2 on one side of the support 1. The temporary fixing layer 3 is formed, for example, by forming a precursor layer of the temporary fixing layer 3 on the metal layer 2 and curing the resin component in the precursor layer or by heating and drying a solvent containing the resin component. Examples of materials for forming the temporary fixing layer 3 include organic materials such as siloxanes, acrylics, and cycloolefin polymers (COP). More specifically, examples of polymers include siloxane polymers, acrylic polymers, cycloolefin polymers (COP), styrene-ethylenebutylene-styrene block copolymers (SEBS), styrene-ethylenepropylene-styrene copolymers (SEPS), styrene-isobutylene-styrene copolymers (SIBS), polyimides, polyamides, and maleimides.

[0033] The polymer may be combined with a thermosetting resin. The thermosetting resin is not particularly limited as long as it is a resin that hardens when heated. Examples of thermosetting resins include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyurethane resin, melamine resin, and urea resin. These may be used alone or in combination of two or more. The thermosetting resin may be an epoxy resin because of its excellent heat resistance, workability, and reliability. When an epoxy resin is used as the thermosetting resin, it may be used in combination with an epoxy resin curing agent. The thickness of the temporary fixing layer 3 is, for example, approximately 5 μm to 100 μm. By setting the thickness of the temporary fixing layer 3 to 5 μm or more, defects in the temporary fixing layer 3 can be suppressed. By setting the thickness of the temporary fixing layer 3 to 100 μm or less, variations in the thickness of the temporary fixing layer 3 can be suppressed.

[0034] The temporary fixing layer 3 may be removable by a method of dissolving it in a solvent, which will be described later, or by a peel-off method. When a rewiring layer 4 is formed on one side of the temporary fixing layer 3, the temporary fixing layer 3 may be removable by a peel-off method, from the viewpoint of the solubility of the rewiring layer 4 in a solvent. When the temporary fixing layer 3 contains a thermosetting resin or a partially cured thermosetting resin, the removal process by peel-off tends to be easier.

[0035] As shown in FIG. 3(b), the rewiring layer forming step S04 is a step of forming a rewiring layer 4 on one surface of the temporary fixing layer 3. The rewiring layer 4 is a layer for embedding the plating layer 7 formed in the subsequent plating layer forming step S06. Here, the rewiring layer 4 is formed directly (without any other layer) on one surface of the temporary fixing layer 3. The rewiring layer 4 is formed, for example, by applying and curing a rewiring material on the temporary fixing layer 3. Examples of the rewiring material include an electrically insulating photosensitive resin material. Examples of the resin material include polyimide, polybenzoxazole, phenol novolac, and polyhydroxystyrene. The thickness of the rewiring layer 4 is, for example, approximately 5 μm to 20 μm. By setting the thickness of the rewiring layer 4 to 5 μm or more, defects in the rewiring layer 4 can be suppressed. By setting the thickness of the rewiring layer 4 to 20 μm or less, variations in the thickness of the rewiring layer 4 can be suppressed.

[0036] As shown in FIG. 3(c), the seed layer formation step S05 is a step of forming a seed layer 5 on one side of the redistribution layer 4. The seed layer 5 is a layer used to supply power for growing the plating layer 7 formed in the subsequent plating layer formation step S06. In the example of FIG. 3(c), the redistribution layer 4 on the temporary fixing layer 3 is not patterned, and the seed layer 5 is formed flat on one side of the redistribution layer 4. The seed layer 5 is formed by, for example, sputtering. Examples of materials for forming the seed layer 5 include titanium, copper, tungsten, nickel, and silver. The thickness of the seed layer 5 is, for example, approximately 1 nm to 100 nm. Setting the thickness of the seed layer 5 to 1 nm or more can prevent defects from occurring in the seed layer. Setting the thickness of the seed layer 5 to 100 nm or less can shorten the sputtering processing time and prevent variations in the thickness of the seed layer 5.

[0037] By forming the seed layer 5, a semiconductor device forming laminate L1 is obtained. That is, the semiconductor device forming laminate L1 includes a support 1, a temporary fixing layer 3 provided on one side of the support 1, a rewiring layer 4 provided on one side of the temporary fixing layer 3, and a seed layer 5 provided on one side of the rewiring layer 4. In the example of FIG. 3(c), a metal layer 2 is provided between the support 1 and the temporary fixing layer 3 in the semiconductor device forming laminate L1. In the method for manufacturing a semiconductor device according to this embodiment, the semiconductor device forming laminate L1 may be prepared in advance and the subsequent steps may be carried out.

[0038] The plating layer forming step S06 is a step of forming a plating layer 7 on the seed layer 5. In the plating layer forming step S06, first, as shown in FIG. 4(a), a resist 6 is formed in a predetermined pattern on the seed layer 5. Next, as shown in FIG. 4(b), the plating layer 7 is formed on the seed layer 5 exposed from the resist 6. The plating layer 7 is formed, for example, by electrolytic plating. An example of a material for forming the plating layer 7 is copper. After the plating layer 7 is formed, the resist 6 is removed, as shown in FIG. 4(c).

[0039] After removing the resist 6, the seed layer 5 remaining on the rewiring layer 4 is removed as shown in FIG. 5(a). The seed layer 5 is removed by, for example, etching. After removing the seed layer 5, the next rewiring layer 4 is formed as shown in FIG. 5(b). The next rewiring layer 4 is formed, for example, by applying and curing a rewiring material on the temporary fixing layer 3. Here, the rewiring layer 4 is patterned to expose the plating layer 7 formed in the plating layer forming step S06 from the rewiring layer 4.

[0040] Thereafter, the seed layer formation step S05, the plating layer formation step S06, and the formation of the next rewiring layer 4 are repeatedly performed to form plating layers 7 of a predetermined pattern on the desired number of rewiring layers 4, as shown in Fig. 6. The plating layers 7 of each layer are electrically connected to each other in the stacking direction of the rewiring layers 4, and form wiring portions that connect the semiconductor chip W (see Fig. 7(a)) and the external extraction electrodes (not shown).

[0041] As shown in FIG. 7(a), the mounting step S07 is a step of mounting a semiconductor chip W on the plating layer 7. The semiconductor chip W is formed by cutting a semiconductor wafer to a predetermined size and dividing it into individual chips. The thickness of the semiconductor chip W may be 1 μm to 1000 μm, 10 μm to 500 μm, or 20 μm to 200 μm, from the viewpoint of miniaturizing and thinning the semiconductor device and preventing cracks during transportation and processing. The semiconductor chip W is provided with solder bumps 8. As shown in FIG. 7(a), the mounting of the semiconductor chip W on the plating layer 7 is achieved by joining the solder bumps 8 to the outermost plating layer 7 exposed from the outermost rewiring layer 4.

[0042] The encapsulation step S08 is a step of encapsulating the semiconductor chip W, as shown in FIG. 7(b). In the encapsulation step S08, for example, an encapsulation layer 9 is formed on the outermost rewiring layer 4 so as to cover the semiconductor chip W and the solder bumps 8. There are no particular limitations on the material constituting the encapsulation layer 9, but from the viewpoints of heat resistance and reliability, a thermosetting resin composition may be used. The composition of the encapsulation layer 9 may contain additives such as a filler and a flame retardant.

[0043] The peeling step S09 is a step of peeling the support 1 from the temporary fixing layer 3. In this embodiment, the metal layer 2 provided between the support 1 and the temporary fixing layer 3 is used, and as shown in FIG. 8( a), the metal layer 2 is irradiated with incoherent light P1 to peel the support 1 from the temporary fixing layer 3. A light source that outputs the incoherent light P1 may be, for example, a xenon lamp. In the example of FIG. 8( a), the incoherent light P1 from the light source is irradiated toward the metal layer 2 from the support 1 side. The metal layer 2 is heated by the irradiation of the incoherent light P1, and the temporary fixing layer 3 is heated via the metal layer 2.

[0044] Heating the temporary fixing layer 3 causes the resin component constituting the temporary fixing layer 3 to melt, and as shown in FIG. 8( b), the metal layer 2 is peeled off from the temporary fixing layer 3, thereby easily peeling the support 1 and the metal layer 2 from the temporary fixing layer 3. The irradiation conditions of the incoherent light P1 can be set arbitrarily, and may be conditions that allow the support 1 and the metal layer 2 to be peeled off from the temporary fixing layer 3 with a single irradiation, or conditions that allow the support 1 and the metal layer 2 to be peeled off from the temporary fixing layer 3 with two or more irradiations. From the viewpoint of reducing damage to the rewiring layer 4, the plating layer 7, and the semiconductor chip W, it is preferable that the irradiation conditions of the incoherent light P1 be conditions that allow the support 1 and the metal layer 2 to be peeled off from the temporary fixing layer 3 with a single irradiation.

[0045] The removal step S10 is a step of removing the temporary fixing layer 3 from the rewiring layer 4, as shown in FIG. 8(c). Methods for removing the temporary fixing layer 3 include, for example, dissolving it in a solvent and peeling it off. The method for removing the temporary fixing layer 3 is appropriately selected depending on the constituent material of the temporary fixing layer 3, etc. If the rewiring layer 4 is easily dissolved in a solvent, it is preferable to select a removal method by peeling it off.

[0046] 9(a), the processing step S11 is a step of processing the rewiring layer 4 to expose the plating layer 7. In the processing step S11, holes are drilled in a predetermined pattern in the rewiring layer 4 on the side opposite to the semiconductor chip W, for example, by irradiating it with laser light, thereby exposing the plating layer 7 (seed layer 5) in the rewiring layer.

[0047] 9(b), the ball mounting step S12 is a step of mounting solder balls 10 on the plating layer 7. In the ball mounting step S12, solder balls 10 are bonded to each of the plating layers 7 (seed layers 5) exposed from the rewiring layer 4 on the side opposite the semiconductor chip W by the processing step S11 so as to protrude from the rewiring layer. Through the above steps, a semiconductor device D1 is obtained in which the solder balls 10 are provided directly on the semiconductor chip W via the rewiring layer 4.

[0048] As described above, in this semiconductor device forming laminate L1 and semiconductor device manufacturing method, the temporary fixing layer 3 is formed on one side of the support 1, and the rewiring layer 4 and the seed layer 5 are formed on one side of the temporary fixing layer 3. As a result, after forming the plating layer 7 in a predetermined pattern on the rewiring layer 4 and mounting and sealing the semiconductor chip W, the support 1 can be easily peeled from the rewiring layer 4 at the temporary fixing layer 3. By being able to easily peel the support 1 from the rewiring layer 4, damage to the rewiring layer 4 is suppressed, and the reliability of the manufactured semiconductor device D1 is improved.

[0049] In this embodiment, a metal layer is provided between the support 1 and the temporary fixing layer 3. This allows the support 1 to be easily peeled off from the rewiring layer 4 by irradiating the metal layer 2 with incoherent light P1 and heating the temporary fixing layer 3 via the metal layer 2. Since the support 1 can be easily peeled off from the rewiring layer 4, stress applied to the rewiring layer 4 during peeling can be suppressed, and peeling of the rewiring layers 4, 4 from each other can be prevented. Furthermore, in this embodiment, no seed layer 5 is formed on the temporary fixing layer 3, so it is possible to avoid the seed layer 5 interfering with the removal of the temporary fixing layer 3 from the rewiring layer 4.

[0050] [Second embodiment] 10 is a flowchart showing a method for manufacturing a semiconductor device according to a second embodiment of the present disclosure. As shown in FIG. 10, the method for manufacturing a semiconductor device according to the second embodiment includes a preparation step S21, a metal layer formation step S22, a temporary fixing layer formation step S23, a redistribution layer formation step S24, a seed layer formation step S25, a plating layer formation step S26, a mounting step S27, a sealing step S28, a peeling step S29, a removal step S30, and a ball mounting step S31.

[0051] The method for manufacturing a semiconductor device according to the second embodiment differs from the method for manufacturing a semiconductor device according to the first embodiment in that the redistribution layer is patterned in the redistribution layer formation step S24, and in that no processing step is provided between the removal step S31 and the ball mounting step S32. The preparation step S21 to the temporary fixing layer formation step S23 are the same as the preparation step S01 to the temporary fixing layer formation step S03 of the first embodiment, and therefore their explanation will be omitted (see FIGS. 11(a), 11(b), and 12(a)).

[0052] 12(b), in the rewiring layer forming step S24, the rewiring layer 4 formed on the temporary fixing layer 3 is patterned to expose the temporary fixing layer 3 in a predetermined pattern from the rewiring layer 4. The patterning of the rewiring layer 4 may be performed, for example, by using a photosensitive resin material as the rewiring layer material and photocuring using a resist of a predetermined pattern.

[0053] 12(c), in the seed layer formation step S25, a seed layer 5 is formed on one surface of the patterned redistribution layer 4. The seed layer 5 is formed on one surface of the redistribution layer 4, on the inner surface of the patterned portion, and on one surface of the temporary fixing layer 3 exposed from the redistribution layer 4. By forming the seed layer 5, a semiconductor device forming laminate L2 is obtained, which has a redistribution layer 4 patterned to expose the temporary fixing layer 3. In the method for manufacturing a semiconductor device according to this embodiment, the semiconductor device forming laminate L2 may also be prepared in advance and the subsequent steps may be carried out.

[0054] The plating layer formation step S26 is the same as in the first embodiment. First, as shown in FIG. 13(a), a resist 6 is formed in a predetermined pattern on the seed layer 5 on the rewiring layer 4. Next, as shown in FIG. 13(b), a plating layer 7 is formed on the seed layer 5 exposed from the resist 6. After the plating layer 7 is formed, the resist 6 is removed as shown in FIG. 13(c). After the resist 6 is removed, the seed layer 5 remaining on the rewiring layer 4 is removed as shown in FIG. 14(a). After the seed layer 5 is removed, the next rewiring layer 4 is formed in a predetermined pattern as shown in FIG. 14(b). Thereafter, the seed layer formation step S25, the plating layer formation step S26, and the formation of the next rewiring layer 4 are repeatedly performed, and as shown in FIG. 15, plating layers 7 in a predetermined pattern are formed on the desired number of rewiring layers 4.

[0055] In the mounting process S27, as shown in FIG. 16(a), a semiconductor chip W is mounted on the plating layer 7 using solder bumps 8. Next, in the sealing process S28, the semiconductor chip W is sealed as shown in FIG. 16(b). In the peeling process S29, as in the first embodiment, as shown in FIG. 17(a), incoherent light P1 is irradiated onto the metal layer 2. This causes the support 1 to be peeled off from the temporary fixing layer 3 as shown in FIG. 17(b).

[0056] 17(c), in the removal step S30, the temporary fixing layer 3 is removed from the rewiring layer 4. In this embodiment, in the rewiring layer formation step S24 described above, the rewiring layer 4 is patterned to expose the temporary fixing layer 3. Therefore, when the temporary fixing layer 3 is removed from the rewiring layer 4, the seed layer 5, which is the starting point of the plating layer 7, is exposed in a predetermined pattern from the rewiring layer 4.

[0057] In the ball mounting process, first, as shown in FIG. 18(a), the seed layer 5 exposed from the rewiring layer 4 is removed to expose the plating layer 7. The seed layer 5 is removed by, for example, etching. After the seed layer 5 is removed, as shown in FIG. 18(b), solder balls 10 are mounted on the plating layer 7 exposed from the rewiring layer 4. A semiconductor device D2 is obtained in which the solder balls 10 are provided directly on the semiconductor chip W via the rewiring layer 4.

[0058] In this embodiment, too, a temporary fixing layer 3 is formed on one side of the support 1, and a rewiring layer 4 and a seed layer 5 are formed on one side of the temporary fixing layer 3. As a result, after a plating layer 7 is formed in a predetermined pattern on the rewiring layer 4 and the semiconductor chip W is mounted and sealed, the support 1 can be easily peeled off from the rewiring layer 4 at the temporary fixing layer 3. By being able to easily peel off the support 1 from the rewiring layer 4, damage to the rewiring layer 4 is suppressed, and the reliability of the manufactured semiconductor device D1 is improved.

[0059] In this embodiment, too, a metal layer is provided between the support 1 and the temporary fixing layer 3. This allows the support 1 to be easily peeled off from the rewiring layer 4 by irradiating the metal layer 2 with incoherent light P1 and heating the temporary fixing layer 3 via the metal layer 2. Since the support 1 can be easily peeled off from the rewiring layer 4, stress applied to the rewiring layer 4 during peeling can be suppressed, and peeling of the rewiring layers 4, 4 from each other can be prevented. Note that in this embodiment, a seed layer 5 is formed on part of the temporary fixing layer 3, but the formation region of the seed layer 5 is limited to the region exposed from the rewiring layer 4, so that the seed layer 5 does not interfere with the removal of the temporary fixing layer 3 from the rewiring layer 4.

[0060] In this embodiment, the rewiring layer 4 is patterned to expose the temporary fixing layer 3. This eliminates the need for a processing step to expose the plating layer 7 from the rewiring layer 4 after peeling off the support 1 and removing the temporary fixing layer 3. This also eliminates the need to clean debris generated in the processing step, simplifying the manufacturing process of the semiconductor device D2. [Variations]

[0061] In the above embodiment, the metal layer 2 is provided between the support 1 and the temporary fixing layer 3, but the formation of the metal layer 2 may be omitted. In this case, as shown in FIG. 19(a), the semiconductor device forming laminate L1 obtained by forming the seed layer 5 has a configuration in which the temporary fixing layer 3 is formed directly on one surface of the support 1. When this configuration is adopted, in the peeling step S09, as shown in FIG. 19(b), the temporary fixing layer 3 is irradiated with coherent light P2. An example of a light source that outputs the coherent light P2 is a light source that outputs an ultraviolet laser. The coherent light P2 is scanned in the in-plane direction of the temporary fixing layer 3, and the temporary fixing layer 3 is divided as shown in FIG. 19(c), thereby easily peeling the support 1 from the rewiring layer 4.

[0062] Although not shown, the semiconductor device forming laminate L2 may also omit the formation of the metal layer 2. In this case, in the peeling step S29, the temporary fixing layer 3 can be divided by scanning the coherent light P2 in the in-plane direction of the temporary fixing layer 3, as in FIG. 19(b), and the support 1 can be easily peeled off from the rewiring layer. [Explanation of symbols]

[0063] 1...support, 2...metal layer, 3...temporary fixing layer, 4...rewiring layer, 5...seed layer, 7...plating layer, L1, L2...laminated body for forming semiconductor device, W...semiconductor chip, P1...incoherent light, P2...coherent light.

Claims

1. A support; a temporary fixing layer provided on one surface of the support; a rewiring layer provided on one surface of the temporary fixing layer; a seed layer provided on one surface side of the rewiring layer.

2. The laminate for forming a semiconductor device according to claim 1 , wherein a metal layer is provided between the support and the temporary fixing layer.

3. 2. The laminate for forming a semiconductor device according to claim 1, wherein the temporary fixing layer is provided directly on one surface of the support.

4. 4. The laminate for forming a semiconductor device according to claim 1, wherein the rewiring layer is patterned so as to expose the temporary fixing layer.

5. a preparation step of preparing a support; a temporary fixing layer forming step of forming a temporary fixing layer on one surface side of the support; a rewiring layer forming step of forming a rewiring layer on one surface of the temporary fixing layer; a seed layer forming step of forming a seed layer on one surface of the rewiring layer; a plating layer forming step of forming a plating layer on the seed layer in the rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; an encapsulation step of encapsulating the semiconductor chip; a peeling step of peeling the support from the temporary fixing layer; a removing step of removing the temporary fixing layer from the rewiring layer.

6. a metal layer forming step of forming a metal layer on one surface of the support between the temporary fixing layer forming step and the rewiring layer forming step; The method for manufacturing a semiconductor device according to claim 5 , wherein in the peeling step, the support is peeled off from the temporary fixing layer by irradiating the metal layer with incoherent light.

7. In the temporary fixing layer forming step, the temporary fixing layer is formed directly on one surface of the support, The method for manufacturing a semiconductor device according to claim 5 , wherein the peeling step peels the support from the temporary fixing layer by irradiating the temporary fixing layer with coherent light.

8. 8. The method for manufacturing a semiconductor device according to claim 5, wherein in the rewiring layer forming step, the rewiring layer is patterned so as to expose the temporary fixing layer.

9. A step of preparing a laminate for forming a semiconductor device according to claim 1; a plating layer forming step of forming a plating layer on the seed layer in the rewiring layer; a mounting step of mounting a semiconductor chip on the plating layer; an encapsulation step of encapsulating the semiconductor chip; a peeling step of peeling the support from the temporary fixing layer; a removing step of removing the temporary fixing layer from the rewiring layer.

10. preparing the semiconductor device forming laminate in which a metal layer is provided between the support and the temporary fixing layer; The method for manufacturing a semiconductor device according to claim 9 , wherein in the peeling step, the support is peeled off from the temporary fixing layer by irradiating the metal layer with incoherent light.

11. preparing the semiconductor device forming laminate in which the temporary fixing layer is provided directly on one surface of the support; The method for manufacturing a semiconductor device according to claim 9 , wherein the peeling step peels the support from the temporary fixing layer by irradiating the temporary fixing layer with coherent light.

12. 11. The method for manufacturing a semiconductor device according to claim 9, further comprising the step of preparing the semiconductor device forming laminate, in which the rewiring layer is patterned so as to expose the temporary fixing layer.

Images