Photoelectric conversion device, imaging system, and moving body

Abstract

To provide a photoelectric conversion device that suitably detects the number of periods in which avalanche multiplication has occurred from among a plurality of periods in the standby state for the avalanche multiplication.SOLUTION: A photoelectric conversion device includes a photodiode that performs avalanche multiplication, a generation circuit that generates a control signal, a first control circuit that controls a standby state in which the avalanche multiplication of the photodiode is possible by the control signal and a recharge state in which the photodiode is returned to a state in which the avalanche multiplication is possible again, and a second control circuit that detects whether the avalanche multiplication has occurred in the standby state using the control signal and a signal corresponding to the output of the photodiode, and counts the number of periods in which the avalanche multiplication has occurred from among a plurality of periods in the standby state.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device, an imaging system, and a moving object. [Background technology]

[0002] There is known a photon counting type photoelectric conversion device that digitally counts the number of photons incident on a photoreceptor that performs avalanche multiplication and outputs the count value from the pixel as a digital signal. Patent Document 1 describes a device that detects whether a photon has been incident on a photodiode by detecting a pulse output from an amplifier that receives a signal from the photodiode during a period between periodically repeated reset pulses. This device obtains a count value corresponding to the number of photons incident on the pixel by accumulating the number of times that an incident result is obtained.

[0003] Specifically, in the device described in Patent Document 1, when a reset pulse is input to the reset transistor, the potential of the photodiode is recharged and the device enters a standby state for the next avalanche multiplication. The input of the reset pulse resets the potential of the input section of the count value holding means. When a photon is again incident on the photodiode, the potential of the input section of the count value holding means changes due to avalanche multiplication. In response to this potential change, the count value holding means adds 1 to the count value it holds. In this way, the number of periods in which avalanche multiplication occurred is counted among multiple periods in the standby state for avalanche multiplication. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Publication No. 7-67043 Summary of the Invention [Problem to be solved by the invention]

[0005] For example, when high-intensity light is incident on a photodiode, a photon may be incident on the photodiode at the time the photodiode is recharged or at a time close thereto. In this case, the potential of the input section of the count value holding means remains unchanged, maintaining the state in which a photon has been detected. This means that this period is not counted as a period in which a photon was obtained. Therefore, the actual count value is smaller than the count value corresponding to the brightness of the incident light, resulting in the brightness of the image being lower than the actual brightness.

[0006] The present invention has been made in view of the above-mentioned problems, and provides a photoelectric conversion device that suitably detects the number of periods in which avalanche multiplication occurs among a plurality of periods in a standby state for avalanche multiplication. [Means for solving the problem]

[0007] The present invention has been made in consideration of the above-mentioned problems, and one aspect of the present invention is a photoelectric conversion device comprising: a photodiode that performs avalanche multiplication; a generation circuit that generates a control signal; a first control circuit that controls the photodiode using the control signal to switch between a standby state in which the photodiode is capable of avalanche multiplication and a recharge state in which the photodiode is again capable of avalanche multiplication; and a second control circuit that uses the control signal and a signal corresponding to the output of the photodiode to detect whether avalanche multiplication has occurred during the standby state, and counts the number of periods in which the avalanche multiplication has occurred among multiple periods in the standby state. [Effects of the Invention]

[0008] According to the present invention, it is possible to provide a photoelectric conversion device that can suitably detect the number of periods in which avalanche multiplication occurs among a plurality of periods in a standby state for avalanche multiplication. [Brief explanation of the drawings]

[0009] [Figure 1] Block diagram showing the schematic configuration of a photoelectric conversion device [Figure 2] A diagram showing the schematic configuration of a pixel [Figure 3] FIG. 1 shows an example of a pixel configuration. [Figure 4] Timing diagram showing pixel operation [Figure 5] FIG. 1 shows an example of pixel configuration (comparison example). [Figure 6] Timing diagram showing pixel operation (comparison example) [Figure 7] FIG. 1 shows an example of a pixel configuration. [Figure 8] FIG. 1 shows an example of a pixel configuration. [Figure 9] FIG. 1 shows an example of a pixel configuration. [Figure 10] Timing diagram showing pixel operation [Figure 11] FIG. 1 shows an example of a pixel configuration. [Figure 12] Block diagram showing the schematic configuration of an imaging system [Figure 13] FIG. 1 is a diagram showing an example of the configuration of an imaging system and a moving object; DETAILED DESCRIPTION OF THE INVENTION

[0010] [First embodiment] A photoelectric conversion device and a driving method thereof according to a first embodiment of the present invention will be described with reference to FIGS. 1 to 3. FIG.

[0011] FIG. 1 is a block diagram showing a schematic configuration of a photoelectric conversion device according to this embodiment.

[0012] As shown in FIG. 1, the photoelectric conversion device 100 according to this embodiment includes a pixel region 10, a vertical selection circuit 30, a signal processing circuit 40, a horizontal selection circuit 50, an output circuit 60, and a control circuit .

[0013] The pixel region 10 has a plurality of pixels P arranged in a matrix across multiple rows and columns. Fig. 1 shows 36 pixels P arranged in six rows (row 0) to row 5 and six columns (column 0) to column 5, along with reference symbols indicating the row and column numbers. For example, the pixel P arranged in the first row and fourth column is assigned the reference symbol "P14."

[0014] The number of rows and columns of the pixel array constituting the pixel region 10 is not particularly limited. Furthermore, the pixels P do not necessarily have to be arranged two-dimensionally in the pixel region 10. For example, the pixel region 10 may be composed of a single pixel P, or the pixels P may be arranged one-dimensionally in the row direction or column direction in the pixel region 10.

[0015] A control line PVSEL is arranged in each row of the pixel array of the pixel region 10, extending in a first direction (the horizontal direction in FIG. 1). The control line PVSEL is connected to each of the pixels P arranged in the first direction, and serves as a signal line common to these pixels P. The first direction in which the control line PVSEL extends may be referred to as the row direction or the horizontal direction. Note that in FIG. 1, the control line PVSEL is shown together with a reference symbol indicating the row number. For example, the control line in the first row is designated by the reference symbol "PVSEL[1]."

[0016] The control line PVSEL of each row is connected to a vertical selection circuit 30. The vertical selection circuit 30 is a circuit section that supplies control signals for driving signal generation circuits (not shown) in the pixels P to the pixels P via the control lines PVSEL.

[0017] In each column of the pixel array in the pixel region 10, an output line POUT is arranged, extending in a second direction (vertical direction in FIG. 1) intersecting the first direction. The output line POUT is connected to each of the pixels P aligned in the second direction and serves as a signal line common to these pixels P. The second direction in which the output line POUT extends may be referred to as the column direction or vertical direction. Note that in FIG. 1, the output line POUT is shown together with a symbol indicating the column number. For example, the output line in the fourth column is labeled "POUT4." Each of the output lines POUT has n signal lines for outputting an n-bit digital signal.

[0018] The output line POUT is connected to a signal processing circuit 40. The signal processing circuits 40 are provided corresponding to each column of the pixel array in the pixel region 10, and are connected to the output line POUT of the corresponding column. The signal processing circuit 40 has a function of holding a signal output from the pixel P via the output line POUT of the corresponding column. Since the signal output from the pixel P is an n-bit signal input via n signal lines of the output lines POUT, each of the signal processing circuits 40 has at least n holding units for holding each bit of the signal.

[0019] The horizontal selection circuit 50 is a circuit section that supplies the signal processing circuit 40 with a control signal for reading out a signal from the signal processing circuit 40. The horizontal selection circuit 50 supplies a control signal to the signal processing circuit 40 of each column via a control line PHSEL. Upon receiving the control signal from the horizontal selection circuit 50, the signal processing circuit 40 outputs the signal held in the holding section to the output circuit 60 via a horizontal output line HSIG. Note that in FIG. 1, the control line PHSEL is shown together with a symbol indicating the column number. For example, the control line for the fourth column is assigned the symbol "PHSEL[4]". The horizontal output line HSIG has n signal lines for outputting an n-bit digital signal.

[0020] The output circuit 60 is a circuit section for outputting a signal supplied via the horizontal output line HSIG as an output signal SOUT to the outside of the photoelectric conversion device 100. The control circuit 70 is a circuit section for supplying control signals that control the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60. Note that at least some of the control signals that control the operations and timings of the vertical selection circuit 30, the signal processing circuit 40, the horizontal selection circuit 50, and the output circuit 60 may be supplied from the outside of the photoelectric conversion device 100.

[0021] FIG. 2 is a diagram showing the configuration of a pixel 11 of the photoelectric conversion device of this embodiment.

[0022] Each pixel 11 includes a photodiode PD, a PD control circuit 14 (first control circuit), and a signal control circuit 15 (second control circuit) connected to the photodiode PD. A voltage VPDL is applied to the photodiode PD. A pulse generation circuit 13 (generation circuit) provided outside the pixel 11 is connected to the PD control circuit 14 and the signal control circuit 15. The PD control circuit 14 includes a PMOS transistor. The gate of the PMOS transistor is connected to the pulse generation circuit 13. A voltage VDD is applied to one of the source and drain of the PMOS transistor, and the photodiode PD and the signal control circuit 15 are connected to the other of the source and drain. In this embodiment, the voltage VDD is approximately 3.3 V, and the voltage VPDL is a negative voltage of approximately −20 V. The signal control circuit 15 outputs a signal POUT to the outside of the pixel 11. When the PMOS transistor is turned on, a reverse bias voltage of the voltages VDD and VPDL is applied to the photodiode PD. Since this reverse bias voltage is set to be larger than the breakdown voltage, the photodiode PD operates as a Geiger-mode avalanche photodiode.

[0023] 3 is a diagram showing details of the signal control circuit 15 of the pixel 11 shown in FIG. 2. The signal control circuit 15 has a counter 16 and an AND circuit 17 (logic circuit). The AND circuit 17 receives an inverted signal of the signal Vcath of the node N1 (first node) to which the photodiode PD and the PD control circuit 14 are connected. The signal Vcath is the output of the photodiode PD. The inverted signal of the signal Vcath input to the AND circuit 17 corresponds to the output of the photodiode PD. The AND circuit 17 receives a signal Pctrl, which is a control signal from the pulse generating circuit 13. The AND circuit 17 outputs a signal Sig, which is the logical AND of the inverted signal Vcath and the signal Pctrl, to the counter 16. The signal Sig is a pulse waveform signal.

[0024] The counter 16 counts the number of times the signal Sig output by the AND circuit 17 transitions from a low level to a high level, thereby generating a count signal having a count value corresponding to the incidence of photons on the photodiode PD.

[0025] Fig. 4 is a timing diagram showing the operation of the pixel 11 shown in Fig. 3. The signals shown in Fig. 4 correspond to the signals shown in Fig. 3. The arrows indicate the timing at which photons enter the photodiode PD.

[0026] During the period before time t1, the signal Pctrl is at a high level (3.3 V). Therefore, the PMOS transistor of the PD control circuit 14 is off. Therefore, the node N1 to which the PD control circuit 14, which is the first control circuit, and the photodiode PD are connected is floating. While the signal Vcath is at a high level, the photodiode PD has been recharged. During the period when the signal Vcath is at a high level, the PD control circuit 14 controls the photodiode PD to a standby state in which avalanche multiplication is possible.

[0027] At time t1, a photon is incident on the photodiode PD, which causes avalanche multiplication in the photodiode PD, causing the signal Vcath to transition from a high level (3.3 V) to a low level (0 V).

[0028] At time t2, the inverted signal of signal Vcath exceeds the logic threshold of AND circuit 17. As a result, signal Sig transitions from low level (0 V) to high level (3.3 V). The transition of signal Sig from low level to high level increases the count value of the count signal of counter 16 by 1 LSB.

[0029] At time t3, the pulse generating circuit 13 changes the signal Pctrl to low level. This turns on the PMOS transistor of the PD control circuit 14, and a recharge operation is performed to return the signal Vcath to voltage VDD. During this period, the PD control circuit 14 is in a recharge state, returning the photodiode PD to a state where avalanche multiplication is possible again. However, FIG. 4 shows a case where photons are incident on the photodiode PD during this recharge operation. As a result of avalanche multiplication occurring again during this recharge operation, the signal Vcath does not return to voltage VDD but remains at a value close to 0V.

[0030] At the same time that the signal Pctrl changes to low level, the signal Sig output from the AND circuit 17 also transitions from high level to low level. That is, the potential at the input section of the signal control circuit 15 (second control circuit) is reset to the initial state.

[0031] At time t4, the pulse generating circuit 13 changes the signal Pctrl to high level. This turns off the PMOS transistor of the PD control circuit 14, and the recharge operation of the signal Vcath ends. In the operation shown in FIG. 4, as described above, the recharge operation does not restore the signal Vcath to the voltage VDD, but rather keeps it close to 0V.

[0032] Furthermore, at time t4, the signal Pctrl transitions to high level, causing the signal Sig to also transition from low level to high level. Therefore, the transition of the signal Sig from low level to high level increases the count value of the count signal of the counter 16 by 1 LSB.

[0033] In this embodiment, an AND circuit 17 is provided that takes the logical product of the signal Pctrl output by the pulse generating circuit 13 and a signal obtained by inverting the signal Vcath. Here, a case where the AND circuit 17 is not provided (comparative example) will be described. FIG. 5 shows a comparative example in which the AND circuit 17 is not provided, and instead the signal Vcath is input to an inverter 152. The inverter 152 outputs to the counter 16 a signal Sig whose potential changes to a High level when the voltage of the signal Vcath becomes lower than a threshold value. In other words, the inverter 152 shapes the waveform based on the signal Vcath and outputs the inverted signal Sig to the counter 16.

[0034] Fig. 6 is a diagram showing the operation of the comparative example of Fig. 5. The signals shown in Fig. 6 correspond to those in Fig. 5. The timing of the photon incidence and the signal change of the signal Pctrl is the same as in Fig. 4.

[0035] At time t2, the signal Sig changes to high level. Then, at time t3, the signal Pctrl changes to low level. However, avalanche multiplication occurs due to incident photons between times t3 and t4. Therefore, the signal Vcath does not return to the voltage VDD by the recharge operation and remains at a value close to 0V.

[0036] As a result, in the circuit of the comparative example, even if the signal Pctrl changes to low level at time t3, the signal Sig remains high level after time t3.

[0037] As a result, neither the waiting period for avalanche multiplication from time t4 to t5 nor the waiting period for avalanche multiplication from time t6 onwards is counted as a period in which avalanche multiplication has occurred, and the count value remains at n+1.

[0038] On the other hand, the pixel 11 of this embodiment has a signal control circuit 15 to which a control signal Pctrl of the pulse generation circuit 13 is input. This makes it possible to suitably detect whether or not avalanche multiplication has occurred while the photodiode PD is in a standby state for avalanche multiplication. This makes it possible to suitably detect whether or not avalanche multiplication has occurred while the photodiode PD is in a standby state for avalanche multiplication, even when high-intensity light is incident.

[0039] In this embodiment, as shown in FIG. 1, the configuration has been described in which all of the components of the pixel 11 are provided on one semiconductor substrate. However, the present invention is not limited to this example, and the photodiode PD may be provided on a first semiconductor substrate, and the signal control circuit 15 may be provided on a second semiconductor substrate. A stacked sensor may also be formed by stacking the first and second semiconductor substrates. The pulse generation circuit 13 and the PD control circuit 14 may be provided on either the first or second semiconductor substrate.

[0040] In another example, the photodiode PD is provided on a first semiconductor substrate, and the pulse generating circuit 13, the PD control circuit 14, and the signal control circuit 15 are provided on a second semiconductor substrate. In this case, the photodiode PD on the first semiconductor substrate and the PD control circuit 14 on the second semiconductor substrate are connected via a node N1, which is a first node. Furthermore, the photodiode PD on the first semiconductor substrate and the signal control circuit 15 on the second semiconductor substrate are connected via a second node.

[0041] It should be noted that this embodiment is not limited to the configuration shown in Fig. 3. For example, as shown in Fig. 7, a level shift circuit 21 may be provided between the photodiode PD and the node N1. The level shift circuit 21 has a PMOS transistor 25 to whose gate a ground voltage is input. The PMOS transistor 25 is in an ON state when the ground voltage is input to its gate. The output of the level shift circuit 21 is connected to the PD control circuit 14 and the signal control circuit 15.

[0042] By providing the level shift circuit 21, the amplitude of the signal Vcath can be reduced compared to the configuration of FIG. 3, even when the reverse bias voltage of the photodiode PD is the same as that of the configuration of FIG. 3. This ensures a sufficient voltage tolerance at the input of the AND circuit 17. An excess voltage greater than the breakdown voltage may be applied to the avalanche photodiode. This excess voltage must be biased to a voltage at which all photodiodes PD can operate in Geiger mode, taking into account variations in breakdown voltage among pixels 11. Furthermore, since the excess voltage corresponds to the amplitude of the signal Vcath during avalanche multiplication and the subsequent recharge operation, it must be a voltage with an amplitude greater than the logic threshold as the input voltage to the signal control circuit 15. By providing the level shift circuit 21, a sufficient excess voltage can be applied to the photodiode PD even when the power supply voltage VDD is smaller than that of the configuration of FIG. 3. In the configuration of FIG. 7, the power supply voltage VDD can also be the same as that of the AND circuit 17. In this case, the power supply voltage VDD and the power supply voltage for the AND circuit 17 can be generated by a common power supply voltage generation circuit, thereby reducing the circuit area of ​​the power supply voltage generation circuit. Note that in the configuration of Figure 3, the power supply voltage VDD and the power supply voltage for the AND circuit 17 may be made different from each other.

[0043] In this embodiment, the timing at which the PD control circuit 14 transitions from the standby state to the recharge state and the timing at which the potential at the input terminal of the counter 16 is reset to the initial state are simultaneous. However, this embodiment is not limited to this example. For example, the potential at the input terminal of the counter 16 may be reset to the initial state after a predetermined delay (e.g., several clock pulse periods) from the timing at which the PD control circuit 14 transitions from the standby state to the recharge state.

[0044] [Second embodiment] The photoelectric conversion device of this embodiment will be described, focusing on the differences from the first embodiment.

[0045] The photoelectric conversion device of this embodiment differs from that of the first embodiment in the configuration of the signal control circuit 15 of the pixel 11.

[0046] FIG. 8 is a diagram showing the configuration of a pixel 11 of this embodiment.

[0047] The signal control circuit 15 of the pixel 11 of this embodiment has a selection circuit 171. A signal Vcath and a power supply voltage VDD are input to the selection circuit 171. The selection circuit 171 is also connected to the pulse generation circuit 13, and receives a signal Pctrl, which is a control signal, as input.

[0048] The selection circuit 171 is a logic circuit that selects one of the signal Vcath and the power supply voltage VDD based on the signal level of the signal Pctrl. The selection circuit 171 then outputs the inverted signal of the selected signal to the counter 16 as the signal Sig.

[0049] When the signal Pctrl is at a high level (avalanche multiplication standby state), the selection circuit 171 selects the signal Vcath and outputs the inverted signal Vcath to the counter 16.

[0050] On the other hand, when the signal Pctrl is at a low level (recharge state), the selection circuit 171 selects the power supply voltage VDD and outputs an inverted signal of the power supply voltage VDD (i.e., a signal at the ground voltage level) to the counter 16.

[0051] The selection circuit 171 typically includes a waveform shaping circuit. That is, when the signal Pctrl is at a low level, the waveform shaping circuit of the selection circuit 171 keeps the signal Sig at a low level until the signal Vcath falls below a predetermined voltage. Then, when the signal Vcath falls below the predetermined voltage, the waveform shaping circuit of the selection circuit 171 sets the signal Sig to a high level.

[0052] The operation of the pixel 11 of this embodiment can be the same as that of Fig. 4. As a result, this embodiment can also achieve the same effects as the photoelectric conversion device of the first embodiment.

[0053] In this embodiment, the level shift circuit 21 shown in FIG. 7 may also be provided.

[0054] [Third embodiment] The photoelectric conversion device of this embodiment will be described, focusing on the differences from the first embodiment.

[0055] The pixel 11 of the photoelectric conversion device of this embodiment differs from the first embodiment in the configurations of the PD control circuit 14 and the signal control circuit 15. Furthermore, the pulse generation circuit 13 outputs signals Pctrl_1 and Pctrl_2 which are a plurality of control signals.

[0056] 9 is a diagram showing the configuration of the pixel 11 of this embodiment. The PD control circuit 14 includes a PMOS transistor 141 and a PMOS transistor 142.

[0057] The pulse generation circuit 13 outputs a signal Pctrl_1 to the gate of the PMOS transistor 141. The pulse generation circuit 13 also outputs a signal Pctrl_2 to the gate of the PMOS transistor 142.

[0058] The signal control circuit 15 has an OR circuit 173 and an AND circuit 175. The input section of the OR circuit 173 is connected to the pulse generating circuit 13, and receives the signals Pctrl_1 and Pctrl_2. The OR circuit 173 outputs the logical sum of the signals Pctrl_1 and Pctrl_2 to the AND circuit 175.

[0059] An input section of the AND circuit 175 is connected to the node N1 and the OR circuit 173, and receives an inverted signal of the signal Vcath and the output of the OR circuit 173. The AND circuit 175 outputs the logical product of the inverted signal of the signal Vcath and the output of the OR circuit 173 to the counter 16 as a signal Sig.

[0060] Fig. 10 is a diagram showing the operation of the pixel 11 shown in Fig. 9. The signals shown in Fig. 10 correspond to the signals shown in Fig. 9.

[0061] The signals Pctrl_1 and Pctrl_2 have the same period, and are signals with different phases.

[0062] Recharge is possible only during the period when signals Pctrl_1 and Pctrl_2 are both at a low level. Therefore, even if the low-level periods of signals Pctrl_1 and Pctrl_2 are long compared to signal Pctrl in FIG. 6, a similar recharge period can be achieved by utilizing the phase difference. As a result, compared to the case of driving with a single signal Pctrl as in FIG. 6, the influence of fluctuations in the recharge period due to waveform rounding in the signal transmission path can be reduced. In this embodiment, the standby state and recharge state of avalanche multiplication can be controlled by multiple control signals, signals Pctrl_1 and Pctrl_2. Then, by inputting multiple control signals, signals Pctrl_1 and Pctrl_2, to the signal control circuit 15, signal Sig transitions from a high level to a low level during the recharge state. This makes it possible to suitably detect whether avalanche multiplication has occurred during the standby state for the next avalanche multiplication.

[0063] In this way, the photoelectric conversion device of this embodiment can also achieve the same effects as the first embodiment.

[0064] The concept of this embodiment can be combined with other embodiments. For example, the PD control circuit 14 of the pixel 11 of FIG. 8 described in the second embodiment can have the same configuration as this embodiment. In this case, signals Pctrl_1 and Pctrl_2, which are the multiple control signals of this embodiment, are input to the selection circuit 171 instead of the signal Pctrl of FIG. 8. Then, the selection circuit 171 selects either the power supply voltage VDD or the signal Vcath based on the signals Pctrl_1 and Pctrl_2.

[0065] [Fourth embodiment] The photoelectric conversion device of this embodiment will be described, focusing on the differences from the first embodiment.

[0066] The pixel 11 of the photoelectric conversion device of this embodiment differs from the first embodiment in the configuration of the PD control circuit 14.

[0067] FIG. 11 shows the configuration of a pixel 11 according to this embodiment. The PD control circuit 14 includes a PMOS transistor 141 and a PMOS transistor 142. A constant voltage VG is applied to the gate of the PMOS transistor 141, and the PMOS transistor 141 functions as a resistor. This configuration allows the gate area of ​​the PMOS transistor 142 to be smaller than that of a single PMOS transistor, as in the configuration of FIG. 5, thereby reducing the gate capacitance of the signal Pctrl. As a result, the effects of waveform rounding of the signal Pctrl can be suppressed. Furthermore, it is preferable that the parasitic capacitance of the PMOS transistor 142 with respect to node N1 be smaller than the parasitic capacitance of the PMOS transistor with respect to node N1 in FIG. 5, since this reduces the amount of charge consumed during avalanche amplification.

[0068] [Fifth embodiment] An imaging system according to a fifth embodiment of the present invention will be described with reference to Fig. 12. Fig. 12 is a block diagram showing a schematic configuration of the imaging system according to this embodiment.

[0069] The photoelectric conversion device 100 described in the first to fourth embodiments can be applied to various imaging systems. Examples of applicable imaging systems include digital still cameras, digital camcorders, surveillance cameras, copiers, fax machines, mobile phones, vehicle-mounted cameras, and observation satellites. Camera modules equipped with an optical system such as a lens and an imaging device are also included in imaging systems. Fig. 12 illustrates a block diagram of a digital still camera as an example of such systems.

[0070] 12 includes an imaging device 201, a lens 202 that forms an optical image of a subject on the imaging device 201, an aperture 204 that adjusts the amount of light passing through the lens 202, and a barrier 206 that protects the lens 202. The lens 202 and the aperture 204 form an optical system that focuses light on the imaging device 201. The imaging device 201 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments, and converts the optical image formed by the lens 202 into image data.

[0071] The imaging system 200 also has a signal processing unit 208 that processes an output signal output from the imaging device 201. The signal processing unit 208 performs AD conversion to convert an analog signal output from the imaging device 201 into a digital signal. The signal processing unit 208 also performs various corrections and compressions as necessary to output image data. An AD conversion unit, which is part of the signal processing unit 208, may be formed on the semiconductor substrate on which the imaging device 201 is provided, or may be formed on a semiconductor substrate separate from the imaging device 201. The imaging device 201 and the signal processing unit 208 may also be formed on the same semiconductor substrate.

[0072] The imaging system 200 further includes a memory unit 210 for temporarily storing image data, and an external interface unit (external I / F unit) 212 for communicating with an external computer or the like. The imaging system 200 also includes a recording medium 214 such as a semiconductor memory for recording or reading out imaging data, and a recording medium control interface unit (recording medium control I / F unit) 216 for recording or reading out data from the recording medium 214. The recording medium 214 may be built into the imaging system 200 or may be removable.

[0073] The imaging system 200 further includes an overall control / calculation unit 218 that performs various calculations and controls the entire digital still camera, and a timing generation unit 220 that outputs various timing signals to the imaging device 201 and the signal processing unit 208. Here, timing signals and the like may be input from an external source, and the imaging system 200 only needs to include at least the imaging device 201 and the signal processing unit 208 that processes the output signal output from the imaging device 201.

[0074] The imaging device 201 outputs an imaging signal to the signal processing unit 208. The signal processing unit 208 performs predetermined signal processing on the imaging signal output from the imaging device 201 and outputs image data. The signal processing unit 208 generates an image using the imaging signal.

[0075] As described above, according to this embodiment, it is possible to realize an imaging system to which the photoelectric conversion device 100 according to the first to fourth embodiments is applied.

[0076] [Sixth embodiment] An imaging system and a moving object according to a sixth embodiment of the present invention will be described with reference to Fig. 13. Fig. 13 is a diagram showing the configuration of the imaging system and the moving object according to this embodiment.

[0077] FIG. 13A shows an example of an imaging system related to an in-vehicle camera. The imaging system 300 includes an imaging device 310. The imaging device 310 is the photoelectric conversion device 100 described in any one of the first to fourth embodiments. The imaging system 300 includes an image processing unit 312 that performs image processing on multiple pieces of image data acquired by the imaging device 310, and a parallax acquisition unit 314 that calculates parallax (phase difference between parallax images) from the multiple pieces of image data acquired by the imaging system 300. The imaging system 300 also includes a distance acquisition unit 316 that calculates the distance to an object based on the calculated parallax, and a collision determination unit 318 that determines whether or not there is a possibility of a collision based on the calculated distance. Here, the parallax acquisition unit 314 and the distance acquisition unit 316 are examples of distance information acquisition means that acquire information about the distance to the object. That is, the distance information is information about the parallax, the defocus amount, the distance to the object, etc. The collision determination unit 318 may determine the possibility of a collision using any of this distance information. The distance information acquisition means may be realized by dedicated hardware, a software module, a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a combination thereof.

[0078] The imaging system 300 is connected to a vehicle information acquisition device 320 and can acquire vehicle information such as vehicle speed, yaw rate, and steering angle. The imaging system 300 is also connected to a control ECU 330, which is a control device that outputs a control signal to generate a braking force on the vehicle based on the determination result of a collision determination unit 318. The imaging system 300 is also connected to an alarm device 340 that issues an alarm to the driver based on the determination result of the collision determination unit 318. For example, if the determination result of the collision determination unit 318 indicates a high possibility of a collision, the control ECU 330 performs vehicle control to avoid the collision and mitigate damage by applying the brakes, releasing the accelerator, suppressing engine output, etc. The alarm device 340 warns the user by sounding an alarm, displaying alarm information on a screen of a car navigation system, etc., or vibrating the seat belt or steering wheel.

[0079] In this embodiment, the surroundings of the vehicle, for example, the front or rear, are imaged by the imaging system 300. Fig. 13(b) shows an imaging system for imaging the area in front of the vehicle (imaging range 350). The vehicle information acquisition device 320 sends instructions to the imaging system 300 or the imaging device 310. This configuration can further improve the accuracy of distance measurement.

[0080] Although the above describes an example of control to prevent collision with other vehicles, the system can also be applied to control of automatic driving by following other vehicles, control of automatic driving to prevent deviation from a lane, etc. Furthermore, the imaging system is not limited to vehicles such as the subject vehicle, but can be applied to moving bodies (moving devices) such as ships, aircraft, and industrial robots. In addition, the imaging system can be applied not only to moving bodies but also to a wide range of devices that use object recognition, such as intelligent transport systems (ITS).

[0081] [Modified embodiment] The present invention is not limited to the above-described embodiment, and various modifications are possible.

[0082] For example, an example in which part of the configuration of any one of the embodiments is added to another embodiment, or an example in which part of the configuration of another embodiment is substituted therefor, is also an embodiment of the present invention.

[0083] Furthermore, the imaging systems shown in the fifth and sixth embodiments above are examples of imaging systems to which the photoelectric conversion device of the present invention can be applied, and imaging systems to which the photoelectric conversion device of the present invention can be applied are not limited to the configurations shown in Figures 12 and 13.

[0084] It should be noted that the above-described embodiments are merely examples of specific embodiments for carrying out the present invention, and the technical scope of the present invention should not be construed as being limited by these embodiments. In other words, the present invention can be carried out in various forms without departing from its technical concept or main features. [Explanation of symbols]

[0085] 11 pixels 13 Pulse generation circuit (generation circuit) 14 PD control circuit (first control circuit) 15 Signal control circuit (second control circuit) 16 Counters

Claims

1. a photodiode that performs avalanche multiplication; a transistor connected to the photodiode and having a gate to which a control signal is input; a logic circuit that receives a pulse signal and a signal based on the output of the photodiode and outputs a signal according to a result of a logical operation between the pulse signal and the signal based on the output of the photodiode; A photoelectric conversion device characterized by:

2. a signal based on the output of the photodiode transitions from a first level to a second level in response to a photon incident on the photodiode; The photoelectric conversion device according to claim 1, characterized in that when the signal based on the output of the photodiode is at the second level, the level of the signal corresponding to the logical operation result transitions in response to the switching of the pulse signal from the third level to the fourth level.

3. a photodiode that performs avalanche multiplication; a transistor connected to the photodiode and having a gate to which a control signal is input; a logic circuit that receives a pulse signal and a signal based on the output of the photodiode and outputs a signal according to a result of a logical operation between the pulse signal and the signal based on the output of the photodiode, a signal based on the output of the photodiode transitions from a first level to a second level in response to a photon incident on the photodiode; A photoelectric conversion device characterized in that, when a signal based on the output of the photodiode is at the second level, the level of the signal corresponding to the logical operation result transitions in response to switching of the pulse signal from the third level to the fourth level.

4. 4. The photoelectric conversion device according to claim 3, wherein the transistor is in an off state when the control signal is at a fifth level, and in an on state when the control signal is at a sixth level.

5. a photodiode that performs avalanche multiplication; a transistor connected to the photodiode and having a gate to which a control signal is input; a logic circuit that receives a pulse signal and a signal based on the output of the photodiode and outputs a signal according to a result of a logical operation between the pulse signal and the signal based on the output of the photodiode, The photoelectric conversion device is characterized in that the control signal is a pulse signal that is periodically input during a period when the photodiode can cause avalanche multiplication.

6. 6. The photoelectric conversion device according to claim 1, wherein the control signal is a clock signal.

7. 7. The photoelectric conversion device according to claim 1, wherein the pulse signal is a clock signal.

8. 8. The photoelectric conversion device according to claim 1, further comprising a counter that counts the number of pulses of a signal corresponding to the logical operation result output from the logic circuit.

9. 9. The photoelectric conversion device according to claim 8, wherein the control signal is a signal whose level changes periodically during a period from when the count value of the counter is reset until when the count value is next reset.

10. 10. The photoelectric conversion device according to claim 8, wherein the pulse signal is a signal whose level changes periodically during a period from when the count value of the counter is reset until when the count value is next reset.

11. 11. The photoelectric conversion device according to claim 1, wherein the logic circuit is an AND circuit.

12. The photoelectric conversion device according to any one of claims 1 to 10, characterized in that the logic circuit is a selection circuit that selects and outputs either a signal of a predetermined level or a signal based on the output of the photodiode depending on the level of the pulse signal.

13. 13. The photoelectric conversion device according to claim 1, further comprising a second transistor having an input connected to the photodiode and an output connected to the logic circuit.

14. 13. The photoelectric conversion device according to claim 1, further comprising a level shift circuit that shifts the level of a signal output from the photodiode and outputs the signal to the logic circuit.

15. a first substrate on which the photodiode is disposed; a second substrate on which the logic circuit is arranged, 15. The photoelectric conversion device according to claim 1, wherein the first substrate and the second substrate are stacked.

16. 16. The photoelectric conversion device according to claim 15, wherein the transistor is disposed on the second substrate.

17. a third transistor connected to the transistor, the third transistor receiving a second control signal at its gate, the second control signal being out of phase with the control signal; A photoelectric conversion device according to any one of claims 1 to 16, characterized in that it has a second logic circuit to which the control signal and the second control signal are input and which outputs a signal to the logic circuit according to the result of a logical operation of the control signal and the second control signal.

18. 17. The photoelectric conversion device according to claim 1, further comprising a fourth transistor having a gate to which a bias voltage is input and connected to the transistor and a node to which a power supply voltage is applied.

19. 19. The photoelectric conversion device according to claim 1, further comprising a pulse generating circuit that generates the control signal and the pulse signal.

20. The photoelectric conversion device according to any one of claims 1 to 19, a signal processing unit that processes a signal output from the photoelectric conversion device; An imaging system comprising:

21. A mobile object, The photoelectric conversion device according to any one of claims 1 to 19, a distance information acquisition means for acquiring distance information to an object based on a signal from the photoelectric conversion device; a control means for controlling the moving object based on the distance information; A moving object characterized by having:

22. A method for controlling a photoelectric conversion device having a photodiode that performs avalanche multiplication, comprising: A control signal is input to a gate of a transistor connected to the photodiode; A control method comprising: outputting a logical operation result between a signal based on the output of the photodiode and a pulse signal; and counting the number of pulses of the signal corresponding to the output logical operation result.

23. a signal based on the output of the photodiode transitions from a first level to a second level in response to a photon incident on the photodiode; 23. The control method according to claim 22, wherein when the signal based on the output of the photodiode is at the second level, the level of the logical operation result transitions in response to the switching of the pulse signal from the third level to the fourth level.

24. 24. The control method of claim 23, wherein the transistor is in an off state when the control signal is at a fifth level and in an on state when the control signal is at a sixth level.

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