Semiconductor device

Abstract

To reduce a circuit area.SOLUTION: A memory device comprises a memory cell for storing data as stored data, an output signal line, and wiring to which voltage is applied. The memory cell includes a comparison circuit performing a comparison operation between the stored data and search data and taking a conduction state or a non-conduction state in accordance with the operation result, and a field-effect transistor controlling writing and holding of the stored data. Voltage of the output signal line is equal to the voltage of the wiring when the comparison circuit is in the conduction state.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] One aspect of the present invention relates to a storage device. [Background technology]

[0002] In recent years, development of data rewritable storage devices has progressed.

[0003] The storage device may be, for example, an associative memory.

[0004] Associative memory is not just a method of rewriting data, but also a method of storing search data in memory cells. It is a storage device that can determine what kind of data is stored in it. .

[0005] The associative memory is used, for example, as a set associative cache memory. The set associative method is a data storage structure that consists of multiple tags. Associative memory is used as the tag. By using associative memory for the cache memory, This allows faster data communication between the CPU and cache memory.

[0006] Furthermore, a memory cell in an associative memory is, for example, a storage circuit for storing data. It is configured using a plurality of comparison circuits that compare the data stored in the memory with specific data (for example, See, for example, Patent Document 1).

[0007] In Patent Document 1, a magnitude comparison circuit and a match detection circuit are used to decode multi-bit data. It is possible to distinguish between different data. [Prior art documents] [Patent documents]

[0008] [Patent Document 1] Japanese Patent Application Laid-Open No. 2004-295967 Summary of the Invention [Problem to be solved by the invention]

[0009] Conventional associative memories have a problem in that the circuit area of ​​each memory cell is large. For example, in the associative memory shown in Patent Document 1, the number of transistors in each memory cell is 11. The circuit area is large.

[0010] In addition, in conventional associative memories, the leakage current of transistors in the off state causes the retention There was a problem that the data stored in the memory cell fluctuated in the state. For example, in the associative memory shown in Patent Document 1, when the supply of power is stopped, the lead of the transistor Therefore, the power supply should be turned off while the data is being held. It must be supplied continuously, resulting in high power consumption.

[0011] In one aspect of the present invention, the circuit area is reduced and the memory cell in the holding state is written One or more of the objectives is to suppress fluctuations in stored data. [Means for solving the problem]

[0012] In one aspect of the present invention, a comparison circuit for comparing data stored in a memory cell with search data is provided. The memory cell is configured by using a control transistor that controls the setting of the data stored in the memory cell. By configuring the memory cell, the number of transistors in the memory cell can be reduced, reducing the circuit area. Plan for small things.

[0013] In one embodiment of the present invention, the control transistor may be a transistor having a wide gate insulating film such as an oxide semiconductor. By using a field effect transistor including a channel forming layer using a gate semiconductor, The leakage current of the control transistor in the off state is reduced, and the control transistor is turned off. The purpose is to suppress fluctuations in the data stored in the memory cells when By suppressing data fluctuations, for example, it is possible to supply power while retaining data in memory cells. Since the supply can be stopped as needed, power consumption can also be reduced.

[0014] One embodiment of the present invention is a memory cell that stores data as memory data, an output signal line, and an electric current. and a wiring to which a voltage is applied, and the memory cell performs a comparison operation between stored data and search data. When the value of the stored data is smaller than the value of the search data, the state is conductive, and the stored data When the value of the stored data matches the search data, or when the value of the stored data is greater than the search data, A comparison circuit that becomes non-conductive when the voltage is low and a field effect transistor that controls the writing and retention of stored data. and a transistor, and when the comparison circuit is in a conductive state, the voltage value of the output signal line is equal to the voltage of the wiring. It is a storage device that has a value equivalent to

[0015] One embodiment of the present invention is a memory cell that stores data as memory data, an output signal line, and an electric current. and a wiring to which a voltage is applied, and the memory cell performs a comparison operation between stored data and search data. When the value of the stored data is greater than the value of the search data, the state is conductive. When the value of the stored data matches the search data, or when the value of the stored data is smaller than the search data, A comparison circuit that becomes non-conductive when the voltage is low and a field effect transistor that controls the writing and retention of stored data. and a transistor, and when the comparison circuit is in a conductive state, the voltage value of the output signal line is equal to the voltage of the wiring. It is a storage device that has a value equivalent to

[0016] Furthermore, one aspect of the present invention is a memory array of N stages each storing one bit of data as storage data. (N is a natural number of 2 or more) memory cells, a first output signal line, a second output signal line, and a a voltage supply line and first to (N-1)th connection wirings, and each of the N stages of memory cells A first comparison operation is performed between 1 bit of stored data and 1 bit of search data, and 1 bit of stored data is When the data value is smaller than the value of the 1-bit search data, it becomes conductive. When the value of the stored data matches the search data of 1 bit, or the value of the stored data of 1 bit a first comparison circuit that is turned off when the value of the first comparison circuit is greater than the value of the 1-bit search data; A second comparison operation is performed between the 1-bit stored data and the 1-bit search data, and the 1-bit stored data is When the value of the data is smaller than the value of the 1-bit search data, or when the value of the 1-bit stored data is When the value of the 1-bit search data matches the value of the 1-bit stored data, a second comparison circuit that is non-conductive when its value is greater than the value of the one-bit search data; a field effect transistor that controls writing and holding of one bit of storage data; The first comparison circuit of the first stage memory cell is turned on or off to determine whether the current is a first-stage memory cell having a function of controlling an electrical connection between the voltage supply line and the first output signal line; The second comparison circuit is in a conductive state or a non-conductive state to determine whether the voltage supply line is in a first connection or a second connection. It has the function of controlling the electrical connection with the interconnect wiring, and is the Kth stage (K is a natural number between 2 and N-1). The first comparison circuit of the memory cell is turned on or off to determine whether the K-1 and a function of controlling the electrical connection between the connection wiring and the first output signal line. The second comparison circuit of the K-1st connecting wire is turned on or off by the conduction or non-conduction state. and a Kth connection wiring, and a first ratio of the Nth stage memory cell The comparison circuit is in a conductive state or a non-conductive state, thereby The second comparison circuit of the Nth stage memory cell has a function of controlling an electrical connection with the signal line, By being in a conductive state or a non-conductive state, the N-1th connection wiring and the second output signal line It is a memory device that has the function of controlling electrical connections.

[0017] Furthermore, one aspect of the present invention is a memory array of N stages each storing one bit of data as storage data. (N is a natural number of 2 or more) memory cells, a first output signal line, a second output signal line, and a a voltage supply line and first to (N-1)th connection wirings, and each of the N stages of memory cells A first comparison operation is performed between 1 bit of stored data and 1 bit of search data, and 1 bit of stored data is When the data value is greater than the value of the 1-bit search data, it becomes conductive. When the value of the stored data matches the search data of 1 bit, or the value of the stored data of 1 bit a first comparison circuit that is turned off when the value of the first comparison circuit is smaller than the value of the 1-bit search data; A second comparison operation is performed between the 1-bit stored data and the 1-bit search data, and the 1-bit stored data is When the value of the data is greater than the value of the 1-bit search data, or when the value of the 1-bit stored data is When the value of the 1-bit search data matches the value of the 1-bit stored data, a second comparison circuit that is non-conductive when its value is smaller than the value of the one-bit search data; a field effect transistor that controls writing and holding of one bit of storage data; The first comparison circuit of the first stage memory cell is turned on or off to determine whether the current is a first-stage memory cell having a function of controlling an electrical connection between the voltage supply line and the first output signal line; The second comparison circuit is in a conductive state or a non-conductive state to determine whether the voltage supply line is in a first connection or a second connection. It has the function of controlling the electrical connection with the interconnect wiring, and is the Kth stage (K is a natural number between 2 and N-1). The first comparison circuit of the memory cell is turned on or off to determine whether the K-1 and a function of controlling the electrical connection between the connection wiring and the first output signal line. The second comparison circuit of the K-1st connecting wire is turned on or off by the conduction or non-conduction state. and a Kth connection wiring, and a first ratio of the Nth stage memory cell The comparison circuit is in a conductive state or a non-conductive state, thereby The second comparison circuit of the Nth stage memory cell has a function of controlling an electrical connection with the signal line, By being in a conductive state or a non-conductive state, the N-1th connection wiring and the second output signal line It is a memory device that has the function of controlling electrical connections.

[0018] In one embodiment of the present invention, a field effect transistor is formed by using an oxide semiconductor in which a channel is formed. It may also be configured to include a body layer. [Effects of the Invention]

[0019] According to one embodiment of the present invention, the number of transistors in a memory cell is reduced, thereby reducing the circuit area. Furthermore, according to one embodiment of the present invention, when the control transistor is in an off state, When this happens, fluctuations in the data stored in the memory cells can be suppressed. [Brief explanation of the drawings]

[0020] [Figure 1] 1A and 1B are diagrams illustrating examples of storage devices. [Figure 2] 1A and 1B are diagrams illustrating examples of storage devices. [Figure 3] 1A and 1B are diagrams illustrating examples of storage devices. [Figure 4] 1A and 1B are diagrams illustrating examples of storage devices. [Figure 5] 1A and 1B are schematic cross-sectional views illustrating examples of the structure of a transistor. [Figure 6] 1A to 1C are schematic cross-sectional views illustrating an example of a method for manufacturing a transistor. [Figure 7] 1A and 1B illustrate an example of the structure of a memory device. [Figure 8] FIG. 1 is a diagram illustrating an example of a processing unit. [Figure 9] 1A to 1C are diagrams illustrating examples of electronic devices. [Figure 10] 1A and 1B are diagrams illustrating the crystal structure of an oxide material. [Figure 11] 1A and 1B are diagrams illustrating the crystal structure of an oxide material. [Figure 12] 1A and 1B are diagrams illustrating the crystal structure of an oxide material. [Figure 13] FIG. 10 is a graph illustrating the gate voltage dependence of mobility obtained by calculation. [Figure 14] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 15] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 16] FIG. 10 is a graph illustrating the gate voltage dependence of drain current and mobility obtained by calculation. [Figure 17] 1A and 1B are diagrams illustrating cross-sectional structures of transistors used in calculations. [Figure 18] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 19] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 20] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 21] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 22] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 23] FIG. 1 shows an XRD spectrum of an oxide material. [Figure 24] FIG. 10 is a diagram showing characteristics of a transistor. [Figure 25] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; [Figure 26] 1A and 1B are a cross-sectional view and a plan view of a semiconductor device; DETAILED DESCRIPTION OF THE INVENTION

[0021] An example of an embodiment for explaining the present invention will be described below with reference to the drawings. The contents of the embodiments may be changed without departing from the spirit and scope of the present invention. It is easy for a person skilled in the art to understand the present invention. Therefore, the present invention is not limited to the description of the following embodiments. It will not be done.

[0022] The contents of each embodiment can be combined with each other as appropriate. The contents of the

[0023] In addition, ordinal numbers such as 1st and 2nd are used to avoid confusion between components. The number of is not limited to the number of ordinal numbers.

[0024] (Embodiment 1) In this embodiment, an example of a storage device capable of determining stored data will be described.

[0025] The memory device according to the present embodiment includes a memory cell and an output signal line. The rule is based on a comparison between stored data (also called stored data) and search data. The memory cell array has a function of determining the data stored therein. The number of memory cells may be multiple. The stored data and search data may be: The output signal line can be used for comparison in the memory cell. This is a wiring to which a voltage value is set according to a calculation. The voltage of the output signal line is the output signal.

[0026] Further, an example of a memory cell will be described with reference to FIGS.

[0027] As shown in FIG. 1 and FIG. 2A, the memory cell includes a comparator circuit 101 (also referred to as Comp1). ), a comparison circuit 102 (also referred to as Comp2), and a transistor 131. The comparison circuit 102 is not necessarily provided. For example, if the storage device has a plurality of memory cells, In this case, a comparison circuit 102 is provided to discriminate data of multiple bits. In this case, the comparison circuit 102 can be configured as shown in FIG. The conduction state between the memory cell indicated by the bit line and other memory cells is controlled.

[0028] As the transistor, for example, a field effect transistor can be used.

[0029] The comparison circuit 101 compares the stored data (also called data Dm) stored in the memory cell with the search data. A first comparison operation is performed using the data (also called data Dsch), and an output is generated according to the operation result. It has a function to control whether or not to change the voltage value of the output signal line OUT. For example, 101 indicates the voltage of the output signal line OUT when the value of the data Dm is smaller than the value of the data Dsch. Function to change the pressure value, or output when the value of data Dm is greater than the value of data Dsch It has the function of changing the voltage value of the signal line OUT.

[0030] The comparison circuit 101 can be configured using transistors. For example, As shown, the comparison circuit 101 includes a transistor 111 and a transistor 112. At this time, the transistor 111 is an N-channel transistor. The transistor 111 has a source and a drain 112. A voltage Vx is applied to one of the terminals, and the voltage of the gate of the transistor 111 is applied to the data Dsch In addition, one of the source and drain of the transistor 112 is connected to the transistor 111. the other of the source and drain of the transistor 112. The other input is electrically connected to the output signal line OUT, and the gate voltage of the transistor 112 is The pressure becomes the data Dm.

[0031] The comparison circuit 102 compares the stored data (data Dm) stored in the memory cell with the search data ( It has the function of performing a second comparison operation using the data Dsch).

[0032] The comparison circuit 102 can be configured using transistors. For example, As shown, the comparison circuit 102 includes a transistor 121 and a transistor 122. At this time, the transistor 121 is an N-channel transistor. The transistor 122 is a P-channel transistor. A voltage Vx is applied to one of the terminals, and the voltage of the gate of the transistor 121 is applied to the data Dsch In addition, one of the source and drain of the transistor 122 is connected to the transistor 121. and the source and drain of the transistor 122. The other input is electrically connected to the other of the source and drain of the transistor 121. The voltage of the gate of the transistor 122 is the data Dm. The value of the voltage Vx is and is set appropriately depending on the polarity of the transistors in the comparison circuit 102.

[0033] The transistor 131 has a function of controlling writing and holding of data Dm. A data signal is input to one of the source and drain of the transistor 131. The other of the source and drain of the transistor 131 is connected to the transistor 112 (comparison circuit 101). The gate of the transistor 122 (comparison circuit 102) is electrically connected to the gate of the transistor 122. The transistor 131 is also called a control transistor. One of the pair of electrodes of the capacitor element is electrically connected to the other of the source and drain of the transistor 131. In this case, the voltage of the other of the pair of electrodes of the capacitance element is set to a value equivalent to the ground potential. Or it can be a voltage of any value.

[0034] The transistor 131 is, for example, a transistor including an oxide semiconductor layer in which a channel is formed. The oxide semiconductor layer has a band gap smaller than that of silicon. is high, for example, 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more. do.

[0035] Furthermore, the transistor including the oxide semiconductor layer has a low off-state current and a channel width of 1 μm. per 10aA (1 x 10 -17 A) or less, preferably 1 aA ( 1×10 -18 A) or less, more preferably 10 zA (1 × 10 -20 A) or less, more preferably 1 zA (1 × 10 -21 A) More preferably, the current is 100 yA (1×10 -22 A) Below be.

[0036] Furthermore, as shown in FIG. 1 and FIG. 2(A), the storage device according to the present embodiment includes The data line Data and the word line Word are provided.

[0037] The data line Data is a wiring for exchanging data with the memory cells. A data signal is input to the Data line. For example, the data line Data shown in FIG. is the gate of transistor 111, the gate of transistor 121, and the gate of transistor 1 This reduces the number of wirings. One of the source and drain of the transistor 131 can be connected to the data line D It may be electrically connected to another wiring instead of the data line Data. A first data signal is input to one wiring, and a second data signal is input to another wiring. The other wiring is also called a bit line.

[0038] The word line Word is a line through which a signal that controls writing and holding of data in a memory cell is input. The word line Word is electrically connected to the gate of the transistor 131. will be done.

[0039] Generally, voltage refers to the difference in electric potential between two points (also called the potential difference). However, voltage and potential values ​​are often expressed in volts (V) in circuit diagrams, etc. Therefore, in this specification, unless otherwise specified, The potential difference between the potential at a point and the reference potential (also called the reference potential) is called the voltage at that point. It may be used.

[0040] Next, as an example of a method for driving the memory device in this embodiment, the memory device shown in FIG. An example of a driving method will be described. Here, as an example, a data signal is set to a high level and a low level. When the voltage Vx is at a high level, The voltage of the data signal when it is at a high level is equal to the voltage of the data signal. The voltage of the data signal at a low level represents data (1), and the voltage of the data signal at a low level represents data (0). However, the voltage of the data signal at a high level represents data (0), and the low level represents data (0). The voltage of the data signal at the low level may represent data (1).

[0041] In the example of the method for driving the memory device according to this embodiment, first, the transistor 131 is turned on. However, the data signal changes the voltage of the gates of the transistors 112 and 122, The value of the data Dm is set, and the data is written to the memory cell. Then, by turning off the transistor 131, the transistors 112 and Therefore, the voltage of the gate of the memory cell 122 (value of the data Dm) is maintained. At this time, the supply of voltage Vx to the memory cell may be stopped. For example, by using a switch, etc., the power consumption can be reduced. The supply of Vx can be controlled.

[0042] Next, the data signal changes the voltages at the gates of transistors 111 and 121, That is, the data Dsch is set.

[0043] At this time, the comparison circuit 101 and the comparison circuit 102 are determined based on the value of the data Dm and the value of the data Dsch. The state of 102 changes. Each state will be explained using FIG. 2(B). (B) shows the value of the data Dm, the value of the data Dsch, the comparison circuit 101, and the comparison circuit 102. FIG.

[0044] As shown in FIG. 2(B), when the value of data Dm is (0) and the value of data Dsch is ( In the case of 1), that is, when the value of data Dm is smaller than the value of data Dsch, the transistor The transistors 111 and 112 are turned on, and the comparator circuit 101 is turned on (state pa ss), and otherwise, the transistors 111 and 112 At least one of them is turned off, and the comparator circuit 101 is in a non-conducting state (also called state x). When the comparator circuit 101 is in a conductive state, the voltage value of the output signal line OUT changes, and the voltage Vx When the comparator circuit 101 is in a non-conductive state, the voltage value of the output signal line OUT is Therefore, the data D It can be determined whether the value of m is smaller than the value of the data Dsch.

[0045] Also, when the value of data Dm is (1) and the value of data Dsch is (0), that is, When the value of the data Dm is greater than the value of the data Dsch, the transistors 121 and 122 When the transistor 122 is turned off, the comparator circuit 102 is turned off. At least one of the transistors 121 and 122 is turned on, and the comparator For example, when the memory device has a plurality of memory cells, the comparison circuit When the path 102 is in a conductive state, the memory cell in which it is provided and the other memory cells are electrically connected. When the comparator circuit 102 is in a non-conductive state, the memory cell in which it is provided and the other memory cells The memory cell is in a non-conductive state.

[0046] The above is a description of an example of the method for driving the memory device according to this embodiment.

[0047] The configuration of the memory cell is not limited to the configuration shown in FIG. For example, as shown in FIG. 3A, the transistor 111 is a P-channel transistor. The transistor 112 is an N-channel transistor, and the transistor 121 is a P-channel transistor. The transistor 121 may be an N-channel transistor. As shown in FIG. 3(B), when the value of data Dm is greater than the value of data Dsch, The comparator circuit 101 is in a conductive state at all other times and is in a non-conductive state at all other times. When the value of m is smaller than the value of the data Dsch, the comparator circuit 102 is in a non-conductive state. Therefore, whether the voltage value of the output signal line OUT changes or not This makes it possible to determine whether the value of data Dm is greater than the value of data Dsch. The comparator circuits 101 and 102 have the same configurations as those shown in FIGS. 2A and 3A. The present invention is not limited to this configuration, and other configurations may be used as long as they have the same functions.

[0048] As described with reference to FIGS. 1 to 3, in the example of the storage device according to this embodiment, and a control transistor that controls the setting of the value of the data stored in the memory cell. By configuring a memory cell that can determine data, the transistor in the memory cell Since the number of capacitors can be reduced, the circuit area can be reduced.

[0049] In the example of the memory device according to the present embodiment, the control transistor is a channel By using a transistor including an oxide semiconductor layer in which This reduces the leakage current of the transistor. It is possible to suppress fluctuations in data stored in the memory cells when the memory cells are in a low-power state. By suppressing fluctuations in the data stored in the memory cell, data can be retained in the memory cell. Since the power supply can be stopped as needed while the device is running, power consumption can also be reduced.

[0050] (Embodiment 2) In this embodiment, an example of a storage device capable of determining multi-bit data will be described.

[0051] An example of a storage device in this embodiment will be described with reference to FIG.

[0052] The memory device shown in FIG. 4 has N stages (N is a natural number of 2 or more) of memory cells 201 (memory cells 2 01_1 to 201_N), an output signal line OUT1, and an output signal line OUT2. , connection wirings CL_1 to CL_N-1, wiring VL to which voltage is applied, and transistor 2 02, a transistor 203, a buffer 204, and a buffer 205. A circuit configured using N stages of memory cells 201 is used as a memory circuit for one row. A configuration may be adopted in which a plurality of circuits are provided to include a plurality of rows of memory circuits.

[0053] The memory cells 201 in the N stages are configured as shown in FIG. Each of the N stages of memory cells 201 includes a comparison circuit 101, a comparison circuit 102, and and a transistor 131. For example, each of the N stages of memory cells 201 includes a memory One bit of data is stored as memory data.

[0054] In each of the N stages of memory cells 201, the comparator circuit 101 stores 1-bit stored data. A first comparison operation is performed between the data Dm and the 1-bit search data Dsch, It has a function to control whether or not to change the voltage value of the output signal line OUT1 depending on the calculation result. For example, when the value of the data Dm is smaller than the value of the data Dsch, the comparator circuit 101 When the value of data Dm matches the value of data Dsch, or when data D When the value of m is greater than the value of data Dsch, the transistor is in a non-conductive state. However, the comparison circuit 101 may determine that the value of the data Dm is greater than the value of the data Dsch. When the value of data Dm matches the value of data Dsch, or When the value of data Dm is smaller than the value of data Dsch, the transistor is in a non-conducting state. The comparison circuit 101 (the other of the source and drain of the transistor 112) may be , and is electrically connected to the output signal line OUT1.

[0055] In each of the N stages of memory cells 201, the comparison circuit 102 stores one bit of data. A second comparison operation is performed between the data (data Dm) and the 1-bit search data (data Dsch). For example, the memory cell 20 in the Kth stage (K is a natural number between 2 and N-1) At 1_K, the comparator 102 determines that the value of the data Dm is smaller than the value of the data Dsch. When the memory cell 201_K-1 in the K-1th row and the memory cell 201_K+1 in the K+1th row are When the value of data Dm is greater than the value of data Dsch, Between the memory cell 201_K-1 in the K-1th row and the memory cell 201_K+1 in the K+1th row For example, the comparator circuit 102 has a function of making the data Dm non-conductive. When the value of data Dm is smaller than the value of data Dsch, or when the value of data Dm is equal to the value of data Dsch When the value of data Dm is greater than the value of data Dsch, the However, the present invention is not limited to this, and the comparison circuit 102 may also be configured to determine whether the value of the data Dm is When the value of data Dm is greater than the value of data Dsch, or when the value of data Dm matches the value of data Dsch When the value of data Dm is smaller than the value of data Dsch, the In addition, the memory cell 201_K in the Kth stage may have a function of being in a normal state. The comparator circuit 102 is a comparator circuit 102 in the memory cell 201_K-1 in the (K-1)th stage and a comparator circuit 102 in the memory cell 201_K-1 in the (K-1)th stage. It is connected to the comparison circuit 102 in the memory cell 201_K+1 in the +1th stage.

[0056] Also, the comparison circuit 101 of the memory cell 201_1 in the first stage is in a conductive state or a non-conductive state. By doing so, the control circuit 100 has a function of controlling the electrical connection between the wiring VL and the output signal line OUT1.

[0057] Also, the comparison circuit 102 of the memory cell 201_1 in the first stage is in a conductive state or a non-conductive state. By doing so, it has a function of controlling the electrical connection between the wiring VL and the first connection wiring CL_1. do.

[0058] Also, the comparison circuit 101 of the K-th stage memory cell 201_K is in a conductive or non-conductive state. By this, the electrical connection between the K-1st connection wiring CL_K-1 and the output signal line OUT1 is established. It has the function of controlling.

[0059] Also, the comparison circuit 102 of the K-th stage memory cell 201_K is in a conductive state or a non-conductive state. By this, the electrical connection between the (K-1)th connection wiring CL_K-1 and the Kth connection wiring CL_K is It has the function of controlling the connection.

[0060] Also, the comparison circuit 101 of the memory cell 201_N in the Nth stage is in a conductive state or a non-conductive state. By doing so, the electrical connection between the (N-1)th connection wiring CL_N-1 and the output signal line OUT1 is established. It has the function of controlling.

[0061] Also, the comparison circuit 102 of the memory cell 201_N in the Nth stage is in a conductive state or a non-conductive state. By doing so, the electrical connection between the (N-1)th connection wiring CL_N-1 and the output signal line OUT2 is established. It has the function of controlling.

[0062] In each of the N stages of memory cells 201, the source and drain of the transistor 131 One of the two is electrically connected to a different data line Data, and the other is connected to a different data line Data. The gate of the transistor 131 is connected to a common It is electrically connected to the word line Word.

[0063] In addition, in the memory cell 201_1 of the first stage, the comparison circuit 101 (the transistor 111 one of the source and drain of the transistor 121) and the comparator circuit 102 (the source and drain of the transistor 121) The wiring VL is connected to one of the inputs of the transistor 121 and one of the source and drain of the transistor 122. Therefore, the output signal line OUT2 is connected to the Nth stage memory cell 201. Each of these is connected to a wiring to which a voltage Va is applied via a comparison circuit 102. The voltage Va is set appropriately depending on the polarity of the transistors that make up the memory cell 201.

[0064] The output signal line OUT1 and the output signal line OUT2 are connected to the respective memory cells 201 in the Nth stage. The output signal line OUT2 is a line whose voltage value is set according to the comparison operation in The memory cell 201_N of the second stage (the other of the source and drain of the transistor 121, and The other of the source and drain of the transistor 122 is electrically connected to the ground potential.

[0065] The explanations of the other components will be given in the first embodiment as appropriate.

[0066] The transistor 202 controls whether or not the voltage of the output signal line OUT1 is set to the reference voltage. For example, one of the source and drain of the transistor 202 is connected to a reference voltage The other of the source and drain of the transistor 202 is connected to the output signal line OUT1. The transistor 202 is electrically connected to the gate of the transistor 202, and a control signal is input to the gate of the transistor 202. The value of the quasi-voltage is set appropriately depending on, for example, the polarity of the transistor in the memory device.

[0067] The transistor 203 controls whether or not the voltage of the output signal line OUT2 is set to the reference voltage. For example, one of the source and drain of the transistor 203 is connected to a reference voltage The other of the source and drain of the transistor 203 is connected to the output signal line OUT2. A control signal is input to the gate of the transistor 203. The control signal and reference voltage may be the same as for transistor 202.

[0068] The buffer 204 adjusts the voltage value on the output signal line OUT1 and outputs the adjusted voltage to the output signal line OUT2. It should be noted that the buffer 204 is not necessarily provided.

[0069] The buffer 205 adjusts the voltage value on the output signal line OUT2 and outputs the adjusted voltage to the output signal line OUT3. It should be noted that the buffer 205 is not necessarily provided.

[0070] Next, as an example of a method for driving a storage device according to this embodiment, a method for driving a storage device shown in FIG. Here, as an example, a data signal is divided into a high level and a low level. The voltage of the data signal when it is at a high level is The voltage of the data signal at a low level represents data (1), and the voltage of the data signal at a low level represents data (0).

[0071] First, the memory cells 201_1 to 201_6 are read by the first data signal to the N-th data signal. Data is written to each of the memory cells 201_N, and stored in each memory cell 201. The value of data Dm is set. Here, data is written for each bit in each memory cell 201. By writing N bits of data into the memory cells 201_1 to 201_N, At this time, the supply of the voltage Va to the memory cell 201_1 in the first stage is stopped. This can reduce power consumption. For example, by using a switch, The supply of voltage Va can be controlled by this.

[0072] Next, the transistor 202 is turned on to turn on the output signal line OUT1 and the output signal line OUT2 The voltage is set to the reference voltage.

[0073] Next, the memory cells 201_1 to 201_2 are read by the first data signal to the N-th data signal. The data Dsch in each of the cells 201_N is set. By setting the data Dsch to data for each bit, the memory cells 201_1 to In memory cell 201_N, N bits of search data can be set.

[0074] At this time, in each memory cell 201, the value of data Dm and the value of data Dsch are , the states of the comparison circuit 101 and the comparison circuit 102 change.

[0075] For example, when the value of data Dm is smaller than the value of data Dsch, the comparator circuit 101 is in a conductive state. When the comparator circuit 101 is in the ON state, the comparator circuit 101 is in the OFF state at other times. When the comparator circuit 101 is in a conducting state, the voltage value of the output signal line OUT1 changes. In the on state, the voltage value of the output signal line OUT1 does not change.

[0076] When the value of the data Dm is greater than the value of the data Dsch, the comparator circuit 102 is in a non-conductive state. In other cases, the comparator circuit 102 is in a conductive state. When the comparator circuit 102 in the memory cell 201_K is in a conductive state, the memory cell 201 in the Kth stage The memory cell 201_K+1 in the Kth stage is electrically connected to the memory cell 201_K+1 in the Kth stage. When the comparator circuit 102 in the memory cell 201_K is in a non-conductive state, the K-th memory cell 201_ A non-conductive state is established between the K and K+1th stage memory cells 201_K+1.

[0077] As an example of the above operation, from the storage data Dm stored in each memory cell 201, The value of N-bit data is calculated from the data Dsch set in each memory cell 201. When the value of the N-bit data is larger than or smaller than the value of the N-bit data, the output signal line OUT1 The voltage value of the output signal line OUT1 changes, and at other times the voltage value of the output signal line OUT1 does not change.

[0078] In addition, the value of N-bit data consisting of data Dm stored in each memory cell 201 is The value of the N-bit data consisting of data Dsch set in memory cell 201 is smaller than the value of the N-bit data consisting of data Dsch. When the size is small or large, the memory cells 201 in the adjacent rows are not electrically connected. , the data stored in each memory cell 201 in the N stages The value of N-bit data consisting of Dm is the data Ds set in each memory cell 201. When the values ​​of the N-bit data consisting of ch are equal, the voltage value of the output signal line OUT2 changes. To become.

[0079] Furthermore, by a comparison operation in each memory cell 201, the output signal line OUT1 and the output signal By setting the voltage value of the signal line OUT2, the voltage stored in each memory cell 201 is The N-bit data consisting of the data Dm is determined.

[0080] For example, the voltage value of the output signal line OUT1 is a value representing data (1), and the voltage value of the output signal line OUT When the voltage value of 2 is a value representing data (1) or data (0), The N-bit data consisting of the stored data Dm is the N-bit data to be searched. is judged to be smaller than

[0081] The voltage value of the output signal line OUT1 is a value that represents data (0), and the voltage value of the output signal line OUT2 is a value that represents data (0). When the voltage value of is a value representing data (1), the data D stored in each memory cell 201 The N-bit data consisting of m is judged to be equal to the N-bit data to be searched. For example, in each of the N stages of memory cells 201, the value of data Dm is changed to the value of data Ds When the value of ch is equal to the voltage value of the output signal line OUT2, the voltage value of the output signal line OUT2 becomes a value that represents data (1).

[0082] The voltage value of the output signal line OUT1 is a value that represents data (0), and the voltage value of the output signal line OUT2 is a value that represents data (0). When the voltage value of is a value representing data (0), the data D stored in each memory cell 201 The N-bit data consisting of m is determined to be larger than the N-bit data to be searched. can be.

[0083] As in the memory device shown in the first embodiment, in each memory cell 201, a comparison circuit 10 If the polarity of the transistors in the comparator circuit 102 is reversed and the value of the voltage Va is changed, The magnitude relationship between the voltage values ​​of the input signal line OUT1 and the output signal line OUT2 and the determination result is reversed.

[0084] As described above, whether the voltage values ​​of the output signal lines OUT1 and OUT2 change or not Therefore, the N-bit data consisting of the data Dm stored in each memory cell 201 can be discriminated. It is possible.

[0085] In addition, when a plurality of memory circuits configured using N stages of memory cells 201 are provided, all The setting operation of the data Dsch in each of the memory cells 201 may be performed simultaneously. stomach.

[0086] The above is a description of an example of the method for driving the memory device according to this embodiment.

[0087] As explained with reference to FIG. 4, a multi-stage memory cell is formed using the memory cells having the configuration shown in the first embodiment. By configuring a storage device having memory cells, it is possible to distinguish between multiple bits of data. A storage device can be provided.

[0088] (Embodiment 3) In this embodiment, an oxide semiconductor applicable to the transistor of the memory device described in the above embodiment will be described. An example of a transistor including a conductor layer will now be described.

[0089] An example of the structure of the transistor including the oxide semiconductor layer will be described with reference to FIGS. 1 is a schematic cross-sectional view illustrating a structural example of a transistor according to this embodiment.

[0090] The transistor shown in FIG. 5A includes a conductive layer 601_a, an insulating layer 602_a, and a semiconductor layer 603_a, a conductive layer 605a_a, a conductive layer 605b_a, an insulating layer 606_a, and a conductive and an electrical layer 608_a.

[0091] The conductive layer 601_a is provided on an element formation layer 600_a.

[0092] The insulating layer 602_a is provided on the conductive layer 601_a.

[0093] The semiconductor layer 603_a overlaps with the conductive layer 601_a with the insulating layer 602_a interposed therebetween.

[0094] The conductive layer 605a_a and the conductive layer 605b_a are each provided on the semiconductor layer 603_a. The semiconductor layer 603_a is electrically connected to the semiconductor layer 603_b.

[0095] The insulating layer 606_a is formed between the semiconductor layer 603_a, the conductive layer 605a_a, and the conductive layer 605b_ It is placed on top of a.

[0096] The conductive layer 608_a overlaps with the semiconductor layer 603_a with the insulating layer 606_a interposed therebetween.

[0097] Note that it is not always necessary to provide either the conductive layer 601_a or the conductive layer 608_a. If the conductive layer 608_a is not provided, the insulating layer 606_a does not have to be provided.

[0098] The transistor shown in FIG. 5B includes a conductive layer 601_b, an insulating layer 602_b, and a semiconductor layer 603_b, conductive layer 605a_b, conductive layer 605b_b, insulating layer 606_b, and conductive and an electrical layer 608_b.

[0099] The conductive layer 601_b is provided on the element formation layer 600_b.

[0100] The insulating layer 602_b is provided on the conductive layer 601_b.

[0101] Each of the conductive layer 605a_b and the conductive layer 605b_b is formed on a part of the insulating layer 602_b. It will be established in.

[0102] The semiconductor layer 603_b is provided on the conductive layer 605a_b and the conductive layer 605b_b. The semiconductor layer 603 is electrically connected to the conductive layer 605a_b and the conductive layer 605b_b. _b overlaps the conductive layer 601_b via an insulating layer 602_b.

[0103] The insulating layer 606_b is formed between the semiconductor layer 603_b, the conductive layer 605a_b, and the conductive layer 605b_b. It is provided on top of b.

[0104] The conductive layer 608_b overlaps with the semiconductor layer 603_b with the insulating layer 606_b interposed therebetween.

[0105] Note that it is not always necessary to provide either the conductive layer 601_b or the conductive layer 608_b. If the layer 608_b is not provided, the insulating layer 606_b does not have to be provided.

[0106] The transistor shown in FIG. 5C includes a conductive layer 601_c, an insulating layer 602_c, and a semiconductor layer 603_c, conductive layer 605a_c, and conductive layer 605b_c.

[0107] The semiconductor layer 603_c includes a region 604a_c and a region 604b_c. The regions 604b_c and 604b_c are separated from each other and are doped regions. The region between the region 604a_c and the region 604b_c becomes a channel formation region. The semiconductor layer 603_c is provided on the element formation layer 600_c. The regions 604a_c and 604b_c may not be provided.

[0108] The conductive layer 605a_c and the conductive layer 605b_c are provided on the semiconductor layer 603_c. The conductive layer 605a_c and the conductive layer 605b are electrically connected to each other. The side of _c is tapered.

[0109] Furthermore, the conductive layer 605a_c overlaps a part of the region 604a_c, but is not necessarily limited to this. By overlapping the conductive layer 605a_c with a part of the region 604a_c, the conductive layer 605a_c is The resistance between the conductive layer 605a_c and the region 604a_c can be reduced. The entire region of the semiconductor layer 603_c overlapping the conductive layer 605a_c is the region 604a_c. good.

[0110] Furthermore, the conductive layer 605b_c overlaps a part of the region 604b_c, but is not necessarily limited to this. By overlapping the conductive layer 605b_c with a part of the region 604b_c, the conductive layer 605b_c is The resistance between the conductive layer 605b_c and the region 604b_c can be reduced. The entire region of the semiconductor layer 603_c overlapping the electrical layer 605b_c may be the region 604b_c. stomach.

[0111] The insulating layer 602_c is made up of a semiconductor layer 603_c, a conductive layer 605a_c, and a conductive layer 605b_c. It is placed on top of c.

[0112] The conductive layer 601_c overlaps with the semiconductor layer 603_c with the insulating layer 602_c interposed therebetween. A region of the semiconductor layer 603_c overlapping with the conductive layer 601_c via the conductive layer 602_c is a channel-type It becomes a mature area.

[0113] The transistor shown in FIG. 5D includes a conductive layer 601_d, an insulating layer 602_d, and a semiconductor layer. It includes a conductor layer 603_d, a conductive layer 605a_d, and a conductive layer 605b_d.

[0114] The conductive layers 605a_d and 605b_d are provided on the element formation layer 600_d. In addition, the side surfaces of the conductive layers 605a_d and 605b_d are tapered.

[0115] The semiconductor layer 603_d includes a region 604a_d and a region 604b_d. The regions 604a_d and 604b_d are spaced apart from each other and are doped regions. The region between the region 604a_d and the region 604b_d is a channel forming region. The semiconductor layer 603_d includes, for example, a conductive layer 605a_d, a conductive layer 605b_d, and a semiconductor layer. The conductive layer 605a_d and the conductive layer 605b_d are electrically connected to each other. It is not necessary to provide the areas 604a_d and 604b_d. good.

[0116] Regions 604a_d are electrically connected to conductive layers 605a_d.

[0117] Region 604b_d is electrically connected to conductive layer 605b_d.

[0118] An insulating layer 602_d is provided on the semiconductor layer 603_d.

[0119] The conductive layer 601_d overlaps with the semiconductor layer 603_d with an insulating layer 602_d interposed therebetween. A region of the semiconductor layer 603_d overlapping with the conductive layer 601_d via the conductive layer 602_d is a channel-type It becomes a mature area.

[0120] Furthermore, each of the components shown in FIGS. 5(A) to 5(D) will be described.

[0121] The element formation layers 600_a to 600_d may be, for example, insulating layers or insulating A substrate having a surface can be used. They can also be used as the layers 600_a to 600_d where elements are to be formed.

[0122] Each of the conductive layers 601_a to 601_d functions as a gate of a transistor. The layer functioning as the gate of a transistor is called a gate electrode or a gate It is also called wiring.

[0123] The conductive layers 601_a to 601_d can be formed of, for example, molybdenum, magnesium, or titanium. Tan, chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium A layer of a metal material such as zinc or an alloy material containing this as a main component can be used. In addition, by stacking layers of materials applicable to the formation of the conductive layers 601_a to 601_d, The conductive layers 601_a to 601_d can also be formed by the conductive layer 601_b.

[0124] The insulating layers 602_a to 602_d are used as gate insulating layers of transistors. It has all the functions.

[0125] The insulating layers 602_a to 602_d may be, for example, a silicon oxide layer or a silicon nitride layer. layer, silicon oxynitride layer, silicon nitride oxide layer, aluminum oxide layer, aluminum nitride layer layer, aluminum oxide nitride layer, aluminum nitride oxide layer, hafnium oxide layer, or lath oxide layer A titanium layer can be used. Alternatively, the insulating layers 602_a to 602_d may be formed by stacking layers of a material that can be used. do.

[0126] The insulating layers 602_a to 602_d may be, for example, the first insulating layer of the periodic table. An insulating layer made of a material containing a group 3 element and an oxygen element can also be used. For example, the semiconductor layer 60 When the semiconductor layers 603_a to 603_d contain a Group 13 element, By using an insulating layer containing a Group 13 element as the insulating layer in contact with the conductor layer 603_d, The state of the interface between the insulating layer and the oxide semiconductor layer can be improved.

[0127] Examples of materials containing a Group 13 element and an oxygen element include gallium oxide and aluminum oxide. , aluminum gallium oxide, and gallium aluminum oxide. Aluminum gallium is a material that has a higher aluminum content (atomic %) than the gallium content (atomic %). Gallium aluminum oxide is a substance with a high gallium content (atomic It refers to a substance whose aluminum content (atomic %) is equal to or greater than that of aluminum. For example, Al2O x (x=3+α, α is a value greater than 0 and less than 1), Ga2O x (x=3+α, α is greater than 0 (a value greater than or equal to 1 and less than 1) or Ga x Al 2-x O 3+α (x is greater than 0 and less than 2 A material expressed as a small value, α being a value greater than 0 and less than 1, can also be used.

[0128] In addition, layers of materials applicable to the insulating layers 602_a to 602_d are stacked to form insulating layers For example, a plurality of GaO x in The insulating layers 602_a to 602_d are formed by stacking layers containing gallium oxide. It may also be composed of GaO x and an insulating layer containing gallium oxide, represented by AlO x The insulating layers 602_a to 602_b are stacked by laminating insulating layers containing aluminum oxide. 602_d may be configured.

[0129] Each of the semiconductor layers 603_a to 603_d is a layer in which a channel of a transistor is formed. The semiconductor layers 603_a to 603_d can be applied to the semiconductor layers 603_a to 603_d. Examples of oxide semiconductors that can be used include quaternary metal oxides, ternary metal oxides, and binary metal oxides. For example, a metal oxide or a single element metal oxide can be used.

[0130] The oxide semiconductor must contain at least indium (In) or zinc (Zn). It is particularly preferable that the oxide semiconductor contains In and Zn. In addition to these, a gas is used as a stabilizer to reduce the variation in the electrical characteristics of the transistor. It is preferable that the alloy contains tin (Sn) as a stabilizer. It is also preferable to have hafnium (Hf) as a stabilizer. It is also preferable to have aluminum (Al) as a stabilizer.

[0131] Other stabilizers include lanthanides such as lanthanum (La) and cerium ( Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), hol Mium (Ho), Erbium (Er), Thulium (Tm), Ytterbium (Yb), Ru It may contain one or more of tetraethion (Te) and tetraethion (Tb).

[0132] Examples of quaternary metal oxides include In-Sn-Ga-Zn-O metal oxides, In-H f-Ga-Zn-O based metal oxides, In-Al-Ga-Zn-O based metal oxides, In-S n-Al-Zn-O metal oxide, In-Sn-Hf-Zn-O metal oxide, In-H f-Al-Zn-O based metal oxides and the like can be used.

[0133] Ternary metal oxides include, for example, In-Ga-Zn-O-based metal oxides and In-Sn-Z nO-based metal oxides, In-Al-Zn-O-based metal oxides, Sn-Ga-Zn-O-based metals oxide, Al-Ga-Zn-O based metal oxide, or Sn-Al-Zn-O based metal oxide, In-Hf-Zn-O based metal oxides, In-La-Zn-O based metal oxides, In-Ce- Zn-O metal oxide, In-Pr-Zn-O metal oxide, In-Nd-Zn-O gold metal oxides, In-Sm-Zn-O metal oxides, In-Eu-Zn-O metal oxides, I n-Gd-Zn-O metal oxide, In-Tb-Zn-O metal oxide, In-Dy-Z nO metal oxide, In-Ho-Zn-O metal oxide, In-Er-Zn-O metal Oxides, In-Tm-Zn-O based metal oxides, In-Yb-Zn-O based metal oxides, In -Lu-Zn-O based metal oxides and the like can be used.

[0134] Examples of binary metal oxides include In-Zn-O based metal oxides and Sn-Zn-O based metal oxides. Oxides, Al-Zn-O metal oxides, Zn-Mg-O metal oxides, Sn-Mg-O metal oxides Metal oxides, In-Mg-O based metal oxides, In-Sn-O based metal oxides, or In-G aO-based metal oxides and the like can be used.

[0135] Examples of single-component metal oxides include In—O-based metal oxides, Sn—O-based metal oxides, and Zn-O based metal oxides can also be used. Possible metal oxides may include silicon oxide.

[0136] In addition, the In-Ga-Zn-O metal oxide is a metal oxide having In, Ga, and Zn as its main components. It means metal oxide, and the ratio of In, Ga, and Zn does not matter. Metal elements other than Zn may be included.

[0137] When an In-Zn-O based metal oxide is used, for example, In:Zn=50:1 or In:Z n=1:2 (converted to a molar ratio of In2O3:ZnO=25:1 or In2O3:Zn In:Zn=1:4), preferably In:Zn=20:1 to In:Zn=1:1 (in terms of molar ratio) In2O3:ZnO=10:1 to In2O3:ZnO=1:2, more preferably Or In:Zn=15:1 or In:Zn=1.5:1 (converted to molar ratio In2 Oxide targets with a composition ratio of In2O3:ZnO=15:2 to In2O3:ZnO=3:4 Using this method, a semiconductor layer of In-Zn-O based metal oxide can be formed. For example, The target used for forming the In-Zn-O based oxide semiconductor is a material with an atomic ratio of In:Zn:O When the ratio is S:U:R, R>1.5S+U. By increasing the amount of In, The mobility of the transistor can be improved.

[0138] The composition ratio of the target used for the In-Sn-Zn-O metal oxide is, in atomic ratio, In:Sn:Zn=1:2:2, In:Sn:Zn=2:1:3, In:Sn:Zn=1 :1:1, or In:Sn:Zn=20:45:35, etc. do.

[0139] In addition, as an oxide semiconductor, InLO3(ZnO) m (m is a number greater than 0 and m Materials expressed as InLO3 (ZnO) can also be used. m The L in , Ga, Fe, Al, Mn, and Co. , as an oxide semiconductor, In3SnO5(ZnO) n (n is a number greater than 0, and n is Materials expressed as integers can also be used.

[0140] In:Ga:Zn=1:1:1 (=1 / 3:1 / 3:1 / 3) or In:Ga : In-Ga-Zn-O system with an atomic ratio of Zn=2:2:1 (=2 / 5:2 / 5:1 / 5) Metal oxides or oxides with similar compositions can be used. n=1:1:1(=1 / 3:1 / 3:1 / 3), In:Sn:Zn=2:1:3(=1 / 3:1 / 6:1 / 2) or In:Sn:Zn=2:1:5(=1 / 4:1 / 8:5 / 8) Use an In-Sn-Zn-O metal oxide with an atomic ratio of 8) or an oxide with a similar composition. It is good.

[0141] However, it is not limited to these, and the required semiconductor characteristics (mobility, threshold, variation, etc.) In order to obtain the required semiconductor properties, a material with an appropriate composition can be used. Carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic bond length, density It is preferable to set the degree etc. appropriately.

[0142] For example, high mobility can be obtained relatively easily with In-Sn-Zn-O based metal oxides. However, even in the In-Ga-Zn-O metal oxide, it is possible to reduce the defect density in the bulk. This can increase the mobility.

[0143] For example, when the atomic ratio of In, Ga, and Zn is In:Ga:Zn=a:b:c(a+b+ The composition of the oxide with c=1) is In:Ga:Zn=A:B:C (A+B+C = 1), a, b, c are in the vicinity of the oxide composition (a-A) 2 +(b-B) 2 + (c-C) 2 ≦r 2 The value of r can be set to, for example, 0.05. The same applies to other oxides.

[0144] The oxide semiconductor may be single-crystal or non-single-crystal. In the latter case, it may be amorphous or polycrystalline. In addition, it may be a structure containing a crystalline portion in an amorphous state or a non-amorphous state. That's fine too.

[0145] Amorphous oxide semiconductors can be easily flattened, This can reduce interface scattering when fabricating a transistor, and can be achieved relatively easily and with relatively high efficiency. High mobility can be obtained.

[0146] In addition, in a crystalline oxide semiconductor, defects in the bulk can be further reduced, and the surface By improving the flatness of the oxide semiconductor, it is possible to obtain a mobility higher than that of an oxide semiconductor in an amorphous state. In order to improve the flatness of the surface, it is preferable to form an oxide semiconductor on a flat surface. Specifically, the average surface roughness (Ra) is 1 nm or less, preferably 0.3 nm or less, and more preferably It is preferable to form it on the surface of 0.1 nm or less.

[0147] For Ra, the centerline average roughness defined in JIS B0601 can be applied to the surface. It is a three-dimensional extension of the method, which is based on the averaging of the absolute values ​​of the deviations from the reference surface to the specified surface. This can be expressed as the "value obtained by dividing the total number of times the

[0148]

number

[0149] In the above, S0 is the measurement surface (coordinates (x1, y1) (x1, y2) (x2, y1 ) (the rectangular region bounded by the four points represented by (x2, y2)), and Z0 is It refers to the average height of the measurement surface. Ra is measured by an atomic force microscope (AFM). The measurement surface is the surface shown by all measurement data. It consists of three parameters (x, y, z) and is expressed as z = F(x, y). The range of x (and y) is 0 to xMAX (and yMAX), and the range of z is is zMIN to zMAX.

[0150] In addition, at least the region where a channel is formed in each of the semiconductor layers 603_a to 603_d The region has crystallinity, is non-single crystal, and has a triangular or hexagonal shape when viewed from the direction perpendicular to the ab plane. , equilateral triangle, or equilateral hexagonal atomic arrangement, and when viewed from a direction perpendicular to the c-axis direction, A phase in which atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers when viewed from the direction perpendicular to the c-axis direction. The material having the above phase may be called CAAC (c axis aligned). It is also called ned crystal.

[0151] When the channel length of the transistor is 30 nm, the semiconductor layers 603_a to 603_b are The thickness of the semiconductor layers 603_a to 603_d may be set to, for example, about 5 nm. If the semiconductor layer 603_d is an oxide semiconductor layer of CAAC, the short channel The Nel effect can be suppressed.

[0152] The regions 604a_c, 604b_c, 604a_d, and 604b_d are N A dopant that imparts P-type or P-type conductivity is added to form the source or drain of the transistor. As a dopant, for example, an element in group 13 of the periodic table can be used. (e.g., boron), elements in group 15 of the periodic table (e.g., nitrogen, phosphorus, and arsenic) one or more of the elements, and noble gas elements (e.g., one or more of helium, argon, and xenon) One or more of the following can be used. The region having the function as the drain of the transistor is also called the source region. The regions 604a_c, 604b_c, 604a_d, and By adding a dopant to the regions 604b_d, the contact resistance with the conductive layer is reduced. This allows for miniaturization of transistors.

[0153] The conductive layers 605a_a to 605a_d and the conductive layers 605b_a to 605 Each of b and d functions as a source or drain of a transistor. The layer that functions as the source of a transistor is also called a source electrode or a source wiring. The layer that functions as the drain of the transistor is also called a drain electrode or a drain wiring. .

[0154] The conductive layers 605a_a to 605a_d and the conductive layers 605b_a to 605 Examples of b_d include aluminum, magnesium, chromium, copper, tantalum, titanium, Metallic materials such as molybdenum or tungsten, or materials containing these metallic materials as the main component For example, a layer of alloy material containing copper, magnesium, and aluminum can be used. The conductive layers 605a_a to 605a_d and the conductive layer 60 The conductive layers 605a_a to 605b_d can be formed. Materials applicable to the conductive layers 605a-d and the conductive layers 605b-a to 605b-d By stacking the layers of the material, the conductive layers 605a_a to 605a_d and the conductive layer 605b The conductive layers 605a to 605d can also be formed of, for example, copper, magnesium, and The conductive layers 605a_a to 605b are formed by laminating layers of an alloy material containing aluminum and layers containing copper. The conductive layers 605a_d and 605b_a to 605b_d can be formed by Cut.

[0155] In addition, the conductive layers 605a_a to 605a_d and the conductive layers 605b_a to 605b_d A layer containing a conductive metal oxide may also be used as 605b_d. Examples of metal oxides include indium oxide, tin oxide, zinc oxide, indium oxide tin oxide, In addition, the conductive layers 605a_a to 605c_a can be formed of zinc oxide, indium oxide, or indium zinc oxide. Conductive layers applicable to the conductive layers 605a_d and the conductive layers 605b_a to 605b_d The reactive metal oxide may include silicon oxide.

[0156] The insulating layers 606_a and 606_b are the insulating layers 602_a to 602_b. The insulating layer 606_a and the insulating layer 606_b can be made of a material that can be applied to the insulating layer 606_c. The insulating layer 606_a and the insulating layer 606_b are formed by laminating materials applicable to the insulating layer 606_b. For example, the insulating layer 606_a and the insulating layer 606_b may be formed of a silicon oxide layer, an aluminum oxide layer, or the like. For example, an aluminum oxide layer may be used to form the insulating layer 606_b. In this way, the effect of suppressing the intrusion of impurities into the semiconductor layer 603_a and the semiconductor layer 603_b can be further enhanced. In addition, the effect of suppressing the desorption of oxygen from the semiconductor layer 603_a and the semiconductor layer 603_b can be achieved. It can be increased.

[0157] Each of the conductive layers 608_a and 608_b functions as a gate of a transistor. Note that when a transistor includes both the conductive layer 601_a and the conductive layer 608_a, or In the case of a structure including both the conductive layer 601_b and the conductive layer 608_b, the conductive layer 601_a and the conductive layer 608_a, or the conductive layer 601_b and the conductive layer 608_b, It is also called a back gate, back gate electrode, or back gate wiring. By providing a plurality of conductive layers each having a channel forming layer therebetween, the threshold voltage of the transistor can be reduced. This makes it easier to control the pressure.

[0158] The conductive layer 608_a and the conductive layer 608_b are, for example, the conductive layers 601_a to 6 A layer of a material applicable to the conductive layer 608_a and the conductive layer 608_d can be used. The conductive layer 608_a and the conductive layer 608_b are formed by stacking layers of material applicable to the layer 608_b. may be configured.

[0159] Note that the transistor of this embodiment is formed by using an oxide semiconductor having a function as a channel formation layer. an insulating layer on a part of the oxide semiconductor layer, the insulating layer being superposed on the oxide semiconductor layer via the insulating layer; A structure including a conductive layer having a function as a source or a drain may be used. In this case, the insulating layer serves as a layer to protect the channel formation layer of the transistor (also called a channel protection layer). ) The insulating layer having the function of a channel protection layer is, for example, A layer of a material applicable to the insulating layers 602_a to 602_d can be used. In addition, the insulating layers 602_a to 602_d are formed by stacking materials applicable to the insulating layers 602_a to 602_d. An insulating layer having a function as a layer may be formed.

[0160] Further, a base layer is formed on the element formation layers 600_a to 600_d. A transistor may be formed on the ground layer. In this case, the base layer may be, for example, an insulating layer 6. A layer of a material applicable to the insulating layers 602_a to 602_d can be used. The base layer may be formed by stacking materials applicable to the layers 602_a to 602_d. For example, the underlayer may be formed by laminating an aluminum oxide layer and a silicon oxide layer. As a result, oxygen contained in the base layer is released through the semiconductor layers 603_a to 603_d. It is possible to prevent the separation.

[0161] Further, as an example of a method for manufacturing a transistor in this embodiment, a transistor shown in FIG. An example of a method for manufacturing a transistor will be described with reference to FIG. 6. 1A to 1C are cross-sectional views illustrating an example of a method for manufacturing a transistor.

[0162] First, as shown in FIG. 6A, an element formation layer 600_a is prepared. A first conductive film is formed on the a, and a part of the first conductive film is etched to form a conductive film. A layer 601_a is formed.

[0163] For example, a film of a material applicable to the conductive layer 601_a can be formed by using a sputtering method. The first conductive film can be formed by the above method. The first conductive film can also be formed by stacking films.

[0164] The sputtering gas may contain impurities such as hydrogen, water, hydroxyl groups, or hydrides. By using a high purity gas from which impurities have been removed, the impurity concentration in the film to be formed is reduced. It is possible.

[0165] Before forming a film using the sputtering method, the preheating chamber of the sputtering device is By carrying out the preheating treatment, hydrogen, moisture, etc. can be removed. Which impurities can be desorbed?

[0166] Furthermore, before forming a film by sputtering, for example, argon, nitrogen, helium, Alternatively, in an oxygen atmosphere, no voltage is applied to the target side, and a voltage is applied to the substrate side using an RF power supply. The treatment is performed by applying a voltage to form plasma and modifying the surface to be treated (also called reverse sputtering). By performing reverse sputtering, powdery substances (particles) adhering to the surface to be formed can be removed. , also called garbage) can be removed.

[0167] When forming a film using a sputtering method, a suction-type vacuum pump or the like is used. It can remove residual moisture in the film-forming chamber. For example, a cryopump, an ion pump, or a titanium sublimation pump may be used. In addition, a turbo molecular pump equipped with a cold trap is used to The residual moisture can also be removed. By using the vacuum pump, the exhaust containing impurities can be It can reduce backflow of air.

[0168] In addition, as in the method for forming the conductive layer 601_a, In the example of the manufacturing method, when a layer is formed by etching a part of a film, for example, photolithography is used. A resist mask is formed on a part of the film by a lithography process, and the film is In this case, after the layer is formed, The resist mask is then removed.

[0169] Alternatively, the resist mask may be formed by an ink-jet method. By using this method, a photomask is no longer required, which reduces manufacturing costs. In addition, an exposure mask having multiple regions with different transmittances (also called a multi-tone mask) is used. A resist mask may be formed by using a multi-tone mask. A resist mask having a region can be formed, and the resist used for manufacturing a transistor can be The number of masks can be reduced.

[0170] Next, as shown in FIG. 6(B), a first insulating film is formed on the conductive layer 601_a. This forms an insulating layer 602_a.

[0171] For example, it can be applied to the insulating layer 602_a using a sputtering method or a plasma CVD method. The first insulating film can be formed by forming a film of such a material. The first insulating film can also be formed by stacking films of materials applicable to 02_a. In addition, high density plasma CVD (e.g., microwaves (e.g., microwaves with a frequency of 2.45 GHz)) A film of a material applicable to the insulating layer 602_a using a high density plasma CVD method using a wave By forming the insulating layer 602_a, the insulating layer 602_a can be made dense. The dielectric strength can be improved.

[0172] Next, as shown in FIG. 6C, an oxide semiconductor film is formed over the insulating layer 602_a. Then, a part of the oxide semiconductor film is etched to form a semiconductor layer 603_a.

[0173] For example, a sputtering method is used to deposit an oxide semiconductor material applicable to the semiconductor layer 603_a. An oxide semiconductor film can be formed by forming a rare gas atmosphere. Alternatively, the oxide semiconductor film may be formed under an oxygen atmosphere or a mixed atmosphere of a rare gas and oxygen. In addition, when an oxide semiconductor layer containing CAAC is formed as the semiconductor layer 603_a, The temperature of the element formation layer on which the oxide semiconductor film is to be formed is set to 100° C. or higher and 50° C. or lower. The oxide semiconductor film is formed at a temperature of 0° C. or lower, preferably 200° C. or higher and 350° C. or lower. When the sputtering apparatus is used, it is preferable that the concentration of impurities such as hydrogen or water in the apparatus is extremely low. For example, by performing heat treatment before forming the oxide semiconductor film, In addition, the concentration of impurities such as hydrogen or water in the insulating layer 60 can be reduced. For example, the average surface roughness of the insulating layer 602_a is 0.5 It is preferably less than 100 nm, and more preferably 0.1 nm or less.

[0174] In addition, the sputtering target was In2O3:Ga2O3:ZnO=1:1:1 An oxide semiconductor film is formed using an oxide target having a composition ratio of [molar ratio]. For example, In2O3:Ga2O3:ZnO=1:1:2 [molar ratio] The oxide semiconductor film may be formed using an oxide target having the following composition ratio:

[0175] In addition, when a sputtering method is used, for example, under a rare gas (typically argon) atmosphere, The semiconductor layer 603_a is formed in an oxygen atmosphere or a mixed atmosphere of rare gas and oxygen. In this case, when the semiconductor layer 603_a is formed under a mixed atmosphere of rare gas and oxygen, the rare gas It is preferable that the amount of oxygen is larger than the amount of water.

[0176] Next, as shown in FIG. 6(D), a second A conductive film is formed, and a part of the second conductive film is etched to form conductive layers 605a_a and and a conductive layer 605b_a.

[0177] For example, a sputtering method or the like is used to form the conductive layer 605a_a and the conductive layer 605b_a. The second conductive film can be formed by forming a film of a material that can be used. By laminating films of materials applicable to the conductive layer 605a_a and the conductive layer 605b_a, A second conductive film may also be formed.

[0178] Next, as shown in FIG. 6(E), an insulating layer 606_a is formed so as to be in contact with the semiconductor layer 603_a. Form.

[0179] For example, in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a mixture of rare gas and oxygen, A film applicable to the insulating layer 606_a is formed by sputtering under a suitable atmosphere. The insulating layer 606_a can be formed by the sputtering method. By forming 606_a, it functions as a back channel of a transistor. The decrease in resistance in the semiconductor layer 603_a can be suppressed. The substrate temperature during the formation of 06_a is preferably from room temperature to 300°C.

[0180] Also, before forming the insulating layer 606_a, a plating process using a gas such as N2O, N2, or Ar is performed. A Zuma process is performed to remove adsorbed water and the like adhering to the surface of the exposed semiconductor layer 603_a. When the plasma treatment is performed, the insulating layer 606 may be subsequently removed without being exposed to the air. It is preferable to form a.

[0181] Furthermore, in an example of a method for manufacturing a transistor shown in FIG. 5A, Heat treatment is performed at a temperature of 0°C or below, or 600°C or above but below the distortion point of the substrate. After forming a semiconductor film, part of the oxide semiconductor film is etched, and then a second conductive film is formed. After that, after etching a part of the second conductive film, or after forming the insulating layer 606_a, The above heat treatment is carried out.

[0182] The heat treatment device for the heat treatment may be an electric furnace or a heating element such as a resistance heating element. It is possible to use a device that heats the object to be treated by heat conduction or heat radiation from the TA (Gas Rapid Thermal Annealing) equipment or LRTA ( RTA (Ra) such as Lamp Rapid Thermal Annealing equipment A pid Thermal Annealing (LRTA) device can be used. The lamps are, for example, halogen lamps, metal halide lamps, xenon arc lamps, carbon Light emitted from lamps such as arc lamps, high-pressure sodium lamps, or high-pressure mercury lamps ( The GRTA device is a device that heats the object to be treated by radiating high-temperature electromagnetic waves. This is an apparatus for performing heat treatment using gas. The high-temperature gas is, for example, a rare gas or a heating An inert gas (for example, nitrogen) that does not react with the object to be treated can be used.

[0183] After the heat treatment, the heating temperature is maintained or the temperature is decreased from the heating temperature. In the process of heating, high-purity oxygen gas, high-purity N2O gas, or Alternatively, ultra-dry air (an atmosphere with a dew point of -40°C or less, preferably -60°C or less) may be introduced. In this case, it is preferable that the oxygen gas or N2O gas does not contain water, hydrogen, etc. The purity of the oxygen gas or N2O gas introduced into the heat treatment device is set to 6N or more, preferably 7N or more. N or more, that is, the impurity concentration in oxygen gas or N2O gas is 1 ppm or less, preferably It is preferable to keep the concentration below 0.1 ppm. Oxygen is supplied to the layer 603_a, reducing defects caused by oxygen deficiency in the semiconductor layer 603_a. It should be noted that the above-mentioned high-purity oxygen gas, high-purity N2O gas, or ultra-dry air can be used. The introduction of may be carried out during the heat treatment.

[0184] After the insulating layer 602_a is formed, the oxide semiconductor film is formed. After forming a conductive layer which becomes a source electrode or a drain electrode, after forming an insulating layer on the conductive layer which becomes a source electrode or a drain electrode, or After the heat treatment, oxygen doping treatment using oxygen plasma may be performed. The oxygen doping process may be performed by using a high density plasma of 1000 Hz. The oxygen doping treatment may be carried out using a silicon dioxide gas. For example, the variation in the electrical characteristics of the oxygen-doped transistor can be reduced. A bonding process is performed to form the insulating layer 602_a and / or the insulating layer 606_a in a stoichiometric manner. Create a state where there is more oxygen than the composition ratio.

[0185] By making the oxygen in the insulating layer in contact with the semiconductor layer 603_a excessive, the semiconductor layer 603_ Therefore, the semiconductor layer 603_a or the insulating layer 602_a and the insulating layer 603_b are easily supplied with the hydrogen. Reducing oxygen defects at the interface between one or both of the edge layers 606_a and the semiconductor layer 603_a Therefore, the carrier concentration of the semiconductor layer 603_a can be further reduced. In addition, the present invention is not limited to this, and any other suitable method may be used to remove excess oxygen from the semiconductor layer 603_a during the manufacturing process. Even if the semiconductor layer 603_a is in a low temperature range, the insulating layer in contact with the semiconductor layer 603_a prevents the semiconductor layer 603_a from being damaged. It is possible to suppress the desorption of oxygen from a.

[0186] For example, gallium oxide may be used as one or both of the insulating layer 602_a and the insulating layer 606_a. When forming an insulating layer containing gallium oxide, oxygen is supplied to the insulating layer, and the composition of gallium oxide is changed to GaO. x It can be made into.

[0187] In addition, one or both of the insulating layer 602_a and the insulating layer 606_a may be made of aluminum oxide. When forming an insulating layer containing aluminum oxide, oxygen is supplied to the insulating layer to change the composition of aluminum oxide to Al. 2O x It can be made into.

[0188] In addition, one or both of the insulating layer 602_a and the insulating layer 606_a may be formed of gallium oxide. When an insulating layer containing aluminum or aluminum gallium oxide is formed, oxygen is added to the insulating layer. The composition of gallium aluminum oxide or aluminum gallium oxide is Ga x Al2 -x O 3+α It can be said that:

[0189] Through the above steps, hydrogen, water, hydroxyl groups, or hydrides (hydrogenated compounds) are removed from the semiconductor layer 603_a. By eliminating impurities such as ions (also called "compounds") and supplying oxygen to the semiconductor layer 603_a, As a result, the oxide semiconductor layer can be highly purified.

[0190] Furthermore, in addition to the above-mentioned heat treatment, after forming the insulating layer 606_a, or heat treatment in an oxygen gas atmosphere (preferably at 200°C or higher and 600°C or lower, for example, 25 0°C or higher and 350°C or lower) may be performed.

[0191] Furthermore, as shown in FIG. 6(E), a third conductive film is formed on the insulating layer 606_a. The conductive film is partly etched to form a conductive layer 608_a.

[0192] For example, a film of a material applicable to the conductive layer 608_a can be formed by sputtering. The third conductive film can be formed by the above method. Films can also be stacked to form a third conductive film.

[0193] Note that although an example of a method for manufacturing the transistor illustrated in FIG. 5A has been described, the present invention is not limited to this. For example, among the components shown in FIGS. 5(B) to 5(D), the names of the components shown in FIG. 5(A) may be the same as those of the components shown in FIG. If the components are the same as those shown in FIG. 5(A) and at least a part of the functions are the same as those shown in FIG. For example, the description of the example of the method for manufacturing the transistor in FIG. 5A can be used as appropriate.

[0194] As shown in FIGS. 5C and 5D, the regions 604a_c and 604a_d Or, when the regions 604b_c to 604b_d are formed, they function as gates. The conductive layer is formed on the side where the semiconductor layer is formed, via an insulating layer having a function as a gate insulating layer. By adding dopants to the conductor layer, regions 604a_c and 604b are formed in a self-aligned manner. a_d, and regions 604b_c and 604b_d are formed.

[0195] For example, dopants can be added using an ion doping device or an ion implantation device. can.

[0196] As described with reference to FIGS. 5 and 6, an example of a transistor in this embodiment is a gate a conductive layer having a function as a gate, an insulating layer having a function as a gate insulating layer, and a gate a conductive layer having a function as a gate, the conductive layer having a function as a gate insulating layer being overlapped with the conductive layer having a function as a gate insulating layer being interposed therebetween; The oxide semiconductor layer in which the channel is formed and the source a conductive layer that functions as one of a source and a drain and a and a conductive layer having a function as the other of the source and the drain.

[0197] The oxide semiconductor layer in which the channel is formed is highly purified to have an i-type or substantially i-type structure. The oxide semiconductor layer is an I-type oxide semiconductor layer. The carrier concentration of the oxide semiconductor layer is 1×10 14 / cm 3 Less than 1 x 10 12 / c m 3 less than 1×10 11 / cm 3 It can be less than By using this structure, the off-current per 1 μm of channel width is reduced to 10 aA (1 × 10 -17 A) or less, and further, the off-current per 1 μm of channel width must be 1 aA (1 × 10 - 18 A) or less, and further, the off-current per 1 μm of channel width is 10 zA (1 × 10 -20 A) or less, and further, the off-current per 1 μm of channel width is set to 1 zA (1 × 10 -21 A) Below Furthermore, the off-current per 1 μm of channel width is 100 yA (1 × 10 -22 A) Below The lower the off-state current of the transistor, the better. The lower limit of the off-state current of the transistor in this state is approximately 10 -30 A / μm can be.

[0198] The transistor including the oxide semiconductor layer of this embodiment may be, for example, By using it as a control transistor in a memory device, data retention in a memory cell can be improved. The period can be extended.

[0199] (Fourth embodiment) In this embodiment mode, a structural example of the storage device in the above embodiment mode will be described.

[0200] The memory device of this embodiment is a semiconductor device in which a channel is formed and which is a semiconductor of Group 14 of the periodic table. A transistor including a semiconductor layer containing a semiconductor (such as silicon) and a channel formed therein. In this case, a channel is formed in the transistor including an oxide semiconductor layer. The transistor including the oxide semiconductor layer is made of a semiconductor of Group 14 of the periodic table (silicon It can be stacked on a transistor that includes a semiconductor layer containing elements such as silicon. A transistor that includes a semiconductor layer containing a semiconductor from Group 14 of the periodic table (such as silicon) The transistors are suitable for the transistors in the comparison circuit 101 and the comparison circuit 102 in FIG. It is used.

[0201] Transistors containing semiconductor layers containing semiconductors from Group 14 of the periodic table (such as silicon) An example of stacking a transistor including an oxide semiconductor layer in which a channel is formed on a transistor is described below. This is shown in Fig. 7. Note that Fig. 7 includes components that are not of actual dimensions.

[0202] In FIG. 7, a semiconductor layer 780, an insulating layer 784a, an insulating layer 784b, a conductive layer 785a, and , conductive layer 785b, insulating layer 786a, insulating layer 786b, insulating layer 786c, and insulating layer 786d, the insulating layer 788, the semiconductor layer 753, the conductive layer 754a, and the conductive layer 754b. , an insulating layer 755, a conductive layer 756, an insulating layer 757a, an insulating layer 757b, and an insulating layer 75 8, insulating layer 759, conductive layer 760a, and conductive layer 760b form a A P-channel transistor including a semiconductor layer containing a semiconductor of Group 14 (such as silicon) a transistor (e.g., corresponding to the transistor 112 shown in FIG. 2A) and an N-channel transistor (e.g., the transistor 111 shown in FIG. 2A) and an oxide semiconductor in which a channel is formed. A transistor including a conductor layer (e.g., corresponding to the transistor 131 shown in FIG. 2A) is configured. will be done.

[0203] Furthermore, the semiconductor layer 780 includes a region 782a, a region 782b, a region 782c, and a region 78 2d. The semiconductor layer 780 is also divided into insulating regions 781a to 781c. , each transistor is electrically isolated.

[0204] The semiconductor layer 780 may be, for example, a semiconductor substrate. The semiconductor layer provided in the insulating film 780 can also be used as the semiconductor layer 780.

[0205] In the semiconductor layer 780, an insulating isolation region may be provided in the region between the plurality of memory cells. stomach.

[0206] The regions 782a and 782b are spaced apart from each other and are doped with P-type conductivity. The regions 782a and 782b are regions doped with a p-channel It functions as a source region or a drain region of a transistor. For example, region 782 Each of the regions 782a and 782b may be electrically connected to a separately provided conductive layer.

[0207] The region 782c and the region 782d are spaced apart from each other and are doped with N-type conductivity. The region 782c and the region 782d are regions to which a peptand is added. It functions as a source region or a drain region of a transistor. For example, region 782 Each of the regions 782c and 782d is formed by a separately provided conductive layer (for example, a layer that functions as a data line). The conductive layer may be electrically connected to the conductive layer.

[0208] Note that low-concentration regions may be provided in parts of the regions 782a to 782d. The depth of the degree region may be smaller than the depth of the other regions 782a to 782d. Good, but not limited to this.

[0209] The insulating layer 784a is a portion of the semiconductor layer 780 sandwiched between the insulating region 781a and the insulating region 781b. The insulating layer 784a is provided on the region. It functions as a layer.

[0210] The insulating layer 784b is a region of the semiconductor layer 780 sandwiched between the insulating region 781b and the insulating region 781c. The insulating layer 784b is provided on the region. It functions as a layer.

[0211] The insulating layer 784a and the insulating layer 784b may be made of, for example, silicon oxide, silicon nitride, or silicon oxide. Silicon nitride, silicon oxynitride, aluminum oxide, aluminum nitride, aluminum oxynitride aluminum, aluminum oxide nitride, hafnium oxide, organic insulating materials (e.g., polyimide or The insulating layer 784a and the insulating layer 784b may be made of a material such as acrylic. The insulating layer 784a and the insulating layer 784b are formed by laminating materials applicable to the layer 784b. Good too.

[0212] The conductive layer 785a overlaps with the semiconductor layer 780 with the insulating layer 784a interposed therebetween. The region of the semiconductor layer 780 overlapping the P-channel transistor is the channel forming region of the P-channel transistor. The conductive layer 785a functions as the gate of the P-channel transistor. .

[0213] The conductive layer 785b overlaps with the semiconductor layer 780 with the insulating layer 784b interposed therebetween. The region of the semiconductor layer 780 overlapping the above-mentioned N-channel transistor is the channel formation region. The conductive layer 785b functions as the gate of the N-channel transistor. .

[0214] The conductive layers 785a and 785b may be made of, for example, molybdenum, magnesium, or titanium. , chromium, tantalum, tungsten, aluminum, copper, neodymium, or scandium A layer of a metal material such as aluminum or an alloy material containing these as the main component can be used. The conductive layers 785a and 785b are formed by stacking materials applicable to the conductive layers 785a and 785b. The conductive layer 785b may also be formed.

[0215] The insulating layer 786a is provided on the insulating layer 784a and is opposite to the conductive layer 785a. It is in contact with one of the pair of opposite sides.

[0216] The insulating layer 786b is provided on the insulating layer 784a and is opposite to the conductive layer 785a. The other of the pair of side surfaces facing each other is in contact with the other of the pair of side surfaces facing each other.

[0217] The insulating layer 786c is provided on the insulating layer 784b and is opposite to the conductive layer 785b. It contacts one of the pair of opposite sides.

[0218] The insulating layer 786d is provided on the insulating layer 784b and is opposite to the conductive layer 785b. The other of the pair of side surfaces facing each other is in contact with the other of the pair of side surfaces facing each other.

[0219] The insulating layer 788 includes an insulating layer 786a, an insulating layer 786b, an insulating layer 786c, and an insulating layer 786 It is placed on d.

[0220] The insulating layers 786a to 786d and the insulating layer 788 include the insulating layer 784a and the insulating layer 784b. Among the materials applicable to the insulating layer 784b, the materials applied to the insulating layer 784a and the insulating layer 784b are The insulating layers 786a to 786c may be made of the same material as the insulating layer 786a or different materials. The insulating layer 786a to 786d are formed by stacking materials applicable to the insulating layer 788. An insulating layer 786d and an insulating layer 788 may also be formed.

[0221] The semiconductor layer 753 is provided on the insulating layer 788. The semiconductor layer 753 includes a region 752a and a region 752b. The regions 752a and 752b are regions to which dopants are added. The dopant is a fluorine atom, and functions as a source region or a drain region. A dopant applicable to a transistor including an oxide semiconductor layer in the embodiment is appropriately used. It is possible.

[0222] The semiconductor layer 753 may be formed of a material that can be used for the semiconductor layer 603_a shown in FIG. A layer of the above can be used.

[0223] An insulating layer 755 is provided on the semiconductor layer 753 .

[0224] The insulating layer 755 functions as a gate insulating layer of the transistor.

[0225] The insulating layer 755 may be made of a material that can be used for the insulating layer 602_a shown in FIG. 5(A). In addition, the insulating layer 755 can be formed by stacking materials applicable to the insulating layer 755. may be configured.

[0226] The conductive layer 756 overlaps with the semiconductor layer 753 with the insulating layer 755 interposed therebetween. It functions as the gate of the transistor.

[0227] The conductive layer 756 may be a layer made of a material that can be used for the conductive layer 601_a shown in FIG. 5A. Alternatively, the conductive layer 756 can be formed by stacking materials applicable to the conductive layer 756. may be configured.

[0228] The insulating layer 757a and the insulating layer 757b are in contact with the side surfaces of the conductive layer 756 and are disposed on the insulating layer 755. It will be established.

[0229] The conductive layer 754a is in contact with and electrically connected to the semiconductor layer 753. The conductive layer 754a is electrically connected to the conductive layer 785a. The gate electrode functions as a source or drain of a transistor.

[0230] The conductive layer 754b is in contact with and electrically connected to the semiconductor layer 753. The conductive layer 754b is electrically connected to the conductive layer 785b. The gate electrode functions as a source or drain of a transistor.

[0231] The conductive layer 754a and the conductive layer 754b may be, for example, the conductive layer 605a-605b shown in FIG. A layer of a material applicable to the conductive layer 7a and the conductive layer 605b_a can be used. The conductive layers 754a and 754b are formed by laminating materials applicable to the conductive layers 754a and 754b. 4b may be constructed.

[0232] The insulating layer 758 is formed by insulating the conductive layer 756, the insulating layer 757a, the insulating layer 757b, the conductive layer 754a, and the insulating layer 758. and conductive layer 754b.

[0233] The insulating layer 758 may be made of a material that can be used for the insulating layer 602_a shown in FIG. 5(A). In addition, the insulating layer 758 can be formed by stacking materials applicable to the insulating layer 758. The insulating layer 758 functions as a protective layer that prevents impurities from entering. do.

[0234] An insulating layer 759 is provided on top of the insulating layer 758 .

[0235] The insulating layer 759 may be made of a material that can be used for the insulating layer 602_a shown in FIG. 5(A). In addition, the insulating layer 759 can be formed by stacking materials applicable to the insulating layer 759. may be configured.

[0236] The conductive layer 760a is connected to the conductive layer 760b through openings provided in the insulating layers 758 and 759. The conductive layer 760a is electrically connected to the gate electrode 54a of the transistor including an oxide semiconductor layer. It functions as a source or a drain.

[0237] The conductive layer 760b is connected to the conductive layer 760b through openings provided in the insulating layers 758 and 759. The conductive layer 760b is electrically connected to the gate insulating film 54b of the transistor including an oxide semiconductor layer. It functions as a source or a drain.

[0238] The conductive layer 760a and the conductive layer 760b may be, for example, the conductive layer 605a-605b shown in FIG. A layer of a material applicable to the conductive layer 7a and the conductive layer 605b_a can be used. The conductive layers 760a and 760b are formed by laminating materials applicable to the conductive layers 760a and 760b. 0b may be configured.

[0239] The above is an explanation of the structural example of the storage device shown in FIG.

[0240] As described with reference to FIG. 7, in the structural example of the storage device according to this embodiment, different materials By stacking transistors using semiconductor layers, the circuit area can be reduced. can be made smaller.

[0241] (Embodiment 5) In this embodiment, an example of a processing unit such as a CPU will be described.

[0242] An example of the arithmetic processing device according to this embodiment will be described with reference to FIG.

[0243] The arithmetic processing device shown in FIG. 8 includes a bus interface (also referred to as IF) 801 and a control device. (also called CTL) 802, a cache memory (also called CACH) 803, and M ( M is a natural number equal to or greater than 3) registers (also called Regi) 804 (registers 804_1 to register 804_M), an instruction decoder (also called IDecoder) 805, and an arithmetic logic and an ALU 806.

[0244] The bus interface 801 is used for exchanging signals with the outside world and for connecting each circuit in the arithmetic processing unit. It has the function of exchanging signals with the

[0245] The control device 802 has the function of controlling the operation of each circuit in the arithmetic processing device.

[0246] The cache memory 803 is controlled by the control unit 802 and is used for the operation of the arithmetic processing unit. It has the function of temporarily storing data at the time of the first cache and the second cache. As a cache, a plurality of cache memories 803 may be provided in the processing unit. For example, The storage device in the above embodiment can be used as an associative memory in the cache memory 803. This can be done.

[0247] The M registers 804 are controlled by the control unit 802 and store data used in the arithmetic processing. For example, a register 804 can be used as a register for the arithmetic logic unit 806. 803 may be used as a register for the instruction decoder 805, and another register 804 may be used as a register for the instruction decoder 805.

[0248] The command decoder 805 has a function of translating the command signal that is read. The command signal is input to the control device 802, which then generates a control signal in accordance with the command signal through arithmetic logic. The data is output to the processing unit 806.

[0249] The arithmetic logic unit 806 is controlled by the control unit 802 and operates in response to input command signals. It has the function of performing calculations using the

[0250] As described with reference to FIG. 8, in the processing unit according to this embodiment, the cache memory By reducing the area of ​​the memory, the area of ​​the processor can be reduced.

[0251] In addition, in an example of the arithmetic processing device according to the present embodiment, the cache memory is By using a storage device in this state, the data stored in the cache memory according to the search data can be A function for selecting whether or not to output data can be added to the cache memory.

[0252] In addition, in the arithmetic processing device according to the present embodiment, when the supply of the power supply voltage is stopped, However, the cache memory retains some of the internal data that was there just before the power supply voltage was stopped. When the supply of power supply voltage is resumed, the state of the arithmetic processing unit can be maintained. Therefore, the supply of power supply voltage can be selectively stopped. Even if the power consumption is reduced by the power supply voltage, normal operation will not start until the power supply voltage is resumed. It can shorten the time it takes to

[0253] (Embodiment 6) In this embodiment, the c-axis is oriented and the crystal is triangular or triangular when viewed from the direction of the ab plane, the surface, or the interface. It has a hexagonal atomic arrangement, and the metal atoms are layered or the metal atoms and oxygen atoms are arranged in the c-axis. The layers are arranged in layers, and the orientation of the a-axis or b-axis is different on the ab plane (rotation around the c-axis). Next, oxides containing the CAAC phase will be described.

[0254] In a broad sense, oxides containing CAAC are non-single crystals that are not single crystals and are not uniform in size when viewed from the direction perpendicular to the ab plane. The atomic arrangement is triangular, hexagonal, equilateral triangular or equilateral hexagonal, and the direction perpendicular to the c-axis direction When viewed from the opposite direction, it is an oxide containing a phase in which metal atoms are arranged in layers, or metal atoms and oxygen atoms are arranged in layers. This refers to...

[0255] CAAC is not a single crystal, but it is not made up of only amorphous material. AC contains crystallized parts (crystalline parts), but the boundary between one crystalline part and another crystalline part is not clearly defined. Sometimes it's impossible to tell for sure.

[0256] When the CAAC contains oxygen, a part of the oxygen may be replaced with nitrogen. The c-axis of each crystalline part that constitutes the CAAC is in a certain direction (for example, the substrate surface on which the CAAC is formed, The CAAC may be aligned in a direction perpendicular to the surface of the CAAC. The normal to the ab plane of the crystalline part of the CAAC is in a certain direction (for example, the substrate surface on which the CAAC is formed, It may be oriented in a direction perpendicular to the surface of C, etc.

[0257] CAAC can be a conductor, a semiconductor, or an insulator depending on its composition. Depending on the composition, they may be transparent or opaque to visible light. Do it.

[0258] An example of such a CAAC is a film-like CAAC that is formed in a direction perpendicular to the film surface or the surface of a supporting substrate. When observed from the side, a triangular or hexagonal atomic arrangement is observed, and when the cross section of the film is observed, Crystals in which layered arrangement of metal atoms or metal atoms and oxygen atoms (or nitrogen atoms) is observed are listed below. It is also possible to do so.

[0259] An example of a crystal structure contained in CAAC will be described in detail with reference to FIGS. 10 to 12, the upward direction is the c-axis direction, and the direction perpendicular to the c-axis direction is the The plane where the two points are aligned is called the ab plane. When we simply refer to the upper half and the lower half, we are referring to the plane ab as the boundary. In Figure 10, the circled O represents a tetrahedral O, and the dihedral O represents a tetrahedral O. The circled O indicates a three-coordinate O.

[0260] Figure 10(A) shows one hexacoordinated In atom and six tetracoordinated oxygen atoms (hereafter referred to as 4) adjacent to the In atom. The structure shown has a metal atom and a nearby oxygen atom. The structure shown in Figure 10(A) is an octahedral structure, but it can be easily For simplicity, the structure is shown as a plane. Each group has four-coordinated O atoms. The small group shown in Figure 10(A) has a zero charge.

[0261] Figure 10(B) shows one pentacoordinate Ga atom and three tricoordinate oxygen atoms (hereafter referred to as 3) adjacent to the Ga atom. The structure shows a tricoordinate O and two adjacent tetracoordinate O. In the upper and lower halves of Figure 10(B), there is one tetracoordinate O atom. In addition, since In also takes five-coordinated positions, it can take the structure shown in Figure 10(B). The small group shown in B) has a charge of 0.

[0262] FIG. 10(C) shows a structure having one tetracoordinate Zn and four tetracoordinate O atoms adjacent to the Zn. The upper half of Figure 10(C) has one tetracoordinate O atom, and the lower half has three tetracoordinate O atoms. In addition, there are three 4-coordinate O atoms in the upper half of Figure 10(C), and one 4-coordinate O atom in the lower half. There may be a coordinated O. The small group shown in Figure 10(C) has a charge of 0.

[0263] FIG. 10(D) shows a structure having one hexacoordinated Sn atom and six tetracoordinated O atoms adjacent to the Sn atom. The upper half of Figure 10(D) has three tetracoordinate O atoms, and the lower half has three tetracoordinate O atoms. The small group shown in Figure 10(D) has a charge of +1.

[0264] Figure 10(E) shows a small group containing two Zn atoms. The upper half of Figure 10(E) shows one Zn atom. The small group shown in Figure 10(E) has four-coordinated O atoms, and one four-coordinated O atom in the lower half. has a charge of -1.

[0265] Here, a collection of multiple small groups is called a medium group, and a collection of multiple medium groups is called a This is called a large group (also called a unit cell).

[0266] Here, we will explain the rules for combining these small groups. The three O atoms in the upper half of the hexacoordinated In have three neighboring In atoms downward, and the three O atoms in the lower half Each O has three neighboring In atoms in the upward direction. One O atom in the upper half of the five-coordinate Ga atom is It has one adjacent Ga in the downward direction, and one O in the lower half has one adjacent Ga in the upward direction. One O atom in the upper half of the tetrahedral Zn atom has one neighboring Zn atom below it, and the three O atoms in the lower half have There are three neighboring Zn atoms in the upward direction. The number of O atoms is equal to the number of neighboring metal atoms below the O atom. The number of coordinated O atoms is equal to the number of neighboring metal atoms above the O atoms. Since O atoms are 4-coordinated, The sum of the number of neighboring metal atoms in the downward direction and the number of neighboring metal atoms in the upward direction is 4. The number of tetrahedral O atoms above a metal atom and the number of tetrahedral O atoms below another metal atom are When the sum of the numbers is 4, two small groups containing metal atoms can bond together. For example, a hexacoordinated metal atom (In or Sn) is bonded via a tetracoordinated O atom in the lower half. In this case, there are three tetracoordinated O atoms, so there are five-coordinated metal atoms (Ga or In) or four-coordinated gold atoms. It will bond to one of the group atoms (Zn).

[0267] Metal atoms with these coordination numbers are bonded in the c-axis direction via four-coordinated oxygen atoms. In addition, multiple small groups are bonded together so that the total charge of the layer structure is zero. Forms a medium group.

[0268] Figure 11(A) shows a model diagram of the middle group that constitutes the In-Sn-Zn-O system layer structure. Figure 11(B) shows a large group consisting of three medium groups. C) shows the atomic arrangement when the layer structure of FIG. 11(B) is observed from the c-axis direction.

[0269] In FIG. 11(A), for simplicity, the tricoordinate O atoms are omitted, and only the number of the tetracoordinate O atoms is shown. For example, the circled circle indicates that there are three tetrahedral O atoms in the upper and lower halves of Sn. Similarly, in FIG. 11(A), the upper and lower halves of In are Each has one tetracoordinate O atom, which is shown as a circled 1. Similarly, in Figure 11(A ) in which the lower half has one tetracoordinate O atom and the upper half has three tetracoordinate O atoms, Z n and Zn, which has one tetrahedral O atom in the upper half and three tetrahedral O atoms in the lower half. It shows.

[0270] In Fig. 11(A), the middle group, which is composed of the In-Sn-Zn-O system layer structure, is Sn has three tetrahedral O atoms in the upper half and one in the lower half, and Sn has one tetrahedral O atom in the upper half. The In bonds to the Zn with three tetracoordinate O atoms in the upper half. The Zn is bonded to the upper half and the lower half via one tetracoordinate O atom. It bonds to the In in the lower half, and the In is connected to two Zn atoms with one tetrahedral O in the upper half. The small group is bonded to a tetracoordinate O atom in the lower half of this small group. The structure is such that three O atoms are bonded to Sn atoms in the upper and lower halves. Multiple units are combined to form a large group.

[0271] Here, the charge per bond for the three-coordinated O and four-coordinated O is -0.66 7, -0.5. For example, In (6-coordinate or 5-coordinate), Zn (4-coordinate ), Sn (pentacoordinated or hexacoordinated) have charges of +3, +2, and +4, respectively. The small group containing n has a charge of +1. Therefore, to form a layer structure containing Sn, The charge -1 is required to cancel the charge +1. The structure that takes the charge -1 is shown in Figure 10 (E ) there is a small group containing two Zn atoms. For example, there is a small group containing Sn atoms. If there is one small group containing two Zn atoms for each group, the charges are cancelled out. , the total charge of the layer structure can be set to zero.

[0272] Specifically, the large group shown in Figure 11(B) is repeated to form In-Sn-Zn -O system crystal (In2SnZn3O8) can be obtained. -Zn-O system layer structure is In2SnZn2O7(ZnO) m (m is 0 or a natural number.) It can be expressed by the following composition formula:

[0273] In addition, there are also quaternary metal oxides, such as In-Sn-Ga-Zn-O metal oxides. and ternary metal oxides, such as In-Ga-Zn-O (also written as IGZO). ), In-Al-Zn-O based metal oxides, Sn-Ga-Zn-O based metal oxides, A In-Ga-Zn-O based metal oxides, Sn-Al-Zn-O based metal oxides, In-Hf- Zn-O metal oxide, In-La-Zn-O metal oxide, In-Ce-Zn-O gold Metal oxides, In-Pr-Zn-O metal oxides, In-Nd-Zn-O metal oxides, I n-Sm-Zn-O metal oxide, In-Eu-Zn-O metal oxide, In-Gd-Z nO-based metal oxides, In-Tb-Zn-O-based metal oxides, In-Dy-Zn-O-based metal oxides Oxides, In-Ho-Zn-O based metal oxides, In-Er-Zn-O based metal oxides, In -Tm-Zn-O metal oxide, In-Yb-Zn-O metal oxide, In-Lu-Zn -O-based metal oxides, binary metal oxides such as In-Zn-O-based metal oxides and Sn-Z nO metal oxide, Al-Zn-O metal oxide, Zn-Mg-O metal oxide, Sn -Mg-O based metal oxides, In-Mg-O based metal oxides, and In-Ga-O based metal oxides , In-O based metal oxides, Sn-O based metal oxides, Zn-O based metal oxides, The same applies when metal oxides or the like are used.

[0274] For example, Figure 12(A) shows a model of the middle group consisting of an In-Ga-Zn-O system layer structure. A diagram is shown.

[0275] In FIG. 12(A), the middle group, which is composed of an In-Ga-Zn-O-based layer structure, is In has three tetracoordinate O atoms in the upper half and three in the lower half, and one tetracoordinate O atom in the upper half. It bonds to a certain Zn, and through the three tetracoordinate O atoms in the lower half of the Zn, one tetracoordinate O atom is attached to each of the Zn atoms. It bonds to Ga atoms in the upper and lower halves of the two atoms, and through one tetracoordinate O atom in the lower half of the Ga atom. In this structure, three tetracoordinate O atoms are bonded to In atoms in the upper and lower halves. Multiple groups combine to form a larger group.

[0276] Figure 12(B) shows a large group consisting of three medium groups. 12(B) shows the atomic arrangement when the layer structure of FIG. 12(B) is observed from the c-axis direction.

[0277] Here, the charges of In (6- or 5-coordinate), Zn (4-coordinate), and Ga (5-coordinate) are respectively Since the electrons are +3, +2, and +3, the small group containing In, Zn, and Ga is Therefore, if these small groups are combined, the total of the medium groups will be The charge is always 0.

[0278] The middle group, which is composed of an In-Ga-Zn-O layer structure, is shown in FIG. Not limited to the middle group, large-sized compounds with different arrangements of In, Ga, and Zn are also available. Groups can also be taken.

[0279] (Embodiment 7) In this embodiment, the field-effect mobility of a transistor will be described.

[0280] The field-effect mobility of insulated gate transistors, not limited to oxide semiconductors, is actually measured as However, the mobility is lower than the original mobility due to various reasons. There are defects inside the semiconductor and defects at the interface between the semiconductor and the insulating film. Using this, we can theoretically derive the field effect mobility assuming that there are no defects inside the semiconductor. Can.

[0281] The intrinsic mobility of the semiconductor is μ0, and the measured field-effect mobility is μ. Assuming the existence of potential barriers (such as grain boundaries), this can be expressed by the following equation:

[0282]

number

[0283] where E is the height of the potential barrier, k is the Boltzmann constant, and T is the absolute temperature. Also, if we assume that the potential barrier originates from defects, the Levinson model gives , which is expressed by the following formula:

[0284]

number

[0285] where e is the elementary charge, N is the average defect density per unit area in the channel, and ε is the where n is the number of carriers contained in the channel per unit area, and Cox is the where V is the gate voltage and t is the channel thickness. In the case of a semiconductor layer, the thickness of the channel can be considered to be the same as the thickness of the semiconductor layer. The drain current Id is given by the following equation:

[0286]

number

[0287] Here, L is the channel length and W is the channel width, where L=W=10 μm. Also, Vd is the drain voltage. Dividing both sides of the above equation by Vg and then taking the logarithm of both sides gives , it becomes as follows:

[0288]

number

[0289] The right side of equation 5 is a function of Vg. As can be seen from this equation, the vertical axis is ln(Id / Vg), The defect density N can be calculated from the slope of the line with 1 / Vg on the horizontal axis. The defect density can be evaluated from the Id-Vg characteristics of the oxide semiconductor. In the case where the ratio of In, tin (Sn), and zinc (Zn) is In:Sn:Zn=1:1:1, The defect density N is 1×10 12 / cm 2 That's about it.

[0290] Based on the defect density thus obtained, equations 2 and 3 are used to calculate μ0 = 120 cm 2 / Vs The mobility measured in defective In-Sn-Zn oxide is 35 cm 2 / V However, oxide semiconductors without defects inside the semiconductor or at the interface between the semiconductor and the insulating film Body mobility μ0 is 120cm 2 It can be expected that / Vs.

[0291] However, even if there are no defects inside the semiconductor, scattering at the interface between the channel and the gate insulating layer can cause The transport properties of the transistor are affected by the interface between the channel and the gate insulating layer. The mobility μ1 at a distance x from the

[0292]

number

[0293] Here, D is the electric field in the gate direction, and B and G are constants. B and G are determined from actual measurement results. From the above measurement results, B = 4.75 × 10 7 cm / s, G=10n m (depth of interface scattering). As D increases (i.e., gate voltage increases), It can be seen that the mobility μ1 decreases because the second term in Equation 6 increases.

[0294] Mobility of a transistor using an ideal oxide semiconductor channel with no internal defects The calculation results for μ2 are shown in Figure 13. The calculation was performed using a Synopsys device simulator. Sentaurus Device, a software company, is used to measure the bandgap of oxide semiconductors. The top, electron affinity, relative permittivity, and thickness are set to 2.8 eV, 4.7 eV, and These values ​​were measured for thin films formed by sputtering. This was obtained by

[0295] Furthermore, the work functions of the gate, source, and drain are set to 5.5 eV and 4.6 eV, respectively. The gate insulating layer had a thickness of 100 nm and a relative dielectric constant of 4.6 eV. The channel length and width were both 10 μm, and the drain voltage Vd was 0. It is 1V.

[0296] As shown in Figure 13, the mobility is 100 cm at a gate voltage of just over 1 V. 2 / Vs or higher peak However, if the gate voltage is further increased, the interface scattering increases and the mobility decreases. In order to reduce interface scattering, the semiconductor layer surface must be flattened at the atomic level (At Omic Layer Flatness is desirable.

[0297] The characteristics of a miniaturized transistor fabricated using an oxide semiconductor with such mobility are as follows: The results of the calculation of the performance are shown in Figs. 14 to 16. The cross-sectional structure of the transistor used in the calculation The structure of the transistor shown in FIG. + Conductivity type of The semiconductor region 2103a and the semiconductor region 2103c are included. The resistivity of the conductor region 2103c is 2×10 -3 Let it be Ωcm.

[0298] The transistor shown in FIG. 17A includes a base insulating layer 2101 and a formed on a buried insulator 2102 made of aluminum oxide so as to be embedded therein The transistor is made up of a semiconductor region 2103a, a semiconductor region 2103c, and a semiconductor region sandwiched between them. The gate electrode 2103 has an intrinsic semiconductor region 2103 b that serves as a channel forming region, and a gate 2105 . The width of the gate 2105 is set to 33 nm.

[0299] Between the gate 2105 and the semiconductor region 2103b, there is a gate insulating layer 2104, On both sides of the gate 2105, there are sidewall insulators 2106a and 2106b. On top of 105, there is an insulator 2107 to prevent short circuits between the gate 2105 and other wiring. The width of the sidewall insulator is set to 5 nm. The source 2108a and the drain 2108b are connected to the transistor 2103c. The channel width of the transistor is set to 40 nm.

[0300] The transistor shown in FIG. 17B has a base insulating layer 2101 and a A semiconductor region 2103a and a semiconductor region 2103c are formed on the buried insulator 2102. and an intrinsic semiconductor region 2103b sandwiched between them, a gate 2105 having a width of 33 nm, and a gate electrode 2106. The sidewall insulator 2106a and the sidewall insulator 2106b are connected to the insulating layer 2104 and the insulating layer 2107. 17A in that it has a source 2108a and a drain 2108b. It is the same as .

[0301] The transistor shown in FIG. 17(A) differs from the transistor shown in FIG. 17(B) in that the sidewall insulation The conductivity type of the semiconductor region under the insulating layer 2106a and the sidewall insulating layer 2106b is shown in FIG. In the transistor shown in FIG. 21, the semiconductor under the sidewall insulator 2106a and the sidewall insulator 2106b is Body region is n + The semiconductor regions 2103a and 2103c have the same conductivity type. In the transistor shown in FIG. 17(B), it is the intrinsic semiconductor region 2103b. The semiconductor region 2103a (semiconductor region 2103c) and the gate 2105 overlap by Loff. This area is called the offset area, and its width Loff is the offset. As is clear from the figure, the offset length is the length of the sidewall insulator 2106a (sidewall insulator The width of the object 2106b is the same as that of the object 2106a.

[0302] The other parameters used in the calculation are as described above. We used the Sentaurus Device simulation software. The drain current (Id, solid line) and mobility ( The graph shows the gate voltage (Vg, the potential difference between the gate and source) dependence of the drain current (μ, dotted line). Id is the drain voltage (potential difference between the drain and source) of +1V, and the mobility μ is the drain The voltage is calculated as +0.1V.

[0303] FIG. 14(A) shows the gate insulating layer with a thickness of 15 nm, and FIG. 14(B) shows the gate insulating layer with a thickness of 10 nm. In Figure 14(C), the thickness is set to 5 nm. The drain current Id (off-state current) in the off state is significantly reduced as the mobility There is no noticeable change in the peak value of μ or the drain current Id (on-state current) in the on-state. It was shown that the drain current exceeded 10 μA at a gate voltage of around 1 V.

[0304] FIG. 15 shows a transistor having the structure shown in FIG. 17(B), in which the offset length Loff is set to 5n Dependence of drain current Id (solid line) and mobility μ (dotted line) on gate voltage Vg for m The drain current Id is calculated by setting the drain voltage to +1V, and the mobility μ is calculated by setting the drain voltage to + The calculation was performed with the gate insulating layer thickness set to 15 nm. FIG. 15(B) shows the result when the thickness is 10 nm, and FIG. 15(C) shows the result when the thickness is 5 nm. It is something.

[0305] FIG. 16 shows the offset length Loff of the transistor having the structure shown in FIG. 17(B). The gate voltage dependence of the drain current Id (solid line) and mobility μ (dotted line) for a 15 nm thick silicon substrate The drain current Id is the drain voltage +1 V, and the mobility μ is the drain voltage The calculation was performed with the gate insulating layer thickness set to 15 nm. FIG. 16(B) shows the thickness at 10 nm, and FIG. 16(C) shows the thickness at 5 nm. This is what was done.

[0306] In both cases, the thinner the gate insulating layer, the more significantly the off-state current decreases, while the peak of the mobility μ decreases. There is no noticeable change in the on-state current or the on-state voltage.

[0307] The peak of the mobility μ is 80 cm in FIG. 2 / Vs, but in Figure 15, cm 2 / Vs, 40cm in Figure 16 2 As / Vs and offset length Loff increase, The off-current also shows a similar trend. On the other hand, the on-current decreases with increasing offset length Lo It decreases as ff increases, but the decrease is much slower than the decrease in off-state current. In addition, it was shown that the drain current exceeded 10 μA at a gate voltage of around 1 V. .

[0308] (Embodiment 8) In this embodiment, an oxide semiconductor containing In, Sn, and Zn as main components is used. The transistors used will be explained.

[0309] A transistor with a channel formation region made of an oxide semiconductor containing In, Sn, and Zn as its main components is The oxide semiconductor film is formed by heating the substrate. By performing heat treatment after forming the film, good properties can be obtained. An element that is contained in an amount of 5 atomic % or more by composition ratio.

[0310] Intentionally heating the substrate after forming an oxide semiconductor film containing In, Sn, and Zn as its main components This makes it possible to improve the field effect mobility of the transistor. This makes it possible to shift the threshold voltage in the positive direction and make the device normally off.

[0311] For example, FIGS. 18(A) to 18(C) show a semiconductor device with a channel length L of 3 μm and containing In, Sn, and Zn as the main components. The oxide semiconductor film has a channel width W of 10 μm and a gate insulating layer with a thickness of 100 nm. These are the characteristics of the transistor used. Vd was set to 10V.

[0312] Figure 18(A) shows the deposition of In, Sn, and Zn as the main components by sputtering without intentionally heating the substrate. The figure shows the transistor characteristics when an oxide semiconductor film having the above structure is formed. The degree is 18.8cm 2 On the other hand, by intentionally heating the substrate, In, S When an oxide semiconductor film containing n or Zn as a main component is formed, the field-effect mobility can be improved. Fig. 18(B) shows the formation of a thin film of In, Sn, and Zn by heating the substrate to 200°C. The transistor characteristics when an oxide semiconductor film is formed are shown. The field-effect mobility is 32.2 cm 2 / Vsec is obtained.

[0313] The field effect mobility was measured by forming an oxide semiconductor film mainly composed of In, Sn, and Zn and then performing a heat treatment. Fig. 18(C) shows the results of the ion implantation of In, Sn, and Zn. After sputtering at 200°C, an oxide semiconductor film containing SiO2 as the main component was heat-treated at 650°C. The transistor characteristics are shown below. In this case, the field effect mobility is 34.5 cm 2 / V sec is obtained.

[0314] By intentionally heating the substrate, moisture is absorbed into the oxide semiconductor film during sputtering. In addition, by performing heat treatment after film formation, the effect of reducing the amount of oxidation can be expected. Hydrogen, hydroxyl groups, or moisture can be released and removed from the oxide semiconductor film. This improvement in field-effect mobility can be achieved by dehydration. Not only do impurities get removed by hydrogenation and dehydrogenation, but the interatomic distance gets shorter due to the increased density. It is also estimated that crystallization can be promoted by removing impurities from an oxide semiconductor and purifying it. Such a highly purified non-single-crystal oxide semiconductor can be ideally 0cm 2 It is estimated that it will be possible to achieve a field-effect mobility of more than 1 / Vsec.

[0315] Oxygen ions are implanted into an oxide semiconductor whose main components are In, Sn, and Zn, and the oxide is then converted into a The hydrogen, hydroxyl groups, or moisture contained in the compound semiconductor is released, and the heat treatment is performed simultaneously or in addition to the heat treatment. The oxide semiconductor may be crystallized by subsequent heat treatment. By the crystallization treatment, a non-single-crystal oxide semiconductor with good crystallinity can be obtained.

[0316] The effect of intentionally heating the substrate during film deposition and / or heat treatment after film deposition is This not only improves the effective mobility but also contributes to making the transistor normally off. The oxide semiconductor, which is mainly composed of In, Sn, and Zn, was formed without intentionally heating the substrate. The threshold voltage of a transistor with a conductive film as the channel formation region shifts negatively. However, when an oxide semiconductor film formed by intentionally heating a substrate is used, In this case, the negative shift of the threshold voltage is eliminated. This tendency is shown in Figure 18(A) and Figure 18(B). ) can also be confirmed by comparing

[0317] The threshold voltage can also be controlled by changing the ratio of In, Sn, and Zn. It is possible to achieve a transistor noise by using a composition ratio of In:Sn:Zn=2:1:3. Furthermore, the target composition ratio is In:Sn:Zn By adjusting the ratio of SiO 2 to ... =2:1:3, an oxide semiconductor film with high crystallinity can be obtained.

[0318] The intentional substrate heating temperature or heat treatment temperature is 150°C or higher, preferably 200°C or higher. The temperature is preferably 400°C or higher, and film formation or heat treatment at higher temperatures can improve the This makes it possible to make the resistor normally off.

[0319] In addition, by intentionally heating the substrate during film formation and / or by performing heat treatment after film formation, it is possible to It can improve the stability against as stress. For example, 2MV / cm, 150℃ , and 1 hour application conditions, the drift is less than ±1.5V, preferably 1.0V You can get less than that.

[0320] In fact, Sample 1 was not subjected to heat treatment after the oxide semiconductor film was formed, and Sample 2 was subjected to heat treatment at 650° C. The BT test was carried out on the transistor of sample 2 that had undergone the above.

[0321] First, the substrate temperature was set to 25°C, Vd was set to 10V, and the Vg-Id characteristics of the transistor were measured. Next, the substrate temperature was set to 150°C and Vd was set to 0.1 V. Next, the gate insulating layer was Apply 20V to Vg so that the applied electric field strength is 2MV / cm, and leave it as it is for 1 hour. Next, Vg was set to 0 V. Next, the substrate temperature was set to 25°C, Vd was set to 10 V, and the temperature was The Vg-Id of the transistor was measured, which is called the Plus BT test.

[0322] Similarly, first set the substrate temperature to 25°C, Vd to 10V, and measure the Vg-Id characteristics of the transistor. Next, the substrate temperature was set to 150°C and Vd was set to 0.1V. Apply -20V to Vg so that the electric field strength applied to the insulating layer is -2MV / cm. The substrate temperature was then increased to 25°C and Vd was increased to 1. The Vg-Id of the transistor was measured at 0 V. This is called a negative BT test.

[0323] The results of the positive BT test for sample 1 are shown in Figure 19(A), and the results of the negative BT test are shown in Figure 19(B). The results of the positive BT test for sample 2 are shown in Figure 20(A), and the results of the negative BT test for sample 2 are shown in Figure 20(B). The results are shown in Figure 20(B).

[0324] The threshold voltage fluctuations of sample 1 due to the positive BT test and the negative BT test were 1 The positive and negative BT tests for sample 2 were 0.80V and -0.42V. The threshold voltage fluctuations due to the experiment were 0.79 V and 0.76 V, respectively. Both sample 1 and sample 2 showed small fluctuations in threshold voltage before and after the BT test, demonstrating high reliability. We can see that.

[0325] The heat treatment can be carried out in an oxygen atmosphere, but it is first necessary to carry out the heat treatment in a nitrogen or inert gas atmosphere, or under reduced pressure. It is also possible to perform heat treatment in an atmosphere containing oxygen after performing heat treatment in an atmosphere containing oxygen. Adding oxygen to the oxide semiconductor after oxidation can enhance the effect of the heat treatment. To add oxygen later, oxygen ions can be accelerated by an electric field and then added to the oxide semiconductor film. An injection method may also be applied.

[0326] Defects due to oxygen vacancies are likely to occur in oxide semiconductors and at the interface with the stacked films. By such heat treatment, excess oxygen is contained in the oxide semiconductor, and thus the oxide semiconductor is steadily generated. The excess oxygen mainly exists in the interstitial The oxygen present in the atmosphere is 1×10 16 / cm 3 Over 2×10 20 / cm 3 If the following conditions are met, the compound can be contained in the oxide semiconductor without causing distortion to the crystal. .

[0327] Furthermore, by making the oxide semiconductor contain crystals at least in part by heat treatment, For example, when the composition ratio of In:Sn:Zn=1, a more stable oxide semiconductor film can be obtained. Oxide film sputtered using a 1:1 ratio target without intentionally heating the substrate. The semiconductor film was analyzed by X-ray diffraction (XRD) to find a halo pattern. The oxide semiconductor film thus formed is crystallized by heat treatment. The heat treatment temperature can be any temperature, but for example, by performing heat treatment at 650°C, X-ray A clear diffraction peak can be observed by diffraction.

[0328] In fact, XRD analysis of the In-Sn-Zn-O film was carried out. Using the AXS D8 ADVANCE X-ray diffractometer, the out-of-plane method was used. Measured.

[0329] Samples A and B were prepared for XRD analysis. The method for producing the above will be described.

[0330] An In-Sn-Zn-O film was formed to a thickness of 100 nm on a dehydrogenated quartz substrate. .

[0331] The In-Sn-Zn-O film was prepared by sputtering in an oxygen atmosphere at a power of 100 W ( The target was In:Sn:Zn=1:1:1 [atomic ratio]. An n-Sn-Zn-O target was used. The substrate heating temperature during film formation was 200°C. The sample prepared in this manner was designated as Sample A.

[0332] Next, a sample prepared in the same manner as sample A was subjected to heat treatment at a temperature of 650°C. The heat treatment is first performed in a nitrogen atmosphere for 1 hour, and then in an oxygen atmosphere without lowering the temperature. The sample was then subjected to a further heat treatment for 1 hour. The sample thus prepared was designated as sample B.

[0333] Figure 23 shows the XRD spectra of sample A and sample B. In sample A, the peaks derived from crystals In sample B, 2θ was observed at around 35 deg and 37 deg to 38 deg. A peak derived from crystals was observed.

[0334] In this way, oxide semiconductors containing In, Sn, and Zn as their main components are intentionally heated during film formation. and / or by performing heat treatment after film formation, the characteristics of the transistor can be improved. Cut.

[0335] This substrate heating and heat treatment removes hydrogen and hydroxyl groups, which are harmful impurities for oxide semiconductors, from the film. It has the effect of preventing oxides from being included in the film or removing them from the film. High purity can be achieved by removing hydrogen, which acts as a donor impurity in semiconductors. This allows the transistor to be normally off, and the oxide semiconductor is highly purified. By doing so, the off-current can be reduced to 1 aA / μm or less. The unit indicates the current value per 1 μm of channel width.

[0336] Figure 24 shows the relationship between the off-state current of a transistor and the reciprocal of the substrate temperature (absolute temperature) at the time of measurement. For simplicity, we use the value obtained by multiplying the reciprocal of the substrate temperature at the time of measurement by 1000 (1000 / T) is the horizontal axis.

[0337] Specifically, as shown in FIG. 24, when the substrate temperature is 125° C., the current is 1 aA / μm (1×1 0 -18 A / μm) or less, and at 85°C it is 100zA / μm (1×10 -19 A / μm ) or less, and at room temperature (27°C), it is 1zA / μm (1×10 -21 A / μm or less Preferably, the current is 0.1 aA / μm (1×10 -19 A / μ m) or less at 85°C, -20 A / μm) at room temperature 0.1zA / μm (1×10 -22 These can be made to be less than 1 / μm. The off-state current is extremely low compared to that of a transistor using Si as a semiconductor film. It is clear that

[0338] However, in order to prevent hydrogen and moisture from being mixed into the oxide semiconductor film during the film formation, Leaks from the chamber and outgassing from the inner walls of the deposition chamber are sufficiently suppressed, resulting in high purity sputtering gas. For example, it is preferable that the sputtering gas has a dew point of -70°C or lower so that moisture is not contained in the film. It is preferable to use a gas that is below the target limit. It is preferable to use a target that has been highly purified so that it does not contain any impurities. Oxide semiconductors whose main components are In, Sn, and Zn can be thermally treated to remove moisture from the film. However, the temperature at which moisture is released is higher than that of oxide semiconductors whose main components are In, Ga, and Zn. Therefore, it is preferable to form a film that does not contain moisture from the beginning.

[0339] In addition, in the sample transistor that was subjected to heat treatment at 650° C. after the oxide semiconductor film was formed, The relationship between the substrate temperature and the electrical characteristics was evaluated.

[0340] The transistor used for the measurement has a channel length L of 3 μm, a channel width W of 10 μm, and Lov The Vd was set to 10 V. The substrate temperature was -40°C. The test was carried out at temperatures of -25°C, 25°C, 75°C, 125°C and 150°C. In this case, the overlap width between the gate electrode and the pair of electrodes is called Lov, and the overlap width with respect to the oxide semiconductor film is called Lov. The protrusion of the pair of electrodes is called dW.

[0341] Figure 21 shows the Vg dependence of Id (solid line) and field-effect mobility (dotted line). (A) shows the relationship between the substrate temperature and the threshold voltage, and (B) shows the relationship between the substrate temperature and the field-effect mobility. Show the relationship.

[0342] From FIG. 22(A), it can be seen that the higher the substrate temperature, the lower the threshold voltage. The range was 1.09V to -0.23V from -40℃ to 150℃.

[0343] Furthermore, it can be seen from FIG. 22(B) that the higher the substrate temperature, the lower the field effect mobility. The temperature range is -40℃ to 150℃ and is 36cm 2 / Vs~32cm 2 / Vs. Therefore, it can be seen that the fluctuations in the electrical characteristics are small within the above temperature range.

[0344] The above-mentioned oxide semiconductor containing In, Sn, and Zn as its main components is used for the channel formation region. According to the transistor, the field effect mobility is 30c while keeping the off current below 1aA / μm. m 2 / Vsec or more, preferably 40cm 2 / Vsec or more, preferably 60cm 2 / Vsec or more, and the on-current value required by the LSI can be satisfied. For example, A FET with L / W=33nm / 40nm, gate voltage 2.7V, drain voltage 1.0V When the on-state current is 12 μA or more, the on-state current required for transistor operation can be Even in a wide temperature range, sufficient electrical characteristics can be ensured. For example, a transistor made of oxide semiconductor is embedded in an integrated circuit made of silicon semiconductor. Even if the chip size is small, it is possible to realize an integrated circuit with new functions without sacrificing operating speed. Cut.

[0345] An example of a transistor using an In-Sn-Zn-O film as an oxide semiconductor film is shown below. explain.

[0346] Figure 25 shows the top of a coplanar top-gate / top-contact transistor. FIG. 25(A) shows a top view of a transistor. ) shows a cross section AB corresponding to the dashed line AB in FIG. 25(A).

[0347] The transistor shown in FIG. 25B includes a substrate 1200 and a base film provided over the substrate 1200. An insulating layer 1202, a protective insulating film 1204 provided around the base insulating layer 1202, and a base insulating film A high resistance region 1206a and a low resistance region 1206b are provided on the insulating layer 1202 and the protective insulating film 1204. The oxide semiconductor film 1206 having the region 1206b and the oxide semiconductor film 1206 a gate insulating layer 1208 formed on the oxide semiconductor film 1206 and a gate insulating layer 1208 formed on the oxide semiconductor film 1206 with the gate insulating layer 1208 interposed therebetween; The gate electrode 1210 is provided so as to overlap with the gate electrode 1210. a pair of electrodes provided in contact with at least the low resistance region 1206b; a gate electrode 1214, at least an oxide semiconductor film 1206, a gate electrode 1210, and a pair of electrodes An interlayer insulating film 1216 is provided to cover the insulating film 1214, and an opening is provided in the insulating film 1216. a wiring 1218 provided so as to be connected to at least one of the pair of electrodes 1214 through the opening; , has.

[0348] Although not shown, a protective film is provided to cover the interlayer insulating film 1216 and the wiring 1218. By providing the protective film, the surface conduction of the interlayer insulating film 1216 can be prevented. This can reduce the minute leakage current that occurs due to the gate insulating film, and reduce the off-state current of the transistor. This can be done.

[0349] In addition, a transistor using an In-Sn-Zn-O film as an oxide semiconductor film, which is different from the above, Another example will be shown.

[0350] 26A and 26B are a top view and a cross-sectional view illustrating the structure of a transistor. 26(B) is a cross-sectional view corresponding to the dashed line AB in FIG. 26(A). FIG.

[0351] The transistor shown in FIG. 26B includes a substrate 1600 and a base film provided over the substrate 1600. The insulating layer 1602, the oxide semiconductor film 1606 provided over the base insulating layer 1602, and the oxide semiconductor film 1606 a pair of electrodes 1614 in contact with the oxide semiconductor film 1606; A gate insulating layer 1608 is provided on the electrode 1614, and an oxide film is formed on the gate insulating layer 1608. A gate electrode 1610 is provided so as to overlap the nitride semiconductor film 1606, and a gate insulating layer 160 8 and the gate electrode 1610, and an interlayer insulating film 1616 provided to cover the interlayer insulating film 161 6, a wiring 1618 connected to a pair of electrodes 1614 through an opening provided in the and a protective film 1620 provided to cover the film 1616 and the wiring 1618.

[0352] The substrate 1600 is a glass substrate, the base insulating layer 1602 is a silicon oxide film, and the base insulating layer 1602 is an acid film. The compound semiconductor film 1606 is an In—Sn—Zn—O film, and the pair of electrodes 1614 is A tungsten film is used as the gate insulating layer 1608, a silicon oxide film is used as the gate electrode 161 0 is a laminated structure of a tantalum nitride film and a tungsten film, and The layer structure is a silicon oxynitride film and a polyimide film, and the wiring 1618 is a titanium film. The protective film 1620 is a laminated structure in which an aluminum film and a titanium film are formed in this order. A polyethyleneimide film was used, respectively.

[0353] In the transistor having the structure shown in FIG. 26A, the gate electrode 1610 and the pair of electrodes The overlapping width with the electrode 1614 is called Lov. The protrusion of the paired electrode 1614 is called dW.

[0354] (Embodiment 9) In this embodiment, an example of an electronic device including the arithmetic processing device in the above embodiment will be described. explain.

[0355] Configuration examples of electronic devices in this embodiment will be described with reference to FIGS. 9A to 9D. Reveal.

[0356] The electronic device shown in Fig. 9(A) is an example of a portable information terminal. The terminal includes a housing 1001a and a display unit 1002a provided in the housing 1001a. do.

[0357] The side surface 1003a of the housing 1001a is provided with a connection terminal for connecting to an external device, and the One or more of the buttons for operating the portable information terminal shown in A) may be provided. .

[0358] The portable information terminal shown in FIG. 9A includes a CPU, a memory circuit, and an external The interface that transmits and receives signals between the internal equipment and the CPU and memory circuit, and the and an antenna for transmitting and receiving signals.

[0359] The portable information terminal shown in FIG. 9(A) is, for example, a telephone, an electronic book, a personal computer, or the like. , and has the function of one or more of a gaming machine.

[0360] The electronic device shown in FIG. 9(B) is an example of a folding portable information terminal. The portable information terminal includes a housing 1001b and a display unit 1002b provided in the housing 1001b. a housing 1004; a display unit 1005 provided on the housing 1004; a housing 1001b; and a shaft portion 1006 that connects to the housing 1004.

[0361] In addition, in the portable information terminal shown in FIG. 9B, the shaft portion 1006 is attached to the housing 1001b or the housing 1001c. By moving the body 1004, the housing 1001b can be superimposed on the housing 1004. do.

[0362] Note that an external device is connected to a side surface 1003b of the housing 1001b or a side surface 1007 of the housing 1004. 9(B) and a button cell for operating the portable information terminal shown in FIG. One or more may be provided.

[0363] Also, the display unit 1002b and the display unit 1005 may display different images or a series of images. The display unit 1005 does not necessarily have to be provided. Alternatively, a keyboard may be provided as an input device.

[0364] The portable information terminal shown in FIG. 9B includes a CPU and a processor in a housing 1001b or a housing 1004. , a memory circuit, and an interface for transmitting and receiving signals between an external device and the CPU and memory circuit The portable information terminal shown in FIG. 9(B) is provided with a An antenna may also be provided.

[0365] The portable information terminal shown in FIG. 9(B) is, for example, a telephone, an electronic book, a personal computer, or the like. , and has the function of one or more of a gaming machine.

[0366] The electronic device shown in Fig. 9(C) is an example of a stationary information terminal. The terminal includes a housing 1001c and a display unit 1002c provided in the housing 1001c. do.

[0367] The display unit 1002c may be provided on the deck 1008 of the housing 1001c. do.

[0368] The stationary information terminal shown in FIG. 9C includes a CPU and a memory circuit in a housing 1001c. and an interface for transmitting and receiving signals between an external device and the CPU and memory circuit. In addition, the stationary information terminal shown in FIG. 9(C) is provided with an antenna for transmitting and receiving signals to and from the outside. It may be provided.

[0369] Furthermore, a ticket is attached to a side surface 1003c of a housing 1001c of the stationary information terminal shown in FIG. 9(C). One or more of a ticket output unit, a coin insertion unit, and a bill insertion unit that output the above may be provided.

[0370] The stationary information terminal shown in FIG. 9(C) is, for example, an automatic teller machine, a device for ordering tickets, etc. It functions as an information and communication terminal (also called a multimedia station) for Has.

[0371] 9(D) is an example of a stationary information terminal. The stationary information terminal shown in FIG. 9(D) has a housing 1 1001d and a display unit 1002d provided on the housing 1001d. A support stand may be provided to support 1001d.

[0372] The side surface 1003d of the housing 1001d is provided with a connection terminal for connecting to an external device, and One or more buttons for operating the installed information terminal shown in D) may be provided. .

[0373] The stationary information terminal shown in FIG. 9(D) includes a CPU and a memory circuit in a housing 1001d. and an interface for transmitting and receiving signals between an external device and the CPU and memory circuit. It should be noted that the stationary information terminal shown in FIG. 9(D) may be provided with an amplifier for transmitting and receiving signals to and from the outside. A tena may be provided.

[0374] The stationary information terminal shown in FIG. 9(D) is, for example, a digital photo frame, a monitor, or a television. It functions as a vision device.

[0375] The arithmetic processing device of the above embodiment may be a CPU of the electronic device shown in FIGS. 9(A) to 9(D). It is used as follows.

[0376] As described with reference to FIG. 9, an example of the electronic device according to the present embodiment includes a CPU. This configuration includes the arithmetic processing device according to the embodiment.

[0377] By using the above configuration, even if power is not supplied, the information in the electronic device can be periodically This allows the time from power supply to normal operation to start quickly. This also reduces power consumption. [Explanation of symbols]

[0378] 101 Comparison circuit 102 Comparison circuit 111 Transistor 112 transistors 121 Transistor 122 transistors 131 Transistor 201 memory cells 202 Transistor 203 Transistor 204 buffer 205 buffers 600 Device formation layer 601 Conductive layer 602 Insulation layer 603 Semiconductor layer 604a area 604b area 605a Conductive layer 605b conductive layer 606 Insulation Layer 608 Conductive layer 751 Conductive layer 752 Insulation layer 752a area 752b area 753 Semiconductor Layer 754a conductive layer 754b Conductive layer 755 Insulation Layer 756 Conductive Layer 757a Insulating layer 757b Insulating layer 758 Insulation Layer 759 Insulation Layer 760a Conductive layer 760b conductive layer 761a Insulating layer 761b Insulating layer 780 Semiconductor Layer 781a Insulation Area 781b Insulation Area 781c Insulation Area 782a area 782b area 782c area 782d area 783a area 783b area 784a Insulating layer 784b Insulating layer 785a conductive layer 785b Conductive layer 786a Insulating layer 786b Insulating layer 786c Insulating layer 786d Insulating layer 788 Insulation Layer 801 bus interface 802 control device 803 Cache Memory 804 Register 805 instruction decoder 806 Arithmetic Logic Unit 1001a housing 1001b housing 1001c case 1001d case 1002a Display section 1002b Display section 1002c Display section 1002d Display section 1003a side 1003b Side 1003c side 1003d side 1004 Case 1005 Display section 1006 Shaft 1007 Side 1008 Deck section 1200 board 1202 Undercoat insulation layer 1204 Protective insulating film 1206 Oxide semiconductor film 1206a High resistance area 1206b Low resistance region 1208 Gate insulating layer 1210 Gate electrode 1212 Sidewall insulating film 1214 Electrode 1216 Interlayer insulating film 1218 Wiring 1600 board 1602 Undercoat insulation layer 1606 Oxide semiconductor film 1608 Gate insulating layer 1610 Gate electrode 1614 Electrode 1616 Interlayer insulating film 1618 Wiring 1620 Protective film 2101 Undercoat insulation layer 2102 Insulators 2103a Semiconductor area 2103b Semiconductor area 2103c Semiconductor field 2104 Gate insulating layer Gate 2105 2106a Sidewall insulator 2106b Sidewall insulator 2107 Insulators 2108a Source 2108b Drain

Claims

1. a first transistor and a second transistor; a semiconductor device in which one of a source electrode or a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor, the first transistor has a channel formation region in an oxide semiconductor layer; a first conductive layer functioning as a gate electrode of the first transistor has a region disposed above the oxide semiconductor layer; a second conductive layer functioning as one of a source electrode and a drain electrode of the first transistor has a region disposed above the oxide semiconductor layer; a third conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor has a region disposed above the oxide semiconductor layer; the first conductive layer, the second conductive layer, and the third conductive layer have regions disposed below a first insulating layer; a fourth conductive layer having a region disposed above the second conductive layer via the first insulating layer, the fourth conductive layer always being electrically connected to the second conductive layer; a fifth conductive layer having a function as a gate electrode of the second transistor has a region disposed below the second conductive layer; the oxide semiconductor layer has a region disposed above a second insulating layer having a region facing a side surface of the fifth conductive layer; a region of the second conductive layer that contacts the fourth conductive layer overlaps with the fifth conductive layer; Semiconductor device.

2. a first transistor, a second transistor, and a capacitor; the capacitance element is always electrically connected to the gate electrode of the second transistor; a semiconductor device in which one of a source electrode or a drain electrode of the first transistor is always electrically connected to a gate electrode of the second transistor, the first transistor has a channel formation region in an oxide semiconductor layer; a first conductive layer functioning as a gate electrode of the first transistor has a region disposed above the oxide semiconductor layer; a second conductive layer functioning as one of a source electrode and a drain electrode of the first transistor has a region disposed above the oxide semiconductor layer; a third conductive layer functioning as the other of the source electrode and the drain electrode of the first transistor has a region disposed above the oxide semiconductor layer; the first conductive layer, the second conductive layer, and the third conductive layer have regions disposed below a first insulating layer; a fourth conductive layer having a region disposed above the second conductive layer via the first insulating layer, the fourth conductive layer always being electrically connected to the second conductive layer; a fifth conductive layer having a function as a gate electrode of the second transistor has a region disposed below the second conductive layer; the oxide semiconductor layer has a region disposed above a second insulating layer having a region facing a side surface of the fifth conductive layer; a region of the second conductive layer that contacts the fourth conductive layer overlaps with the fifth conductive layer; Semiconductor device.

3. In claim 1 or claim 2, a region of the oxide semiconductor layer that overlaps with the first conductive layer is separated from a region of the oxide semiconductor layer that overlaps with the second conductive layer in a cross-sectional view of the first transistor in a channel length direction; a region of the oxide semiconductor layer overlapping with the first conductive layer is separated from a region of the oxide semiconductor layer overlapping with the third conductive layer in a cross-sectional view of the first transistor in a channel length direction; Semiconductor device.

4. In any one of claims 1 to 3, the oxide semiconductor layer contains an In—O-based metal oxide; Semiconductor device.

Images