Seed substrate and method for manufacturing group iii nitride semiconductor

Abstract

To provide a method for manufacturing a group III nitride semiconductor, capable of increasing the area of a group III nitride semiconductor to be grown.SOLUTION: A method for manufacturing a group III nitride semiconductor comprises: a substrate preparation step of preparing a seed substrate 9 including a plurality of seed crystals 2 consisting of a group III nitride semiconductor and discretely arranged on a substrate 1; and a crystal growth step of contacting the seed crystals 2 to a melt containing alkali metal and group III metal to dissolve nitrogen in the melt and grow a group III nitride semiconductor on the seed crystal 2. The plurality of seed crystals 2 are arranged in an arrangement area 10 having a predetermined planar pattern; and the arrangement area 10 has a hexagonal area 11 and an expansion area 12 continued on two sides at least adjacent to each other in the sides 11a of the hexagonal area 11, expanding an area on the outside of the hexagonal area 11 and being a planar pattern having sides parallel to the continued sides.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a seed substrate and a method for manufacturing a Group III nitride semiconductor. [Background technology]

[0002] The Na flux method is a well-known method for producing GaN. In the Na flux method, nitrogen is dissolved in a molten mixture of Ga and Na to grow GaN in the liquid phase. In the Na flux method, a seed substrate is generally placed in the molten mixture and GaN is grown on the seed substrate.

[0003] In the Na flux method, a method using a multi-point seed (MPS) substrate as a seed substrate is known as a method for growing large-area GaN crystals with low dislocation density and warpage. An MPS substrate has many tiny dot-shaped seed crystals periodically arranged on a substrate such as sapphire.

[0004] Patent Document 1 describes that the seed crystal placement region on an MPS substrate is the interior of a circle or a regular hexagon. It describes that when the seed crystal placement region is a circle, minute irregularities are formed on part of the periphery of the grown GaN, which can cause breakage or cracking. On the other hand, it describes that when the seed crystal placement region is a regular hexagon, the periphery of the grown GaN can be made linear, which can suppress breakage or cracking. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2020-132475 Summary of the Invention [Problem to be solved by the invention]

[0006] However, when the seed crystal is arranged inside a regular hexagon as in Patent Document 1, the unevenness of the outer periphery of the grown GaN can be reduced, but the area of ​​the GaN becomes small.

[0007] The present invention has been made in view of the above background, and aims to provide a method for producing a Group III nitride semiconductor, and a seed substrate, which enable the area of ​​the grown Group III nitride semiconductor to be increased. [Means for solving the problem]

[0008] One aspect of the present invention is a substrate preparation step of preparing a seed substrate having a plurality of seed crystals made of a Group III nitride semiconductor discretely arranged on a substrate; a crystal growth step of contacting the seed crystal with a melt containing an alkali metal and a Group III metal, dissolving nitrogen in the melt, and growing a Group III nitride semiconductor on the seed crystal, the plurality of seed crystals are arranged within an arrangement region having a predetermined planar pattern; The placement area is a hexagonal region of a hexagon; and an extended region which is a planar pattern that is continuous with at least two adjacent sides of the hexagonal region, extends the region outside the hexagonal region, and has sides parallel to the one side.

[0009] Another aspect of the present invention is A substrate; a plurality of seed crystals made of a Group III nitride semiconductor, the seed crystals being discretely arranged on the substrate; the plurality of seed crystals are arranged within an arrangement region having a predetermined planar pattern; The placement area is a hexagonal region of a hexagon; and an expanded region which is a planar pattern that is continuous with at least two adjacent sides of the hexagonal region, expands the region outside the hexagonal region, and has sides parallel to the continuous sides. [Effects of the Invention]

[0010] In the above embodiment, the arrangement region has a hexagonal region and an extended region that is a planar pattern that is continuous with at least two adjacent sides of the hexagonal region, extends the region outside the hexagonal region, and has sides parallel to one side, thereby increasing the area of ​​the grown Group III nitride semiconductor.

[0011] As described above, according to the above aspects, it is possible to provide a method for producing a Group III nitride semiconductor and a seed substrate that enable the area of ​​the grown Group III nitride semiconductor to be increased. [Brief explanation of the drawings]

[0012] [Figure 1] 1 is a cross-sectional view showing the configuration of a seed substrate in Embodiment 1, the cross-section being perpendicular to the main surface of the substrate. [Figure 2] FIG. 2 is a plan view of the seed substrate according to the first embodiment, viewed from above. [Figure 3] FIG. 2 is a plan view showing a seed crystal arrangement region of the seed substrate in the first embodiment. [Figure 4] 1A to 1C are diagrams showing the manufacturing process of a Group III nitride semiconductor. [Figure 5] A schematic diagram of the FFC process. [Figure 6] A diagram showing the planar pattern of a crystal. [Figure 7] FIG. 10 is a plan view of a seed substrate according to a second embodiment, viewed from above. [Figure 8] FIG. 11 is a plan view of a seed substrate according to a third embodiment, viewed from above. DETAILED DESCRIPTION OF THE INVENTION

[0013] The method includes a substrate preparation step of preparing a seed substrate having a plurality of seed crystals made of a Group III nitride semiconductor discretely arranged on the substrate, and a crystal growth step of bringing the seed crystals into contact with a melt containing an alkali metal and a Group III metal, dissolving nitrogen in the melt, and growing a Group III nitride semiconductor on the seed crystals, wherein the plurality of seed crystals are arranged within an arrangement region having a predetermined planar pattern, and the arrangement region has a hexagonal region and an extended region having a planar pattern of sides that are continuous with at least two adjacent sides of the hexagonal region, extend the region outside the hexagonal region, and have sides that are parallel to the continuous sides.

[0014] In the method for producing a Group III nitride semiconductor, the planar pattern of the expansion region may be a trapezoid, and the bottom of the trapezoid may overlap with a side of the hexagonal region. By forming the expansion region in such a pattern, the area of ​​the Group III nitride semiconductor to be grown can be made larger.

[0015] In the method for producing a Group III nitride semiconductor, the legs of the trapezoid may coincide with the m-plane of the seed crystal, thereby reducing irregularities on the periphery of the grown Group III nitride semiconductor.

[0016] In the method for producing a Group III nitride semiconductor, the length of the bottom of the trapezoid may be shorter than the length of the sides of the hexagonal region, thereby increasing the area of ​​the grown Group III nitride semiconductor.

[0017] In the method for producing a Group III nitride semiconductor, each side of the hexagonal region may coincide with an m-plane of the seed crystal, thereby reducing irregularities on the periphery of the grown Group III nitride semiconductor.

[0018] In the method for producing a Group III nitride semiconductor, the vertices formed by the upper base and legs of the trapezoid and the vertices of the hexagonal region may be located on the circumference of a circle centered at the center of the hexagonal region. This allows for a larger area of ​​the grown Group III nitride semiconductor. Furthermore, the midpoint of the upper base of the trapezoid and the vertices formed by the legs and lower base of the trapezoid may be located on the circumference of a circle centered at the center of the hexagonal region. This makes it easier to combine crystals on adjacent enlarged regions.

[0019] In the method for manufacturing a Group III nitride semiconductor, the placement region may have a second enlarged region which is a planar pattern that is continuous with the upper base of the trapezoid of the enlarged region, extends the region outside the enlarged region, and has sides parallel to the upper base, thereby making it possible to increase the area of ​​the grown Group III nitride semiconductor.

[0020] The seed substrate includes a substrate and a plurality of seed crystals made of a Group III nitride semiconductor that are discretely arranged on the substrate. The plurality of seed crystals are arranged within an arrangement region that is a predetermined planar pattern. The arrangement region includes a hexagonal region and an extended region that is a planar pattern that is continuous with at least two adjacent sides of the hexagonal region, expands the region outside the hexagonal region, and has sides that are parallel to the continuous sides.

[0021] In the seed substrate, the planar pattern of the enlarged region may be a trapezoid, and the bottom of the trapezoid may overlap with the sides of the hexagonal region.

[0022] In the seed substrate, the legs of the trapezoid may coincide with the m-plane of the seed crystal.

[0023] In the seed substrate, the length of the lower base of the trapezoid may be shorter than the length of the sides of the hexagonal region.

[0024] In the seed substrate, each side of the hexagonal region may coincide with an m-plane of the seed crystal.

[0025] In the seed substrate, the vertices formed by the upper base and legs of the trapezoid and the vertices of the hexagonal regions may be located on a circumference centered at the center of the hexagonal regions, and the midpoint of the upper base of the trapezoid and the vertices formed by the legs and lower base of the trapezoid may be located on a circumference centered at the center of the hexagonal regions.

[0026] In the seed substrate, the placement region may have a second enlarged region that is a planar pattern that is continuous with the upper base of the trapezoid of the enlarged region, extends outside the enlarged region, and has sides parallel to the upper base.

[0027] (Embodiment 1) 1. Overview of the flux method Embodiment 1 is a method for producing a Group III nitride semiconductor by a flux method, in which a Group III nitride semiconductor is grown by supplying and dissolving a nitrogen-containing gas into a mixed melt containing an alkali metal flux and a Group III metal raw material, thereby epitaxially growing a Group III nitride semiconductor in the liquid phase.

[0028] The Group III metal raw material is at least one of gallium (Ga), aluminum (Al), and indium (In), and the composition of the Group III nitride semiconductor to be grown can be controlled by adjusting the ratio thereof, allowing for the growth of GaN, AlN, InN, AlGaN, InGaN, AlGaInN, etc. The present invention is particularly suitable for growing GaN.

[0029] The alkali metal used as the flux is usually sodium (Na), but potassium (K) may also be used, or a mixture of Na and K. Furthermore, lithium (Li) or an alkaline earth metal may also be mixed.

[0030] Carbon (C) may be added to the mixed melt. The addition of C can increase the crystal growth rate. Dopants other than C may also be added to the mixed melt for the purposes of controlling the conductivity type, magnetism, and other physical properties of the group III nitride semiconductor to be grown, promoting crystal growth, suppressing miscellaneous crystals, and controlling the growth direction. For example, germanium (Ge) can be used as an n-type dopant, and magnesium (Mg), zinc (Zn), calcium (Ca), and the like can be used as p-type dopants.

[0031] The nitrogen-containing gas is a gas of nitrogen molecules or a compound such as ammonia that contains nitrogen as a constituent element, or may be a mixed gas thereof, or may be a gas in which the nitrogen-containing gas is mixed with an inert gas such as a rare gas.

[0032] 2. Seed Substrate Structure In the first embodiment, a seed substrate 9 is placed in the mixed melt, and a Group III nitride semiconductor is grown on the seed substrate 9. The seed substrate 9 may be placed in the mixed melt before heating and pressurizing, but it is preferable to place the seed substrate 9 in the mixed melt after heating and pressurizing to reach the growth temperature and growth pressure. This can prevent the seed crystal 2 on the seed substrate 9 from melting back.

[0033] An MPS (multi-point seed) substrate is used as the seed substrate 9. The MPS substrate is a substrate in which a plurality of dot-shaped seed crystals 2 are periodically arranged on a substrate 1. FIG. 1 is a cross-sectional view of the seed substrate 9, which is a cross-section perpendicular to the main surface of the substrate. FIG. 2 is a plan view of the seed substrate 9 seen from above, showing an enlarged partial region. FIG. 3 is a plan view of the seed substrate 9 seen from above, showing an arrangement region 10 of the seed crystals 2.

[0034] Substrate 1 can be made of a group III nitride semiconductor, sapphire, aluminum oxynitride, SiC, Si, spinel, ZnO, gallium oxide, etc. In the case of a sapphire substrate, the main surface is, for example, the c-plane or the a-plane.

[0035] A plurality of seed crystals 2 are provided on the substrate 1 via a buffer layer (not shown). The seed crystals 2 are arranged in a regular triangular lattice pattern. The buffer layer and the seed crystals 2 are made of a group III nitride semiconductor of any composition, such as GaN, AlGaN, or AlN. An appropriate material for the buffer layer is selected depending on the material of the seed crystals 2. For example, if the seed crystals 2 are made of GaN, the buffer layer is preferably made of GaN. The material for the seed crystals is usually a group III nitride semiconductor of the same composition as the group III nitride semiconductor to be grown by the flux method. The seed crystals 2 may be grown by any method, such as MOCVD, HVPE, or MBE, but MOCVD or HVPE is preferred in terms of crystallinity, growth time, etc.

[0036] The planar pattern of the seed crystal 2 is a circle or a polygon such as a regular hexagon, square, or equilateral triangle. Figure 2 shows the case of a circle. The planar pattern of the seed crystal 2 is preferably a regular hexagon, and in particular, a regular hexagon in which each side is aligned with the m-plane of the seed crystal 2 (each side coincides with the a-axis direction) is preferred. Because Group III nitride semiconductors are hexagonal crystals, a regular hexagonal shape allows the Group III nitride semiconductors grown from various crystals 2 to be uniformly combined. However, it is not necessary to completely align the a-axis, and an angular deviation of about 10 degrees is permissible. An angular deviation of 1 degree or less is preferred.

[0037] The diameter D of the seed crystal 2 (the diameter of the circumscribing circle in a plan view) is preferably 10 to 500 μm. Within this range, a Group III nitride semiconductor with fewer dislocations and warpage can be grown. The diameter is more preferably 50 to 300 μm, and even more preferably 100 to 200 μm.

[0038] The height of the seed crystal 2 is preferably 5 to 50 μm. Within this range, a flatter Group III nitride semiconductor can be grown. Also, the time required for forming the seed crystal 2 can be reduced. For the same reason, the diameter D of the seed crystal 2 is preferably 0.2 to 100 times the height of the seed crystal 2.

[0039] As shown in FIG. 2, the seed crystals 2 are arranged in a regular triangular lattice pattern. Any periodic arrangement is possible, not limited to a regular triangular lattice pattern, but highly symmetrical patterns such as a square lattice pattern or a regular triangular lattice pattern are preferred. This allows the Group III nitride semiconductors grown from the various crystals 2 to be uniformly combined, enabling the growth of a Group III nitride semiconductor with fewer dislocations and warpage. When a regular triangular lattice pattern is used, it is preferable that the arrangement direction coincide with the a-axis direction or m-axis direction of the seed crystals 2. Here, "match" does not mean perfect match; an angular deviation of about 10 degrees is acceptable as an error. An angular deviation of 1 degree or less is preferred.

[0040] The distance L1 between the centers of adjacent seed crystals 2 is preferably 100 to 2000 μm. Within this range, a Group III nitride semiconductor with fewer dislocations and warpage can be grown. It is more preferably 200 to 1500 μm, and even more preferably 300 to 1000 μm.

[0041] 3. Regarding the placement region 10 of the seed crystal 2 As shown in Figure 3, the substrate 1 is circular in plan view. An arrangement region 10 in which the seed crystals 2 are to be arranged is set inside the circle. A plurality of seed crystals 2 are arranged in the form of a regular triangular lattice inside the arrangement region 10 as described above. When we say that the seed crystals 2 are inside the arrangement region 10, it does not necessarily mean that all of the seed crystals 2 are inside the arrangement region 10, and some of the seed crystals 2 may be located on the outer periphery of the arrangement region 10.

[0042] As shown in FIG. 3, the placement area 10 has a hexagonal area 11 and an expanded area 12 that is continuous with the hexagonal area 11.

[0043] 3, the hexagonal region 11 is a regular hexagon in plan view. It does not necessarily have to be a regular hexagon and may be any hexagonal shape. However, because Group III nitride semiconductors are hexagonal crystals and the area of ​​the grown Group III nitride semiconductor is to be as large as possible, it is preferable that the hexagonal region 11 be a regular hexagon.

[0044] Each side 11a of the periphery of the hexagonal region 11 is preferably aligned with the m-plane of the seed crystal 2 (aligned with the a-axis direction). Here, "aligned" does not mean perfect alignment, and an angular deviation of about 10 degrees is allowed as an error. An angular deviation of 1 degree or less is preferable. By setting each side 11a of the periphery of the hexagonal region 11 in this way, it is possible to reduce the irregularities on the periphery of the grown Group III nitride semiconductor, and to suppress breakage and cracks.

[0045] The expanded regions 12 are six regions that are continuous with each side 11a of the hexagon of the hexagonal region 11 and expanded outside the hexagonal region 11. As shown in FIG. 3, each expanded region 12 is an isosceles trapezoid in plan view. Hereinafter, the lower base of the isosceles trapezoid is designated as 12a, the upper base as 12b, the legs as 12c, and the vertex formed by the upper base 12b and the legs 12c as 12d. The lower base 12a overlaps with a portion of the hexagonal side 11a of the hexagonal region 11. The length W2 of the lower base 12a of the expanded region 12 is shorter than the length W1 of the side of the hexagonal region 11. For example, W2 is 0.5 to 0.9 times W1.

[0046] The upper base 12b of the trapezoid is parallel to the lower base 12a and is parallel to the sides of the periphery of the hexagonal region 11 to which the enlarged region 12 is continuous. Therefore, like each side of the periphery of the hexagonal region 11, the upper base 12b of the trapezoid is preferably aligned with the m-plane of the seed crystal 2. This can reduce the irregularities on the periphery of the grown Group III nitride semiconductor.

[0047] The interior angle formed by the lower base 12a and the legs 12c of the trapezoid may be any angle as long as it is 90 degrees or less. However, it is preferable that the legs 12c of the trapezoid coincide with the m-plane of the seed crystal 2 (along the a-axis direction). Here, "match" does not mean perfect match, and an angular deviation of about 10 degrees is acceptable as an error. An angular deviation of 1 degree or less is preferable. By matching the legs 12c of the trapezoid with the m-plane of the seed crystal 2, it is possible to further reduce the unevenness of the outer periphery of the grown Group III nitride semiconductor.

[0048] The distance L2 from the apex 12d of the expansion region 12 to the outer periphery of the substrate 1 is preferably 0.15 mm or more. When forming the seed crystals 2, the shape of the seed crystals 2 in the region near the outer periphery of the substrate 1 may differ from that in other regions, which may make it difficult to grow crystals uniformly from the various crystals 2. Therefore, by setting the distance L2 to 0.15 mm or more to ensure a sufficient distance from the outer periphery of the substrate 1, the shapes of the various crystals 2 can be made uniform. Furthermore, to ensure that the expansion region 12 is sufficiently wide, the distance L2 is preferably 20 mm or less. A more preferable range for the distance L2 is 2 to 10 mm.

[0049] The height H of the trapezoid (the distance between the lower base 12a and the upper base 12b) may be any value, but it is preferable that the height H is set so that the distance L2 falls within the above-mentioned range.

[0050] Preferably, vertex 11d of hexagonal region 11 and vertex 12d of the trapezoid of enlarged region 12 are on the circumference of a circle centered at the center of hexagonal region 11. This allows the area of ​​the grown Group III nitride semiconductor to be larger. However, they do not have to be on the exact same circumference; for example, the ratio of the diameter of the circumference passing through vertex 12d to the diameter of the circumference passing through vertex 11d may be in the range of 0.9 to 1.1.

[0051] Furthermore, the midpoint of the upper base 12b of the trapezoid of the enlarged region 12 and the vertex formed by the legs 12c and the lower base 12a of the trapezoid may be located on a circumference centered at the center of the hexagonal region 11. This makes it easier to combine crystals grown on adjacent enlarged regions 12. In this case, too, they do not have to be on the exact same circumference; for example, the ratio of the diameter of the circumference passing through the midpoint of the upper base 12b of the trapezoid to the diameter of the circumference passing through the vertex formed by the legs 12c and the lower base 12a of the trapezoid may be in the range of 0.9 to 1.1.

[0052] In the first embodiment, the expanded region 12 is an isosceles trapezoid, but any shape may be used as long as it is a planar pattern that is continuous with each side of the hexagonal region 11, expands the region outside the hexagonal region 11, and has a side parallel to one side of the continuous hexagonal region 11. For example, the expanded region 12 may be a rectangle or a non-isosceles trapezoid. However, for the reasons described above, an isosceles trapezoid whose leg 12c coincides with the m-plane is preferred.

[0053] As described above, by providing the enlarged region 12 continuous with the hexagonal region 11 as the arrangement region 10 of the seed crystal 2, the area of ​​the grown Group III nitride semiconductor can be increased. In addition, the irregularities on the periphery of the grown Group III nitride semiconductor can be reduced.

[0054] 4. Method for manufacturing seed substrate The seed substrate 9 can be fabricated, for example, as follows. First, a mask having a plurality of openings is formed on the substrate 1. The plurality of openings are arranged in a regular triangular lattice pattern. The openings are shaped in a pattern such as a circle or a regular hexagon. The openings are also arranged within the placement region 10. The mask may be made of any material that can prevent the growth of a group III nitride semiconductor on the mask, such as SiO2.

[0055] Next, a buffer layer and a seed crystal 2 are selectively grown in this order on the substrate exposed in the opening by a method such as MOCVD or HVPE. Next, the mask is removed by wet etching using hydrofluoric acid or the like. In this way, a seed substrate 9 can be produced.

[0056] 5. Method for manufacturing Group III nitride semiconductors Next, a method for manufacturing a Group III nitride semiconductor according to the first embodiment will be described with reference to the drawings.

[0057] First, the atmosphere inside the furnace is replaced with an inert gas, the inside of the furnace is heated, and then the furnace is evacuated to a vacuum, thereby sufficiently reducing outgas components such as oxygen inside the furnace.

[0058] Next, predetermined amounts of alkali metal and Group III metal are weighed in a glove box where the atmosphere, including oxygen and dew point, is controlled. Then, the weighed predetermined amounts of alkali metal and Group III metal are charged into the crucible 100. If necessary, an additive element such as carbon may be charged.

[0059] Next, the crucible 100 containing the raw materials and the seed substrate 9 are placed in a reaction vessel, which is then evacuated, and a nitrogen-containing gas is supplied to the reaction vessel. When the pressure inside the reaction vessel reaches the crystal growth pressure, the temperature inside the furnace is raised to the crystal growth temperature. The crystal growth temperature is, for example, 700°C or higher and 1000°C or lower, and the crystal growth pressure is, for example, 2 MPa or higher and 10 MPa or lower. During the temperature increase process, the solid alkali metal and solid Group III metal in the crucible 100 melt and become liquid, forming a mixed melt 101. At this stage, the seed substrate 9 is not yet introduced into the mixed melt 101.

[0060] When the temperature and pressure inside the reaction vessel reach the crystal growth temperature and pressure, and the nitrogen dissolved in the mixed melt 101 becomes supersaturated, the seed substrate 9 is placed into the mixed melt 101 in the crucible 100. Then, a group III nitride semiconductor crystal 3 begins to grow from the various crystals 2 on the seed substrate 9. At this time, the (10-11) plane appears predominantly as the crystal face, and the crystal 3 takes on a truncated pyramidal or pyramidal shape. The crystal 3 continues to grow until adjacent crystals 3 begin to coalesce (see FIG. 4(a)). Note that the gaps between the seed crystals 2 remain unfilled.

[0061] Once adjacent crystals 3 begin to coalesce, crystal growth is performed using the FFC (flux film coating) method. The FFC method involves repeatedly removing a seed substrate 9 from a mixed melt 101 and then plunging it back into the mixed melt 101 at a predetermined interval (see Figure 5). When adjacent crystals 3 begin to coalesce, depressions 4 appear on the coalescence surface. When the seed substrate 9 is removed from the mixed melt 101, the mixed melt 101 accumulates in the depressions 4 between the adjacent crystals 3. This allows crystals 5 to grow along the depressions 4 (see Figure 4(b)).

[0062] Here, the mixed melt 101 accumulated in the recess 4 is thin, so it is prone to nitrogen supersaturation. This can speed up the crystal growth. On the other hand, because the amount of accumulated mixed melt 101 is small, the amount of Group III metal is also small, and crystal growth stops after a while. Therefore, the seed substrate 9 is again placed in the mixed melt 101 and the substrate is removed from the mixed melt 101, so that the mixed melt 101 containing the Group III metal is intermittently supplied to the recess 4. The FFC method is performed until the growth of the crystal 5 fills the recess 4. This allows the growth of a crystal with a flat c-plane.

[0063] Although it is not always necessary to perform the FFC growth step, it is preferable to perform the FFC growth step in order to further improve the flatness of the crystal and further reduce warpage.

[0064] Once the depressions 4 are filled and a flat crystal surface is formed, the seed substrate 9 is again placed into the mixed melt 101. Then, the Group III nitride semiconductor crystal 6 is grown to a thickness.

[0065] Here, as shown in FIG. 6( a), the crystal 6 has a planar pattern similar to that of the arrangement region 10 of the seed crystal 2 in the initial growth stage. Thereafter, the crystal 6 grows from the legs 12c of the trapezoid of the enlarged region 12 in a direction parallel to the upper base 12b, and reaches the apex of the hexagonal region 11 as shown in FIG. 6( b). Then, crystal growth from the legs 12c of the enlarged region 12 further progresses, and adjacent enlarged regions 12 merge with each other as shown in FIG. 6( c). As a result, the crystal 6 has a hexagonal pattern that is wider than the hexagonal region 11 in a planar view. In this way, by making the planar pattern of the arrangement region 10 a pattern having the hexagonal region 11 and the enlarged region 12, the crystal 6 can be made wider than the hexagonal region 11.

[0066] Depending on the growth conditions, the adjacent expanded regions 12 may not merge, resulting in a pattern such as that shown in Figure 6(a) or 6(b). However, even in this case, the crystal 6 can be made wider than the hexagonal region 11.

[0067] Once the crystal 6 has grown to the desired thickness, the temperature is lowered to room temperature, and the pressure is also lowered to atmospheric pressure, completing the growth of the Group III nitride semiconductor. At this point, the gaps between the seed crystals 2 remain unfilled. Therefore, the substrate 1 can naturally peel off when the temperature is lowered due to the difference in thermal expansion coefficients.

[0068] As described above, according to the method for manufacturing a Group III nitride semiconductor in embodiment 1, the arrangement region 10 of the seed crystal 2 has a structure including the hexagonal region 11 and the enlarged region 12, so that the area of ​​the grown crystal 6 can be increased.

[0069] (Embodiment 2) 7 is a plan view showing the arrangement region 20 of the seed crystal 2 in the embodiment 2. In the embodiment 2, the arrangement region 10 of the seed crystal 2 on the seed substrate 9 in the embodiment 1 is changed to the following arrangement region 20. Other than that, the embodiment 2 is the same as the embodiment 1.

[0070] The arrangement region 20 is obtained by providing an expanded region 22 in addition to the expanded region 12 of the arrangement region 10 in the first embodiment.

[0071] As shown in FIG. 7(a), the expansion region 22 is continuous with the upper base 12b of the expansion region 12 and is expanded outside the expansion region 12. The planar pattern of the expansion region 22 is an isosceles trapezoid. The lower base of the trapezoid of the expansion region 22 overlaps with a portion of the upper base 12b of the trapezoid of the expansion region 12. The length of the lower base of the trapezoid of the expansion region 22 is shorter than the length of the upper base 12b of the trapezoid of the expansion region 12. For example, it is 0.5 to 0.9 times the length of the upper base 12b. It is preferable that the legs of the trapezoid of the expansion region 22 coincide with the m-plane, like the legs of the expansion region 12.

[0072] 7(b), it is preferable that the vertex 22a of the enlarged region 22, the vertex 12d of the enlarged region 12, and the vertex 11d of the hexagonal region 11 are configured to be located on the circumference C whose center coincides with the center of the hexagonal region 11. This allows the area of ​​the grown Group III nitride semiconductor to be increased. In addition, the unevenness of the periphery of the grown Group III nitride semiconductor can be reduced.

[0073] As described above, in the second embodiment, a two-stage structure is formed in which an additional expansion region 22 is provided to expand the expansion region 12. This allows the area of ​​the grown Group III nitride semiconductor to be further increased.

[0074] In the second embodiment, the expansion region 22 is further provided within the expansion region 12 to form a two-stage structure, but it is also possible to provide three or more stages of expansion regions by providing repeated expansion regions, thereby making it possible to further increase the area of ​​the grown Group III nitride semiconductor.

[0075] (Embodiment 3) 8 is a plan view showing the arrangement region 30 of the seed crystal 2 in the embodiment 3. In the embodiment 3, the enlarged region 12 in the embodiment 1 is changed to the enlarged region 32 described below. Other than that, the embodiment 3 is the same as the embodiment 1.

[0076] The expansion region 32 has an isosceles trapezoidal shape in plan view, with the length of its lower base being the same as the length of the sides of the hexagonal region 11. Other than that, it is the same as the expansion region 12. When the expansion region 32 has such a planar pattern, the same effect as the expansion region 12 can be obtained. That is, the area of ​​the grown Group III nitride semiconductor can be increased. Furthermore, it becomes easier to combine crystals from adjacent expansion regions 32.

[0077] In the third embodiment, similarly to the second embodiment, the enlarged region 32 may be further provided with repeated enlarged regions to form a structure of two or more stages.

[0078] (Other variations) In the first to third embodiments, the expansion regions are provided on all sides of the hexagonal region 11, but this is not necessarily required, and it is sufficient that the expansion regions are provided on at least two adjacent sides of each side. However, in order to increase the area of ​​the grown Group III nitride semiconductor, it is preferable to provide the expansion regions on all sides. [Explanation of symbols]

[0079] 1: Circuit board 2: Seed crystal 4: Depression 5, 6: Crystal 9: Seed substrate 10~30: Placement area 11:Hexagonal area 12, 22, 32: Expanded area

Claims

1. a substrate preparation step of preparing a seed substrate having a plurality of seed crystals made of a Group III nitride semiconductor discretely arranged on a substrate; a crystal growing step of bringing the seed crystal into contact with a melt containing an alkali metal and a Group III metal, dissolving nitrogen in the melt, and growing a Group III nitride semiconductor on the seed crystal, the plurality of seed crystals are arranged within an arrangement region having a predetermined planar pattern; The placement area is a hexagonal region of a hexagon; an extended region which is a planar pattern that is continuous with at least two adjacent sides of the hexagonal region, extends the region outside the hexagonal region, and has sides parallel to the continuous sides.

2. The method for producing a Group III nitride semiconductor according to claim 1 , wherein the planar pattern of the enlarged region is a trapezoid, and a bottom of the trapezoid overlaps with a side of the hexagonal region.

3. The method for producing a Group III nitride semiconductor according to claim 2 , wherein the legs of the trapezoid coincide with the m-plane of the seed crystal.

4. The method for producing a Group III nitride semiconductor according to claim 2 , wherein the length of the lower base of the trapezoid is shorter than the length of the sides of the hexagonal region.

5. 5. The method for producing a Group III nitride semiconductor according to claim 1, wherein each side of the hexagonal region coincides with an m-plane of the seed crystal.

6. 5. The method for producing a Group III nitride semiconductor according to claim 2, wherein a vertex formed by an upper base and a leg of the trapezoid and a vertex of the hexagonal region are located on a circumference of a circle centered at a center of the hexagonal region.

7. 5. The method for producing a Group III nitride semiconductor according to claim 2, wherein a midpoint of an upper base of the trapezoid and a vertex formed by a leg of the trapezoid and a lower base of the trapezoid are located on a circumference of a circle centered at a center of the hexagonal region.

8. 5. The method for producing a Group III nitride semiconductor according to claim 2, wherein the placement region includes a second enlarged region that is a planar pattern that is continuous with an upper base of the trapezoid of the enlarged region, that enlarges the region outside the enlarged region, and that has sides that are parallel to the upper base.

9. A substrate; a plurality of seed crystals made of a Group III nitride semiconductor, the seed crystals being discretely arranged on the substrate; the plurality of seed crystals are arranged within an arrangement region having a predetermined planar pattern; The placement area is a hexagonal region of a hexagon; an expanded region that is a planar pattern that is continuous with at least two adjacent sides of the hexagonal region, expands the region outside the hexagonal region, and has sides parallel to the continuous sides.

10. The seed substrate according to claim 9 , wherein the planar pattern of the enlarged region is a trapezoid, and a bottom of the trapezoid overlaps with a side of the hexagonal region.

11. The seed substrate of claim 10 , wherein a leg of the trapezoid coincides with an m-plane of the seed crystal.

12. The seed substrate according to claim 10 , wherein a length of a lower base of the trapezoid is shorter than a length of a side of the hexagonal region.

13. The seed substrate according to claim 9 , wherein each side of the hexagonal region coincides with an m-plane of the seed crystal.

14. 13. The seed substrate according to claim 10, wherein a vertex formed by an upper base and a leg of the trapezoid and a vertex of the hexagonal region are located on a circumference of a circle centered at a center of the hexagonal region.

15. 13. The seed substrate according to claim 10, wherein a midpoint of an upper base of the trapezoid and a vertex formed by a leg and a lower base of the trapezoid are located on a circumference of a circle centered at a center of the hexagonal region.

16. 13. The seed substrate according to claim 10, wherein the placement region includes a second enlarged region that is a planar pattern that is continuous with an upper base of the trapezoid of the enlarged region, expands the region outside the enlarged region, and has sides that are parallel to the upper base.

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