Photoelectric conversion device and apparatus

Abstract

To provide a technique advantageous for suppressing a peak value of current consumption in a pixel array.SOLUTION: A photoelectric conversion device comprises a plurality of pixels that are arranged to form a plurality of rows and a plurality of columns, and a control unit that divides the plurality of pixels into a plurality of blocks to perform control. Each of the plurality of blocks includes pixels arranged on the same column and pixels arranged on columns different from each other. Each pixel includes a photoelectric conversion element, and an in-pixel read-out part that performs an in-pixel read-out operation of reading out a signal from the photoelectric conversion element and holding the signal. The control unit controls the plurality of pixels so that periods for causing the in-pixel read-out parts of the plurality of pixels to perform the in-pixel read-out operation are the same in the individual block and are different from each other between the plurality of blocks.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] The present invention relates to a photoelectric conversion device and an apparatus. [Background technology]

[0002] Patent Documents 1 and 2 describe a global shutter CMOS image sensor in which each pixel has a memory for storing a signal. In the global shutter system, charge accumulation operations start and end simultaneously in all pixels. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2022-51548 [Patent Document 2] International Publication No. 2016 / 009832 Summary of the Invention [Problem to be solved by the invention]

[0004] However, in a global shutter CMOS image sensor, the signal corresponding to the charge accumulated in the photoelectric conversion element is written to memory simultaneously in all pixels, which can cause the peak value of current consumption in the pixel array to become very large, and therefore requires a power supply circuit and power supply lines that take such peak values ​​into account.

[0005] An object of the present invention is to provide an advantageous technique for suppressing the peak value of current consumption in a pixel array. [Means for solving the problem]

[0006] One aspect of the present invention relates to a photoelectric conversion device having a plurality of pixels arranged to form a plurality of rows and a plurality of columns, the photoelectric conversion device including a control unit that divides the plurality of pixels into a plurality of blocks and controls them, each of the plurality of blocks including pixels arranged in the same row and pixels arranged in different rows, each pixel including a photoelectric conversion element and an in-pixel readout unit that performs an in-pixel readout operation to read and hold a signal from the photoelectric conversion element, and the control unit controls the plurality of pixels so that the period during which the in-pixel readout unit of the plurality of pixels performs the in-pixel readout operation is the same within each block and differs from one another among the plurality of blocks. [Effects of the Invention]

[0007] According to the present invention, an advantageous technique is provided for suppressing the peak value of current consumption in a pixel array. [Brief explanation of the drawings]

[0008] [Figure 1] FIG. 1 is a block diagram showing the configuration of a photoelectric conversion device according to a first embodiment. [Figure 2] 2 is a diagram illustrating an example of the circuit configuration of one pixel and one column of the photoelectric conversion device according to the first embodiment. FIG. [Figure 3] 1A and 1B are diagrams illustrating a global shutter operation and a partial global shutter operation, respectively; [Figure 4] FIG. 10 is a timing diagram illustrating a signal readout operation in a pixel. [Figure 5] FIG. 10 is a timing diagram illustrating a readout operation of a signal from a pixel array. [Figure 6] FIG. 2 is a diagram showing an example of division of a pixel array in the first embodiment. [Figure 7] FIG. 3 is a diagram showing an example of a method for driving a plurality of blocks in the first embodiment. [Figure 8] FIG. 10 is a diagram showing a modified example of the circuit configuration of a pixel. [Figure 9] 9 is a timing chart illustrating a signal readout operation in the pixel of FIG. 8. [Figure 10]9 is a timing diagram illustrating a readout operation of a signal from a pixel array configured with the pixels of FIG. 8. [Figure 11A] FIG. 10 is a diagram showing an example of a method for driving a plurality of blocks in the second embodiment. [Figure 11B] FIG. 10 is a diagram showing an example of a method for driving a plurality of blocks in the second embodiment. [Figure 12] FIG. 11 is a diagram showing an example of a method for driving a plurality of blocks in the third embodiment. [Figure 13] FIG. 10 is a block diagram showing the configuration of a part of a photoelectric conversion device according to a third embodiment. [Figure 14] FIG. 13 is a diagram showing an example of a method for driving a plurality of blocks in the fourth embodiment. [Figure 15] FIG. 13 is a diagram showing an example of division of a pixel array in the fifth embodiment. [Figure 16] FIG. 13 is a diagram illustrating the circuit configuration of one pixel and the circuit configuration of one column in the sixth embodiment. [Figure 17] FIG. 13 is a diagram illustrating the circuit configuration of one pixel and the circuit configuration of one column in the sixth embodiment. [Figure 18] FIG. 1 is a diagram illustrating an example of the configuration of an apparatus according to an embodiment. [Figure 19] FIG. 20 is a timing chart illustrating a readout operation of a signal from a pixel array in the seventh embodiment. [Figure 20] FIG. 23 is a timing chart illustrating a readout operation of a signal from a pixel array in the eighth embodiment. [Figure 21] FIG. 23 is a timing chart illustrating a readout operation of a signal from a pixel array in the ninth embodiment. [Figure 22] FIG. 23 is a timing chart illustrating a readout operation of a signal from a pixel array in the tenth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0009] Hereinafter, embodiments will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the scope of the invention claimed. Although multiple features are described in the embodiments, not all of these multiple features are necessarily essential to the invention, and multiple features may be combined arbitrarily. Furthermore, in the accompanying drawings, the same reference numerals are used to designate the same or similar components, and redundant explanations will be omitted. [First embodiment] 1 is a block diagram showing an example of the configuration of a photoelectric conversion device 100 according to the first embodiment. The photoelectric conversion device 100 may be configured, for example, as an image sensor that captures an optical image to generate image data and outputs the image data. Alternatively, the photoelectric conversion device 100 may be configured, for example, as a sensor that captures an optical image to generate image data and outputs information obtained by processing the image data.

[0010] The photoelectric conversion device 100 may include, for example, a pixel array 10, a vertical drive circuit 30, a drive circuit group 40, a column circuit group 50, a horizontal drive circuit 60, a signal processing circuit 70, an output circuit 80, and a system control unit 90. The pixel array 10 has a plurality of pixels 12 arranged in a plurality of rows and a plurality of columns. The vertical drive circuit 30 functions as a control unit that divides the plurality of pixels 12 into a plurality of blocks and controls them. As described below, each pixel 12 may include a photoelectric conversion element and an in-pixel readout unit that performs an in-pixel readout operation to read and store a signal from the photoelectric conversion element. The plurality of pixels 12 may include, in addition to effective pixels that output a signal corresponding to the amount of incident light, optical black pixels in which the photoelectric conversion element is shielded, and dummy pixels that do not output a signal. The vertical drive circuit 30 (control unit) may control the plurality of pixels 12 so that the period during which the in-pixel readout unit of each of the plurality of pixels 12 performs the readout operation is the same within each block but different between the plurality of blocks. The pixel array 10 may include effective pixels that output pixel signals according to the amount of incident light, as well as optical black pixels whose photoelectric conversion elements are shielded from light, and / or dummy pixels that do not output signals.

[0011] In each row of the pixel array 10, a control line group 14 may be arranged to extend in a first direction (the horizontal direction in FIG. 1 ). The control line group 14 in each row may include a plurality of signal lines. The signal lines constituting the control line group 14 in each row may be connected to a plurality of pixels 12 arranged along the first direction (the number of pixels 12 constituting one row). In other words, the signal lines constituting the control line group 14 in each row are shared by the plurality of pixels 12 arranged in that row. The first direction is a direction parallel to the rows (i.e., the row direction) and may also be referred to as the horizontal direction. The control line group 14 is connected to and driven by a vertical drive circuit 30.

[0012] In each column of the pixel array 10, a vertical output line 16 may be arranged to extend in a second direction (the vertical direction in FIG. 1 ) intersecting the first direction. The vertical output line 16 in each column may be connected to a plurality of pixels 12 (the number of pixels 12 constituting one column) arranged along the second direction. In other words, the vertical output line 16 in each column is shared by the plurality of pixels 12 arranged in that column. The second direction is a direction parallel to the columns (i.e., the column direction) and may also be referred to as the vertical direction. Each vertical output line 16 may be composed of a plurality of output lines. The vertical output line 16 is connected to a drive circuit group 40.

[0013] In response to control signals supplied from the system control unit 90, the vertical drive circuit 30 generates control signals for driving the plurality of pixels 12 that make up the pixel array 10, and supplies the control signals to the plurality of pixels 12 via a plurality of control line groups 14. The vertical drive circuit 30 may include a shift register and / or an address decoder, etc.

[0014] The vertical drive circuit 30 may be configured to control the plurality of pixels 12 using a partial global shutter (PGS) system. Alternatively, the vertical drive circuit 30 may have a partial global shutter mode in which the plurality of pixels 12 are controlled using the partial global shutter (PGS) system, and a global shutter mode in which the plurality of pixels 12 are controlled using the global shutter (GS) system. The mode control may be performed, for example, by a mode command signal sent externally to the system control unit 90. The partial global shutter (PGS) system divides the plurality of pixels 12 constituting the pixel array 10 into a plurality of blocks, and drives each block using the global shutter system. Each block may include pixels arranged in the same row and pixels arranged in different rows. In other words, each block may include any number of pixels 12 whose positions are specified by two or more rows and two or more columns. The vertical drive circuit 30 may control the plurality of pixels 12 constituting the pixel array 10 so that the periods during which the photoelectric conversion elements of the plurality of pixels 12 perform charge accumulation operations are the same within each block and different between the plurality of blocks. Here, the vertical drive circuit 30 can control the pixels 12 so that the timing at which the photoelectric conversion elements of the pixels 12 constituting the pixel array 10 start the charge accumulation operation is the same within each block but differs between the blocks. Also, the vertical drive circuit 30 can control the pixels 12 so that the timing at which the photoelectric conversion elements of the pixels 12 constituting the pixel array 10 end the charge accumulation operation is the same within each block but differs between the blocks.

[0015] The drive circuit group 40 has a plurality of drive circuits 41 provided so that one drive circuit 41 corresponds to the vertical output line 16 of each column of the pixel array 10. Each drive circuit 41 can control the connection between the pixel array 10 and the corresponding column circuit 51 of the column circuit group 50, and can control the potential of the vertical output line 16, in response to a control signal supplied from the system control unit 90. The column circuit group 50 has a plurality of column circuits 51 provided so that one column circuit 51 corresponds to the vertical output line 16 of each column of the pixel array 10.

[0016] The signal processing circuit 70 has a function of performing predetermined signal processing on pixel signals supplied from the column circuit group 50. The signal processing circuit 70 can perform, for example, amplification processing, correction processing using correlated double sampling (CDS), analog-to-digital conversion (AD conversion), and the like. The reference signal generator 50A is connected to the multiple column circuits 51 of the column circuit group 50. In response to a control signal output from the system control unit 90, the reference signal generator 50A generates a reference signal to be used for AD conversion and supplies the reference signal to the multiple column circuits 51 of the column circuit group 50. The reference signal to be used for AD conversion has a predetermined amplitude according to the range of the pixel signals and has a signal level that changes over time. The reference signal is not particularly limited, but may be, for example, a ramp signal whose signal level increases or decreases over time.

[0017] The counter circuit 50B is connected to the plurality of column circuits 51 of the column circuit group 50. The counter circuit 50B performs a counting operation in response to a control signal output from the system control unit 90, and supplies count signals having count values ​​generated thereby to the plurality of column circuits 51 of the column circuit group 50. The counter circuit 50B starts its counting operation in synchronization with the timing at which the signal level of the reference signal supplied from the reference signal generator 50A starts to change.

[0018] In response to a control signal supplied from the system control unit 90, the horizontal drive circuit 60 generates a control signal for reading out pixel signals from the column circuit group 50 and supplies the signal to the plurality of column circuits 51 in the column circuit group 50. The horizontal drive circuit 60 sequentially selects the plurality of column circuits 51 in the column circuit group 50 and causes each of the column circuits 51 to output the pixel signals held therein to the signal processing circuit 70. The horizontal drive circuit 60 may include a shift register and / or an address decoder, etc.

[0019] The output circuit 80 has an external interface circuit and is a circuit for outputting signals processed by the signal processing circuit 70 to the outside of the photoelectric conversion device 100. The external interface circuit included in the output circuit 80 is not particularly limited. The external interface circuit may include, for example, a SerDes (SERializer / DESerializer) transmission circuit. The SerDes transmission circuit may include an LVDS (Low Voltage Differential Signaling) circuit or an SLVS (Scalable Low Voltage Signaling) circuit. The system control unit 90 generates control signals that control the operations of the vertical drive circuit 30, the drive circuit group 40, the column circuit group 50, the horizontal drive circuit 60, etc. The drive circuit group 40, the column circuit group 50, the horizontal drive circuit 60, etc. constitute an extra-pixel readout unit RC that reads out signals from the pixel array 10 (pixels 12).

[0020] Control signals for controlling the operations of the vertical drive circuit 30, the drive circuit group 40, the column circuit group 50, the horizontal drive circuit 60, etc. do not necessarily need to be supplied from the system control unit 90, and at least some of these may be supplied from outside the photoelectric conversion device 100. In Fig. 1, the signal paths are shown below the pixel region 10, but this is not limiting and circuits related to the signal paths may also be arranged above the pixel region 10.

[0021] Next, an example configuration of a pixel 12 will be described with reference to FIG. 2. FIG. 2 illustrates the configuration of each pixel 12 constituting the pixel array 10. The pixel 12 may include, for example, a photoelectric conversion element PD and an in-pixel readout unit PRD that performs an in-pixel readout operation of reading and holding a signal from the photoelectric conversion element PD. The in-pixel readout unit PRD may include a source follower circuit. The in-pixel readout unit PRD or the source follower circuit may include an amplification transistor M3, a current source M5, and a control transistor M6. The amplification transistor M3, the current source M5, and the control transistor M6 are connected in series, and the vertical drive circuit 30 (control unit) performs a readout operation by turning on the control transistor M6. In other words, the control transistor M6 is a transistor that controls the current source M5. The current source M5 may be configured as a transistor (MOS transistor) whose gate is supplied with a bias potential VB. The in-pixel readout unit PRD or source follower circuit may further include a selection transistor M4 connected in series with the amplification transistor M3, the current source M5, and the control transistor M6. Alternatively, instead of the control transistor M6, the selection transistor M4 connected in series with the amplification transistor M3 and the current source M5 may be used to control enabling and disabling of the readout operation.

[0022] The in-pixel readout unit PRD or source follower circuit may further include a charge-voltage conversion unit FD, a transfer unit M1 that transfers the charge of the photoelectric conversion element PD to the charge-voltage conversion unit FD, and a reset unit M2 that resets the charge-voltage conversion unit FD. The in-pixel readout unit PRD or source follower circuit may read out a signal corresponding to the voltage of the charge-voltage conversion unit FD as a signal of the photoelectric conversion element PD and output it to node N1. In this embodiment, the transfer unit M1 and the reset unit M2 are configured with transistors, but may also be configured with other elements.

[0023] The in-pixel readout unit PRD may include a first memory CN and a second memory CS. A readout operation by the in-pixel readout unit PRD may include a first operation of reading a noise level from the photoelectric conversion element PD to a node N1 and storing the noise level in the first memory CN, and a second operation of reading an optical signal level from the photoelectric conversion element PD to a node N1 and storing the optical signal level in the second memory CS. The in-pixel readout unit PRD may include a sample-and-hold transistor M7 for storing the noise level in the first memory CN and reading the noise level stored in the first memory CN to the node N1. The in-pixel readout unit PRD may also include a sample-and-hold transistor M8 for storing the optical signal level read out to the node N1 in the second memory CS and reading the optical signal level stored in the second memory CS to the node N1.

[0024] The pixel 12 may include an amplifier M10 that outputs levels corresponding to the noise level and optical signal level read out from the first memory CN and the second memory CS to the node N1 to the vertical output line 16, and a reset unit M9 that resets the node N1. The pixel 12 may also include a selection transistor M11 that connects the amplifier M10 to the vertical output line 16. The selection transistor M11 may also be understood as a transistor that controls the operation of outputting the signal of the pixel 12 to the vertical output line 16.

[0025] The pixel 12 may have a microlens and a color filter disposed on the optical path of incident light before being guided to the photoelectric conversion element PD. The microlens focuses the incident light onto the photoelectric conversion element PD. The color filter selectively transmits light of a predetermined color.

[0026] The photoelectric conversion element PD is, for example, a photodiode. The anode of the photoelectric conversion element PD is connected to a reference voltage node, and the cathode of the photoelectric conversion element PD may be connected to the source of a transistor constituting the transfer unit M1. The drain of the transistor constituting the transfer unit M1 may be connected to the source of a transistor constituting the reset unit M1 and the gate of the amplification transistor M3. The node to which the drain of the transistor constituting the transfer unit M1, the source of the transistor constituting the reset unit M2, and the gate of the amplification transistor M3 are connected constitutes a charge-voltage conversion unit FD, which may also be called a floating diffusion. The charge-voltage conversion unit FD has a capacitance and converts the charge generated by the photoelectric conversion element PD into a voltage. The capacitance of the charge-voltage conversion unit FD may include, for example, pn junction capacitance and wiring capacitance.

[0027] The drain of transistor M2 constituting reset unit M2 and the drain of amplifying transistor M3 may be connected to a node to which a power supply voltage (voltage VDD) is supplied. The source of amplifying transistor M3 may be connected to the drain of selection transistor M4. The source of selection transistor M4 (node ​​N1) may be connected to the drain of transistor M5 constituting current source M5, the sources of sample-and-hold transistors M7 and M8, the gate of amplifying transistor M10, and the sources of transistors constituting reset unit M9.

[0028] The source of the transistor constituting the current source M5 may be connected to the drain of the control transistor M6, and the source of the control transistor M6 may be connected to a ground node. The transistor constituting the current source M5 supplies a bias current for driving the amplifier transistor M3.

[0029] The drains of the sample-and-hold transistors M7 and M8 may be connected to first terminals of the first memory CN and second memory CS, respectively. The second terminals of the first memory CN and second memory CS may be connected to a ground node. The drains of the amplifier transistor M10 and the transistors constituting the reset unit M9 may be connected to a node to which a voltage VDD is supplied. The source of the amplifier transistor M10 may be connected to the drain of the selection transistor M11. The source of the selection transistor M11 may be connected to a vertical output line 16. A current source 17 may be connected to the vertical output line 16.

[0030] 2, the control line group 14 for each row includes signal lines connected to the gate of the transistor M1 that constitutes the transfer unit M1, the gate of the transistor that constitutes the reset unit M2, the gate of the selection transistor M4, and the gate of the control transistor M6. The control line group 14 for each row also includes signal lines connected to the gates of the sample-and-hold transistors M7 and M8, the gate of the transistor that constitutes the reset unit M9, and the gate of the selection transistor M11.

[0031] Specifically, a control signal TX is supplied from the vertical drive circuit 30 to the gate of the transistor that constitutes the transfer unit M1. A control signal RES is supplied from the vertical drive circuit 30 to the gate of the transistor that constitutes the reset unit M2. A control signal GSSEL is supplied from the vertical drive circuit 30 to the gate of the selection transistor M4. A control signal SW is supplied from the vertical drive circuit 30 to the gate of the control transistor M6. A bias voltage VB is supplied from a bias supply circuit (not shown) to the gate of the transistor that constitutes the current source M5. Control signals GSTXN and GSTXS are supplied from the vertical drive circuit 30 to the gates of the sample and hold transistors M7 and M8. A control signal RES1 is supplied from the vertical drive circuit 30 to the gate of the transistor that constitutes the reset unit M9. A control signal SEL is supplied from the vertical drive circuit 30 to the gate of the selection transistor M11.

[0032] When each transistor is an N-type MOS transistor, the corresponding transistor turns on when a high-level control signal is supplied from the vertical drive circuit 30. On the other hand, the corresponding transistor turns off when a low-level control signal is supplied from the vertical drive circuit 30.

[0033] In this specification, the description will be made assuming that electrons, among electron-hole pairs generated in the photoelectric conversion element PD by incident light, are used as signal charges. When electrons are used as signal charges, each transistor constituting the pixel 12 may be configured as an N-type MOS transistor. However, the signal charges are not limited to electrons, and holes may also be used as signal charges. When holes are used as signal charges, the conductivity type of each transistor is opposite to that described in this embodiment.

[0034] The names of the source and drain of a MOS transistor may differ depending on the conductivity type of the transistor and the function of interest. Some or all of the names of the source and drain used in this specification may be called by the reverse names.

[0035] The photoelectric conversion element PD converts incident light into an electric charge in an amount corresponding to the amount of light (photoelectric conversion), and accumulates the resulting electric charge. When the transistor constituting the transfer unit M1 is turned on, it transfers the electric charge held by the photoelectric conversion element PD to the charge-voltage conversion unit FD. The electric charge transferred from the photoelectric conversion element PD is held in the capacitance of the charge-voltage conversion unit FD. As a result, the charge-voltage conversion in the charge-voltage conversion unit FD becomes a potential corresponding to the amount of electric charge transferred from the photoelectric conversion element PD.

[0036] When the selection transistor M4 is turned on, it connects the amplification transistor M3 to node N1. A voltage VDD is supplied to the drain of the amplification transistor M3, and a bias current is supplied to the source of the amplification transistor M3 from a current source M5 via the selection transistor M4, forming a source follower circuit with the gate as an input node. This causes the amplification transistor M3 to output a voltage or signal corresponding to the voltage of the charge-voltage converter FD to node N1 via the selection transistor M4. By controlling the transfer unit M1, reset unit M2, and selection transistor M4, it is possible to output to node N1 a noise level corresponding to the reset voltage of the charge-voltage converter FD and an optical signal level corresponding to the amount of light incident on the photoelectric conversion element PD.

[0037] When the amplification transistor M3 outputs a noise level to the node N1, the sample-and-hold transistor M7 is turned on and the noise level is written to the first memory CN. When the amplification transistor M3 outputs an optical signal level to the node N1, the sample-and-hold transistor M8 is turned on and the optical signal level is written to the second memory CS.

[0038] When the selection transistor M11 is turned on, the amplification transistor M10 is connected to the vertical output line 16. A voltage VDD is supplied to the drain of the amplification transistor M10, and a bias current is supplied to the source of the amplification transistor M10 from the current source 17 via the selection transistor M11, forming a source follower circuit with the gate as an input node. When the sample and hold transistor M7 is turned on, the amplification transistor M10 outputs a level corresponding to the noise level held in the first memory CN to the vertical output line 16. When the sample and hold transistor M8 is turned on, the amplification transistor M10 outputs a level corresponding to the optical signal level held in the second memory CS to the vertical output line 16. The amount of current flowing through the current source M5 is smaller than the amount of current flowing through the current source 17.

[0039] Furthermore, AD conversion is performed in each column circuit 51. In this manner, the sample-and-hold transistors M7 and M8, the first memory CN, the second memory CS, the amplifying transistor M10, and the selection transistor M11 function as a sample-and-hold circuit that temporarily holds the signal output from the photoelectric conversion unit PD.

[0040] When the transistor constituting the reset unit M2 is turned on, it supplies a voltage (a voltage corresponding to the voltage VDD) to the charge-voltage conversion unit FD for resetting (the voltage of) the charge-voltage conversion unit FD. By simultaneously turning on the transistor constituting the reset unit M2 and the transistor constituting the transfer unit M1, it is also possible to reset the photoelectric conversion element PD to a voltage corresponding to the voltage VDD.

[0041] In the first embodiment, each of the plurality of pixels 12 has a first memory CN and a second memory CS. The first memory CN and the second memory CS can temporarily hold a level corresponding to the charge accumulated in the photoelectric conversion unit PD. This realizes a global shutter function in which the start and end times of the charge accumulation operation are the same for all pixels.

[0042] FIG. 3(a) schematically illustrates the operation of the photoelectric conversion device 100 in global shutter (GS) mode. Period A is an accumulation period during which the photoelectric conversion element PD accumulates electric charges. Period B is a period during which the in-pixel readout unit PRD reads signals (noise level, optical signal level) from the photoelectric conversion element PD and writes them to the holding unit HLD (first memory CN, second memory CS), and is referred to as the in-pixel readout period. Period C is a period during which the extra-pixel readout unit RC reads signals (signals corresponding to the noise level and optical signal level) from the pixels 12, and is referred to as the extra-pixel readout period. In global shutter mode, the operation during period A is performed simultaneously for all pixels 12, and the operation during period B is performed simultaneously for all pixels 12. In addition, in global shutter (GS) mode, the operation during period C is performed to sequentially read out signals from the pixel array 10 in units of one or a predetermined number of rows.

[0043] 4 illustrates an example of an in-pixel readout operation during period B. The accumulation period is until just before time t1, and period B, i.e., the in-pixel readout period, is from time t1 to time t6. Just before time t1, the control signal RES is at a high level, the transistor constituting the reset unit M2 is on, and the charge-voltage conversion unit FD is set to a voltage corresponding to the voltage VDD. Also, just before time t1, the control signal RES1 is at a high level, the transistor M9 constituting the reset unit M9 is on, and the node N1 is set to a voltage corresponding to the voltage VDD. Furthermore, the control signals GSTXN and GSTXS are also at a high level, and the sample-and-hold transistors M7 and M8 are on, so that one ends of the memories CN and CS are set to a voltage corresponding to the voltage VDD.

[0044] Next, at time t1, the control signal RES1 changes from high to low, causing the transistors constituting the reset unit M9 to change from on to off. Furthermore, the control signals GSTXN and GSTXS change from high to low, causing the sample-and-hold transistors M7 and M8 to change from on to off. That is, the first memory CN and the second memory CS retain the voltages they had just before time t1. Furthermore, the control signals GSSEL and SW change from low to high, causing the selection transistor M4 and the control transistor M6 to change from off to on. This allows current to flow through the amplification transistor M3.

[0045] Subsequently, at time t2, the control signal RES goes low, turning off the transistor constituting the reset unit M2 and releasing the reset state of the charge-voltage conversion unit FD. From time t2 to time t3, the control signal GSTXN goes high, turning on the sample-and-hold transistor M7, thereby writing a noise signal voltage (hereinafter referred to as the N signal) corresponding to the noise level to the first memory CN. Then, at time t3, the control signal GSTXN goes from high to low, turning the sample-and-hold transistor M7 from on to off, and the first memory CN goes into the hold state.

[0046] Next, from time t4 to time t5, the control signal TX is set to high level, the transistor constituting the transfer unit M1 is turned on, and the charge of the photoelectric conversion element PD is transferred to the charge-voltage conversion unit FD. From time t5 to time t6, the control signal GSTXS is set to high level. This turns on the sample-and-hold transistor M8, and an optical signal voltage (hereinafter referred to as an S signal) according to the optical signal level corresponding to the amount of charge of the photoelectric conversion element PD is written to the second memory CS.

[0047] Then, at time t6, the control signal GSTXS changes from high to low, causing the sample-and-hold transistor M8 to change from on to off, placing the second memory CS in a hold state. In this way, the N signal and S signal are held in the first memory CN and second memory CS in each pixel 12. After that, the control signals GSSEL and SW go low, stopping the current supply from the current source M5.

[0048] 5 illustrates an operation during period C (out-of-pixel readout operation). Period B ends by time t21. The period from time t21 to time t30 is the readout period (one horizontal scanning period) of signals from the pixels 12 in the first row. FIG. 5 shows the readout periods of signals from the pixels 12 in the first and second rows.

[0049] At time t21, the control signal SEL(1) of the first row (the row number is shown in parentheses) changes from low to high. At this time, the current source 17 is turned on. Note that the timing at which the current source 17 turns on is not limited to this example, and the current source 17 may be turned on before time t21. When the current source 17 turns on, a current flows through the amplification transistor M10, and a signal can be read out from the pixel 12.

[0050] During the period from time t21 to time t22, the control signal RES1 is set to a high level, and the node N1 is set to a voltage corresponding to the voltage VDD. Note that the node N1 may be set to another reference voltage. Thereafter, during the period from time t23 to time t24, the control signal GSTXN is set to a high level, and the sample-and-hold transistor M7 is turned on, thereby setting the N signal held in the first memory CN to the gate of the amplification transistor M10. As a result, a signal corresponding to the N signal is supplied to the column circuit 51 via the selection transistor M11 and the vertical output line 16, and AD conversion is performed.

[0051] Subsequently, from time t24 to time t25, the control signal RES1 is set to high level, and the node N1 is again set (initialized) to a voltage corresponding to the voltage VDD. This operation can reduce the influence on the signal read from the selected memory that is caused by the state before the signal is read from the selected memory.

[0052] During the period from time t26 to time t27, the control signal GSTXS is set to a high level, and the sample-and-hold transistor M8 is turned on, so that the S signal held in the second memory capacitor CS is set to the gate of the amplification transistor M10, and a signal corresponding to the S signal is supplied from the vertical output line 16 to the column circuit 51 via the selection transistor M11, and AD conversion is performed.

[0053] Also, at time t30, the control signal SEL(1) changes from high level to low level, causing the selection transistor M11 to change from on to off. Meanwhile, the control signal SEL(2) changes from low level to high level, causing the readout operation of signals from the pixels 12 in the second row to start. In this manner, signals can be read out from all the pixels 12 and AD converted. Note that the current source 17 may be changed from on to off at the timing when the readout operation of signals from all the pixels 12 is completed.

[0054] In the global shutter (GS) mode described above, the current sources M5 of all pixels 12 operate simultaneously, which can result in a very large peak current consumption for the entire pixel array 10. This can cause the current value supplied by the current source M5 to fall below the design value, or the power supply voltage to drop, which can result in a degradation of image quality. Therefore, the partial global shutter (PGS) mode described below is advantageous.

[0055] FIG. 3(b) schematically illustrates the operation of the photoelectric conversion device 100 in partial global shutter (PGS) mode. FIG. 3(b) illustrates an example in which the pixels 12 constituting the pixel array 10 are divided into six blocks BLK1 to BLK6 as an example of dividing the pixels 12 into multiple blocks. First, the period A (accumulation period) will be described. In the partial global shutter (PGS) mode, a period A (accumulation period) is determined for each block. In the example of FIG. 3(b), six periods A (accumulation periods) are determined corresponding to the six blocks BLK1 to BLK6, respectively. The vertical drive circuit 30 (controller) controls the pixels 12 so that the period during which the pixels 12 perform the accumulation operation is the same within each block but different between the multiple blocks. Here, the vertical drive circuit 30 controls the pixels 12 so that the timing at which the pixels 12 start the accumulation operation is the same within each block but different between the multiple blocks. Furthermore, the vertical drive circuit 30 controls the pixels 12 so that the timing for ending the accumulation operation for the pixels 12 is the same within each block and differs between the blocks. On the other hand, the vertical drive circuit 30 controls the pixels 12 so that the length of the accumulation operation period for the pixels 12 is the same for all blocks, in other words, for all pixels 12.

[0056] Next, the period B (intra-pixel readout period) will also be described. The vertical drive circuit 30 (controller) controls the plurality of pixels 12 so that the period during which the intra-pixel readout units PRD of the plurality of pixels 12 perform the readout operation is the same within each block but different between the plurality of blocks. Here, the vertical drive circuit 30 controls the plurality of pixels 12 so that the timing at which the intra-pixel readout units PRD of the plurality of pixels 12 start the readout operation is the same within each block but different between the plurality of blocks. The vertical drive circuit 30 also controls the plurality of pixels 12 so that the timing at which the intra-pixel readout units PRD of the plurality of pixels 12 end the readout operation is the same within each block but different between the plurality of blocks. Meanwhile, the vertical drive circuit 30 controls the plurality of pixels 12 so that the length of the period B (intra-pixel readout period) is the same in all blocks, in other words, the same for all the pixels 12.

[0057] Next, the period C (outside-pixel readout period) will also be described. The period C (outside-pixel readout period) in the partial global shutter (PGS) mode is the same as the period C (outside-pixel readout period) in the global shutter (GS) mode.

[0058] 3(b), after the accumulation periods of all of the pixels 12 have ended, the extra-pixel readout unit RC starts reading out signals from the pixels 12. Such a configuration is advantageous for suppressing the peak value of current consumption in the photoelectric conversion device 100. However, the extra-pixel readout unit RC may start reading out signals from the pixels 12 before the accumulation periods of all of the pixels 12 have ended.

[0059] FIG. 6 schematically illustrates an example in which the pixel array 10 (a plurality of pixels 12 constituting the pixel array 10) is divided vertically into a plurality of blocks BLK1 to BLK6, as exemplarily described with reference to FIG. 3(b). FIG. 7 schematically illustrates an intra-pixel readout operation in the plurality of blocks BLK1 to BLK6. In FIG. 7, "readout operation" refers to the intra-pixel readout operation. In FIG. 7, the horizontal axis represents time. The period from time t100 to t200 corresponds to period B for block BLK1 and the period from time t1 to t6 in FIG. 4. During the period from time t100 to t200, the current sources M5 of all pixels 12 in block BLK1 are activated, and an intra-pixel readout operation is performed. As a result, in all pixels 12 in block BLK1, the noise level and the optical signal level are written to the first memory CN and the second memory CS, respectively. The period from time t200 to t300 corresponds to period B for block BLK2 and the period from time t1 to t6 in Figure 4. During the period from time t200 to t300, the current sources M5 of all pixels 12 in block BLK2 are activated, and an intra-pixel readout operation is performed. As a result, the noise level and optical signal level are written to the first memory CN and second memory CS, respectively, for all pixels 12 in block BLK2.

[0060] Similarly, the period from times t300 to t400 corresponds to period B for block BLK3 and the period from times t1 to t6 in Figure 4, the period from times t400 to t500 corresponds to period B for block BLK4 and the period from times t1 to t6 in Figure 4, the period from times t500 to t600 corresponds to period B for block BLK5 and the period from times t1 to t6 in Figure 4, and the period from times t600 to t700 corresponds to period B for block BLK6 and the period from times t1 to t6 in Figure 4.

[0061] As described above, in the first embodiment, the vertical drive circuit 30 (controller) controls the pixels 12 so that the period during which the intra-pixel readout units PRD of the pixels 12 perform intra-pixel readout operations is the same within each block and different between the blocks. From another perspective, the vertical drive circuit 30 (controller) divides the pixels 12 constituting the pixel array 10 into blocks, drives the pixels 12 within each block for the same period, and drives the pixels 12 belonging to different blocks for different periods. This makes it possible to reduce distortion in the entire image by eliminating image distortion within a block while suppressing peak current consumption.

[0062] In the above example, the pixel array (a plurality of pixels constituting the pixel array) is divided into six, but the present invention is not limited to this. Furthermore, the number of vertical output lines 16 and the number of column circuits (for example, AD conversion circuits) may be determined according to the number of pixels constituting each block.

[0063] Furthermore, in the above example, one pixel 12 has one photoelectric conversion element PD, but one pixel 12 may have multiple photoelectric conversion elements PD. Furthermore, the multiple photoelectric conversion elements PD included in one pixel 12 may share one charge-voltage converter FD. Furthermore, the pixel 12 may include a photoelectric conversion element for focus detection, or an element for changing gain. In this case, the circuit configuration for reading out signals may be changed as appropriate.

[0064] For example, Fig. 8 shows a modified example of the photoelectric conversion device 100 of the first embodiment, in which each pixel 12 has two photoelectric conversion elements PDA and PDB. Matters not mentioned in the modified example shown in Fig. 8 may follow the above description.

[0065] In the modification shown in FIG. 8, each pixel 12 includes two transfer units M1A and M1B. The transfer units M1A and M1B are each configured with a transistor, and control signals TXA and TXB may be supplied to their gates from the vertical drive circuit 30. Each pixel 12 may also include sample and hold transistors M7, M12, and M13 and corresponding memories CN, CSA, and CSAB. Sources of the sample and hold transistors M7, M12, and M13 may be connected to node N1. Second terminals of the memories CN, CSA, and CSAB may be connected to a ground node. Gates of the sample and hold transistors M7, M12, and M13 may be supplied with control signals GSTXN, GSTXSA, and GSTXSAB from the vertical drive circuit 30.

[0066] FIG. 9 illustrates an example of an in-pixel readout operation during period B of the modified example shown in FIG. 8. Matters not described here may follow the above explanation. The accumulation period is until just before time t1, and period B, i.e., the in-pixel readout period, is from time t1 to time t10. Just before time t1, the control signal RES is at a high level, the transistor constituting the reset unit M2 is on, and the charge-voltage converter FD is set to a voltage corresponding to the voltage VDD. Also, just before time t1, the control signal RES1 is at a high level, the transistor constituting the reset unit M9 is on, and the node N1 is set to a voltage corresponding to the voltage VDD. Furthermore, the control signals GSTXN, GSTXSA, and GSTXSAB are also at a high level, and the sample-and-hold transistors M7, M12, and M13 are on, so that one ends of the memories CN, CSA, and CSAB are set to a voltage corresponding to the voltage VDD.

[0067] From this point on, the operation during the period from time t1 to time t3 is the same as the example in FIG. 4. Next, from time t4 to time t5, the control signal TXA is set to high level, the transistor constituting the transfer unit M1A is turned on, and the charge of the photoelectric conversion element PDA is transferred to the charge-voltage conversion unit FD. From time t5 to time t6, the control signal GSTXSA is set to high level. This turns on the sample-and-hold transistor M12, and a first image signal voltage (hereinafter referred to as the SA signal) corresponding to the charge of the photoelectric conversion element PDA is written to the memory CSA. Then, at time t6, the control signal GSTXSA changes from high level to low level, and the sample-and-hold transistor M12 changes from on to off, causing the memory CSA to enter a hold state.

[0068] During the period from time t7 to time t8, the control signals TXA and TXB are set to high level, turning on the transistors constituting the transfer units M1A and M1B, respectively, and transferring the charges of the photoelectric conversion elements PDA and PDB to the charge-voltage converter FD. That is, in the charge-voltage converter FD, the charge of the photoelectric conversion element PDB is added to the charge of the photoelectric conversion element PDA. At this time, it is possible to appropriately select whether or not to transfer the charge of the photoelectric conversion element PDA again to the charge-voltage converter FD using the control signal TXA.

[0069] During the period from time t9 to time t10, the control signal GSTXSAB is set to high level. This turns on the sample and hold transistor M13, and a second image signal voltage (hereinafter referred to as SAB signal) corresponding to the charges of the photoelectric conversion elements PDA and PDB is written to the memory CSAB. Then, at time t10, the control signal GSTXSAB changes from high level to low level, and the sample and hold transistor M13 changes from on to off, so that the capacitor CSAB enters a hold state.

[0070] In this way, the N signal, SA signal, and SAB signal are held in the memories CN, CSA, and CSAB in each pixel 12. Thereafter, the control signals GSSEL and SW go low, thereby stopping the supply of current by the current source M5.

[0071] 10 illustrates an operation (out-of-pixel readout operation) during period C of the modified example shown in FIG. 8. Matters not described here may follow the above explanation. Period B ends by time t21. During the period from time t26 to time t27, the control signal GSTXSA is set to a high level, and the sample-and-hold transistor M12 is turned on, thereby setting the SA signal held in the memory CSA to the gate of the amplification transistor M10. As a result, a signal corresponding to the SA signal is supplied to the column circuit 51 via the selection transistor M11 and the vertical output line 16, and AD conversion is performed.

[0072] Furthermore, from time t27 to time t28, the control signal RES1 is again changed from low level to high level, and the node N1 is again set (initialized) to a voltage corresponding to the voltage VDD.

[0073] During the period from time t29 to time t30, the control signal GSTXSAB is set to high level, and the sample-and-hold transistor M13 is turned on, so that the SAB signal held in the memory CSAB is set to the gate of the amplification transistor M10. As a result, a signal corresponding to the SAB signal is supplied from the vertical output line 16 to the column circuit 51 via the selection transistor M11, and AD conversion is performed. The operation after time t30 is the same as the example in FIG. 5.

[0074] In the pixel 12, a large number of photoelectric conversion elements may share one charge-voltage converter FD. The pixel 12 may also include an element for changing the gain. In this case, the circuit configuration for reading out the signal may be changed as appropriate. The configuration of the memory that stores the signal and the configuration of the current source may also be changed as appropriate.

[0075] The pixels 12 may have an AD conversion function, and for example, the configuration described in Patent Document 2 can be applied. Even in this case, the timing at which the in-pixel readout units of the multiple pixels start the in-pixel readout operation is the same within each block, but is different between the multiple blocks, so that the peak value of current consumption can be suppressed.

[0076] In this embodiment, the current source M5 (first current source) is configured or controlled to supply a first current to the amplification transistor M3. The current source 17 (second current source) is configured or controlled to supply a second current to the amplification transistor M10. Here, it is preferable that the first current (its magnitude) is smaller than the second current (its magnitude). It is preferable that the first current (its magnitude) satisfies at least one of the following conditions: less than 90%, less than 80%, less than 70%, less than 60%, less than 50%, less than 40%, less than 30%, less than 20%, or less than 10% of the second current (its magnitude). Alternatively, it is preferable that the first current (its magnitude) satisfies at least one of the following conditions: less than 1 / 2, less than 1 / 4, less than 1 / 8, less than 1 / 16, less than 1 / 32, less than 1 / 64, less than 1 / 128, less than 1 / 256, or less than 1 / 512 of the second current (its magnitude).

[0077] The advantage of making the first current (magnitude) smaller than the second current (magnitude) will be described below. One amplifier transistor M3, to which one current source M5 supplies the first current, writes a signal to only one of the memories CN, CA, and CAB at a time. Therefore, the current (magnitude) required for one current source M5 is relatively small.

[0078] On the other hand, one amplification transistor M10 to which the current source 17 supplies the second current needs to drive the load (capacitance) of the vertical output line 16 extending in the column direction and the multiple selection transistors M11 connected thereto. Therefore, the current (magnitude) required for one current source 17 is relatively large. Therefore, the first current (magnitude) may be smaller than the second current (magnitude). In global shutter mode, the current sources M5 of the multiple pixels 12 constituting the pixel array 10 operate simultaneously during the intra-pixel readout period of period B. Therefore, making the first current (magnitude) smaller than the second current (magnitude) is useful for suppressing the peak value of current consumption. Suppressing the peak value of current consumption stabilizes the power supply potential and ground potential, thereby advantageous for reducing noise. Suppressing the peak value of current consumption is also advantageous for reducing power consumption. [Second embodiment] The second embodiment will be described below with reference to Figures 11A and 11B. Figure 11B shows a detailed example of operation during the period from time t100 to t300 in Figure 11A. Matters not mentioned in the second embodiment may follow the first embodiment.

[0079] In the second embodiment, the vertical drive circuit 30 (controller) controls the plurality of pixels 12 to perform a preliminary operation prior to an intra-pixel readout operation. At this time, the vertical drive circuit 30 controls the execution of the preliminary operation for each of the plurality of blocks BLK1 to BLK6. The preliminary operation includes an operation of turning on the control transistor M6 while causing the reset unit M2 to reset the charge-voltage converter FD.

[0080] The vertical drive circuit 30 may control the plurality of pixels 12 so that, during at least a portion of a period in which an in-pixel readout operation is performed in one of the plurality of blocks, a preparatory operation is performed in the block in which the next in-pixel readout operation is to be performed among the plurality of blocks. Alternatively, the vertical drive circuit 30 may control the plurality of pixels 12 so that, during a period in which an in-pixel readout operation is performed in one of the plurality of blocks, a preparatory operation is performed in the block in which the next in-pixel readout operation is to be performed among the plurality of blocks. Alternatively, the vertical drive circuit 30 may control the plurality of pixels 12 so that, during the entire period in which an in-pixel readout operation is performed in one of the plurality of blocks, a preparatory operation is performed in the block in which the next in-pixel readout operation is to be performed among the plurality of blocks.

[0081] As described above, by performing the preparatory operation prior to the in-pixel readout operation, the operation of the constant current M5 of the in-pixel readout unit PRD can be stabilized before the in-pixel readout operation starts, thereby improving image quality. The current value flowed by the current source M5 in the preparatory operation may be the same as the current value flowed by the current source M5 in the in-pixel readout operation, or may be smaller than the current value flowed by the current source M5 in the in-pixel readout operation. [Third embodiment] The third embodiment will be described below with reference to Fig. 12 and Fig. 11B. Fig. 11B, which is used in the third embodiment, shows a detailed example of operation during the period from time t100 to t300 in Fig. 12. The third embodiment is a modification of the second embodiment, and matters not mentioned in the third embodiment may follow the second embodiment.

[0082] The vertical drive circuit 30 can control the multiple pixels 12 so that preparatory operations are performed in other blocks during a period in which an intra-pixel readout operation is performed last in one of the multiple blocks BLK1 to BLK6. From another perspective, the vertical drive circuit 30 can control the multiple pixels 12 so that the number of blocks on which preparatory operations are simultaneously performed is constant. In the example shown in Fig. 12, the vertical drive circuit 30 controls the multiple pixels 12 so that the number of blocks on which preparatory operations are simultaneously performed is constant at one.

[0083] According to the third embodiment, fluctuations in current consumption during the period when the intra-pixel readout circuit PRD is performing an intra-pixel readout operation can be suppressed, and image quality can be improved. [Fourth embodiment] The fourth embodiment will be described below with reference to Fig. 11B in addition to Fig. 13 and Fig. 14. Fig. 11B, which is used in the fourth embodiment, shows a detailed example of operation during the period from time t100 to t300 in Fig. 14. The fourth embodiment is a modification of the second or third embodiment, and matters not mentioned in the fourth embodiment may follow the second or third embodiment.

[0084] The photoelectric conversion device 100 of the fourth embodiment includes a dummy current source 700. The vertical drive circuit 30 can operate the dummy current source 700 during a period from t600 to t700 when an intra-pixel readout operation is performed in block BLK6, which is the last of the multiple blocks BLK1 to BLK6 to undergo an intra-pixel readout operation.

[0085] The current value flowed by the dummy current source 700 may be the same as the current value flowed by the current source M5 in the in-pixel reading operation, or may be different from the current value flowed by the current source M5 in the in-pixel reading operation, but it is preferable that it be the same as the current value flowed by the current source M5 in the preliminary operation. [Fifth embodiment] The fifth embodiment will be described below with reference to Fig. 15. Matters not mentioned in the fifth embodiment may follow those of the first to fourth embodiments. The fifth embodiment relates to a method of dividing the pixel array 10 (the plurality of pixels 12 constituting the pixel array 10).

[0086] The multiple blocks BLK1 to BLK6 that make up the pixel array 10 can be arranged to form multiple block rows and multiple block columns, as illustrated in FIG. 15. A block row is a row made up of two or more blocks, and a block column is a column made up of two or more blocks. The vertical drive circuit 30 supplies control signals to blocks that belong to the same block row through different control line groups 14. The vertical drive circuit 30 can be configured to drive the multiple blocks BLK1 to BLK6 that make up the pixel array 10 in a predetermined order. [Sixth embodiment] The sixth embodiment will be described below with reference to Figs. 16 and 17. Matters not mentioned in the sixth embodiment may follow those of the first to fifth embodiments. In the sixth embodiment, the photoelectric conversion device 100 may be configured by a laminated substrate in which multiple substrates 1000, 1001, and 1002 are stacked. Each of the multiple substrates includes a semiconductor layer.

[0087] In one example, at least a part of the extra-pixel readout unit RC, which may be composed of the drive circuit group 40, the column circuit group 50, the horizontal drive circuit 60, etc., may be arranged on a substrate 1002 (third substrate) different from the substrate 1000 (first substrate) or the substrate 10001 (second substrate) on which the plurality of pixels 12 are arranged. For example, the extra-pixel drive unit RC (the drive circuit group 40, the column circuit group 50, and the horizontal drive circuit 60), the signal processing circuit 70, the output circuit 80, and the system control unit 90 may be arranged on the substrate 1002.

[0088] The components of multiple pixels 12 may be arranged on two or more substrates 1000 and 1001. In the example shown in FIG. 16, the first substrate 1000 is arranged with a photoelectric conversion element PD, a transfer unit M1, a reset unit M2, an amplifier transistor M3, and a selection transistor M4. The second substrate 1001 is arranged with a current source M5, a control transistor M6, memories CN and CS, sample-and-hold transistors M7 and M8, an amplifier transistor M10, a selection transistor M11, and a reset unit M9. The third substrate 1002 is arranged with a vertical output line 16, a current source 17, and circuits subsequent to the AD conversion circuit. Here, the connection structure between the substrates indicated by the connection units 1003 and 1004 is not particularly limited. Furthermore, the elements arranged on each substrate and their combinations are not limited to those shown. For example, a configuration such as that shown in FIG. 8, in which one pixel has multiple photoelectric conversion elements, can be applied. The use of a stacked substrate improves area efficiency, thereby easing constraints on element arrangement and simplifying element size and circuit arrangement. Furthermore, by reducing crosstalk, degradation of image quality can be reduced. [Seventh embodiment] The seventh embodiment will be described below with reference to FIG. 19. The seventh embodiment provides a first modified example of the operation of the photoelectric conversion device 100 of the first embodiment. More specifically, in the circuit configuration of FIG. 2, the seventh embodiment differs from the first embodiment in the intra-pixel readout operation during the intra-pixel readout period of period B in FIG. 3. Here, the intra-pixel readout operation of the seventh embodiment will be described, focusing on the differences from the intra-pixel readout operation of the first embodiment described with reference to FIG. 4.

[0089] The first difference is that in the seventh embodiment, the control signal SW of the control transistor M6 is voltage-controlled by three types of voltages: L level (low level), M level (middle level), and H level (high level). Note that the control voltages have the relationship of L level < M level < H level. The on-resistance of the control transistor M6 decreases as the control voltage increases. The second difference is the control of the control signal SW. First, at time t1, the control signal SW is changed from the L level to the M level, and at time t1a, the control signal SW is changed from the M level to the H level. Also, at time t6a within the period from time t5 to time t6, the control signal GSTXS changes from the H level to the L level. Then, at time t6a, the control signal SW is changed from the H level to the M level, and at time t6, the control signal SW is changed from the M level to the L level.

[0090] The point to note here is that the voltage level of the control signal SW is sequentially switched, or in other words, the resistance value of the control transistor M6 is sequentially changed. In the seventh embodiment, instead of rapidly changing the resistance value from the high resistance in the OFF state to the low resistance in the ON state or from the low resistance to the high resistance, it is controlled to be an intermediate resistance between the high resistance and the low resistance to reduce the change in resistance. According to such control, a sudden current change where a large current suddenly flows or the current suddenly cuts off does not occur in the pixel internal readout unit PRD.

[0091] The fact that a sudden current change does not occur means that fluctuations in the power supply voltage are less likely to occur. This is advantageous for suppressing problems such as the signal readout from the pixel being unstable and taking a long time for readout, and the image quality deteriorating due to the influence of noise.

[0092] Note that in the seventh embodiment, an example where the voltage level of the control signal SW is three types is shown, but the number of types of voltage levels is not limited to this example, and more than three types of voltage levels may be provided. [Eighth Embodiment] The eighth embodiment will be described below with reference to FIG. 20. The eighth embodiment provides a second modified example of the operation of the photoelectric conversion device 100 of the first embodiment. More specifically, in the circuit configuration of FIG. 2, the eighth embodiment differs from the first and seventh embodiments in the intra-pixel readout operation during the intra-pixel readout period of period B in FIG. 3. Here, the intra-pixel readout operation of the seventh embodiment will be described, focusing on the differences from the intra-pixel readout operation of the seventh embodiment described with reference to FIG. 19.

[0093] In the eighth embodiment, the voltage level of the control signal SW is changed over time from L level to H level or from H level to L level. In this way, a sudden change in current, such as a sudden current flow or current cutoff, does not occur in the in-pixel readout unit PRD, as described in the seventh embodiment.

[0094] Therefore, the eighth embodiment is also advantageous in that it can prevent problems such as unstable readout of signals from pixels, which takes a long time to read, and problems such as deterioration of image quality due to the influence of noise. [Ninth embodiment] The ninth embodiment will be described below with reference to Fig. 21. The ninth embodiment provides a third modified example of the operation of the photoelectric conversion device 100 of the first embodiment. More specifically, in the circuit configuration of Fig. 8, the ninth embodiment differs from the first embodiment in the intra-pixel readout operation during the intra-pixel readout period of period B in Fig. 3.

[0095] In the ninth embodiment, the voltage level of the control signal SW is switched sequentially at time t1, time t1a, and then time t10a and time t10, thereby sequentially changing the resistance value of the control transistor M6 and suppressing abrupt current changes.

[0096] Therefore, the ninth embodiment is also advantageous in that it can prevent problems such as unstable readout of signals from pixels, which takes a long time to read, and problems such as deterioration of image quality due to the influence of noise. [Tenth embodiment] The tenth embodiment will be described below with reference to Fig. 22. The tenth embodiment provides a fourth modified example of the operation of the photoelectric conversion device 100 of the first embodiment. More specifically, in the circuit configuration of Fig. 8, the tenth embodiment differs from the first and ninth embodiments in the intra-pixel readout operation during the intra-pixel readout period of period B in Fig. 3.

[0097] In the tenth embodiment, the voltage level of the control signal SW is changed over time at time t1, time t1a, and further at time t10a and time t10, thereby changing the resistance value of the control transistor M6 and suppressing abrupt current changes.

[0098] Therefore, the tenth embodiment is also advantageous in that it can prevent problems such as unstable readout of signals from pixels, which takes a long time to read, and problems such as deterioration of image quality due to the influence of noise. [Application example] One application example of the photoelectric conversion device 100 is an imaging device that generates an image (image data) by capturing an optical image. Other application examples of the photoelectric conversion device include a distance measuring device (a device that measures distance using focus detection or TOF (Time Of Flight)), a photometric device (a device that measures the amount of incident light), etc.

[0099] Hereinafter, an apparatus EQ incorporating a photoelectric conversion device 100 will be described with reference to FIG. 18. The apparatus EQ may include at least one of the photoelectric conversion device 100 configured as an image sensor, an optical device 1040, a control device 1050, a processing device 1060, a display device 1070, a storage device 1080, and a mechanical device 1090. The optical device 1040 is, for example, a lens, a shutter, or a mirror. The control device 1050 controls the semiconductor chip 210. The control device 1050 is, for example, a semiconductor device such as an ASIC.

[0100] The processing device 1060 processes the signal output from the semiconductor chip 210. The processing device 1060 is a semiconductor device such as a CPU or ASIC for configuring an analog front end (AFE) or a digital front end (DFE). The display device 1070 is an EL display device or a liquid crystal display device that displays information (images) obtained by the semiconductor chip 210. The storage device 1080 is a magnetic device or a semiconductor device that stores information (images) obtained by the semiconductor chip 210. The storage device 1080 is a volatile memory such as an SRAM or a DRAM, or a non-volatile memory such as a flash memory or a hard disk drive.

[0101] The mechanical device 1090 has a moving part or a propulsion part such as a motor or an engine. In the device EQ, the signal output from the semiconductor chip 210 is displayed on the display device 1070, or transmitted to the outside by a communication device (not shown) included in the device EQ. For this purpose, the device EQ may further include a storage device 1080 and a processing device 1060 in addition to the storage circuit and arithmetic circuit included in the semiconductor chip 210. The mechanical device 1090 may be controlled based on the signal output from the semiconductor chip 210.

[0102] The device EQ is also suitable for electronic devices such as information terminals with a photographing function (e.g., smartphones and wearable terminals) and cameras (e.g., interchangeable lens cameras, compact cameras, video cameras, and surveillance cameras). The mechanical device 1090 in the camera can drive components of the optical device 1040 for zooming, focusing, and shutter operation. Alternatively, the mechanical device 1090 in the camera can move the semiconductor chip 210 for vibration isolation operations.

[0103] Furthermore, the equipment EQ may be transportation equipment such as a vehicle, a ship, or an aircraft. The mechanical device 1090 in transportation equipment may be used as a moving device. The equipment EQ as transportation equipment is suitable for transporting semiconductor chips 210 or for assisting and / or automating driving (piloting) using a photographing function. The processing device 1060 for assisting and / or automating driving (piloting) can perform processing for operating the mechanical device 1090 as a moving device based on information obtained by the semiconductor chip 210. Alternatively, the equipment EQ may be a medical device such as an endoscope, a measuring device such as a distance measuring sensor, an analytical device such as an electron microscope, an office machine such as a copier, or an industrial device such as a robot. [Disclosures] The present specification and drawings include the following disclosure. (Item 1) A photoelectric conversion device having a plurality of pixels arranged to form a plurality of rows and a plurality of columns, a control unit that divides the plurality of pixels into a plurality of blocks and controls the plurality of pixels; each of the plurality of blocks includes pixels arranged in the same row and pixels arranged in different rows; Each pixel includes a photoelectric conversion element and an in-pixel readout unit that performs an in-pixel readout operation of reading and holding a signal from the photoelectric conversion element, the control unit controls the pixels so that periods during which the in-pixel readout units of the pixels perform the in-pixel readout operation are the same within each block and different from one another among the blocks. A photoelectric conversion device characterized by: (Item 2) the control unit controls the plurality of pixels so that the timings at which the in-pixel readout units of the plurality of pixels start the in-pixel readout operation are the same within each block and different from one another among the plurality of blocks. 2. The photoelectric conversion device according to item 1, (Item 3) the in-pixel readout unit includes a source follower circuit; 3. The photoelectric conversion device according to item 1 or 2, (Item 4) the source follower circuit includes an amplifying transistor, a current source, and a control transistor, the amplifying transistor, the current source, and the control transistor being connected in series; the control unit causes the in-pixel readout operation to be performed by turning on the control transistor; 4. The photoelectric conversion device according to item 3, (Item 5) the in-pixel readout unit further includes a charge-voltage conversion unit, a transfer unit that transfers the charge of the photoelectric conversion element to the charge-voltage conversion unit, and a reset unit that resets the charge-voltage conversion unit, and the source follower circuit reads out a signal corresponding to a voltage of the charge-voltage conversion unit as a signal of the photoelectric conversion element; 5. The photoelectric conversion device according to item 4, (Item 6) the in-pixel readout operation includes a first operation of reading out a noise level from the photoelectric conversion element and a second operation of reading out an optical signal level corresponding to incident light from the photoelectric conversion element; the in-pixel readout unit includes a first memory that stores the noise level and a second memory that stores the optical signal level; 6. The photoelectric conversion device according to item 5, (Item 7) the control unit controls the pixels to perform a preparatory operation prior to the intra-pixel readout operation; the control unit controls the execution of the preparatory movement for each of the plurality of blocks; the preliminary operation includes an operation of turning on the control transistor in a state in which the reset unit resets the charge-voltage conversion unit. 7. The photoelectric conversion device according to item 6, (Item 8) the control unit controls the plurality of pixels so that, during at least a part of a period in which the intra-pixel readout operation is performed in one of the plurality of blocks, the preparatory operation is performed in a block of the plurality of blocks in which the intra-pixel readout operation is to be performed next. 8. The photoelectric conversion device according to item 7, (Item 9) the control unit controls the plurality of pixels so that, during a period in which the intra-pixel readout operation is performed in one block among the plurality of blocks, the preparatory operation is performed in a block among the plurality of blocks in which the intra-pixel readout operation is to be performed next. 8. The photoelectric conversion device according to item 7, (Item 10) the control unit controls the plurality of pixels so that the preliminary operation is performed in another block during a period in which the intra-pixel readout operation is performed last in the block among the plurality of blocks. 10. The photoelectric conversion device according to item 9, (Item 11) the control unit controls the plurality of pixels so that the number of blocks on which the preparatory operation is simultaneously performed is constant. 10. The photoelectric conversion device according to item 9, (Item 12) further comprising a dummy current source; the control unit operates the dummy current source during a period in which the intra-pixel readout operation is performed in a block among the plurality of blocks in which the intra-pixel readout operation is performed last; 10. The photoelectric conversion device according to item 9, (Item 13) the control unit controls the plurality of pixels so that a period during which the photoelectric conversion elements of the plurality of pixels perform a charge accumulation operation is the same within each block and different among the plurality of blocks. 13. The photoelectric conversion device according to any one of items 1 to 12, characterized in that: (Item 14) the control unit controls the plurality of pixels so that the timings at which the photoelectric conversion elements of the plurality of pixels start the charge accumulation operation are the same within each block and different among the plurality of blocks. Item 14. The photoelectric conversion device according to item 13, (Item 15) further comprising an extra-pixel readout unit that reads out signals from the plurality of pixels; after the intra-pixel readout operation in all of the plurality of pixels is completed, the extra-pixel readout unit starts reading out signals from the plurality of pixels. Item 15. The photoelectric conversion device according to item 14. (Item 16) the source follower circuit further includes a selection transistor disposed between the amplification transistor and the current source. 13. The photoelectric conversion device according to any one of items 4 to 12, wherein: (Item 17) the plurality of blocks are arranged to form a plurality of block rows and a plurality of block columns; 17. The photoelectric conversion device according to any one of items 1 to 16, (Item 18) further comprising an extra-pixel readout unit that reads out signals from the plurality of pixels; At least a part of the extra-pixel readout unit is arranged on a third substrate different from the first substrate or the second substrate on which the plurality of pixels are arranged. 18. The photoelectric conversion device according to any one of items 1 to 17, (Item 19) The plurality of pixel components are disposed on two or more substrates. 19. The photoelectric conversion device according to any one of items 1 to 18, (Item 21) a current flowing through the source follower circuit is controlled by a switch transistor; The gate voltage of the switch transistor is controlled by at least three voltages. 4. The photoelectric conversion device according to item 3, (Item 22) a current flowing through the source follower circuit is controlled by a switch transistor; The gate voltage of the switch transistor is controlled by a time-varying slope voltage. 4. The photoelectric conversion device according to item 3, (Item 22) The photoelectric conversion device according to any one of items 1 to 21, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

[0104] The invention is not limited to the above-described embodiments, and various changes and modifications can be made without departing from the spirit and scope of the invention. Accordingly, the following claims are appended to apprise the public of the scope of the invention. [Explanation of symbols]

[0105] 10: pixel array, 12: pixel, 16: vertical output line, 17: current source, 30: vertical drive circuit, 40: drive circuit group, 41: drive circuit, 50: column circuit group, 50A: reference signal generator, 50B: counter circuit, 51: column circuit, 60: horizontal drive circuit, 70: signal processing circuit, 80: output circuit, 90: system control unit, 100: photoelectric conversion device, 400: current source, PRD: in-pixel readout unit, RC: extra-pixel readout unit

Claims

1. A photoelectric conversion device having a plurality of pixels arranged to form a plurality of rows and a plurality of columns, a control unit that divides the plurality of pixels into a plurality of blocks and controls the plurality of pixels; each of the plurality of blocks includes pixels arranged in the same row and pixels arranged in different rows; Each pixel includes a photoelectric conversion element and an in-pixel readout unit that performs an in-pixel readout operation of reading and holding a signal from the photoelectric conversion element, the control unit controls the pixels so that periods during which the in-pixel readout units of the pixels perform the in-pixel readout operation are the same within each block and different from one another among the blocks. A photoelectric conversion device characterized by:

2. the control unit controls the plurality of pixels so that the timings at which the in-pixel readout units of the plurality of pixels start the in-pixel readout operation are the same within each block and different from one another among the plurality of blocks.

2. The photoelectric conversion device according to claim 1.

3. the in-pixel readout unit includes a source follower circuit; 2. The photoelectric conversion device according to claim 1.

4. the source follower circuit includes an amplifying transistor, a current source, and a control transistor, the amplifying transistor, the current source, and the control transistor being connected in series; the control unit causes the in-pixel readout operation to be performed by turning on the control transistor; 4. The photoelectric conversion device according to claim 3.

5. the in-pixel readout unit further includes a charge-voltage conversion unit, a transfer unit that transfers the charge of the photoelectric conversion element to the charge-voltage conversion unit, and a reset unit that resets the charge-voltage conversion unit, and the source follower circuit reads out a signal corresponding to a voltage of the charge-voltage conversion unit as a signal of the photoelectric conversion element; 5. The photoelectric conversion device according to claim 4.

6. the in-pixel readout operation includes a first operation of reading out a noise level from the photoelectric conversion element and a second operation of reading out an optical signal level corresponding to incident light from the photoelectric conversion element; the in-pixel readout unit includes a first memory that stores the noise level and a second memory that stores the optical signal level; 6. The photoelectric conversion device according to claim 5.

7. the control unit controls the pixels to perform a preparatory operation prior to the intra-pixel readout operation; the control unit controls the execution of the preparatory movement for each of the plurality of blocks; the preliminary operation includes an operation of turning on the control transistor in a state in which the reset unit resets the charge-voltage conversion unit.

7. The photoelectric conversion device according to claim 6.

8. the control unit controls the plurality of pixels so that, during at least a part of a period in which the intra-pixel readout operation is performed in one of the plurality of blocks, the preparatory operation is performed in a block of the plurality of blocks in which the intra-pixel readout operation is to be performed next.

8. The photoelectric conversion device according to claim 7.

9. the control unit controls the plurality of pixels so that, during a period in which the intra-pixel readout operation is performed in one block among the plurality of blocks, the preparatory operation is performed in a block among the plurality of blocks in which the intra-pixel readout operation is to be performed next.

8. The photoelectric conversion device according to claim 7.

10. the control unit controls the plurality of pixels so that the preliminary operation is performed in another block during a period in which the intra-pixel readout operation is performed last in the block among the plurality of blocks.

10. The photoelectric conversion device according to claim 9.

11. the control unit controls the plurality of pixels so that the number of blocks on which the preparatory operation is simultaneously performed is constant.

10. The photoelectric conversion device according to claim 9.

12. further comprising a dummy current source; the control unit operates the dummy current source during a period in which the intra-pixel readout operation is performed in a block among the plurality of blocks in which the intra-pixel readout operation is performed last; 10. The photoelectric conversion device according to claim 9.

13. the control unit controls the plurality of pixels so that a period during which the photoelectric conversion elements of the plurality of pixels perform a charge accumulation operation is the same within each block and different among the plurality of blocks.

2. The photoelectric conversion device according to claim 1.

14. the control unit controls the plurality of pixels so that the timings at which the photoelectric conversion elements of the plurality of pixels start the charge accumulation operation are the same within each block and different among the plurality of blocks.

14. The photoelectric conversion device according to claim 13.

15. further comprising an extra-pixel readout unit that reads out signals from the plurality of pixels; after the intra-pixel readout operation in all of the plurality of pixels is completed, the extra-pixel readout unit starts reading out signals from the plurality of pixels.

15. The photoelectric conversion device according to claim 14.

16. the source follower circuit further includes a selection transistor disposed between the amplification transistor and the current source.

5. The photoelectric conversion device according to claim 4.

17. the plurality of blocks are arranged to form a plurality of block rows and a plurality of block columns; 2. The photoelectric conversion device according to claim 1.

18. further comprising an extra-pixel readout unit that reads out signals from the plurality of pixels; at least a part of the extra-pixel readout unit is disposed on a third substrate different from the first substrate or the second substrate on which the plurality of pixels are disposed; 2. The photoelectric conversion device according to claim 1.

19. The plurality of pixel components are disposed on two or more substrates.

2. The photoelectric conversion device according to claim 1.

20. a current flowing through the source follower circuit is controlled by a switch transistor; The gate voltage of the switch transistor is controlled by at least three voltages.

4. The photoelectric conversion device according to claim 3.

21. a current flowing through the source follower circuit is controlled by a switch transistor; The gate voltage of the switch transistor is controlled by a time-varying slope voltage.

4. The photoelectric conversion device according to claim 3.

22. The photoelectric conversion device according to any one of claims 1 to 21, a processing device that processes a signal output from the photoelectric conversion device; An apparatus characterized by comprising:

Images