Power semiconductor device

Abstract

To suppress a decrease in detection accuracy of a current flowing in a main cell region.SOLUTION: A power semiconductor device includes: a semiconductor chip 20 having a main cell region Rm, a sense cell region Rs, and an outer peripheral region Rp surrounding the main cell region Rm and the sense cell region; a control circuit part 300 electrically connected to the semiconductor chip 20 to perform processing; and a coupling member 50 connected to the semiconductor chip 20. When a portion of an electrode 209 in the main cell region Rm that faces a portion to which a connecting member 50 is joined with a joining member is defined as a facing part 510, a main connection wiring 230 is connected to a side of the electrode 209 in the main cell region Rm that is different from a side on which distances d1 to d4 between the facing part 510 and sides Rm1 to Rm4 forming the contour of the electrode 209 are the longest.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present disclosure relates to a power semiconductor device including a semiconductor chip having a main cell region and a sense cell region. [Background technology]

[0002] Conventionally, power semiconductor devices have been proposed that include a semiconductor chip having a main cell region where a main element is formed and a sense cell region where a sense element is formed (see, for example, Patent Document 1). Specifically, the semiconductor chip of this power semiconductor device has MOSFET (Metal Oxide Semiconductor Field Effect Transistor) elements of the same configuration formed in the main cell region and the sense cell region, and is formed so that the main cell region and the sense cell region have a predetermined area ratio. Also, this semiconductor chip has a Kelvin source pad connected to the source electrode of the main cell region via a main connection wiring, and a sense source pad connected to the source electrode of the sense cell region via a sense connection wiring. In this power semiconductor device, the gate electrode of the main cell region and the gate electrode of the sense cell region are connected to a common gate pad.

[0003] In the power semiconductor device, the current flowing in the sense cell region is detected while the potentials of the Kelvin source pad and the sense source pad are controlled to be the same, and the current flowing in the main cell region is detected based on the current flowing in the sense cell region and the area ratio between the main cell region and the sense cell region. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] Japanese Patent Application Laid-Open No. 2017-69412 Summary of the Invention [Problem to be solved by the invention]

[0005] The present inventors have been studying a power semiconductor device in which a connecting member is disposed on a source electrode of a semiconductor chip. Specifically, a protective film having an opening for exposing the source electrode is disposed on the semiconductor chip, and the connecting member is connected to the source electrode exposed through the opening. The source electrode has an inner edge exposed through the opening in the protective film and an outer edge covered by the protective film.

[0006] However, in such a power semiconductor device, the portion of the source electrode other than the portion connected to the connecting member has lower heat dissipation properties compared to the portion connected to the connecting member. More specifically, the portion of the source electrode other than the portion connected to the connecting member is likely to have a larger area where heat cannot be dissipated by the connecting member, or to have lower heat dissipation properties in the portion away from the connecting member. Furthermore, in a power semiconductor device having a semiconductor chip with a power element that carries a large current, repeated load short circuits or excessive thermal stress are likely to cause cracks in the portion of the source electrode of the main element with low heat dissipation properties. For example, in a power semiconductor device configured with a sealing member made of a resin or the like that covers the semiconductor chip and the connecting member, cracks are likely to occur in the portion of the source electrode of the main element with low heat dissipation properties where the protective film and the sealing member, which have different linear expansion coefficients, come into contact with each other.

[0007] In such a power semiconductor device, if the main connection wiring is connected to a portion of the source electrode in the main cell region that is prone to cracking, the cracked portion will not be conductive, and the potential gradient will increase, making it more likely that a potential difference will occur between the source electrode and the Kelvin source pad. Therefore, in such a power semiconductor device, the sense ratio will vary, and the detection accuracy of the current flowing in the main cell region may decrease.

[0008] An object of the present disclosure is to provide a power semiconductor device that can suppress a decrease in the detection accuracy of a current flowing through a main cell region. [Means for solving the problem]

[0009] According to one aspect of the present disclosure, a power semiconductor device includes a semiconductor chip (20) having a main cell region (Rm), a sense cell region (Rs), and an outer periphery region (Rp) surrounding the main cell region and the sense cell region, a control circuit unit (300) electrically connected to the semiconductor chip for processing, and a connecting member (50) connected to the semiconductor chip, wherein the semiconductor chip has a semiconductor substrate (200) on which the main cell region, the sense cell region, and the outer periphery region are configured, and the main cell region and the sense cell region have the same configuration. The trench gate structure includes a drift layer (201) of a first conductivity type, a base layer (202) of a second conductivity type formed on the drift layer, a gate insulating film (204) arranged on the wall surface of a trench (203) that penetrates the base layer and reaches the drift layer, and a gate electrode (205) arranged on the gate insulating film; a first impurity region (206) of the first conductivity type formed in a surface layer portion of the base layer, having a higher impurity concentration than the drift layer and in contact with the trench; and a second impurity region (210) of a second conductivity type, the main cell region has an electrode (209) connected to the first impurity region and the base layer, the sense cell region has an electrode connected to the first impurity region and the base layer, and is arranged in the outer periphery region and has a main connection wiring (230) connected to the electrode of the main cell region and a sense connection wiring (240) connected to the electrode of the sense cell region, the main connection wiring and the sense connection wiring are connected to the control circuit section and cover the outer edge of the electrode of the main cell region, The main cell region has a protective film (220) having an opening (220a) that exposes the inner edge, and the connecting member is connected to the portion of the electrode in the main cell region that is exposed from the opening of the protective film via a joining member (120). If the portion of the electrode in the main cell region that faces the portion where the connecting member is joined to the joining member is defined as an opposing portion (510), the main connection wiring is connected to a side of the electrode in the main cell region that is different from the side where the distance (d1 to d4) between the opposing portion and the side (Rm1 to Rm4) that forms the outline of the electrode is longest.

[0010] According to this, the main connection wiring is connected to a side of the electrode that is different from the side that defines the longest distance between the opposing portion and the side of the electrode. Therefore, the main connection wiring is connected to a part of the electrode that is different from the part that is prone to cracking, and it is possible to suppress the occurrence of a potential difference between the electrode and the main connection wiring. Therefore, when detecting the current flowing in the main cell region with the main connection wiring and the sense connection wiring at the same potential, it is possible to suppress a decrease in the detection accuracy of the current flowing in the main cell region.

[0011] According to another aspect of the present disclosure, a power semiconductor device includes: a semiconductor chip (20) having a main cell region (Rm), a sense cell region (Rs), and a peripheral region (Rp) surrounding the main cell region and the sense cell region; a control circuit unit (300) electrically connected to the semiconductor chip; and a connecting member (50) connected to the semiconductor chip, wherein the semiconductor chip has a semiconductor substrate (200) having the main cell region, the sense cell region, and the peripheral region, the main cell region and the sense cell region having the same configuration, a trench gate structure having a first conductivity type drift layer (201), a second conductivity type base layer (202) formed on the drift layer, a gate insulating film (204) arranged on a wall surface of a trench (203) that penetrates the base layer and reaches the drift layer, and a gate electrode (205) arranged on the gate insulating film; a first conductivity type first impurity region (206) formed in a surface layer portion of the base layer, having a higher impurity concentration than the drift layer and in contact with the trench; and a second impurity region (210) of a first conductivity type or a second conductivity type formed on the opposite side to the base layer, the main cell region having an electrode (209) connected to the first impurity region and the base layer, the sense cell region having an electrode connected to the first impurity region and the base layer, and arranged in the outer periphery region, having a main connection wiring (230) connected to the electrode of the main cell region and a sense connection wiring (240) connected to the electrode of the sense cell region, the main connection wiring and the sense connection wiring being connected to a control circuit unit, and having a protective film (220) covering the outer edge of the electrode of the main cell region and having an opening (220a) that exposes the inner edge, the connecting member being connected to the portion of the electrode of the main cell region that is exposed from the opening of the protective film via a bonding member (120), the trench being formed with one direction in the surface direction of the semiconductor substrate as its longitudinal direction, and the main connection wiring being connected to a side of the electrode of the main cell region that forms the outline of the electrode that intersects with the longitudinal direction.

[0012] According to this, the main connection wiring is connected to the side of the electrode that intersects with the longitudinal direction of the trench. Therefore, even if a crack occurs near the portion of the electrode that is connected to the main connection wiring, current flows through the semiconductor substrate, thereby preventing a potential difference from occurring between the electrode and the main connection wiring. Therefore, when detecting a current flowing in the main cell region with the main connection wiring and the sense connection wiring at the same potential, a decrease in the detection accuracy of the current flowing in the main cell region can be prevented.

[0013] The reference symbols in parentheses attached to each component indicate an example of the correspondence between the component and the specific components described in the embodiments described below. [Brief explanation of the drawings]

[0014] [Figure 1] FIG. 1 is a plan view of a power semiconductor device according to a first embodiment. [Figure 2] FIG. 2 is a cross-sectional view taken along line II-II in FIG. [Figure 3] FIG. 1 is a circuit diagram of a power semiconductor device according to a first embodiment. [Figure 4] FIG. 2 is a plan view of a semiconductor chip. [Figure 5] FIG. 5 is a cross-sectional view taken along line VV in FIG. [Figure 6] FIG. 5 is a plan view of the semiconductor chip shown in FIG. 4 to which trenches are added. [Figure 7] 3 is a schematic diagram showing a current flow when a crack occurs in the power semiconductor device of the first embodiment. FIG. [Figure 8] FIG. 10 is a schematic diagram showing a current flow when a crack occurs in the power semiconductor device of the comparative example. [Figure 9A] FIG. 10 is a plan view of a semiconductor chip according to a modified example of the first embodiment. [Figure 9B] FIG. 10 is a plan view of a semiconductor chip according to a modified example of the first embodiment. [Figure 9C] FIG. 10 is a plan view of a semiconductor chip according to a modified example of the first embodiment. [Figure 9D] FIG. 10 is a plan view of a semiconductor chip according to a modified example of the first embodiment. [Figure 10] FIG. 10 is a plan view of a semiconductor chip according to a second embodiment. [Figure 11A] FIG. 10 is a plan view of a semiconductor chip according to a modified example of the second embodiment. [Figure 11B] FIG. 10 is a plan view of a semiconductor chip according to a modified example of the second embodiment. [Figure 12] FIG. 10 is a plan view of a semiconductor chip according to a third embodiment. [Figure 13] FIG. 11 is a plan view of a semiconductor chip according to a modified example of the third embodiment. [Figure 14] FIG. 10 is a plan view of a semiconductor chip according to a fourth embodiment. [Figure 15] FIG. 10 is a plan view of a power semiconductor device according to a fifth embodiment. [Figure 16] FIG. 13 is a plan view of a power semiconductor device according to a sixth embodiment. DETAILED DESCRIPTION OF THE INVENTION

[0015] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, identical or equivalent parts will be denoted by the same reference numerals.

[0016] (First embodiment) A power semiconductor device according to a first embodiment will be described with reference to the drawings. The power semiconductor device according to the present embodiment is suitable for use as a device mounted on a vehicle such as an automobile to drive various electronic devices for the vehicle.

[0017] As shown in Figures 1 and 2, the power semiconductor device of this embodiment comprises a first support member 10, a semiconductor chip 20, a circuit chip 30, a second support member 40, a connecting member 50, a sealing member 60, etc., which are integrated together.

[0018] First, the circuit configuration of the power semiconductor device of this embodiment will be described with reference to Fig. 3. As shown in Fig. 3, in the power semiconductor device of this embodiment, a semiconductor chip 20 is connected to a circuit chip 30 via a connecting member 70 such as a bonding wire. The semiconductor chip 20 has a main element Me and a sense element Se formed thereon, as will be described in detail later. The main element Me and the sense element Se are formed of the same semiconductor element, which in this embodiment is a MOSFET element. The main element Me and the sense element Se are formed to have a predetermined area ratio (for example, 5000:1).

[0019] The main element Me and the sense element Se are connected to a power supply P via a common drain electrode 211, and connected to the circuit chip 30 via a common gate pad 103. The main element Me is connected to a load M via a source electrode 209, and is also connected to the circuit chip 30 via a Kelvin source pad 101 connected to the source electrode 209. The sense element Se is connected to the circuit chip 30 via a sense source pad 102.

[0020] The above is the circuit configuration of the power semiconductor device of this embodiment. In the power semiconductor device of this embodiment, the current flowing through the main element Me is detected as follows. That is, in the semiconductor chip 20 of this embodiment, the same semiconductor element is formed in the main element Me and the sense element Se, but the areas of the main element Me and the sense element Se are different. Therefore, a current flows through the main element Me and the sense element Se according to their area ratio.

[0021] The circuit chip 30, the details of which will be described later, is configured to include a predetermined control circuit unit 300, and controls the gate-source (i.e., Kelvin source pad) voltage of the main element Me to be equal to the gate-source (i.e., sense source pad) voltage of the sense element Se. The circuit chip 30 then detects the current flowing through the sense element Se and the current flowing through the main element Me (i.e., main cell region Rm, described later) based on the area ratio between the main element Me and the sense element Se.

[0022] Next, the configuration of the power semiconductor device of this embodiment will be described.

[0023] 1 and 2, the first support member 10 is formed of, for example, a lead frame made of copper, iron, or an alloy thereof, and is plate-shaped having a surface 10a and a back surface 10b opposite to the surface 10a. Note that, for ease of understanding, Fig. 1 shows only the outline of the sealing member 60, and the parts arranged inside the sealing member 60 are also shown by solid lines as appropriate.

[0024] As shown in Figure 4, the semiconductor chip 20 is configured to have a main cell region Rm in which the main element Me is formed, a sense cell region Rs in which the sense element Se is formed, and a peripheral region Rp surrounding the main cell region Rm and the sense cell region Rs.

[0025] The main cell region Rm of this embodiment has a planar shape that has first to fourth sides Rm1 to Rm4 that form the outline (i.e., the outer shape), and is a substantially rectangular shape with a portion of the fourth side Rm4 cut out. The sense cell region Rs is disposed in the cut-out portion of the main cell region Rm and is substantially surrounded by the main cell region Rm. In the outer periphery region Rp, a Kelvin source pad 101, a sense source pad 102, a gate pad 103, etc. are arranged side by side along one side of the outer shape of the semiconductor chip 20.

[0026] The configurations of the main cell region Rm, sense cell region Rs, and outer peripheral region Rp of this embodiment will be described below with reference to FIG. 5. Note that, as described above, MOSFET elements of the same configuration are formed in the main cell region Rm and sense cell region Rs of this embodiment. Therefore, the following description will be given using the configuration of the main cell region Rm as an example, but the configuration of the sense cell region Rs is also similar. Furthermore, as described above, the main cell region Rm and the sense cell region Rs are formed to have a predetermined area ratio (for example, 5000:1).

[0027] 5, the semiconductor chip 20 is configured using a semiconductor substrate 200. The semiconductor substrate 200 is made of N - The semiconductor substrate 200 has a P-type drift layer 201, and a P-type base layer 202 having a relatively low impurity concentration is disposed on the drift layer 201. In the following description, the surface of the semiconductor substrate 200 on the base layer 202 side will be referred to as one surface 200a of the semiconductor substrate 200, and the surface of the semiconductor substrate 200 on the drift layer 201 side will be referred to as the other surface 200b.

[0028] A plurality of trenches 203 are formed in the semiconductor substrate 200 so as to penetrate the base layer 202 from the one surface 200a side to reach the drift layer 201, and the base layer 202 is separated into a plurality of pieces by the trenches 203. The plurality of trenches 203 are elongated in one of the planar directions of the one surface 200a of the semiconductor substrate 200, and are arranged so as to form stripes at equal intervals. In this embodiment, the trenches 203 are formed so as to elongate in the direction along the second and fourth sides Rm2 and Rm4.

[0029] Each trench 203 is filled with a gate insulating film 204 formed to cover the wall surface of each trench 203, and a gate electrode 205 made of polysilicon or the like formed on the gate insulating film 204. This forms a trench gate structure. In this embodiment, the gate electrode 205 in the main cell region Rm and the gate electrode 205 in the sense cell region Rs are connected to a common gate pad 103 via gate wiring formed in the peripheral region Rp, although details will be omitted.

[0030] The surface layer of the base layer 202 contains N + The source region 206 and P +A contact region 207 having a type of impurity is formed in the source region 206. Specifically, the source region 206 has a higher impurity concentration than the drift layer 201, terminates in the base layer 202, and is formed to contact the side surface of the trench 203. The contact region 207 has a higher impurity concentration than the base layer 202, and, like the source region 206, is formed to terminate in the base layer 202.

[0031] More specifically, the source region 206 is structured to extend in a rod shape in the region between the trenches 203 along the longitudinal direction of the trenches 203 so as to contact the side surface of the trench 203, and to terminate inside the tip of the trench 203. The contact region 207 is sandwiched between the two source regions 206 and extends in a rod shape along the longitudinal direction of the trench 203 (i.e., the source region 206). Note that the contact region 207 in this embodiment is formed deeper than the source region 206 with respect to one surface 200a of the semiconductor substrate 200. In this embodiment, the source region 206 corresponds to a first impurity region.

[0032] An interlayer insulating film 208 made of BPSG (abbreviation of borophosphosilicate glass) or the like is formed on one surface 200a of the semiconductor substrate 200. A source electrode 209 is formed on the interlayer insulating film 208 and is electrically connected to the source region 206 and the contact region 207 (i.e., the base layer 202) through a contact hole 208a formed in the interlayer insulating film 208. Although not shown in the drawings, the source electrode 209 in the main cell region Rm and the source electrode in the sense cell region Rs are formed separately. Therefore, the source electrode 209 in the main cell region Rm is electrically connected to the source region 206 and the contact region 207 formed in the main cell region Rm. The source electrode in the sense cell region Rs is electrically connected to the source region 206 and the contact region 207 formed in the sense cell region Rs. In this embodiment, the source electrode 209 in the main cell region Rm is formed to match the outer shape of the main cell region Rm. In other words, the main cell region Rm can be said to be a region in which the source electrode 209 is formed, and the first to fourth sides Rm1 to Rm4 of the main cell region Rm can be said to be the respective sides in the planar shape of the source electrode 209. For this reason, hereinafter, the respective sides forming the outline of the planar shape of the source electrode 209 will also be referred to as the first to fourth sides Rm1 to Rm4. Note that the planar shape can also be said to be the shape when viewed from the normal direction to the one surface 200a of the semiconductor substrate 200, or the shape in the normal direction to the one surface 200a of the semiconductor substrate 200. In addition, in this embodiment, the source electrode 209 corresponds to an electrode, and can also be said to be a first electrode.

[0033] A drain layer 210 having a higher impurity concentration than the drift layer 201 is formed on the side of the drift layer 201 opposite to the base layer 202 side (i.e., the other surface 200b side of the semiconductor substrate 200). The drain layer 210 is also formed in the peripheral region Rp, and is formed over the entire other surface 200b of the semiconductor substrate 200. A drain electrode 211 electrically connected to the drain layer 210 is formed on the drain layer 210 (i.e., the other surface 200b of the semiconductor substrate 200). That is, in this embodiment, the drain layers 210 in the main cell region Rm and the sense cell region Rs are connected to a common drain electrode 211. In this embodiment, the drain layer 210 corresponds to a second impurity region. The drain electrode 211 can also be said to be a second electrode.

[0034] The peripheral region Rp has a drift layer 201 similar to the main cell region Rm and the sense cell region Rs. In order to suppress electric field concentration in the main cell region Rm and the sense cell region Rs, a P + A mold deep layer 212 is formed. In this embodiment, the deep layer 212 is formed deeper than the base layer 202, and is formed so as to surround the main cell region Rm and the sense cell region Rs.

[0035] In addition, in the outer peripheral region Rp, a guard ring 213 is formed in the surface layer portion of the drift layer 201 so as to surround the deep layer 212. In reality, a plurality of guard rings 213 are formed, each having an annular structure surrounding the main cell region Rm and the sense cell region Rs. In other words, the guard rings 213 are formed to form a multi-ring structure.

[0036] In the peripheral region Rp, similarly to the main cell region Rm, an interlayer insulating film 208 is formed on one surface 200a of the semiconductor substrate 200. A contact hole 208b exposing the deep layer 212 is formed in the interlayer insulating film 208, and the source electrode 209 is also connected to the deep layer 212 through the contact hole 208b.

[0037] A protective film 220 made of polyimide or the like is formed on one surface 200a of the semiconductor substrate 200. The protective film 220 has openings 220a that cover the outer edges of the source electrodes 209 in the main cell region Rm while exposing the inner edges. In this embodiment, as shown in FIG. 4, the openings 220a are formed so that the inner edges of the source electrodes 209 in the main cell region Rm are exposed in a planar rectangular shape. However, the openings 220a in this embodiment are formed so that at least one of the distances between the openings 220a and the first to fourth sides Rm1 to Rm4 of the source electrodes 209 is different. Furthermore, although not shown, the protective film 220 also has openings that expose the pads 101 to 103 in the outer periphery region Rp. However, in this embodiment, the source electrodes in the sense cell region Rs are covered by the protective film 220.

[0038] Furthermore, in the semiconductor chip 20, a main connection wiring 230 is arranged in the peripheral region Rp, connecting the source electrode 209 in the main cell region Rm and the Kelvin source pad 101. In the semiconductor chip 20, a sense connection wiring 240 is arranged, connecting the source electrode 209 in the sense cell region Rs and the sense source pad 102. Although cross-sectional views are omitted, the main connection wiring 230 and the sense connection wiring 240 are arranged on one surface 200a of the semiconductor substrate 200 via an interlayer insulating film 208, similar to the source electrode 209. The detailed arrangement location of the main connection wiring 230 will be described later.

[0039] The above is the configuration of the semiconductor chip 20 in this embodiment. In this embodiment, N type, N- type, and N+ type correspond to the first conductivity type, and P type and P+ type correspond to the second conductivity type.

[0040] As shown in FIGS. 1 and 2, the semiconductor chip 20 is arranged such that the drain electrode 211 side is attached to the first support member 10 via a bonding member 110 made of solder or the like.

[0041] As shown in FIG. 1 , the circuit chip 30 is mounted on a first support member 10 via a bonding member such as solder, and is connected to each of the pads 101-103 formed on the semiconductor chip 20 via connecting members 70 such as bonding wires. The circuit chip 30 includes a control circuit 300 including, for example, an analog circuit (not shown), a CPU, and various storage units such as ROM, RAM, and nonvolatile RAM. The circuit chip 30 controls the ON state, in which current flows through the main cell region Rm and the sense cell region Rs, and the OFF state, in which current does not flow, by adjusting the gate voltage applied to the gate pad 103. The circuit chip 30 also controls the Kelvin source pad 101 and the sense source pad 102 to have the same potential, and detects the current flowing through the main element Me according to the current flowing through the sense element Se. CPU stands for Central Processing Unit, ROM stands for Read Only Memory, and RAM stands for Random Access Memory. In addition, various storage media such as ROM are non-transitory tangible storage media.

[0042] Similar to the first support member 10, the second support member 40 is formed of a lead frame or the like made of, for example, copper, iron, or an alloy thereof, and is formed into a plate shape having a front surface 40a and a back surface 40b opposite the front surface 40a, as shown in Fig. 2. In addition, the second support member 40 has the same thickness as the first support member 10. In this embodiment, the second support member 40 is disposed so that the back surface 40b is located on the same plane as the back surface 40b of the first support member 10.

[0043] The connecting member 50 is made of a Cu clip or the like, and connects the source electrode 209 of the semiconductor chip 20 to the second support member 40. In this embodiment, the connecting member 50 has a generally L-shaped cross section, with one end portion connected to the source electrode 209 and the other end portion connected to the second support member 40 bent between them. One end portion of the connecting member 50 is connected to the source electrode 209 via a bonding member 120, and the other end portion is connected to the second support member 40 via a bonding member 130. The bonding members 120 and 130 are made of, for example, solder or the like.

[0044] More specifically, the bonding member 120 is disposed in an opening 220a formed in the protective film 220 of the semiconductor chip 20. The linking member 50 is provided with a connection portion 500 at one end thereof that protrudes toward the semiconductor chip 20, and the connection portion 500 is connected to the bonding member 120. The connection portion 500 of this embodiment has a rectangular shape in plan view corresponding to the shape of the opening 220a, but is slightly smaller than the opening 220a in consideration of the intersection dimensions of the opening 220a and the connection portion 500, misalignment of the mounting position of the linking member 50, and the like. In FIG. 4, the portion facing the connection portion 500 that is connected to the bonding member 120 is indicated by a dashed line as a facing portion 510.

[0045] The sealing member 60 is made of molding resin, potting resin, or the like, and is formed to seal the first support member 10, semiconductor chip 20, circuit chip 30, second support member 40, connecting member 50, etc. Specifically, the sealing member 60 is formed so that the back surface 10b of the first support member 10 and the back surface 40b of the second support member 40 are exposed.

[0046] In the power semiconductor device described above, the semiconductor chip 20 generates heat when the device is in an on state. The portion of the source electrode 209 that is different from the portion connected to the connecting member 50 has lower heat dissipation properties than the portion of the source electrode 209 that is connected to the connecting member 50. More specifically, the portion of the source electrode 209 that is different from the portion connected to the connecting member 50 is more likely to have lower heat dissipation properties as the area where heat cannot be dissipated by the connecting member 50 becomes larger and the portion is more distant from the connecting member 50. In the source electrode 209 of such a power semiconductor device, cracks are likely to occur in the portions that are likely to have lower heat dissipation properties and that come into contact with the protective film 220 and the sealing member 60, which have different linear expansion coefficients.

[0047] 4, in this embodiment, the fourth distance d4 is the longest of the first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4 of the source electrode 209. Therefore, in this power semiconductor device, there is a high possibility that a crack will be introduced into a portion of the source electrode 209 located near the fourth side Rm4.

[0048] Therefore, the main connection wiring 230 of this embodiment is drawn out from a side of the source electrode 209 that is different from the fourth side Rm4, and connected to the Kelvin source pad 101. Specifically, the main connection wiring 230 of this embodiment is connected to the first side Rm1 of the source electrode 209. As a result, in the power semiconductor device of this embodiment, it is possible to suppress the occurrence of a potential difference between the source electrode 209 and the Kelvin source pad 101 (i.e., the main connection wiring 230), and to suppress a decrease in the detection accuracy of the current flowing through the main cell region Rm.

[0049] Furthermore, the source electrode 209 and the connecting member 50 have a thicker overall thickness where they overlap, resulting in a smaller potential gradient. However, the portion of the source electrode 209 not connected to the connecting member 50 has a thinner thickness, resulting in a larger potential gradient. In this case, for example, at the first side Rm1, the distance from the portion of the source electrode 209 connected to the connecting member 50 (i.e., the facing portion 510) other than the corner is constant, resulting in a constant potential gradient. However, at the corner, the distance from the portion of the source electrode 209 connected to the connecting member 50 is likely to be longer, resulting in a larger potential gradient. Furthermore, when the connecting member 50 is misaligned, the distance from the corner to the portion connected to the connecting member 50 is likely to change significantly. Therefore, the main connection wiring 230 of this embodiment is further connected to a portion of the first side Rm1 of the source electrode 209 other than the portion connected to the second and fourth sides Rm2 and Rm4 that forms the corner. This can prevent a potential difference from occurring between the source electrode 209 and the Kelvin source pad 101, thereby preventing a decrease in the detection accuracy of the current flowing through the main cell region Rm. In this case, the main connection wiring 230 is preferably connected to an inner portion (i.e., the side away from the corner) of the first side Rm1, which intersects with a virtual line extending from the opposing portion 510 in a direction along the second and fourth sides Rm2 and Rm4 (i.e., the longitudinal direction of the trench 203 in this embodiment). More specifically, even if the linking member 50 is displaced toward the second side Rm2 or the fourth side Rm4, the main connection wiring 230 is preferably connected to an inner portion of the first side Rm1, which intersects with a virtual line extending from the opposing portion 510 in a direction along the second and fourth sides Rm2 and Rm4. This can prevent a change in the potential gradient up to the portion connected to the main connection wiring 230, even if the linking member 50 is displaced toward the second side Rm2 or the fourth side Rm4.

[0050] Furthermore, as described above, the trench 203 of this embodiment is formed with the direction along the second and fourth sides Rm2 and Rm4 as its longitudinal direction. Therefore, as shown in Fig. 6, it can be said that the main connection wiring 230 is connected to the side of the source electrode 209 that intersects with the longitudinal direction of the trench 203. In other words, it can be said that the main connection wiring 230 is connected to the side of the source electrode 209 that faces the end of the longitudinal direction of the trench 203. Note that in Fig. 6, the longitudinal direction of the trench 203 is the left-right direction on the page, and all of the trenches 203 are shown with solid lines to make the longitudinal direction of the trench 203 easier to understand.

[0051] 7, if a crack C occurs in the source electrode 209 near the first side Rm1, a current flows through the semiconductor substrate 200 located between adjacent trenches 203, as indicated by arrow A. Therefore, in this embodiment, even if a crack C occurs, the detour path is shortened, which can prevent a potential difference from occurring between the source electrode 209 and the Kelvin source pad 101 and prevent a decrease in the detection accuracy of the current flowing in the main cell region Rm.

[0052] Here, a comparative power semiconductor device is defined as a power semiconductor device in which the trench 203 is formed with its longitudinal direction along the first and third sides Rm1 and Rm3, and the main connection wiring 230 is connected to the first side Rm1 of the source electrode 209. In the comparative power semiconductor device, as shown in FIG. 8 , if a crack C occurs near the first side Rm1, current cannot flow in the semiconductor substrate 200 in a direction intersecting the longitudinal direction of the trench 203. Therefore, as shown by arrow B, the current flows through the source electrode 209, bypassing the portion where the crack C is formed. Therefore, in the comparative power semiconductor device, the voltage drop before reaching the main connection wiring 230 is likely to be large, and the potential difference between the source electrode 209 and the Kelvin source pad 101 is likely to be large. In other words, in the power semiconductor device of this embodiment, even in relation to the longitudinal direction of the trench 203 and the connection point between the main connection wiring 230 and the source electrode 209, it is possible to suppress the occurrence of a potential difference between the source electrode 209 and the Kelvin source pad 101, and it is possible to suppress a decrease in the detection accuracy of the current flowing in the main cell region Rm.

[0053] According to the present embodiment described above, the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that constitutes the longest first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4. Therefore, the main connection wiring 230 is connected to a part of the source electrode 209 that is different from a part that is prone to cracking, and it is possible to prevent a potential difference from occurring between the source electrode 209 and the Kelvin source pad 101 (i.e., the main connection wiring 230). Therefore, it is possible to prevent a decrease in the detection accuracy of the current flowing through the main cell region Rm.

[0054] (1) In this embodiment, the main connection wiring 230 is connected to a side of the source electrode 209 that intersects with the longitudinal direction of the trench 203. Therefore, even if a crack C occurs near a portion of the source electrode 209 that is connected to the main connection wiring 230, a current flows through the semiconductor substrate 200, and therefore, it is possible to further suppress the occurrence of a potential difference between the source electrode 209 and the Kelvin source pad 101 (i.e., the main connection wiring 230).

[0055] (2) In this embodiment, the main connection wiring 230 is connected to a portion of the source electrode 209 that is different from the corner portion. Therefore, the main connection wiring 230 is connected to a portion of the source electrode 209 that is different from the portion where the crack C is likely to occur, and it is possible to suppress the occurrence of a potential difference between the source electrode 209 and the Kelvin source pad 101.

[0056] (3) In this embodiment, the control circuit 300 detects the current flowing through the main cell region Rm while maintaining the same potential between the Kelvin source pad 101 and the sense source pad 102. This prevents the gate-source voltage of the main element Me from differing from the gate-source voltage of the sense element Se, thereby preventing a decrease in the detection accuracy of the current flowing through the main cell region Rm.

[0057] (4) In this embodiment, the semiconductor chip 20, the circuit chip 30, and the connecting member 50 are integrated with the sealing member 60. Therefore, compared to a case where the circuit chip 30 is disposed outside the sealing member 60, for example, the power semiconductor device can be made smaller.

[0058] (Modification of the first embodiment) A modification of the first embodiment will be described. In the above first embodiment, an example has been described in which the main connection wiring 230 is connected to the first side Rm1 of the source electrode 209. However, the side to which the main connection wiring 230 is connected can be changed as appropriate, as long as the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that forms the longest first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4.

[0059] For example, as shown in FIG. 9A, the main connection wiring 230 may be connected to the second side Rm2. Furthermore, as shown in FIG. 9B, the opening 220a may be a recessed hexagon formed by combining two rectangles with different long sides. In other words, the opening 220a may be a recessed hexagon including a protrusion that protrudes from one corner of the rectangle toward the fourth side Rm4. Furthermore, when the opening 220a is formed in this manner, the connection portion 500 of the coupling member 50 has a shape corresponding to the shape of the opening 220a, and has a recessed hexagonal shape in plan view in which a protrusion is added to a rectangular shape, and the facing portion 510 has a recessed hexagonal shape including a protrusion 520 that corresponds to the protrusion of the connection portion 500. 9B , the fourth distance between the facing portion 510 and the fourth side Rm4 is a fourth distance d4a between the protruding portion 520 of the facing portion 510 and the fourth side Rm4, and a fourth distance d4b between a portion of the facing portion 510 where the protruding portion 520 is not formed and the fourth side Rm4. In this configuration, the fourth distance d4b between the portion of the facing portion 510 where the protruding portion 520 is not formed and the fourth side Rm4 is the longest. Therefore, in this configuration, the main connection wiring 230 may be connected to, for example, a portion of the fourth side Rm4 of the source electrode 209 that faces the protruding portion 520.

[0060] 9C, the facing portion 510 may be configured so that the second distance d2 is the longest. In this configuration, the main connection line 230 may be connected to the fourth side Rm4 of the source electrode 209.

[0061] Furthermore, as shown in FIG. 9D, the facing portion 510 may be configured so that the third distance d3 is the longest.

[0062] (Second embodiment) A second embodiment will be described. This embodiment is different from the first embodiment in that the number of main connection wirings 230 is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0063] In the semiconductor chip 20 of this embodiment, as shown in FIG. 10 , the Kelvin source pad 101 is connected to the source electrode 209 of the main cell region Rm via two main connection wirings 230. However, each main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that forms the longest distance between the opposing portion 510 and the first to fourth sides Rm1 to Rm4. In this embodiment, one of the two main connection wirings 230 is connected to the first side Rm1, and the other main connection wiring 230 is connected to the third side Rm3. In this embodiment, since the two main connection wirings 230 are connected to the source electrode 209 in this manner, it can also be said that the two main connection wirings 230 are connected to opposing sides of the source electrode 209. Note that the gate pad 103 is omitted from FIG. 10 .

[0064] According to the present embodiment described above, the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that defines the longest first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4. Therefore, the same effects as those of the first embodiment can be obtained.

[0065] (1) In this embodiment, the source electrode 209 and the Kelvin source pad 101 are connected via two main connection wirings 230. This makes it easier to maintain the connection between the source electrode 209 and the Kelvin source pad 101.

[0066] (2) In this embodiment, the two main connection wirings 230 are connected to opposing sides of the source electrode 209. Therefore, even if the connection point between the semiconductor chip 20 and the linking member 50 (i.e., the position of the opposing portion 510) varies, fluctuations in the potential of the Kelvin source pad 101 can be suppressed. That is, for example, in the case where the main connection wirings 230 are connected only to the first side Rm1 of the source electrode 209 as in the first embodiment, if the opposing portion 510 is shifted toward the first side Rm1, the potential difference between the source electrode 209 and the Kelvin source pad 101 decreases, and if the opposing portion 510 is shifted toward the third side Rm3, the potential difference between the source electrode 209 and the Kelvin source pad 101 increases. Therefore, by connecting the main connection wirings 230 to opposing sides of the source electrode 209, it becomes easier to cancel the influence of the shifting of the opposing portion 510, and it is possible to improve robustness against sense ratio fluctuations due to mounting variations.

[0067] (Modification of the second embodiment) A modified example of the second embodiment will be described. In the second embodiment, the number of main connection wirings 230 can be changed as appropriate. For example, as shown in FIG. 11A, three main connection wirings 230 may be provided and connected to a first side Rm1, a second side Rm2, and a third side Rm3 of the source electrode 209. In this configuration, the main connection wirings 230 connected to the first side Rm1 and the third side Rm3 of the source electrode 209 are connected to opposing sides of the source electrode 209.

[0068] 11B, the opening 220a (i.e., the opposing portion 510) may be formed in a recessed hexagonal shape similar to that of FIG. 9B. In this configuration, for example, four main connection wirings 230 may be provided, and connected to portions of the first side Rm1, the second side Rm2, the third side Rm3, and the fourth side Rm4 of the source electrode 209 that face the protrusion 520. In this configuration, the main connection wirings 230 connected to the first side Rm1 and the third side Rm3 of the source electrode 209 are connected to the opposing sides of the source electrode 209. In this configuration, the main connection wirings 230 connected to the portions of the second side Rm2 and the fourth side Rm4 of the source electrode 209 that face the protrusion 520 are connected to the opposing sides of the source electrode 209.

[0069] (Third embodiment) A third embodiment will be described. This embodiment is different from the second embodiment in that the shape of the main connection wiring 230 is changed. As the rest is the same as the second embodiment, a description thereof will be omitted here.

[0070] In the semiconductor chip 20 of this embodiment, as shown in FIG. 12 , four main connection wirings 230 are connected to the source electrode 209. In this embodiment, two main connection wirings 230 are connected to the first side Rm1, and two main connection wirings 230 are connected to the third side Rm3. In this case, as in the first embodiment, the two main connection wirings 230 connected to the first side Rm1 are preferably connected to the inner side of the portion of the first side Rm1 that intersects with the imaginary lines extending from the opposing portion 510 in the directions along the second and fourth sides Rm2 and Rm4. Similarly, the two main connection wirings 230 connected to the third side Rm3 are preferably connected to the inner side of the portion of the third side Rm3 that intersects with the imaginary lines extending from the opposing portion 510 in the directions along the second and fourth sides Rm2 and Rm4. Each main connection wiring 230 is also connected to the same Kelvin source pad 101. In FIG. 12, the gate pad 103 is omitted.

[0071] Furthermore, each main connection wiring 230 is formed so that it has the same resistance value. In this embodiment, each main connection wiring 230 has the same length, so that it has the same resistance value. However, the detailed configuration of each main connection wiring 230 can be changed as appropriate as long as the resistance values ​​are the same. For example, each main connection wiring 230 may be formed so that it has the same resistance value by appropriately adjusting the material, thickness, width, length, etc.

[0072] According to the present embodiment described above, the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that defines the longest first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4. Therefore, the same effects as those of the first embodiment can be obtained.

[0073] (1) In this embodiment, a plurality of main connection wirings 230 are provided, and the main connection wirings 230 have the same resistance value. Therefore, it is possible to suppress variations in voltage drop in the main connection wirings 230.

[0074] (Fourth embodiment) A fourth embodiment will be described. This embodiment is different from the first embodiment in that the connection location of the main connection wiring 230 is changed. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0075] In the first embodiment, the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that defines the longest first to fourth distances d1 to d4 between the opposing portion 510 and the first to fourth sides Rm1 to Rm4. However, as described in the first embodiment, the main connection wiring 230 is connected to a side that intersects with the longitudinal direction of the trench 203, which can also suppress the generation of a potential difference between the source electrode 209 and the Kelvin source pad 101, and can suppress a decrease in the detection accuracy of the current flowing in the main cell region Rm.

[0076] 13, in this embodiment, the trench 203 is extended such that its longitudinal direction is along the first and third sides Rm1 and Rm3. Note that, as in the first embodiment, the first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4 are such that the fourth distance d4 is the longest. In this embodiment, the fourth distance d4 is the longest, but the main connection wiring 230 is connected to the fourth side Rm4 of the source electrode 209, which is the side that intersects with the extension direction of the trench 203.

[0077] In the present embodiment described above, the main connection wiring 230 is connected to the side of the source electrode 209 that intersects with the longitudinal direction of the trench 203. Therefore, even if a crack C occurs near the portion of the source electrode 209 that is connected to the main connection wiring 230, a current flows through the semiconductor substrate 200, and it is therefore possible to prevent a potential difference from occurring between the source electrode 209 and the Kelvin source pad 101. Therefore, it is possible to prevent a decrease in the detection accuracy of the current flowing in the main cell region Rm.

[0078] (Modification of the fourth embodiment) A modification of the fourth embodiment will be described. In the fourth embodiment, similarly to the second embodiment, a plurality of main connection wirings 230 may be provided. For example, as shown in FIG. 14, the opening 220a (i.e., the facing portion 510) may be formed in a recessed hexagonal shape similarly to FIG. 9B. One of the two main connection wirings 230 may be connected to the second side Rm2 intersecting the extension direction of the trench 203, and the other main connection wiring 230 may be connected to a portion of the fourth side Rm4 intersecting the extension direction of the trench 203 that faces the protruding portion 520. In this case, although not particularly shown, the other main connection wiring 230 may be connected to a portion of the fourth side Rm4 intersecting the extension direction of the trench 203 that faces a portion of the facing portion 510 where the protruding portion 520 is not formed.

[0079] Although not particularly shown, when the fourth embodiment is combined with the third embodiment and a plurality of main connection wires 230 are provided, the resistance values ​​of the main connection wires 230 may be set to be equal to each other.

[0080] (Fifth embodiment) A fifth embodiment will be described. This embodiment differs from the second embodiment in that it is provided with two Kelvin source pads 101. As the rest of the configuration is the same as the second embodiment, a description thereof will be omitted here.

[0081] First, when a plurality of main connection wirings 230 are provided as in the second embodiment, it may be difficult to route the wiring when attempting to connect the plurality of main connection wirings 230 to the same Kelvin source pad 101. For this reason, in this embodiment, two Kelvin source pads 101 are arranged on the semiconductor chip 20 as shown in Fig. 15. Specifically, in the semiconductor chip 20 of this embodiment, the pads 101 to 103 are arranged in the order of the Kelvin source pad 101, sense source pad 102, gate pad 103, and Kelvin source pad 101.

[0082] In this embodiment, two main connection wirings 230 are connected to the source electrode 209. One of the two main connection wirings 230 is connected to one of the two Kelvin source pads 101, and the other main connection wiring 230 is connected to the other of the two Kelvin source pads 101. The two Kelvin source pads 101 are connected to the circuit chip 30 via the connection members 70, and are electrically connected within the circuit chip 30 to be connected to the control circuit unit 300.

[0083] According to the present embodiment described above, the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that defines the longest first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4. Therefore, the same effects as those of the first embodiment can be obtained.

[0084] (1) In this embodiment, the semiconductor chip 20 is provided with two main connection wirings 230 and two Kelvin source pads 101, and each main connection wiring 230 is connected to a different Kelvin source pad 101. Therefore, compared to the case where each main connection wiring 230 is connected to the same Kelvin source pad 101, routing of the wiring can be made easier.

[0085] (Sixth embodiment) A sixth embodiment will now be described. In this embodiment, unlike the first embodiment, the control circuit section 300 of the circuit chip 30 is formed on the semiconductor chip 20. As the rest is the same as the first embodiment, a description thereof will be omitted here.

[0086] 16, the semiconductor chip 20 of this embodiment is formed as a single chip with the control circuit section 300 formed in the peripheral region Rp, and does not have the Kelvin source pad 101 and the sense source pad 102. The main connection wiring 230 and the sense connection wiring 240 are directly connected to the control circuit section 300 within the semiconductor chip 20.

[0087] In addition, the semiconductor chip 20 of this embodiment is provided with a gate wiring 250 that is connected to the gate pad 103 and connected to the control circuit section 300 within the semiconductor chip 20. However, the gate electrode 205 of the main cell region Rm and the gate electrode of the sense cell region Rs may each be directly connected to the control circuit section 300.

[0088] According to the present embodiment described above, the main connection wiring 230 is connected to a side of the source electrode 209 that is different from the side that defines the longest first to fourth distances d1 to d4 between the facing portion 510 and the first to fourth sides Rm1 to Rm4. Therefore, the same effects as those of the first embodiment can be obtained.

[0089] (1) In this embodiment, the main cell region Rm, the sense cell region Rs, the outer peripheral region Rp, and the control circuit unit 300 are integrated into a single chip. Therefore, compared to when the control circuit unit 300 is disposed outside the semiconductor chip 20, the power semiconductor device can be made smaller.

[0090] (Other embodiments) Although the present disclosure has been described with reference to the embodiments, it is understood that the present disclosure is not limited to the embodiments or structures. The present disclosure also encompasses various modifications and modifications within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms including only one element, more than one element, or less than one element, are also within the scope and spirit of the present disclosure.

[0091] In the above-described embodiments, a power semiconductor device having a semiconductor chip 20 on which MOSFET elements of an N-channel type trench gate structure, in which the first conductivity type is N-type and the second conductivity type is P-type, is formed is described. However, the semiconductor elements formed on the semiconductor chip 20 can be changed as appropriate, and for example, P-channel type MOSFET elements in which the conductivity types of each component are reversed to those of an N-channel type may be formed. Furthermore, the semiconductor chip 20 may be configured to have an IGBT of a similar structure formed thereon in addition to the MOSFET elements. In the case of an IGBT, the N-channel type MOSFET elements in the above-described embodiments may be formed on the semiconductor chip 20. + The drain layer is P + Other than the change to the collector layer of the MOSFET, this embodiment is the same as the MOSFET described in each of the above embodiments.

[0092] Furthermore, in each of the above embodiments, the second support member 40 may be arranged so that its back surface 40b is not positioned on the same plane as the back surface 10b of the first support member 10, but is positioned on the opposite side of the first support member 10 across the semiconductor chip 20.

[0093] Furthermore, in each of the above embodiments, the planar shape of the main cell region Rm (i.e., the source electrode 209) may not be a rectangular shape with a portion cut out, but may be a perfect rectangular shape, or may be another shape different from a rectangular shape.

[0094] In the first to fifth embodiments, the control circuit section 300 may be disposed outside the sealing member 60.

[0095] The above embodiments can also be combined as appropriate. For example, the second embodiment can be combined with any of the fourth to sixth embodiments to provide a plurality of main connection wirings 230. The third embodiment can be combined with any of the fourth to sixth embodiments to provide the same resistance value for the plurality of main connection wirings 230. Furthermore, the fourth embodiment can be combined with any of the fifth and sixth embodiments to connect the main connection wiring 230 to a side that intersects with the longitudinal direction of the trench 203, and the main connection wiring 230 can be connected to a side of the source electrode 209 that constitutes the longest first to fourth distances d1 to d4 between the opposing portion 510 and the first to fourth sides Rm1 to Rm4.

[0096] The controller and methods described herein may be implemented by a special-purpose computer configured with a processor and memory programmed to perform one or more functions embodied in a computer program. Alternatively, the controller and methods described herein may be implemented by a special-purpose computer configured with a processor configured with one or more dedicated hardware logic circuits. Alternatively, the controller and methods described herein may be implemented by one or more special-purpose computers configured with a processor and memory programmed to perform one or more functions in combination with a processor configured with one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by a computer on a computer-readable non-transitory storage medium. [Explanation of symbols]

[0097] 20 Semiconductor chips 209 Source Electrode 220 Protective film 220a opening 230 Main connection wiring 510 Opposite part Rm Main cell area Rs Sense cell area Rm1~Rm4 1st to 4th sides d1~d4 1st to 4th distance

Claims

1. A power semiconductor device, a semiconductor chip (20) having a main cell region (Rm), a sense cell region (Rs), and an outer peripheral region (Rp) surrounding the main cell region and the sense cell region; A control circuit unit (300) electrically connected to the semiconductor chip for processing; a connecting member (50) connected to the semiconductor chip, The semiconductor chip has a semiconductor substrate (200) in which the main cell region, the sense cell region, and the outer periphery region are configured, the main cell region and the sense cell region have the same configuration; A drift layer (201) of a first conductivity type; a base layer (202) of a second conductivity type formed on the drift layer; a trench gate structure including a gate insulating film (204) disposed on a wall surface of a trench (203) that penetrates the base layer and reaches the drift layer, and a gate electrode (205) disposed on the gate insulating film; a first impurity region (206) of a first conductivity type formed in a surface layer portion of the base layer, having a higher impurity concentration than the drift layer, and in contact with the trench; a second impurity region (210) of the first conductivity type or the second conductivity type formed on the opposite side of the drift layer from the base layer, the main cell region has an electrode (209) connected to the first impurity region and the base layer; the sense cell region has an electrode connected to the first impurity region and the base layer, a main connection wiring (230) disposed in the outer peripheral region and connected to the electrode in the main cell region, and a sense connection wiring (240) connected to the electrode in the sense cell region; the main connection wiring and the sense connection wiring are connected to the control circuit unit; a protective film (220) that covers the outer edge of the electrode in the main cell region and has an opening (220a) that exposes the inner edge, the connecting member is connected to a portion of the electrode in the main cell region that is exposed through an opening in the protective film via a joining member (120); When the portion of the electrode in the main cell region that faces the portion where the connecting member is joined to the joining member is defined as an opposing portion (510), the main connection wiring is connected to a side of the electrode in the main cell region that is different from the side that forms the outline of the electrode (Rm1 to Rm4) with the longest distance (d1 to d4) between the opposing portion and the side (Rm1 to Rm4) that forms the outline of the electrode.

2. 2. The power semiconductor device according to claim 1, wherein a plurality of the main connection wirings are provided, each connected to a side of the electrode in the main cell region that is different from a side where a distance between the opposing portion and a side that forms the outline of the electrode is longest.

3. the trench is formed with a longitudinal direction extending in one direction in a surface direction of the semiconductor substrate, 3. The power semiconductor device according to claim 1, wherein the main connection wiring is connected to a side of the electrode in the main cell region that intersects with the longitudinal direction.

4. A power semiconductor device, a semiconductor chip (20) having a main cell region (Rm), a sense cell region (Rs), and an outer peripheral region (Rp) surrounding the main cell region and the sense cell region; a control circuit section (300) electrically connected to the semiconductor chip; a connecting member (50) connected to the semiconductor chip, The semiconductor chip has a semiconductor substrate (200) having the main cell region, the sense cell region, and the outer periphery region; the main cell region and the sense cell region have the same configuration; A drift layer (201) of a first conductivity type; a base layer (202) of a second conductivity type formed on the drift layer; a trench gate structure including a gate insulating film (204) disposed on a wall surface of a trench (203) that penetrates the base layer and reaches the drift layer, and a gate electrode (205) disposed on the gate insulating film; a first impurity region (206) of a first conductivity type formed in a surface layer portion of the base layer, having a higher impurity concentration than the drift layer, and in contact with the trench; a second impurity region (210) of the first conductivity type or the second conductivity type formed on the opposite side of the drift layer from the base layer, the main cell region has an electrode (209) connected to the first impurity region and the base layer; the sense cell region has an electrode connected to the first impurity region and the base layer, a main connection wiring (230) disposed in the outer peripheral region and connected to the electrode in the main cell region, and a sense connection wiring (240) connected to the electrode in the sense cell region; the main connection wiring and the sense connection wiring are connected to the control circuit unit; a protective film (220) that covers the outer edge of the electrode in the main cell region and has an opening (220a) that exposes the inner edge, the connecting member is connected to a portion of the electrode in the main cell region that is exposed through an opening in the protective film via a joining member (120); the trench is formed with a longitudinal direction extending in one direction in a surface direction of the semiconductor substrate, The main connection wiring is connected to a side of the electrode in the main cell region that intersects with the longitudinal direction and defines the outline of the electrode.

5. 5. The power semiconductor device according to claim 4, wherein a plurality of the main connection wires are provided, each connected to a side of the electrode in the main cell region that forms the outline of the electrode and intersects with the longitudinal direction.

6. The power semiconductor device according to claim 2 or 5, wherein the plurality of main connection wires are connected to opposing sides of the electrodes in the main cell region.

7. 6. The power semiconductor device according to claim 2, wherein the plurality of main connection wires have the same resistance value.

8. the electrodes in the main cell region have a planar shape with corners, The power semiconductor device according to claim 1 or 4, wherein the main connection wiring is connected to a portion different from the corner portion.

9. 5. The power semiconductor device according to claim 1, wherein the control circuit is connected to the main connection wiring and the sense connection wiring, and maintains the main connection wiring and the sense connection wiring at the same potential.

10. A circuit chip (30) having the control circuit portion is provided, 5. The power semiconductor device according to claim 1, wherein the semiconductor chip, the connecting member, and the circuit chip are sealed and integrated with a sealing member (60).

11. The power semiconductor device according to claim 1 or 4, wherein the control circuit section is formed on the semiconductor chip.

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