Multilayer ceramic capacitor and manufacturing method for the same

Abstract

To provide a multilayer ceramic capacitor having a high breakdown voltage and a manufacturing method for the same.SOLUTION: The multilayer ceramic capacitor has a multilayer body formed by alternately stacking in the height direction a plurality of internal electrode layers and a plurality of effective layers including dielectric ceramic. The total concentration of a predetermined additive element contained in the dielectric ceramic at the periphery of the multilayer body is 0.1 to 10 atom% higher than the total concentration of the additive element contained in the dielectric ceramic at the center of the multilayer body.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] The present invention relates to a multilayer ceramic capacitor and a method for manufacturing the same. [Background technology]

[0002] In recent years, there has been an increasing demand for small, high-capacity multilayer ceramic capacitors and multilayer ceramic capacitors with high voltage resistance. In order to ensure voltage resistance characteristics in such medium- to high-voltage multilayer ceramic capacitors, the ceramic layers have been made thicker, and the resulting decrease in capacitance has been compensated for by increasing the size of the multilayer ceramic capacitor. In addition, the dielectric layers of small, high-capacity multilayer ceramic capacitors are becoming thinner, and capacitors with thicknesses of less than 1 μm are now being mass-produced. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2021-108360 [Patent Document 2] Patent Publication No. 2021-108361 [Patent Document 3] Patent Publication No. 2021-108363 [Patent Document 4] Patent Publication No. 2021-108364 [Patent Document 5] Japanese Patent Publication No. 2021-197458 Summary of the Invention [Problem to be solved by the invention]

[0004] However, due to the structural characteristics of multilayer ceramic capacitors, no matter how much the resistance of the dielectric element is improved, electric field concentration and electrostrictive stress concentration occur around the periphery of the electrodes, which has been found to be an obstacle to designing multilayer ceramic capacitors with high voltage resistance. In view of this situation, an object of the present invention is to provide a multilayer ceramic capacitor with a high breakdown voltage and a method for manufacturing the same. [Means for solving the problem]

[0005] As a result of extensive research, the present inventors have completed the present invention as described below.

[0006] The multilayer ceramic capacitor of the present invention has a laminate and external electrodes. The laminate has a substantially rectangular parallelepiped shape with height, length, and width directions that are perpendicular to one another. The external electrodes are formed on a pair of end faces of the laminate facing each other in the longitudinal direction, and are insulated from each other. The laminate has internal electrode layers and effective layers. The internal electrode layers are stacked layer by layer, with some connecting to only one of the pair of external electrodes and others connecting to only the other of the pair of external electrodes. The effective layers are made of dielectric ceramics. The internal electrodes are stacked at intervals in the height direction. The effective layers occupy the area of ​​the laminate other than the internal electrode layers.

[0007] The laminate has a central portion and an outer peripheral portion defined as described below. The total concentration of the additive elements contained in the dielectric ceramic of the outer peripheral portion is 0.1 to 10 atom % higher than the total concentration of the additive elements contained in the dielectric ceramic of the central portion. Here, the additive elements are rare earth elements, Mg element, Ca element, Mn element, V element, and Ni element.

[0008] The center of the laminate is defined as follows. The central portion is a roughly rectangular parallelepiped region that shares a center with the laminate and has dimensions that are reduced to 30% of the laminate in the height, length, and width directions.

[0009] The outer periphery of the laminate is defined as follows. The outer peripheral portion is a region that combines four portions from the surface of each of four of the six faces of the laminate that are parallel to the height direction to the respective imaginary cutting planes. Here, the imaginary cutting planes are planes that are parallel to each of the four faces and are spaced a predetermined distance from the end of the internal electrode layer toward the center. Here, the predetermined distance is the smallest length among (A) 30 μm, (B) 10% of the dimension in the length direction of the internal electrode layer, and (C) 10% of the dimension in the width direction of the internal electrode layer.

[0010] A suitable method for producing the multilayer ceramic capacitor of the present invention is also included in the present invention. In the manufacturing method of the present invention, a laminate having internal electrode layers and effective layers is obtained by firing, and precursors thereof, precursor layers of the effective layers containing a first organic resin and a dielectric ceramic and precursors of the internal electrode layers containing a second organic resin and a metal, are alternately stacked in the height direction to obtain a pre-fired chip.

[0011] Next, the first and second organic resins contained in the obtained pre-fired chips are removed by heating, and then the above-mentioned additive elements are impregnated into the pre-fired chips by a vapor phase method or a liquid phase method. As described above, this makes the total concentration of the additive elements contained in the dielectric ceramic of the outer periphery 0.1 to 10 atom % higher than the total concentration of the additive elements contained in the dielectric ceramic of the center. The pre-fired chips thus impregnated with the additive elements are fired to obtain a laminate. [Effects of the Invention]

[0012] According to the present invention, it is possible to further increase the breakdown voltage of a multilayer ceramic capacitor. The mechanism by which this effect is realized will be described later. [Brief explanation of the drawings]

[0013] [Figure 1] 1 is a schematic cross-sectional view of a multilayer ceramic capacitor according to the present invention. [Figure 2]10 shows the relationship between the position in the length direction of the effective layer and the simulation results of the electric field intensity in a conventional multilayer ceramic capacitor. DETAILED DESCRIPTION OF THE INVENTION

[0014] The present invention will be described in detail below with reference to the drawings as appropriate, but the present invention is not limited to the illustrated embodiments.

[0015] The multilayer ceramic capacitor of the present invention comprises a substantially rectangular parallelepiped laminate and external electrodes. The laminate has internal electrode layers and effective layers. There are at least one pair of external electrodes, and the pair of external electrodes are formed on one end face of the laminate and the opposite end face, insulated from each other. The direction in which the pair of external electrodes face each other is defined as the longitudinal direction (L direction) of the laminate.

[0016] Fig. 1 is a schematic cross-sectional view of a multilayer ceramic capacitor of the present invention. In Fig. 1(A), the left-right direction of the drawing is the width direction (W direction), and the up-down direction of the drawing is the height direction (T direction). In Fig. 1(B), the left-right direction of the drawing is the length direction (L direction), and the up-down direction of the drawing is the height direction (T direction). Fig. 1 depicts the TW cross section and the TL cross section of a laminate 1 that constitutes the multilayer ceramic capacitor.

[0017] External electrodes are not depicted in Figure 1. The external electrodes are formed in the length direction (L direction) of the laminate, which runs from the front of the paper to the back of the paper in Figure 1(A), in other words, on both the left and right end surfaces of the paper in Figure 1(B). In the present invention, the stacking direction of the internal electrode layers and effective layers is defined as the height direction (T direction) of the laminate. The direction perpendicular to both the length direction (L direction) and the height direction (T direction) defined above is defined as the width direction (W direction) of the laminate.

[0018] The laminate structure of the laminate is depicted in Figure 1. The laminate is formed by alternately stacking internal electrode layers 12 and effective layers 11 in the height direction (T direction). The internal electrode layers 12 are stacked layer by layer, with some connecting to only one of a pair of external electrodes and others connecting to only the other of the pair of external electrodes. In the present invention, the lamination form of the internal electrode layers and effective layers in the laminate is not particularly limited, and conventionally known techniques in the relevant technical field can be adopted as appropriate.

[0019] The central portion and the peripheral portion of the laminated body will be described with reference to the drawings.

[0020] <Center> In Figures 1(A) and 1(B), the area surrounded by a dotted line and indicated by the reference numeral 13 is the center. The laminate 1 and the center 13 share a center. Here, the "center" is a point located at 1 / 2 of the length in each of the height direction, length direction, and width direction. The length of the center 13 in each of the height direction, height direction, length direction, and width direction is 30% of the length of the laminate 1 in each of the height direction, height direction, length direction, and width direction.

[0021] <Outer periphery> In Figures 1(A) and 1(B), the area surrounded by the dotted line indicated by the reference numeral 14 is the outer periphery. The outer periphery exists near both end faces in the width direction (W direction) depicted in Figure 1(A) and near both end faces in the length direction (L direction) depicted in Figure 1(B). The outer periphery exists from both end faces in the width direction (W direction) and both end faces in the length direction (L direction) of the laminate 1 toward the center of the laminate 1. The boundary of the outer periphery closer to the center of the laminate 1 is depicted by dotted lines indicated by the reference numerals 14A and 14B in Figure 1(A), and by dotted lines indicated by the reference numerals 14C and 14D in Figure 1(B). For convenience, the boundary lines of the outer periphery depicted by the dotted lines 14A to 14D are referred to as imaginary cross-sections.

[0022] The imaginary cutting planes 14A and 14B are parallel to the height and width directions (TW planes) of the laminate, and the imaginary cutting planes 14C and 14D are parallel to the height and length directions (TL planes) of the laminate. The imaginary cutting planes 14A to 14D are located at a predetermined distance d from the end of the internal electrode 12 toward the center of the laminate 1. Here, the predetermined distance d is the shortest length among the following (A) to (C). (A) 30 μm, (B) 10% of the length of the internal electrode layer 12, (C) 10% of the width of the internal electrode layer 12 In the above (B) and (C), the reason why 10% of the length or width direction of the internal electrode layer 12 is set as the predetermined distance d for defining the outer periphery is because this 10% length is an area where electric field concentration and electrostrictive stress concentration are likely to occur. However, if the internal electrode layer is extremely large and the value of 10% of the length or width direction is too large, the meaning of the present invention is lost, so the specific value of 30 μm is set in (A).

[0023] When setting the imaginary cross sections 14A to 14D at positions spaced a predetermined distance d from the end of the internal electrode 12 toward the center of the laminate 1, the end of the internal electrode 12 is defined as the portion closest to each end face of the laminate (excluding the portion contacting the external electrode). In the TW cross section of the laminate depicted in FIG. 1(A), the ends of the internal electrodes 12 are usually aligned and easily defined. In the TL cross section of the laminate depicted in FIG. 1(B), the internal electrode layers 12 are usually stacked layer by layer, with one connecting to only one of a pair of opposing external electrodes (not shown) and the other connecting to only the other of the pair. In such cases, the end of the internal electrode 12 is defined not at the portion connected to the external electrode, but at the portion not connected to the external electrode. FIGS. 1(A) and 1(B) illustrate how the imaginary cross sections 14A to 14D are defined at a distance d from the end of the internal electrode 12.

[0024] The total concentration of the additive elements contained in the dielectric ceramics in the central and peripheral parts of the laminate 1 defined above is higher by 0.1 to 10 atom %, more preferably by 0.1 to 10 atom %, than the total concentration of the additive elements described below contained in the dielectric ceramic in the central part. 5 The additive elements are rare earth elements, Mg, Ca, Mn, V, and Ni. Among the above elements, preferred elements to be contained in the outer periphery of the laminate 1 include Dy, Mg, Mn, and V.

[0025] The inventors consider that the reason why the multilayer ceramic capacitor of the present invention is expected to have a high breakdown voltage is that the difference in the total concentration of the additive elements between the central portion and the peripheral portion as described above is important in suppressing heat generation due to electric field concentration near the ends of the internal electrodes.

[0026] Figure 2 is a graph showing the relationship between the position in the length direction (L direction) of the effective layer of a conventional multilayer ceramic capacitor and the simulation results of the electric field strength at that position. In this simulation, it is assumed that the ratio of elements contained in the effective layer of the conventional capacitor is uniform throughout the entire area. The point where L is zero is the point where the effective layer contacts one of the external electrodes. A peak in the electric field strength is observed where L is approximately 0.3 mm, which corresponds to the vicinity of the end of the internal electrode layer.

[0027] In this way, the electric field strength increases significantly near the ends of the internal electrode layers. In response to this, the inventors speculate as follows about the mechanism by which the heat generation due to the electric field concentration is suppressed by increasing the total concentration of the additive elements by a predetermined amount in the peripheral portion compared to the center portion, as described above. By increasing the concentration of the additive elements near the ends of the internal electrodes, the relative permittivity or insulation resistance value of the effective layer (dielectric) near the ends of the internal electrodes changes, and as a result, the heat generation or electrostrictive stress concentration due to the electric field concentration in those areas is suppressed. The inventors speculate that this effect flattens the peak of the electric field strength near the end of the internal electrode on the side in contact with the ceramic effective layer.

[0028] Conventionally known techniques can be appropriately adopted for manufacturing a multilayer ceramic capacitor. Non-limiting examples of manufacturing methods are given below. A conventionally known method can be used to apply a paste for internal electrode layers to ceramic green sheets for active layers in a predetermined pattern, and then stack multiple ceramic green sheets after application to obtain a pre-fired chip.

[0029] Here, the ceramic green sheets contain a first organic resin and a dielectric ceramic. The dielectric ceramic may be a barium titanate ceramic. The paste for the internal electrode layers contains a second organic resin and a metal. The first and second organic resins contained in the pre-fired chip can be any conventionally known organic resin.

[0030] As described above, in the present invention, the means for obtaining pre-fired chips is not limited to applying paste for internal electrode layers to ceramic green sheets.

[0031] The pre-fired chips thus obtained are heated to remove the first and second organic resins. A conventionally known method can be appropriately adopted as the specific heating method for removing the organic resins. The pre-fired chips from which the first and second organic resins have been removed are impregnated with the additive element described above. Various impregnation techniques, such as a gas phase method or a liquid phase method, can be adopted as the method for impregnating the additive element. During the impregnation, a predetermined difference in concentration of the additive element is achieved between the center and the periphery. Examples of methods for achieving a difference in concentration of the additive element between the center and the periphery include the ALD method (Atomic Layer Depositon), liquid vacuum impregnation, and liquid vacuum pressure impregnation.

[0032] By firing the pre-fired chips thus impregnated with the additive elements, a laminate for a multilayer ceramic capacitor can be obtained. The firing conditions can be determined by appropriately adopting conventional techniques. By forming external electrodes on the resulting laminate, a multilayer ceramic capacitor can be obtained. [Example]

[0033] The present invention will be described in detail below based on examples, but the present invention is not limited to these examples.

[0034] (Experimental Example 1) The laminated ceramic capacitors of the comparative example and the example were manufactured with the following part specifications: The main component of the active layer was barium titanate, and the main component of the internal electrodes was nickel. Effective layer thickness: 2.0 μm, Internal electrode layer dimensions: length 1800 μm, width 1000 μm, thickness 1.0 μm Number of layers: 400 Multilayer ceramic capacitor size: length (L direction) 2.0 mm, width (W direction) 1.25 mm Capacitance as a capacitor: 10μF

[0035] In manufacturing the multilayer ceramic capacitor, first, a pre-fired chip was obtained by laminating precursors of the internal electrode layer and the active layer, and then the pre-fired chip was heated to remove the binder (organic resin). After the organic resin was removed, the pre-fired chip was impregnated with additive elements under different conditions for each sample. The impregnated pre-fired chip was then fired to obtain a laminate. A paste for external electrodes was applied to both longitudinal end faces of the obtained laminate, and the external electrodes were formed by baking. In this way, a multilayer ceramic capacitor was obtained. The concentrations of additive elements in the center and outer periphery, as well as the breakdown voltage, of the obtained multilayer ceramic capacitor were measured.

[0036] Ceramic composition of the part corresponding to the effective layer in the chip before firing: Barium titanate, Dy, Mg, Ca, Mn, V, Si Internal electrode metal type: Nickel

[0037] The concentration of additive elements in the center and outer periphery, as well as the breakdown voltage, of the resulting multilayer ceramic capacitors were measured. The concentration of additive elements in the outer periphery was measured in the dielectric effective layer 30 μm inward from the edge of the internal electrode. Elemental concentration was analyzed using spot analysis with FE-EPMA to analyze the composition of the center and outer periphery, and the concentration (atom%) of each additive element was calculated. FE-EPMA spot analysis was performed at 10,000x magnification at five random points within the center and outer periphery, and the average value was calculated.

[0038] The impregnation conditions of the additive elements for each sample, the concentrations of the additive elements in the central and peripheral portions after firing, and the breakdown voltage of the resulting multilayer ceramic capacitor are as follows:

[0039] Comparative Example: Impregnation conditions: No impregnation treatment with added elements. Center after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Outer periphery after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Breakdown voltage: 148V

[0040] Example 1: Impregnation conditions: Dy elements were added by the vapor phase method. The specific raw materials and procedures are as follows: The pre-fired chips from which the organic resin had been removed were impregnated with Dy elements using the ALD method. Center after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Outer periphery after firing: Dy (2.5 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Breakdown voltage: 173V

[0041] Example 2: Impregnation conditions: Mg element was added by the vapor phase method. The specific raw materials and procedures are as follows: organic The resin-removed pre-fired chips were impregnated with Mg element using the ALD method. Center after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Outer periphery after firing: Dy (2.0 atom%), Mg (1.5 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Breakdown voltage: 161V

[0042] Example 3: Impregnation conditions: Dy and Mg elements were added by the vapor phase method. The specific raw materials and procedures are as follows: The pre-fired chips from which the organic resin had been removed were impregnated with Dy and Mg elements using the ALD method. Center after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Outer periphery after firing: Dy (2.5 atom%), Mg (1.5 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Breakdown voltage: 166V

[0043] Example 4: Impregnation conditions: Dy and Mg elements were added using the liquid phase method. The specific raw materials and procedures are as follows: The pre-fired chips from which the organic resin had been removed were impregnated with Dy and Mg elements using the liquid vacuum impregnation method. Center after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Outer periphery after firing: Dy (2.5 atom%), Mg (1.5 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Breakdown voltage: 163V

[0044] Example 5: Impregnation conditions: Dy element was added by the vapor phase method. The specific raw materials and procedures are as follows: The pre-fired chips from which the organic resin had been removed were impregnated with Dy element using the ADL method. Center after firing: Dy (2.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Outer periphery after firing: Dy (7.0 atom%), Mg (1.0 atom%), Mn (0.2 atom%), V (0.1 atom%), Si (1.5 atom%) Breakdown voltage: 196V [Explanation of symbols]

[0045] 1. Laminate 11 Effective Layer 12 Internal electrode layer 13 Center 14 Outer periphery 14A~14D Virtual cutting plane

Claims

1. A multilayer ceramic capacitor comprising: a laminate having a substantially rectangular parallelepiped shape with a height direction, a length direction, and a width direction that are perpendicular to one another; and a pair of external electrodes formed on a pair of end faces of the laminate facing each other in the length direction, and insulated from each other, the laminate is configured by alternately stacking a plurality of internal electrode layers and a plurality of effective layers made of dielectric ceramics in a height direction, and the internal electrode layers are stacked in layers such that one of the internal electrode layers is connected to only one of the pair of external electrodes and the other of the pair of external electrodes is connected to only the other of the pair of external electrodes, The laminate has a central portion and an outer periphery as defined below, the total concentration of the additive element described below contained in the dielectric ceramic of the outer periphery is higher by 0.1 to 10 atom % than the total concentration of the additive element described below contained in the dielectric ceramic of the center; the additional elements are rare earth elements, Mg element, Ca element, Mn element, V element, and Ni element, the central portion is a substantially rectangular parallelepiped region that shares a center with the laminate and has dimensions that are reduced to 30% of the laminate in each of a height direction, a length direction, and a width direction, the outer periphery is a region that combines four portions from the surfaces of four of the six faces of the laminate that are parallel to the height direction to the respective virtual cross-sections described below, the virtual cutting plane is a plane parallel to each of the four faces and spaced a predetermined distance (described later) from an end of the internal electrode layer toward the center, The predetermined distance is the minimum length among (A) 30 μm, (B) 10% of the dimension in the length direction of the internal electrode layer, and (C) 10% of the dimension in the width direction of the internal electrode layer. The multilayer ceramic capacitor.

2. A method for manufacturing a multilayer ceramic capacitor, comprising: The multilayer ceramic capacitor to be manufactured is the multilayer ceramic capacitor according to claim 1, a step of alternately stacking precursor layers of the active layers, each containing a first organic resin and a dielectric ceramic, and precursors of the internal electrode layers, each containing a second organic resin and a metal, in a height direction to obtain a pre-fired chip; a step of removing the first and second organic resins contained in the pre-fired chips by heating, and then impregnating the pre-fired chips with the additive element by a gas phase method or a liquid phase method; a step of obtaining the laminate by firing the pre-fired chips impregnated with the additive element; The above manufacturing method.

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